阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 久米一平 中村一彦 野田有辉 于 2017-08-02 设计创作，主要内容包括：本发明的实施方式提供一种能够减小贯通电极与半导体元件之间的接触电阻的半导体装置。本实施方式的半导体装置具备半导体衬底,所述半导体衬底具有第1面及第2面,所述第1面具有半导体元件,所述第2面位于该第1面的相反侧。第1绝缘膜设置在半导体衬底的第1面上。导电体设置在第1绝缘膜上。金属电极设置在第1面与第2面之间,贯通半导体衬底并与导电体接触。第2绝缘膜设置在金属电极与半导体衬底之间。第1绝缘膜与第2绝缘膜的边界面位于较半导体衬底的第1面更靠导电体侧,且随着向金属电极的中心部靠近而以向导电体接近的方式倾斜。(Embodiments of the invention provide a semiconductor device capable of reducing contact resistance between a through electrode and a semiconductor element. The semiconductor device of the present embodiment includes a semiconductor substrate having a 1 st surface and a 2 nd surface, the 1 st surface having a semiconductor element, and the 2 nd surface being located on the opposite side of the 1 st surface. The 1 st insulating film is provided on the 1 st surface of the semiconductor substrate. The conductor is provided on the 1 st insulating film. The metal electrode is provided between the 1 st surface and the 2 nd surface, penetrates the semiconductor substrate, and is in contact with the conductor. The 2 nd insulating film is provided between the metal electrode and the semiconductor substrate. The boundary surface between the 1 st insulating film and the 2 nd insulating film is located closer to the conductor than the 1 st surface of the semiconductor substrate, and is inclined so as to approach the conductor as it approaches the center portion of the metal electrode.)

1. A semiconductor device, characterized by comprising:

a semiconductor substrate having a 1 st surface and a 2 nd surface located on an opposite side of the 1 st surface, the 1 st surface having a 1 st opening, the 2 nd surface having a 2 nd opening, and the 1 st through hole connecting the 1 st opening and the 2 nd opening;

a semiconductor element formed on the 2 nd surface side of the semiconductor substrate;

a 1 st insulating film provided on the 2 nd surface side of the semiconductor substrate and having a 2 nd through hole;

a 1 st electrode disposed on the 1 st insulating film;

a 2 nd electrode provided inside the 1 st through hole and the 2 nd through hole and connected to the 1 st electrode; and

a 2 nd insulating film formed between the sidewall of the 1 st through hole and the 2 nd electrode; and is

When the direction from the 1 st surface to the 2 nd surface is defined as a 1 st direction and the direction perpendicular to the 1 st direction and within the 1 st surface is defined as a 2 nd direction,

in a cross section in a direction substantially perpendicular to the 1 st and 2 nd surfaces, a 1 st central axis along the 1 st direction of an upper portion of the 2 nd electrode and a 2 nd central axis along the 1 st direction of a lower portion of the 2 nd electrode are offset along the 2 nd direction.

2. The semiconductor device according to claim 1, wherein:

the upper part of the 2 nd electrode is: a portion of the 2 nd electrode in the vicinity of the 1 st face at a height along the 1 st direction;

the lower part of the 2 nd electrode is: a portion of the 2 nd electrode in the vicinity where the 2 nd electrode is connected to the 1 st electrode at a height along the 1 st direction.

3. The semiconductor device according to claim 1, wherein:

when a boundary surface between the 1 st insulating film and the 2 nd insulating film is defined as a 1 st boundary surface and a boundary surface between the 2 nd electrode and the 1 st insulating film or the 2 nd insulating film is defined as a 2 nd boundary surface,

the 2 nd boundary surface is: along the 1 st direction, is closer to perpendicular when below the 1 st boundary surface than when in the vicinity of the 2 nd surface and above the 1 st boundary surface.

4. The semiconductor device according to claim 3, wherein:

the 2 nd boundary surface is: along the 1 st direction, the direction is closer to perpendicular in the vicinity of the 1 st surface than in the vicinity of the 2 nd surface and above the 1 st boundary surface.

5. The semiconductor device according to claim 1, wherein:

when a boundary surface between the 2 nd electrode and the 1 st insulating film or the 2 nd insulating film is defined as a 2 nd boundary surface,

the 2 nd boundary surface is: the 1 st electrode is oriented from the 1 st surface in the 1 st direction, and the surface substantially perpendicular to the 1 st electrode is changed into an inclined surface and is further close to a perpendicular surface.

6. The semiconductor device according to claim 1, wherein:

the 1 st center axis is a center axis of the 1 st through hole;

the 2 nd center axis is a center axis of the 2 nd through hole.

7. A semiconductor device, characterized by comprising:

a semiconductor substrate having a 1 st surface and a 2 nd surface located on an opposite side of the 1 st surface, the 1 st surface having a 1 st opening, the 2 nd surface having a 2 nd opening, and the 1 st through hole connecting the 1 st opening and the 2 nd opening;

a semiconductor element formed on the 2 nd surface side of the semiconductor substrate;

a 1 st insulating film provided on the 2 nd surface side of the semiconductor substrate and having a 2 nd through hole;

a 1 st electrode disposed on the 1 st insulating film;

a 2 nd electrode provided inside the 1 st through hole and the 2 nd through hole and connected to the 1 st electrode; and

a 2 nd insulating film formed between the sidewall of the 1 st through hole and the 2 nd electrode; and is

When the direction from the 1 st surface to the 2 nd surface is the 1 st direction and the boundary surface between the 2 nd electrode and the 1 st insulating film or the 2 nd insulating film is the 2 nd boundary surface,

in a cross section in a direction substantially perpendicular to the 1 st and 2 nd surfaces, a height from the 1 st surface to the 1 st electrode along the 1 st direction is set to a 1 st height, a 2 nd height, and a 3 rd height in this order from a side closer to the 1 st surface,

the 2 nd boundary surfaces at the 1 st and 3 rd heights are: a surface closer to vertical than the 2 nd boundary surface at the 2 nd height.

8. The semiconductor device according to claim 7, wherein:

the 1 st height is: a height in the vicinity of the 1 st face along the 1 st direction.

9. The semiconductor device according to claim 7, wherein:

the 3 rd height is: a height in the vicinity of the 1 st electrode along the 1 st direction.

10. The semiconductor device according to claim 7, wherein:

when the boundary surface of the 1 st insulating film and the 2 nd insulating film is defined as a 1 st boundary surface,

the 2 nd height is: a height above the 1 st boundary surface and closer to the 2 nd surface than the 1 st surface.

11. The semiconductor device according to claim 7, wherein:

when a direction perpendicular to the 1 st direction and within the 1 st plane is taken as the 2 nd direction,

in a cross section in a direction substantially perpendicular to the 1 st and 2 nd surfaces, a 1 st central axis along the 1 st direction of an upper portion of the 2 nd electrode and a 2 nd central axis along the 1 st direction of a lower portion of the 2 nd electrode are offset along the 2 nd direction.

12. A semiconductor device, characterized by comprising:

a semiconductor substrate having a 1 st surface and a 2 nd surface located on an opposite side of the 1 st surface, the 1 st surface having a 1 st opening, the 2 nd surface having a 2 nd opening, and the 1 st through hole connecting the 1 st opening and the 2 nd opening;

a semiconductor element formed on the 2 nd surface side of the semiconductor substrate;

a 1 st insulating film provided on the 2 nd surface side of the semiconductor substrate and having a 2 nd through hole;

a 1 st electrode disposed on the 1 st insulating film;

a 2 nd electrode provided inside the 1 st through hole and the 2 nd through hole and connected to the 1 st electrode; and

a 2 nd insulating film formed between the sidewall of the 1 st through hole and the 2 nd electrode; and is

When the direction from the 1 st surface to the 2 nd surface is defined as a 1 st direction, and when a boundary surface between the 2 nd electrode and the 1 st insulating film on both sides of the 2 nd electrode is defined as a 3 rd and a 4 th boundary surface and a boundary surface between the 2 nd insulating film and the semiconductor substrate on both sides of the 2 nd electrode is defined as a 5 th and a 6 th boundary surface in a cross section in a direction perpendicular to the 1 st surface and the 2 nd surface, a 1 st centerline is shifted from a 2 nd centerline toward a 2 nd direction, the 1 st centerline is a line passing through a 1 st center point that is a center between the 3 rd and 4 th boundary surfaces and along the 1 st direction, the 2 nd centerline is a line passing through a 2 nd center point that is a center between the 5 th and 6 th boundary surfaces and along the 1 st direction, the 2 nd direction is a direction perpendicular to the 1 st direction and within the 1 st plane.

13. The semiconductor device according to claim 12, wherein:

at the height along the 1 st direction,

the 1 st center point is a center point between the 5 th boundary surface and the 6 th boundary surface at a height near the 1 st surface,

the 2 nd center point is a center point between the 3 rd and 4 th boundary surfaces at a height near the 1 st electrode.

14. The semiconductor device according to claim 12, wherein:

a 2 nd boundary surface which is a boundary surface between the 2 nd electrode and the 1 st insulating film or the 2 nd insulating film is: along the 1 st direction, from the 1 st surface to the 1 st electrode, from a substantially vertical surface to an inclined surface,

after the inclined surface is formed, the inclined surface is further a surface which is vertical as the inclined surface faces the 1 st electrode.

15. The semiconductor device according to claim 14, wherein:

when the boundary surface of the 1 st insulating film and the 2 nd insulating film is defined as a 1 st boundary surface,

the inclined surface is above the 1 st boundary surface.

16. The semiconductor device according to any one of claims 1 to 15, wherein:

when the boundary surface of the 1 st insulating film and the 2 nd insulating film is defined as a 1 st boundary surface,

the 1 st boundary surface is located on a side closer to the 1 st electrode than the 2 nd boundary surface in the 1 st direction.

17. The semiconductor device according to any one of claims 1 to 15, wherein:

the 2 nd electrode is a metal electrode.

18. The semiconductor device according to any one of claims 1 to 15, wherein:

the semiconductor element includes an array of memory cells.

19. The semiconductor device according to any one of claims 1 to 15, wherein:

the 2 nd electrode is electrically connected to the bump electrode on the 1 st surface side.

Technical Field

Embodiments of the invention relate to a semiconductor device and a method of manufacturing the same.

Background

Semiconductor chips such as semiconductor memories are sometimes stacked from the viewpoint of higher functionality and higher integration. In order to electrically connect elements between the stacked semiconductor chips, Through-electrodes called TSVs (Through-Silicon vias) are used. The TSV penetrates the substrate to electrically connect an element of the substrate to an element of another substrate. It is desirable that parasitic resistance and parasitic capacitance of the TSV be small so as not to affect the characteristics of the element.

However, although the TSV itself is made of metal and has low resistance, the contact hole for the TSV formed in the substrate has a high aspect ratio. Therefore, the contact area between the TSV and the wiring at the bottom of the contact hole is reduced, and the contact resistance between the TSV and the wiring is increased.

Disclosure of Invention

Embodiments of the invention provide a semiconductor device capable of reducing contact resistance between a through electrode and a semiconductor element, and a method for manufacturing the same.

The semiconductor device of the present embodiment includes a semiconductor substrate having a 1 st surface and a 2 nd surface, the 1 st surface having a semiconductor element, and the 2 nd surface being located on the opposite side of the 1 st surface. The 1 st insulating film is provided on the 1 st surface of the semiconductor substrate. The conductor is provided on the 1 st insulating film. The metal electrode is provided between the 1 st surface and the 2 nd surface, penetrates the semiconductor substrate, and is in contact with the conductor. The 2 nd insulating film is provided between the metal electrode and the semiconductor substrate. The boundary surface between the 1 st insulating film and the 2 nd insulating film is located closer to the conductor than the 1 st surface of the semiconductor substrate, and is inclined so as to approach the conductor as it approaches the center of the metal electrode.

Drawings

Fig. 1 is a sectional view showing an example of the structure of a semiconductor chip according to embodiment 1.

Fig. 2 is a cross-sectional view showing a structure on the 2 nd surface side of the wiring structure in more detail.

Fig. 3 is a sectional view showing a structure in which the boundary surface is not inclined.

Fig. 4 is a sectional view showing an example of the method for manufacturing a semiconductor chip according to embodiment 1.

Fig. 5 is a sectional view showing a method of manufacturing a semiconductor chip subsequent to fig. 4.

Fig. 6 is a sectional view showing a method of manufacturing a semiconductor chip following fig. 5.

Fig. 7 is a sectional view showing a method of manufacturing a semiconductor chip following fig. 6.

Fig. 8 is a sectional view showing an example of the structure of the semiconductor chip according to embodiment 2.

Fig. 9 is a sectional view showing an example of the method for manufacturing a semiconductor chip according to embodiment 2.

Fig. 10 is a sectional view showing an example of the method for manufacturing the semiconductor chip following fig. 9.

Fig. 11 is a sectional view showing an example of the method for manufacturing the semiconductor chip following fig. 10.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present embodiment does not limit the present invention. In the following embodiments, the vertical direction of the semiconductor substrate means a relative direction when a surface on which the semiconductor element is provided or a surface opposite thereto is an upper surface, and may be different from the vertical direction according to the gravitational acceleration.

(embodiment 1)

Fig. 1 is a sectional view showing an example of the structure of a semiconductor chip according to embodiment 1. The semiconductor chip 1 may be a semiconductor chip having, for example, an EEPROM (Electrically Erasable and Programmable Read-Only Memory) of a NAND type or the like. Fig. 1 shows a TSV of the semiconductor chip 1 and its peripheral portion.

The semiconductor chip 1 includes a semiconductor substrate 10, STI (Shallow Trench Isolation)20, a pad (bump) 30, a TSV40, a spacer film 50, and a bump 60.

The semiconductor substrate 10 is, for example, a silicon substrate, and is thinned to, for example, about 30 μm or less. The semiconductor substrate 10 has a 1 st surface F1 and a 2 nd surface F2 located on the opposite side of the 1 st surface F1. The 1 st surface F1 of the semiconductor substrate 10 has active regions for forming semiconductor devices, and sti (shallow Trench isolation)20 for electrically separating the active regions from each other. In the active region, semiconductor elements (not shown) such as a memory cell array, a transistor, a resistance element, and a capacitance element are formed. An insulating film such as a silicon oxide film is used for STI 20. Although no semiconductor element is provided on the STI20, a pad 30 and a wiring structure 35 for electrically connecting the semiconductor element and the TSV40 are provided. Hereinafter, the pad 30 and the wiring structure 35 are also collectively referred to as the conductors 30 and 35. The semiconductor element and the wiring are not provided on the 2 nd surface F2 of the semiconductor substrate 10, but the bump 60 and the like electrically connected to the TSV40 are provided.

STI20 as a 1 st insulating film is provided on the 1 st face F1 of the semiconductor substrate 10. As described above, an insulating film such as a silicon oxide film is used for the STI 20.

The conductive bodies 30 and 35 are provided on the STI20 and electrically connected to a semiconductor element (for example, a transistor) provided on the 1 st surface F1 of the semiconductor substrate 10. A low resistance metal such as tungsten or titanium is used for the bonding pad 30. For example, polysilicon, the low-resistance metal, or the like is used for the wiring structure 35.

TSV40 and barrier metal BM, which are metal electrodes, are provided between the 1 st surface F1 and the 2 nd surface F2 of semiconductor substrate 10 and penetrate through semiconductor substrate 10. Furthermore, the TSV40 and the barrier metal BM penetrate the STI20 and are electrically connected to the conductors 30 and 35. Thus, the TSV40 and the barrier metal BM extend the electrical connection with the conductors 30 and 35 located on the 1 st surface F1 side to the 2 nd surface F2 side. TSV40 uses a low resistance metal such as nickel. The barrier metal BM is disposed at the side of the spacer film 50. The barrier metal BM is, for example, Ti, Ta, Ru or a laminate film thereof. Hereinafter, TSV40 and barrier metal BM are also collectively referred to as metal electrode 40 and BM. Further, as long as TSV40 can be embedded well in contact hole CH, barrier metal BM is not necessarily provided.

A spacer film 50 as a 2 nd insulating film is provided between the metal electrodes 40, BM and the semiconductor substrate 10, electrically separating the metal electrodes 40, BM and the semiconductor substrate 10. Further, the spacer film 50 is also provided on the 2 nd face F2 of the semiconductor substrate 10. The spacer film 50 is an insulating film such as a silicon oxide film.

The bump 60 is disposed on the TSV40 on the 2 nd face F2 side of the semiconductor substrate 10. The bump 60 is made of a metal such as tin or copper.

Fig. 2 is a cross-sectional view showing a structure closer to the 2 nd surface F2 than the wiring structure 35 in more detail. In fig. 2, for easy understanding, the connection portion between TSV40 or barrier metal BM and electrical conductors 30 and 35 is shown with emphasis schematically.

Here, the boundary surface Fb1 between the STI20 and the spacer film 50 is closer to the conductors 30 and 35 than the 1 st surface F1 of the semiconductor substrate 10, and is inclined so as to approach the conductors 30 and 35 toward the center of the TSV 40. That is, the boundary surface Fb1 is closer to the conductors 30 and 35 than the 1 st surface F1 of the semiconductor substrate 10, and is inclined in a direction away from the semiconductor substrate 10 toward the center of the TSV 40. In other words, boundary surface Fb1 is located between semiconductor substrate 10 and TSV40, and gradually approaches conductors 30 and 35 toward the center of contact hole CH in which TSV40 is provided (the center of TSV 40). Therefore, in the region having the contact hole CH, the thickness of the STI20 becomes thinner as it approaches the center portion of the TSV 40.

In addition, along with the inclination of the boundary face Fb1, the boundary face Fb2 between the TSV40 or the barrier metal BM and the spacer film 50 or the STI20 is also inclined along the boundary face Fb 1. For example, the boundary surface Fb2 has a slightly reverse tapered shape near the 1 st surface F1 (upper portion of the TSV 40) of the semiconductor substrate 10, or is a surface substantially perpendicular to the 1 st surface F1. The boundary surface Fb2 is inclined so as to approach the conductors 30 and 35 directly above the boundary surface Fb1 in the vicinity of the 2 nd surface F2 of the semiconductor substrate 10, toward the center of the TSV40 and toward the center of the TSV 40. Further, the boundary surface Fb2 approaches in the direction perpendicular to the 1 st surface F1 and reaches the conductors 30 and 35.

As described above, according to the present embodiment, the inner surface of the spacer film 50 between the semiconductor substrate 10 and the metal electrodes 40, BM has almost no surface substantially parallel to the 1 st surface F1, and extends in a direction substantially perpendicular to the 1 st surface F1 or is smoothly inclined.

Fig. 3 is a sectional view showing a structure in which the boundary surface Fb1 is not inclined. If the boundary surface Fbl is not inclined and is substantially parallel to the 1 st surface F1 or the 2 nd surface F2 of the semiconductor substrate 10 (for example, is substantially the same plane as the 2 nd surface F2) as in fig. 3, the boundary surface Fb2 is also substantially parallel to the 1 st surface F1 or the 2 nd surface F2 of the semiconductor substrate 10. In this case, the thickness of the STI20 directly below the spacer film 50 is substantially the same as the thickness of the STI20 below the semiconductor substrate 10. Therefore, the area of the bottom of contact hole CH becomes small, and the contact resistance between TSV40 and barrier metal BM and conductors 30 and 35 becomes high. When the boundary surface Fbl is not inclined and is substantially flush with the 2 nd surface F2, the inner surface of the partition film 50 has a step ST as shown in fig. 3. When there is a step ST on the inner side surface of the spacer film 50, coverage of the barrier metal provided on the inner side surface of the spacer film 50 becomes poor, and it becomes difficult to fill the metal material of the TSV 40.

In contrast, according to this embodiment, as shown in fig. 2, the inner surface of the spacer film 50 between the semiconductor substrate 10 and the metal electrodes 40 and BM has almost no surface substantially parallel to the 1 st surface F1, and extends in a direction substantially perpendicular to the 1 st surface F1 or is smoothly inclined. Thus, in the region below the contact hole CH, the thickness of the STI20 becomes thinner toward the center of the metal electrode 40, BM. In this case, the sum of the film thicknesses of the spacer film 50 and the STI20 becomes thinner toward the center portion of the contact hole CH. Thus, when the bottom of the contact hole CH is etched, the contact hole CH easily penetrates the spacer film 50 and the STI 20. Therefore, even if overetching is performed for a short time, the diameter of the contact hole CH formed in the spacer film 50 and the STI20 increases. This relatively increases the area of the bottom surface of the contact hole CH, and decreases the contact resistance between the metal electrode 40 and BM and the conductors 30 and 35. In addition, when etching the bottom of the contact hole CH, the time for overetching can be shortened, and therefore, the contact hole CH can be prevented from penetrating the wiring structure 35.

Further, the inner side surface of the spacer film 50 between the semiconductor substrate 10 and the metal electrode 40, BM extends in a direction substantially perpendicular to the 1 st surface F1 or is smoothly inclined. Thus, there is no step ST on the inner surface of the spacer film 50, and the barrier metal BM is covered well. Thus, the metal material of TSV40 is also easily filled.

Next, a method for manufacturing the semiconductor chip 1 of the present embodiment will be described.

Fig. 4 to 7 are sectional views showing an example of the method for manufacturing a semiconductor chip according to embodiment 1. Fig. 5 to 7 are schematic cross-sectional views similar to fig. 2, in order to easily understand a method of forming TSV40 or a connection portion between barrier metal BM and conductors 30 and 35.

Hereinafter, a method of forming the TSV40 on the semiconductor chip 1 will be mainly described.

First, STI20 is formed on the 1 st surface F1 of the semiconductor substrate 10 to determine an active region. The semiconductor substrate 10 is, for example, a silicon substrate. STI20 is, for example, a silicon oxide film. Next, a semiconductor device (not shown) is formed in the active region. The semiconductor element may be, for example, a memory cell array, a transistor, a resistive element, a capacitive element, or the like. In forming a semiconductor element, for example, the wiring structure 35 is formed on the STI 20. The semiconductor element and the wiring structure 35 are covered with insulating films 37 and 38. Next, the pad 30 is formed so as to be connected to the wiring structure 35. Thus, electrical conductors 30, 35 are formed over STI 20.

Next, the semiconductor substrate 10 is etched from the 2 nd surface F2 of the semiconductor substrate 10 located on the opposite side of the 1 st surface F1 by using a photolithography technique and an RIE (Reactive Ion Etching) method. That is, the contact hole CH is formed from the 2 nd surface F2 (rear surface) opposite to the 1 st surface F1 on which the semiconductor element is formed, using the resist layer 80 as a mask. Thereby, a contact hole CH is formed from the 2 nd surface F2 to the 1 st surface F1. In order to connect TSV40 with electrical conductors 30, 35, contact hole CH is formed on the region where electrical conductors 30, 35 are present in the region of STI 20. STI20 is exposed by forming contact hole CH.

Next, as shown in fig. 5, a part of ST120 located on the bottom surface of contact hole CH is etched by RIE. At this time, the etching gas of the material (e.g., silicon oxide film) of the STI20 is different from the etching gas of the material (e.g., silicon) of the semiconductor substrate 10. For example, the etching gas for silicon is SF₆、SiF₄、CF₄、C₄F₈、Ar、HBr、O₂A gas, a mixed gas thereof, or the like. Etching gas for silicon oxide film is CF₄、CHF₃、Ar、O₂A gas, a mixed gas thereof, or the like. Therefore, the etching step of STI20 is different from the etching step of semiconductor substrate 10. For example, the etching of STI20 may be performed after the etching of semiconductor substrate 10 using a different apparatus than the apparatus that performs the etching of semiconductor substrate 10. Alternatively, the etching of STI20 may be performed in the same apparatus as the etching of semiconductor substrate 10, but the etching gas needs to be replaced.

Since the ions of the etching gas are more difficult to reach the end portions than the central portion of the bottom portion of the contact hole CH, the film thickness T20c at the central portion of the STI20 is thinner than the film thickness T20e at the end portions as shown in fig. 5 at the bottom portion of the contact hole CH. Thus, the bottom surface of the contact hole CH is bowl-shaped. That is, the bottom surface of the contact hole CH is recessed toward the conductors 30 and 35 from the 1 st surface F1 of the semiconductor substrate 10, and is inclined so as to approach the conductors 30 and 35 as it approaches the center of the contact hole CH. Therefore, the thickness of the STI20 becomes thinner as it approaches the center portion of the contact hole CH.

After removing the photoresist Layer 80, as shown in fig. 6, the spacer film 50 is formed on the inner surface and bottom surface of the contact hole CH and the 2 nd surface F2 of the semiconductor substrate 10 by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The spacer film 50 is formed along the inner surface of the contact hole CH, and therefore, the spacer film 50 formed on the bottom surface of the contact hole CH is formed on the semiconductor substrate 10 and the STI20 with good coverage along the bowl shape of the contact hole CH.

The spacer film 50 is substantially bowl-shaped recessed in the same manner as the bottom surface of the contact hole CH. That is, the spacer film 50 on the bottom surface of the contact hole CH is inclined so as to approach the conductors 30 and 35 as it approaches the center portion of the contact hole CH. Accordingly, the boundary surface Fb1 between the STI20 and the spacer film 50 is also closer to the conductors 30 and 35 than the 1 st surface F1 of the semiconductor substrate 10, and is inclined so as to approach the conductors 30 and 35 as it approaches the center of the contact hole CH. That is, boundary Fbl is closer to conductors 30 and 35 than to face F1 of semiconductor substrate 10, and is inclined in a direction away from semiconductor substrate 10 toward the center of contact hole CH filling TSV 40.

In reality, the aspect ratio of the contact hole CH is relatively high, and therefore, the spacer film 50 formed in the opening of the contact hole CH becomes thicker than the spacer film 50 formed inside the contact hole CH. Therefore, as shown in fig. 6, the spacer film 50 projects in a direction substantially parallel to the 1 st plane F1 at the opening end of the contact hole CH. Hereinafter, a portion of the spacer film 50 protruding from the opening end of the contact hole CH is also referred to as an overhang portion OH. Such an overhang portion OH of the spacer film 50 makes the opening diameter of the contact hole CH slightly narrower than the diameter of the middle portion of the contact hole CH. Like fig. 6, if the opening diameter of the contact hole CH of the overhang portion OH of the spacer film 50 is set to be Φ 1 and the diameter of the middle portion of the contact hole CH is set to be Φ 2, Φ 1< Φ 2.

Next, as shown in fig. 7, the spacer film 50 and the STI20 at the bottom of the contact hole CH are etched by RIE using the spacer film 50 on the inner surface of the contact hole CH and the 2 nd surface F2 of the semiconductor substrate 10 as a mask. Thus, the contact hole CH penetrates the spacer film 50 and the STI20 and reaches the conductors 30 and 35 located under the STI 20. That is, the contact hole CH extends to the conductors 30, 35 under the STI 20. At this time, as described above, the diameter Φ 1 of the opening of the contact hole CH is narrowed compared to the diameter Φ 2 of the middle portion of the contact hole CH by the overhang portion OH of the spacer film 50. The spacer film 50 and STI20 at the bottom of the contact hole CH are etched using the overhang OH of the spacer film 50 as a mask. Therefore, the diameter of the contact hole CH formed in the lower portion of the spacer film 50 and the STI20 is substantially Φ 1.

On the other hand, the bottom surface of the contact hole CH is bowl-shaped and recessed, and the sum Ttlc of the film thicknesses of the central portions of the STI20 and the spacer film 50 is thinner than the sum TtIe of the film thicknesses of the end portions thereof. Therefore, the spacer film 50 and the STI20 are easily penetrated, and the diameter Φ c of the contact hole CH formed in the spacer film 50 and the STI20 can be relatively increased even by short-time overetching. This reduces the contact resistance between TSV40 and conductors 30 and 35 to be formed next. Further, since the time for performing the overetching can be shortened, the contact hole CH can be prevented from penetrating the wiring structure 35. Further, since the bottom surface of the contact hole CH is bowl-shaped, the inner surface of the contact hole CH has almost no surface substantially parallel to the 1 st surface F1, and extends or smoothly inclines in a direction substantially perpendicular to the 1 st surface F1. That is, the inner surface of the contact hole CH becomes a smooth inclined surface with almost no step. Therefore, the coverage of the barrier metal BM and the TSV40 described below becomes good.

Next, as in fig. 2, a barrier metal BM is formed in the contact hole CH, and a metal material of the TSV40 is deposited. Thereby, the metal electrodes 40, BM are formed in the contact holes CH. The barrier metal BM is, for example, Ti, Ta, Ru or a laminate film thereof. TSV40 uses a metal material such as nickel. This allows the metal electrodes 40 and BM to be connected to the conductors 30 and 35 and to be drawn out to the 2 nd surface F2 side. At this time, as described above, the inner surface of the contact hole CH becomes a smooth inclined surface with almost no step. This makes the coverage of the metal material of barrier metal BM and TSV40 good.

Next, the TSV40 and the barrier metal BM are processed using photolithography and RIE. Thereby, the material of the TSV40 and the barrier metal BM on the 2 nd face F2 (field) is removed.

Next, as shown in fig. 2, bumps 60 are formed on TSVs 40 using a plating method or the like. For the bump 60, tin or the like is used, for example. This completes the semiconductor chip 1 of the present embodiment. Thereafter, the semiconductor chip 1 and other semiconductor chips may be stacked and electrically connected to each other through the TSV40 and the bump 60.

As described above, according to the present embodiment, after the semiconductor substrate 10 is etched and before the spacer film 50 is formed, the upper portion of the STI20 at the bottom of the contact hole CH is etched. Thus, the bottom of the contact hole CH is bowl-shaped and dented, and the coverage of the spacer film 50 is improved. Further, the spacer film 50 is also bowl-shaped recessed substantially in the same manner as the bottom surface of the contact hole CH. Accordingly, since the thicknesses of the STI20 and the spacer film 50 become thinner toward the center of the contact hole CH or the TSV40, the contact hole CH easily penetrates the spacer film 50 and the STI20 when the bottom of the contact hole CH is etched. Therefore, the diameter of the contact hole CH formed in the spacer film 50 and the STI20 is relatively large, and the contact resistance between the metal electrode 40 and BM and the conductors 30 and 35 is low. Furthermore, overetching can be reduced, and therefore, penetration of the contact hole CH into the wiring structure 35 can be suppressed. Further, since there is no step ST on the inner surface of the spacer film 50, the coverage of the barrier metal BM or the metal material of the TSV40 becomes good.

(embodiment 2)

Fig. 8 is a sectional view showing an example of the structure of the semiconductor chip according to embodiment 2. The semiconductor chip 1 of embodiment 2 is different from embodiment 1 in the shape of the TSV40, the spacer film 50, and the like. Other configurations of embodiment 2 may be the same as those of embodiment 1. Fig. 8 also shows the connection between TSV40 or barrier metal BM and conductors 30 and 35 in a schematic manner, as in fig. 2, for ease of understanding.

In the semiconductor chip 1 according to embodiment 2, in a cross section in a direction substantially perpendicular to the 1 st plane F1 and the 2 nd plane F2 of the semiconductor substrate 10, boundary surfaces between the metal electrode 40, BM, and STI20 on both sides of the metal electrode 40, BM are defined as a 1 st boundary surface Fb11 and a 2 nd boundary surface Fb12, and boundary surfaces between the spacer film 50 on both sides of the metal electrode 40, BM and the semiconductor substrate 10 are defined as a 3 rd boundary surface Fb13 and a 4 th boundary surface Fb 14. At this time, the center C11_12 between the 1 st and 2 nd boundary surfaces Fb11 and Fb12 is shifted from the center C13_14 between the 3 rd and 4 th boundary surfaces Fb13 and Fb14 in the 1 st direction D1.

Further, of the boundary surfaces between the metal electrode 40 and BM on the 2 nd surface F2 side of the semiconductor substrate 10 and the spacer film 50, the boundary surface in the 1 st direction D1 is curved (with curvature) at the end E21 on the 2 nd surface F2 side. That is, the end E21 between the upper surface F50t1 and the side surface F50s1 of the spacer film 50 is chamfered and inclined with respect to both the upper surface F50t1 and the side surface F50s 1. On the other hand, of the boundary surfaces between the metal electrode 40, BM and the spacer film 50, the boundary surface located in the direction opposite to the 1 st direction D1 is not bent at the end E22 on the 2 nd surface F2 side. That is, the end E22 between the upper surface F50t2 and the side surface F50s2 of the spacer film 50 is not chamfered, and is substantially flush with either the upper surface F50t2 or the side surface F50s 2.

As described above, the direction D1 of the deviation of the center C11 — 12 between the 1 st boundary surface Fb11 and the 2 nd boundary surface Fb12 is substantially the same as the direction in which the curved boundary surface Fb21 is provided, as viewed from the center of the TSV 40. Such a configuration can be formed by the following manufacturing method of the semiconductor chip 1.

Fig. 9 to 11 are sectional views showing an example of a method for manufacturing a semiconductor chip according to embodiment 2. Hereinafter, a method of forming the TSV40 on the semiconductor chip 1 will be mainly described.

The steps up to the formation of the contact hole CH may be the same as those in embodiment 1. In embodiment 2, the etching of STI20 located on the bottom surface of contact hole CH is not performed at this stage. Therefore, the bottom surface of the contact hole CH is substantially parallel to the 1 st or 2 nd surfaces F1 and F2.

Next, as shown in fig. 9, the spacer film 50 is formed on the inner surface of the contact hole CH, the bottom surface of the contact hole CH, and the 2 nd surface F2 of the semiconductor substrate 10 by CVD or ALD. At this time, the aspect ratio of the contact hole CH is relatively high, and therefore, the spacer film 50 has an overhang portion OH at the open end of the contact hole CH. Further, as described below, a resist film 70 is formed on the spacer film 50 on the 2 nd surface F2. Thus, the thickness of the spacer film 50 on the 2 nd surface F2 is increased by the thickness of the resist film 70, and the thickness of the mask material including the spacer film 50 and the resist film 70 is sufficiently increased. Thus, the spacer film 50 does not need to be formed excessively thick in consideration of the function as a mask material, and may be formed relatively thin. By making the thickness of the spacer film 50 thin, the overhang OH of the spacer film 50 becomes small. This can relatively increase the opening diameter Φ 1 of the contact hole CH. As a result, the contact area between the metal electrodes 40 and BM and the conductors 30 and 35 increases, and the contact resistance decreases.

Next, as shown in fig. 10, a resist film 70 is formed as a part of a mask material on the spacer film 50 on the 2 nd surface F2 of the semiconductor substrate 10 by using a photolithography technique. When the resist film 70 is applied to the 2 nd surface F2 of the semiconductor substrate 10, the resist film 70 may or may not enter the contact hole CH. The resist film 70 located on the contact hole CH is removed by exposure and development of the resist film 70, and the other resist film 70 remains. Thus, as shown in fig. 10, the opening OP70 of the resist film 70 is formed to substantially correspond to the opening ophh of the contact hole CH.

However, the center C70 of the opening OP70 of the resist film 70 does not coincide with the center Cch1 of the opening of the contact hole CH. Therefore, as shown in fig. 10, when viewed from above the 2 nd surface F2, the one end E22 of the spacer film 50 is hidden by the resist film 70, and the other end E21 is exposed from the resist film 70. For example, the end E70_1 of the resist film 70 in the D1 direction is retracted in the D1 direction compared to the end E21 of the spacer film 50 in the D1 direction. On the other hand, the end E70_2 of the resist film 70 opposite to the direction D1 protrudes in the direction D1 compared to the end E22 of the spacer film 50 opposite to the direction D1. The protruding amount of the end E21 or the end E70_2 of the resist film 70 is, for example, about 1 μm.

The end E70_1 of the resist film 70 is preferably located between the end E21 of the spacer film 50 and the end E11 of the semiconductor substrate 10 when viewed from above the 2 nd face F2. This can suppress the end E21 of the spacer film 50 from being excessively etched, and can suppress the semiconductor substrate 10 from being electrically shorted to the metal electrode 40 and BM. Further, the end E70_1 is preferably located closer to the end E21 than an intermediate position between the end E21 of the spacer film 50 and the end E11 of the semiconductor substrate 10. This can more reliably suppress an electrical short between the semiconductor substrate 10 and the metal electrodes 40, BM.

In addition, as described above, when the resist film 70 is formed on the spacer film 50 on the 2 nd surface F2, the thickness of the spacer film 50 can be made thin. This can reduce the overhang OH of the spacer film 50. This contributes to enlargement of the contact area of the metal electrodes 40, BM and the electrical conductors 30, 35.

Next, as shown in fig. 11, the spacer film 50 and the STI20 located at the bottom of the contact hole CH are etched by RIE using the resist film 70 and the spacer film 50 as masks. At this time, the end E22 of the spacer film 50 is hidden by the resist film 70 and is therefore not etched. Therefore, the end E22 is held at 90 degrees or more. On the other hand, the end E21 of the spacer film 50 is exposed from the resist film 70 and is thus etched. Thus, the end E21 of the blanking film 50 is chamfered and curved. The end E21 of the spacer film 50 is inclined with respect to both the upper surface F50t1 and the side surface F50s 1.

In addition, at the bottom of the contact hole CH, the spacer film 50 and the STI20 are etched using the resist film 70 or the spacer film 50 shifted in the D1 direction as a mask. Therefore, the center Cch2 of the lower contact hole CH formed in the spacer film 50 and the STI20 is shifted in the direction D1 from the center Cch1 of the upper contact hole CH formed in the semiconductor substrate 10. This offset amount is substantially the same as the offset amount of the center C70 of the opening of the resist film 70 with respect to the center Cch1 of the opening of the contact hole CH. Thus, the center between the 1 st and 2 nd boundary surfaces Fb11 and Fb12 is shifted from the center between the 3 rd and 4 th boundary surfaces Fb13 and Fb14 in the 1 st direction D1.

Next, barrier metal BM, TSV40 and bump 60 are formed as described in embodiment 1. Thereby, the semiconductor chip 1 of embodiment 2 shown in fig. 8 is completed.

According to the manufacturing method of embodiment 2, after the spacer film 50 is formed, the resist film 70 is formed on the 2 nd surface F2. Thus, the thickness of the mask material including the spacer film 50 and the resist film 70 can be sufficiently increased on the 2 nd surface F2, and the thickness of the spacer film 50 can be made thin. By reducing the overhang portion OH by making the thickness of the spacer film 50 thin, the opening diameter φ 1 of the contact hole CH becomes large. This increases the contact area between the metal electrode 40 and BM and the conductors 30 and 35, and reduces the contact resistance. In addition, the inverse tapered shape of the spacer film 50 is relaxed by reducing the overhang portion OH, and therefore, the coverage of the barrier metal BM or the metal material of the TSV40 becomes good.

Embodiment 2 may also be combined with embodiment 1. Thereby, the contact area of the metal electrodes 40, BM and the electric conductors 30, 35 is further increased, and the coverage of the metal material of the barrier metal BM or the TSV40 becomes better.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications are included in the invention described in the claims and the equivalent range thereof as long as they are included in the scope and gist of the invention.

[ description of symbols ]

1 semiconductor chip

10 semiconductor substrate

20 STI

30 pad

35 wiring structure

BM barrier metal

40 TSV

50 compartment film

60 bump