阅读说明：本技术 高效重分布层拓扑结构 (High efficiency redistribution layer topology ) 是由 V·S·斯里德哈兰 C·D·曼纳克 J·刘 于 2021-06-09 设计创作，主要内容包括：本申请题为“高效重分布层拓扑结构”。在一些示例中,芯片级封装(CSP)(106)包括半导体管芯(108)；邻接半导体管芯的钝化层(209)；延伸通过钝化层的通孔(210)；和邻接通孔的第一金属层(218)。CSP还包括邻接第一金属层的绝缘层(216),其中绝缘层具有小于32400平方微米的最大水平面积的孔口(217)。CSP进一步包括邻接绝缘层并适于耦合到焊球(112)的第二金属层(224)。第二金属层在由绝缘层中的孔口限定的接触点处邻接第一金属层。(The application is entitled "efficient redistribution layer topology". In some examples, a Chip Scale Package (CSP) (106) includes a semiconductor die (108); a passivation layer (209) adjacent the semiconductor die; a via (210) extending through the passivation layer; and a first metal layer (218) adjacent to the via. The CSP also includes an insulating layer (216) abutting the first metal layer, where the insulating layer has an aperture (217) with a maximum horizontal area of less than 32400 square microns. The CSP further includes a second metal layer (224) abutting the insulating layer and adapted to be coupled to the solder balls (112). The second metal layer abuts the first metal layer at contact points defined by apertures in the insulating layer.)

1. A Chip Scale Package (CSP), the CSP comprising:

a semiconductor die;

a passivation layer abutting the semiconductor die;

a via extending through the passivation layer;

a first metal layer adjoining the via;

an insulating layer abutting the first metal layer, the insulating layer having an aperture with a maximum horizontal area of less than 32400 square microns; and

a second metal layer abutting the insulating layer and adapted to be coupled to a solder ball, the second metal layer abutting the first metal layer at a contact point defined by the aperture in the insulating layer.

2. The CSP of claim 1, wherein:

the passivation layer has a first passivation layer surface and a second passivation layer surface opposite the first passivation layer surface,

the via has a first via surface and a second via surface opposite the first via surface, an

The first passivation layer surface is substantially flush with the first via surface, and the second passivation layer surface is substantially flush with the second via surface.

3. The CSP of claim 1, wherein said maximum horizontal area is less than 350 square microns.

4. The CSP of claim 1, wherein said maximum horizontal area is less than 80 square microns.

5. The CSP of claim 1, the CSP further comprising:

a second via extending through the passivation layer; and

a third metal layer adjoining the second via,

wherein the insulating layer insulates the third metal layer from the first metal layer.

6. The CSP of claim 5, further comprising a second aperture in the insulating layer, the second aperture defining a second contact point where the third metal layer abuts the second metal layer.

7. The CSP of claim 5, wherein the insulating layer insulates the third metal layer from the second metal layer.

8. The CSP of claim 1, wherein a first vertical plane passes through both the first via and the second metal layer, and wherein a second vertical plane passes through both the second via and the second metal layer.

9. The CSP of claim 1, wherein said aperture has a horizontal cross-sectional shape selected from the group consisting of circular, elliptical, oblong, and polygonal.

10. An electronic device, comprising:

a Printed Circuit Board (PCB);

solder balls coupled to the PCB; and

a Chip Scale Package (CSP) coupled to the solder balls, the CSP comprising:

a semiconductor die;

a passivation layer abutting the semiconductor die;

a first via extending through the passivation layer, the first via having first and second surfaces that are substantially flush with the first and second surfaces of the passivation layer, respectively;

a second via extending through the passivation layer, the second via having first and second surfaces that are substantially flush with the first and second surfaces of the passivation layer, respectively;

a first metal layer abutting the first via;

an insulating layer adjoining the first metal layer and having first and second apertures, each of the first and second apertures having a maximum horizontal area of less than 750 square microns;

a second metal layer adjoining the first metal layer through the first aperture; and

a third metal layer abutting the second via, the second metal layer abutting the third metal layer through the second aperture,

wherein the first and second vias are vertically aligned with the second metal layer.

11. The electronic device of claim 10, wherein the passivation layer has a substantially uniform thickness.

12. The electronic device of claim 10, wherein the passivation layer does not abut the first and second surfaces of the first via, and wherein the passivation layer does not abut the first and second surfaces of the second via.

13. The electronic device of claim 10, wherein the first and second apertures have different shapes and sizes.

14. The electronic device of claim 10, wherein each of the first and second apertures has a maximum horizontal area of 250 square microns or less.

15. A Chip Scale Package (CSP), the CSP comprising:

a semiconductor die;

a passivation layer abutting the semiconductor die;

a first metal layer coupled to the semiconductor die through a first via in the passivation layer;

a second metal layer coupled to the semiconductor die through a second via in the passivation layer;

an insulating layer isolating the first and second metal layers from each other, wherein the insulating layer comprises an aperture having a maximum horizontal area of 350 square microns; and

a third metal layer coupled to the first metal layer through the aperture,

wherein the first via and the second via are vertically aligned with the third metal layer.

16. The CSP of claim 15, wherein the insulating layer isolates the second and third metal layers from one another.

17. The CSP of claim 15, wherein the insulating layer includes a second aperture, wherein the second metal layer and the third metal layer are coupled to each other through the second aperture.

18. The CSP of claim 17, wherein said second aperture has a maximum horizontal area of 250 square microns.

19. The CSP of claim 15, wherein said passivation layer has a substantially uniform thickness.

20. The CSP of claim 15, wherein:

the first via has a first surface coupled to the semiconductor die and a second surface coupled to the first metal layer, the second surface of the first via not abutting the passivation layer; and

the second via has a first surface coupled to the semiconductor die and a second surface coupled to the second metal layer, the second surface of the second via not abutting the passivation layer.

21. The CSP of claim 15, wherein said first metal layer consists of copper or aluminum, and wherein said second metal layer consists of copper or aluminum.

22. The CSP of claim 15, wherein said third metal layer comprises at least one of copper, titanium, tungsten, or nickel.

23. The CSP of claim 15, wherein the first via is comprised of tungsten or copper, and wherein the second via is comprised of tungsten or copper.

24. The CSP of claim 15, wherein said semiconductor die includes a fourth metal layer on a portion of said passivation layer opposite said first metal layer, said fourth metal layer being coupled to said first via, said fourth metal layer consisting of copper or aluminum.

Background

During manufacture, a semiconductor chip (also commonly referred to as a "die") is typically mounted on a die pad of a leadframe and is wire bonded, clamped, or otherwise coupled to the leads of the leadframe. Other devices may be similarly mounted on the leadframe pad. The assembly is later covered with a mold compound (e.g., epoxy) to protect the assembly from potentially damaging heat, physical trauma, moisture, and other deleterious factors. The completed assembly is referred to as a semiconductor package, or more simply, a package. The leads are exposed at a surface of the package and are used to electrically couple the packaged chip to a device external to the chip.

However, the configuration of other types of packages, commonly referred to as flip chip packages, differs from that described above. A flip chip package includes a die, metal bumps (e.g., solder bumps), and a redistribution layer (RDL) that interfaces between the die and the metal bumps in order to properly route signals between the bumps and active circuitry formed on the die. Examples of such flip chip packages include Chip Scale Packages (CSPs), such as Wafer Chip Scale Packages (WCSPs).

Disclosure of Invention

In some examples, a Chip Scale Package (CSP) includes a semiconductor die; a passivation layer adjacent the semiconductor die; a via extending through the passivation layer; and a first metal layer adjoining the via. The CSP also includes an insulating layer abutting the first metal layer, where the insulating layer has an aperture with a maximum horizontal area of less than 32400 square microns. The CSP also includes a second metal layer abutting the insulating layer and adapted to be coupled to the solder balls. The second metal layer abuts the first metal layer at contact points defined by apertures in the insulating layer.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

fig. 1 is a schematic diagram of an electronic device including a Chip Scale Package (CSP) implementing a high efficiency redistribution layer (RDL) topology, according to various examples.

Fig. 2 is a cross-sectional view of a portion of an electronic device including a CSP implementing a high-efficiency RDL topology, according to various examples.

Fig. 3 is a cross-sectional view of a portion of an electronic device including a CSP implementing another efficient RDL topology, according to various examples.

Fig. 4A-4I are schematic layered bottom-up views of different efficient RDL topologies according to various examples.

Fig. 5A-5G are process flow diagrams of techniques for manufacturing CSPs that implement efficient RDL topologies according to various examples.

Fig. 6 is a flow diagram of a method for manufacturing a CSP implementing an efficient RDL topology, according to various examples.

Detailed Description

Various types of redistribution layers (RDLs) are used in Chip Scale Packages (CSPs) to route electrical signals between semiconductor dies of the CSP to solder balls of the CSP. Many RDLs include a passivation layer adjacent the semiconductor die to protect the semiconductor die from external elements and stresses. These passivation layers have apertures that facilitate the transmission of electrical signals between the semiconductor die and the metal layers of the RDL. In some RDLs, the passivation layer (referred to as a non-planar passivation layer) has a non-uniform thickness, particularly adjacent to the aperture, where the passivation layer may include a raised segment. These bump segments may be susceptible to detrimental effects of mechanical stress exerted by the solder balls and the Under Bump Metallization (UBM) coupled to the solder balls. To protect the passivation layer, and particularly the raised segments, from such stresses, the passivation layer raised segments and apertures may be located relatively far from the UBM. In this way, stress from the UBM does not damage the passivation layer. However, this topology is inefficient in its use of space.

Other RDLs eliminate the need to place passivation layer bump segments and apertures away from the UBM by eliminating bump segments. In contrast, such RDLs include a passivation layer having a substantially uniform thickness without raised segments (referred to as a planar passivation layer), and such passivation layer further includes a plurality of vias that facilitate electrical communication between the semiconductor die and the UBM. This topology enables the vias to be placed anywhere, e.g., directly under the UBM, which would not be possible with other types of passivation layers. However, RDLs with this topology still inefficiently use space because they include large capture pads, which are metal layers placed under the UBM coupling the UBM to the vias or other metal layers, and because they include large apertures between the capture pads and the UBM, which limits the flexibility of the RDL topology design. Such capture pads with large apertures result in a large amount of space for each solder bump and UBM that might otherwise be more effectively used for other RDL features, such as metal layers connected to vias, other solder balls, and the like. This inefficient use of space results in an undesirably large CSP.

The present disclosure describes various examples of efficient RDL topologies that address the challenges described above. In particular, the RDL includes a passivation layer abutting the semiconductor die of the CSP and a via extending through the passivation layer. The RDL includes a first metal layer adjacent the via and an insulating layer adjacent the first metal layer. The insulating layer has an aperture with a maximum horizontal dimension of less than 50 microns. The RDL also includes a second metal layer abutting the insulating layer and adapted to be coupled to the solder balls. The second metal layer abuts the first metal layer at contact points defined by apertures in the insulating layer. Because the apertures are relatively small, the size of the capture pads is reduced, and because the size of the capture pads is reduced, the space that would otherwise be occupied by the capture pads can now be used for other RDL features, such as metal layers connected to vias, other solder balls, and the like. This topology has several advantages. For example, efficient use of space can enable CSP size reduction. The improved layout capability of the RDL improves the electromigration performance of the CSP at lower metal levels of the semiconductor die. This topology also has application specific advantages resulting from the efficient use of space. For example, a CSP semiconductor die implementing a Field Effect Transistor (FET) and the RDL topology described herein may experience an on-resistance (R) at drain to source_DS(ON)) And eliminating significant improvements in FET metal layers while achieving comparable or superior performance. Examples of RDL topologies are now described with reference to the figures.

Fig. 1 is a schematic diagram of an electronic device including a Chip Scale Package (CSP) implementing an efficient Redistribution (RDL) topology, according to various examples. In particular, fig. 1 shows an electronic device 100, such as a laptop or notebook computer, a workstation, a smart phone, an automobile, an airplane, a television, or any other suitable electronic device. The electronic device 100 includes a Printed Circuit Board (PCB)102, which may have any of a variety of electronic components coupled thereto, including processors, microcontrollers, memory, passive components, Application Specific Integrated Circuits (ASICs), and the like. The PCB 102 may include conductive terminals 104 (e.g., copper pads or traces) that facilitate coupling to such electronic components. The electronic device 100 includes a CSP 106 coupled to the conductive terminals 104. Although fig. 1 shows one CSP, in an example, the electronic device 100 includes a plurality of CSPs. Fig. 1 shows the content of an electronic device 100 in a sectional view.

The CSP 106 implements an efficient RDL topology according to various examples. In an example, the CSP 106 includes a semiconductor die 108 coupled to an RDL110 having an efficient topology. This specification describes various such efficient RDL topologies, and in the generalized example RDL110 of fig. 1, the RDL110 may implement any such RDL topology or variations thereof. The RDL110 is coupled to solder balls (also referred to as solder bumps) 112. The solder balls 112 are in turn coupled to the conductive terminals 104. In this manner, circuitry formed in and/or on the semiconductor die 108 is configured to communicate with circuitry on the PCB 102 via the solder balls 112 and the RDL110, which interfaces the circuitry of the semiconductor die 108 with the solder balls 112.

The size of the CSP 106 is determined at least in part by the topological efficiency of the RDL 110. Efficient use of space in RDL110 reduces the size of RDL110, and thus CSP 106, assuming that the functionality of CSP 106 remains unchanged. Alternatively, given that the size of the CSP 106 remains the same, efficient use of space in the RDL110 can incorporate additional circuitry in the CSP 106, and thus add functionality.

Fig. 2 is a cross-sectional view of a portion of an electronic device including a CSP implementing a high-efficiency RDL topology, according to various examples. In particular, FIG. 2 shows a detailed view of RDL 110. In an example, the RDL110 includes a passivation layer 209 configured to protect the semiconductor die 108 from the effects of passivationAnd (6) sounding. For example, the passivation layer 209 may be formed of a suitable oxide layer, a suitable nitride layer, or any other suitable type of layer (e.g., SiO)₂、Si₃N₄SiN, SiON). The passivation layer 209 may have any suitable thickness suitable for a given application. The passivation layer 209 may include a plurality of vias that extend through the passivation layer 209 and facilitate the transmission of electrical signals through the passivation layer 209 (e.g., between a lower level metal layer (e.g., copper or aluminum) in the semiconductor die 108 and the rest of the RDL 110). These vias (e.g., vias 210, 212, 214) may be composed of a suitable conductive material, such as a metal (e.g., tungsten, copper) or metal alloy, and may have any suitable shape and size (e.g., horizontal area ranging from 0.0625 square microns to 6400 square microns). In an example, the passivation layer 209 is a planar passivation layer, which means that the thickness of the passivation layer 209 is substantially uniform throughout. As used herein, a substantially uniform thickness is a thickness that does not vary by more than 1 micron from the thickest to the thinnest section. In other words, in some examples, no portion of the passivation layer 209 abuts a top surface (e.g., abuts a surface of the semiconductor die 108) or a bottom surface (e.g., abuts a surface of the metal layers 218, 220, 222) of any of the vias 210, 212, 214. In other words, the top and bottom surfaces of the vias 210, 212, 214 are substantially flush with the top and bottom surfaces of the passivation layer 209, respectively. As used herein, the term substantially flush refers to flush in the range of plus or minus 1 micron. When the passivation layer 209 is planar, it is not susceptible to mechanical stress from the solder balls 112 once the solder balls 112 have been coupled to the PCB 102. None of the regions of the passivation layer 209 are significantly more stressed than any other region of the passivation layer 209. Thus, since the passivation layer 209 is uniform in this sense, the vias 210, 212, 214 may be placed in the passivation layer 209 as desired. This is in contrast to other CSPs in which the passivation layer is non-planar and includes raised sections near or on conductive terminals that couple the metal layer of the RDL to the semiconductor die. In such a CSP, the non-planar regions of the passivation layer are susceptible to the aforementioned mechanical stressesAnd (6) sounding. Thus, the non-planar regions of the passivation layer and thus the conductive terminals co-located with these non-planar regions of the passivation layer are located relatively far from the solder balls.

In an example, RDL110 further includes an insulating layer 216 (e.g., polyimide, polybenzoxazolobenzocyclobutene) abutting portions of passivation layer 209, and also includes metal layers 218, 220, 222 abutting portions of passivation layer 209. RDL110 also includes a metal layer 224 (also referred to as an underbump metallization or UBM), which may include at least one of copper, titanium, tungsten, and/or nickel and may have an area ranging from 2000 square microns to 62000 square microns. The insulating layer 216 and the metal layers 218, 220, 222, 224 are patterned to achieve a topology that establishes the desired connections between the solder balls 112 and the vias 210, 212, 214 coupled to the metal layer 224. In an example, the metal layers 218, 220, 222, 224 facilitate transmission of electrical signals, and as shown, the insulating layer 216 insulates the metal layers 218, 220, 222 from one another. In an example, the metal layer 218 abuts the via 210. In an example, metal layer 220 abuts via 212. In an example, the metal layer 222 abuts the via 214. The metal layer 224 is coupled to the metal layer 218 via the aperture 217. The physical dimensions of the insulating layer 216 and the metal layers 218, 220, 222, including various lengths, widths, and thicknesses, may be varied as appropriate for a given application. In an example, each of the metal layers 218, 220, 222 is composed of copper or aluminum.

The metal layers 218, 224 are coupled to each other at the aperture 217. Thus, the aperture 217 defines a contact point at which the metal layers 218, 224 are coupled to each other. In an example, the aperture 217 has a maximum horizontal dimension of less than 100 microns. In an example, the aperture 217 has a maximum horizontal dimension of less than 75 microns. In an example, the aperture 217 has a maximum horizontal dimension of less than 50 microns. In an example, the aperture 217 has a maximum horizontal dimension of less than 35 microns. In an example, the aperture 217 has a maximum horizontal dimension of less than 20 microns. In an example, the aperture 217 has a maximum horizontal dimension of less than 10 microns. Narrower apertures 217 are generally more efficient at using space in RDL110 because narrower apertures 217 enable other metal layers (e.g., metal layers 220 and 222) to be placed closer to metal layer 218. Another benefit of the narrower aperture 217 is that it enables design flexibility through miniaturization of the metal layer 218. The miniaturization of the metal layer 218 enables the design of flexible geometries for high electrical efficiency of circuits such as field effect transistors. Thus, the RDL110 topology is denser, and therefore more efficient, than if the aperture 217 was wider. In fig. 2, vertical planes 200, 202, 204, 205, 206, 208 illustrate the vertical alignment of the various vias 210, 212, 214 and metal layers 224, indicating that increased density of RDLs 110 is possible due to relatively narrow apertures 217. The narrower the aperture 217, the more efficient the topology of the RDL 110. However, reducing the diameter of the conductor can reduce its current throughput. Thus, narrowing the orifice 217 may restrict current flow through the orifice 217. The current flow may also be limited by electromigration effects at the interface of the metal layer 224 and the solder balls 112, and such effects may limit the current flow more than the size of the aperture 217, meaning that these effects are bottlenecks to the current flow rather than the aperture 217. However, it is possible that the orifice 217 may be narrowed to the extent that the orifice 217 becomes a major restriction (e.g., a bottleneck) to current flow. Thus, in some examples, the particular maximum horizontal size of the orifice 217 may be selected based on the current flow limit imposed by the electromigration effects described above. In other words, the limitations on current flow caused by these effects and/or by the maximum horizontal size of the orifice 217 may be balanced with the improvements in RDL110 density and efficiency achieved with a smaller maximum horizontal size of the orifice 217.

In an example, the maximum horizontal dimension of the aperture 217 is the maximum horizontal dimension in any direction in the horizontal plane. For example, if the aperture 217 has an oblong shape, the maximum horizontal dimension may refer to the length of the oblong shape in the horizontal plane. If the aperture 217 has a rectangular (or polygonal) shape, the maximum horizontal dimension may refer to the length of the rectangle in the horizontal plane. Similarly, if the aperture 217 has a circular shape, the maximum horizontal dimension may refer to the diameter or radius of the circle in the horizontal plane. In an example, the maximum horizontal size of the aperture 217 refers to the total horizontal area of the aperture 217 in the horizontal plane. Thus, for example, if the aperture 217 is circular, the total horizontal area may be determined as the product of π times the square of the radius of the circle. In some such examples, the maximum horizontal area of the aperture 217 is 32400 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 3000 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 1875 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 750 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 350 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 250 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 80 square microns. In some such examples, the maximum horizontal area of the aperture 217 is 20 square microns. In some such examples, the maximum horizontal area of the aperture 217 ranges from 20 square microns to 32400 square microns. Other horizontal areas are contemplated and are included within the scope of the present disclosure.

Determining the size of the maximum horizontal dimension has an impact on RDL110 topology and density. For example, if the aperture 217 is a rectangle of a length different from its width, orienting the rectangle in different directions will result in different possible RDL topologies. For example, orienting the rectangle in a first direction may mean that certain metal layers may be placed near the aperture 217, while orienting the rectangle in a second direction may mean that those same metal layers may not be placed near the aperture 217. Thus, not only the size of the apertures 217, but also their shape and orientation, may affect the topology and density of the RDL110, and are therefore relevant factors to consider when designing the RDL 110.

Other factors may also affect current throughput, such as the number and size of the vias 210, 212, 214 (which may have horizontal cross-sectional dimensions ranging from 0.25 square microns to 4000 square microns in some examples), and the number of metal layers coupled to the solder balls 112 and to the semiconductor die 108. Thus, the maximum horizontal size, shape, and orientation of the apertures 217 are not only a design choice, but have unexpected effects on various aspects of the CSP 106, including the topology and density of the RDLs 110, the current throughput between the solder balls 112 and the semiconductor die 108, the number and size of the vias 210, 212, 214, the connections between the various metal layers, and the like, each of which is a consideration in determining the appropriate maximum horizontal size, shape, and orientation of the apertures 217.

In operation, electrical signals flow between the semiconductor die 108 and the PCB 102 via the conductive terminals 104, the solder balls 112, the metal layer 224, the apertures 217, the metal layer 218, and the vias 210. The metal layers 220, 222 are coupled to other solder balls that are not explicitly shown and may be located remotely from the solder balls 112.

Fig. 3 is a cross-sectional view of a portion of an electronic device including a CSP implementing another efficient RDL topology, according to various examples. The CSP 106 of fig. 3 is virtually identical to the CSP 106 of fig. 2, except that the CSP 106 of fig. 3 includes an aperture 219 through which a metal layer 224 is coupled to a metal layer 222. The aperture 219 is formed by the insulating layer 216, and the aperture 219 defines a contact point where the metal layers 222, 224 abut each other. Because metal layer 224 is coupled to both metal layers 218, 222, a communication path is established between solder ball 112 and vias 210, 214. The description provided above regarding the size of aperture 217 also applies to aperture 219. In an example, the apertures 217, 219 have the same shape but different sizes. In an example, the apertures 217, 219 have different shapes but the same size. In an example, the apertures 217, 219 have different shapes and different sizes. In the example, the apertures 217, 219 have the same shape and the same size.

Fig. 4A-4I are schematic layered bottom-up views of different efficient RDL topologies according to various examples. In particular, fig. 4A is a bottom-up view of the structure of fig. 3, with PCB 102, conductive terminals 104, and solder balls 112 excluded. As shown, metal layer 224 is coupled to metal layers 218, 222 through apertures 217, 219, respectively. Fig. 4A shows metal layer 222 present over metal layer 224, but as in fig. 3, metal layers 222, 224 are not coupled to each other. Fig. 4A shows orifices 217, 219 having an oblong horizontal cross-sectional shape. As described above, the orientation of the ports 217, 219 may affect the topology of the RDL 110. For example, if the apertures 217, 219 are held the same size, but rotated 90 degrees, as shown in fig. 4A, it may no longer be possible to accommodate the metal layer 220 in its current position, and thus some or all aspects (e.g., position, shape, orientation, size) of the metal layers 218, 220, and/or 222 will be adjusted accordingly.

Fig. 4B is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4B shows metal layer 400 coupled to metal layers 406, 410 through apertures 402, 404, respectively. The metal layers 400, 408 are not coupled to each other. As in fig. 4A, the horizontal cross-sectional shape of the apertures 402, 404 is oblong.

Fig. 4C is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4C shows metal layer 412 coupled to metal layers 418, 422 through vias 414, 416, respectively. The metal layers 412, 420 are not coupled to each other. As shown in fig. 4C, the horizontal cross-sectional shape of the apertures 414, 416 is oblong.

Fig. 4D is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4D shows metal layer 424 coupled to metal layer 430 through aperture 426. Metal layer 424 is not coupled to metal layers 428, 432. As shown in fig. 4D, the horizontal cross-sectional shape of the aperture 426 is oblong.

Fig. 4E is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4E shows metal layer 434 coupled to metal layer 440 through aperture 436. Metal layer 434 is not coupled to metal layers 438, 442. As shown in fig. 4E, the horizontal cross-sectional shape of the orifice 436 is oblong.

Fig. 4F is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4F shows the metal layer 444 coupled to the metal layer 450 through the aperture 446. Metal layer 444 is not coupled to metal layers 448, 452, 454, 456, or 458. As shown in fig. 4F, the horizontal cross-sectional shape of the aperture 446 is circular.

Fig. 4G is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4G shows the metal layer 460 coupled to the metal layer 446 through the aperture 462. Metal layer 460 is not coupled to metal layer 464. As shown in fig. 4G, the horizontal cross-sectional shape of the aperture 462 is elliptical.

Fig. 4H is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4H shows metal layer 468 coupled to metal layers 476, 488 through apertures 470, 472, respectively. Metal layer 468 is not coupled to metal layers 474, 478, 480, 482, 484, 486, or 490. As shown in fig. 4H, the horizontal cross-sectional shape of the apertures 470, 472 is circular.

Fig. 4I is a bottom-up view of another example CSP implementing the efficient RDL topology described herein. Fig. 4I shows a metal layer 492 coupled to the metal layers 401, 413 through apertures 494, 496, respectively. Metal layer 492 is not coupled to metal layer 498, 403, 405, 407, 409, 411, or 415. As shown in fig. 4I, the horizontal cross-sectional shape of the apertures 494, 496 is circular.

Fig. 5A-5G are process flow diagrams of techniques for manufacturing CSPs that implement efficient RDL topologies according to various examples. Fig. 6 is a flow diagram of a method 600 for manufacturing CSPs implementing an efficient RDL topology, according to various examples. Thus, the process flow of fig. 5A-5G is now described in parallel with method 600. For example, the process flow and method 600 may be used to form the CSP 106 of FIG. 2.

The method 600 begins by providing a semiconductor die having a passivation layer and a via in the passivation layer (602). Fig. 5A shows the semiconductor die 108 having a passivation layer 209 disposed over the semiconductor die 108. The passivation layer 209 includes vias 210, 212, 214. The vias 210, 212, 214 may be formed, for example, using a photolithographic process to form apertures in the passivation layer 209 that are filled with a suitable seed layer and plated to form the vias 210, 212, 214 (e.g., using copper).

The method 600 includes depositing a seed layer and applying a photoresist layer (also referred to as a resist layer) using a photolithography process (604). Fig. 5B shows the deposition of a seed layer 500 and the application of a resist layer 502. The photolithography process forms a pattern in the resist layer 502.

The method 600 includes electroplating the metal layer and removing the resist layer (606). Fig. 5C shows the electroplated metal layers 218, 220, 222, and the resist layer 502 (fig. 5B) has been removed. Metal layer 218 abuts via 210, metal layer 220 abuts via 212, and metal layer 222 abuts via 214.

The method 600 includes applying an insulating layer using photolithography (608). Fig. 5D shows the insulating layer 216 that has been patterned using a photolithographic process. As shown, the insulating layer 216 abuts the metal layers 218, 220, 222 and the passivation layer 209.

The method 600 includes depositing a seed layer and applying a resist layer using photolithography (610). Fig. 5E shows the deposition of a seed layer 504 and the application of a resist layer 506. The photolithography process forms a pattern in the resist layer 506.

The method 600 includes electroplating the metal layer and removing the resist layer (612). Fig. 5F shows the metal layer 224 formed using an electroplating technique and the resist layer 506 that has been removed (fig. 5E). As shown, the metal layer 224 abuts the metal layer 218 through the aperture 217.

The method 600 includes depositing solder balls (614). Fig. 5G shows solder balls 112 that have been deposited on the metal layer 224. Solder balls 112 may be used to couple the example CSP 106 of FIG. 5G to any suitable electronic device, such as a PCB.

The term "coupled" is used throughout the specification. The term may encompass a connection, communication, or signal path that achieves a functional relationship consistent with the description of the specification. For example, if device a generates a signal to control device B to perform an action, then in a first example, device a is coupled to device B; or in the second example, if the intermediate component C does not substantially change the functional relationship between device a and device B such that device B is controlled by device a via a control signal generated by device a, device a is coupled to device B through intermediate component C. An a-device "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) at the time of manufacture by the manufacturer to perform that function, and/or may be configurable (or reconfigurable) by a user after manufacture to perform that function and/or other additional or alternative functions. The configuration may be through firmware and/or software programming of the device, through construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, circuits or devices described herein as including certain components may instead be adapted to be coupled to those components to form the described circuits or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and/or inductors), and/or one or more sources (e.g., voltage sources and/or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or an Integrated Circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and/or sources to form the described structure, e.g., at the time of manufacture or after manufacture, by an end user and/or a third party. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value refers to +/-10% of the stated value. In the described examples, modifications are possible, and other examples are possible within the scope of the claims.