阅读说明：本技术 集成电路器件及制造集成电路器件的方法 (Integrated circuit device and method of manufacturing an integrated circuit device ) 是由 裵德汉 金盛民 朴柱勋 李留利 郑润永 洪秀妍 于 2021-04-13 设计创作，主要内容包括：集成电路器件可以包括：鳍型有源区,在衬底上在第一水平方向上延伸；栅极线,在所述鳍型有源区上在第二水平方向上延伸；源/漏区,在所述鳍型有源区上并且与所述栅极线相邻；以及源/漏接触图案,连接到所述源/漏区。所述源/漏接触图案可以包括：第一部分和第二部分,所述第一部分具有第一高度,并且所述第二部分具有小于所述第一高度的第二高度。所述源/漏接触图案可以包括：金属插塞,在所述第一部分和所述第二部分中；以及导电阻挡膜,在所述第一部分和所述第二部分中在所述金属插塞的侧壁上。所述第二部分中的导电阻挡膜的第一顶表面低于所述第二部分中的金属插塞的顶表面。(The integrated circuit device may include: a fin-type active region extending in a first horizontal direction on the substrate; a gate line extending in a second horizontal direction on the fin-shaped active region; a source/drain region on the fin active region and adjacent to the gate line; and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include: a first portion and a second portion, the first portion having a first height and the second portion having a second height less than the first height. The source/drain contact pattern may include: a metal plug in the first portion and the second portion; and a conductive barrier film on sidewalls of the metal plugs in the first and second portions. The first top surface of the conductive barrier film in the second portion is lower than the top surface of the metal plug in the second portion.)

1. An integrated circuit device, comprising:

a fin-type active region extending in a first horizontal direction on the substrate;

a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region;

a source/drain region on the fin active region and adjacent to the gate line; and

a source/drain contact pattern electrically connected to the source/drain region and including a first portion having a first height in a vertical direction and a second portion having a second height in the vertical direction smaller than the first height,

wherein the source/drain contact pattern includes a metal plug and a conductive barrier film, the metal plug is in the first portion and the second portion, and the conductive barrier film is on a sidewall of the metal plug in the first portion and the second portion, and a first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion with respect to the substrate.

2. The integrated circuit device of claim 1, wherein a second top surface of the conductive barrier film in the first portion and a top surface of the metal plug in the first portion are equidistant from the substrate.

3. The integrated circuit device of claim 1, further comprising: a buried insulating film on the second portion of the source/drain contact pattern and the gate line,

wherein the buried insulating film includes a buried protrusion on the second portion of the source/drain contact pattern, and the buried protrusion is in contact with the first top surface of the conductive barrier film in the second portion.

4. The integrated circuit device of claim 1, wherein the metal plug in the second portion of the source/drain contact pattern comprises a protruding top at a higher height level than the first top surface of the conductive barrier film, the protruding top comprising a flat top surface.

5. The integrated circuit device of claim 1, wherein the metal plug in the second portion of the source/drain contact pattern comprises a protruding top at a higher height level than the first top surface of the conductive barrier film, the protruding top comprising a rounded corner.

6. The integrated circuit device of claim 1, wherein the metal plug in the second portion of the source/drain contact pattern comprises a protruding top at a higher height level than the first top surface of the conductive barrier film, the protruding top comprising a top surface that protrudes in a direction away from the substrate.

7. The integrated circuit device of claim 1, wherein the metal plugs in the second portion of the source/drain contact pattern comprise protruding tops at a higher height level than the first top surface of the conductive barrier film, the protruding tops comprising a double-hump protrusion that is raised in a direction away from the substrate.

8. An integrated circuit device, comprising:

a plurality of fin-type active regions extending parallel to each other in a first horizontal direction on a substrate;

a gate line extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions;

a source/drain region on the plurality of fin-type active regions and adjacent to the gate line; and

a source/drain contact pattern electrically connected to the source/drain region,

wherein the source/drain contact pattern includes a first portion and a second portion, the first portion having a first height in a vertical direction and the second portion having a second height in the vertical direction that is less than the first height,

the first portion comprises a first portion of a metal plug and a first portion of a conductive barrier film on sidewalls of the first portion of the metal plug, and the second portion comprises a second portion of the metal plug and a second portion of the conductive barrier film on sidewalls of the second portion of the metal plug, and

a first top surface of the first portion of the conductive barrier film and a second top surface of the first portion of the metal plug are coplanar with each other and at a first vertical height level, and a third top surface of the second portion of the conductive barrier film is lower than a fourth top surface of the second portion of the metal plug relative to the substrate.

9. The integrated circuit device of claim 8, further comprising:

a contact insulating spacer surrounding the first and second portions of the source/drain contact pattern;

an insulating cover line extending in the second horizontal direction on the gate line; and

a buried insulating film on the insulating cover line and the contact insulating spacer,

wherein the buried insulating film includes a buried protrusion protruding toward the substrate and in a space defined by the third top surface of the second portion of the conductive barrier film, the sidewall of the second portion of the metal plug, and a sidewall of the contact insulating spacer.

10. The integrated circuit device of claim 8, wherein the second portion of the metal plug comprises a protruding top at a higher height level than the third top surface of the second portion of the conductive barrier film, the protruding top comprising a rounded corner.

11. An integrated circuit device, comprising:

a first fin-type active region and a second fin-type active region both extending parallel to each other in a first horizontal direction on a substrate and spaced apart from each other in a second horizontal direction crossing the first horizontal direction;

a gate line extending longitudinally in the second horizontal direction on the first fin-shaped active region and the second fin-shaped active region;

a source/drain region on the first fin-shaped active region and the second fin-shaped active region; and

a source/drain contact pattern electrically connected to the source/drain region,

wherein the source/drain contact pattern includes a first portion overlapping the first fin-type active region in a vertical direction and having a first height in the vertical direction, and a second portion overlapping the second fin-type active region in the vertical direction and having a second height in the vertical direction that is less than the first height, and

the source/drain contact pattern includes a metal plug and a conductive barrier film, the metal plug including a protruding top in the second portion, and the conductive barrier film in the second portion being on a sidewall of the metal plug in the second portion and including a first top surface lower than a top surface of the protruding top with respect to the substrate.

12. A method of fabricating an integrated circuit device, the method comprising:

forming a fin-type active region extending in a first horizontal direction on a substrate;

forming a source/drain region on the fin-shaped active region; and

forming a source/drain contact pattern electrically connected to the source/drain region, the source/drain contact pattern including a first portion having a first height in a vertical direction and a second portion having a second height in the vertical direction that is less than the first height, the source/drain contact pattern including a metal plug in the first portion and the second portion and a conductive barrier film on a sidewall of the metal plug in the first portion and the second portion, and the conductive barrier film in the second portion including a first top surface that is lower than a top surface of the metal plug in the second portion with respect to the substrate.

13. The method of claim 12, wherein forming the source/drain contact pattern comprises: planarizing a top surface of the first portion, wherein a second top surface of the conductive barrier film in the first portion and a top surface of the metal plug in the first portion are equidistant from the substrate after planarizing the top surface of the first portion.

14. The method of claim 12, wherein forming the source/drain contact pattern comprises:

forming an insulating film on the source/drain region;

forming a source/drain contact hole in the insulating film, the source/drain contact hole exposing the source/drain region;

forming a preliminary source/drain contact in the source/drain contact hole, the preliminary source/drain contact including a preliminary conductive barrier film and a preliminary metal plug;

forming a mask pattern on a portion of the preliminary source/drain contact; and

the second portion of the source/drain contact pattern is then formed by etching the preliminary source/drain contact using the mask pattern as an etch mask.

15. The method of claim 14, wherein forming the source/drain contact pattern further comprises: forming an upper recess exposing sidewalls of the preliminary metal plug of the preliminary source/drain contact by removing a portion of the preliminary conductive barrier film after forming the preliminary source/drain contact and before forming the mask pattern,

wherein the mask pattern overlaps with a first portion of the upper recess portion and does not overlap with a second portion of the upper recess portion, and

wherein forming the second portion comprises: forming a lower recess exposing the sidewall of the metal plug in the second portion by etching the preliminary conductive barrier film using the mask pattern as an etching mask.

16. The method of claim 14, further comprising: forming an upper recess exposing sidewalls of the preliminary metal plug of the preliminary source/drain contact by removing a portion of the preliminary conductive barrier film while the mask pattern is on the portion of the preliminary source/drain contact after forming the mask pattern and before forming the second portion,

wherein forming the second portion comprises: forming a lower recess exposing the sidewall of the metal plug in the second portion by etching the preliminary conductive barrier film using the mask pattern as an etching mask.

17. The method of claim 14, further comprising: forming a lower recess exposing sidewalls of the preliminary metal plug by selectively etching the preliminary conductive barrier film using the mask pattern as an etching mask after forming the second portion.

18. The method of claim 12, wherein forming the source/drain contact pattern comprises:

forming an under-recess exposing a portion of the sidewall of the metal plug and the first top surface of the conductive barrier film in the second portion, wherein after forming the under-recess, the metal plug in the second portion includes a protruding top that protrudes beyond the first top surface of the conductive barrier film.

19. A method of fabricating an integrated circuit device, the method comprising:

forming a fin-type active region extending in a first horizontal direction on a substrate;

forming a source/drain region on the fin-shaped active region;

forming an insulating film on the source/drain region;

forming a source/drain contact hole in the insulating film, the source/drain contact hole exposing the source/drain region; and

forming a source/drain contact pattern in the source/drain contact hole, the source/drain contact pattern including a first portion and a second portion, the first portion having a first height in a vertical direction and the second portion having a second height in the vertical direction that is less than the first height,

wherein forming the source/drain contact pattern comprises:

forming a preliminary source/drain contact in the source/drain contact hole, the preliminary source/drain contact including a preliminary conductive barrier film and a preliminary metal plug;

forming a mask pattern on a portion of the preliminary source/drain contact; and

then forming a metal plug and a conductive barrier film by etching the preliminary conductive barrier film and the preliminary metal plug using the mask pattern as an etching mask, wherein the metal plug is in the first portion and the second portion, and the conductive barrier film covers sidewalls of the metal plug in the first portion and the second portion, and the conductive barrier film in the second portion includes a first top surface lower than a top surface of the metal plug in the second portion with respect to the substrate.

20. A method of fabricating an integrated circuit device, the method comprising:

forming a first fin-type active region and a second fin-type active region, both extending parallel to each other in a first horizontal direction on a substrate and spaced apart from each other in a second horizontal direction crossing the first horizontal direction;

forming a source/drain region on the first fin-shaped active region and the second fin-shaped active region, the source/drain region being electrically connected to the first fin-shaped active region and the second fin-shaped active region;

forming an insulating film on the source/drain region; and

forming a source/drain contact pattern that passes through the insulating film and is connected to the source/drain region, the source/drain contact pattern including a first portion that overlaps the first fin-type active region in a vertical direction and has a first height in the vertical direction, and a second portion that overlaps the second fin-type active region in the vertical direction and has a second height in the vertical direction that is smaller than the first height,

wherein forming the source/drain contact pattern comprises: forming a metal plug and a conductive barrier film, the metal plug comprising a protruding top in the second portion, and the conductive barrier film being on a sidewall of the metal plug in the second portion and comprising a first top surface lower than a top surface of the protruding top with respect to the substrate.

Technical Field

The present inventive concept relates to an integrated circuit device and a method of fabricating the same, and more particularly, to an integrated circuit device including a fin field effect transistor and a method of fabricating the same.

Background

As the size of integrated circuit devices decreases, the accuracy of the operation of the integrated circuit devices and the fast operating speed of the integrated circuit devices become important considerations. Therefore, techniques for reducing the area occupied by the wiring and the contact, reliably ensuring the distance between the wiring and the contact for electrical isolation, and improving reliability have been developed.

Disclosure of Invention

Embodiments of the inventive concept provide an integrated circuit device having a structure that improves reliability of an integrated circuit device having a device area reduced by size reduction.

Embodiments of the inventive concept also provide methods of fabricating integrated circuit devices having structures that improve the reliability of integrated circuit devices having device regions that are reduced by size reduction.

According to some embodiments of the inventive concept, there is provided an integrated circuit device, including: a fin-type active region extending in a first horizontal direction on the substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region; a source/drain region on the fin active region and adjacent to the gate line; and a source/drain contact pattern electrically connected to the source/drain region and including a first portion having a first height in a vertical direction and a second portion having a second height in the vertical direction smaller than the first height, wherein the source/drain contact pattern includes a metal plug and a conductive barrier film, the metal plug being in the first portion and the second portion, and the conductive barrier film being on a sidewall of the metal plug in the first portion and the second portion and a first top surface of the conductive barrier film in the second portion being lower than a top surface of the metal plug in the second portion with respect to the substrate.

According to some embodiments of the inventive concept, there is provided an integrated circuit device, including: a plurality of fin-type active regions extending parallel to each other in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions; a source/drain region on the plurality of fin-type active regions and adjacent to the gate line; and a source/drain contact pattern electrically connected to the source/drain region, wherein the source/drain contact pattern includes a first portion having a first height in a vertical direction and a second portion having a second height in the vertical direction smaller than the first height; the first portion comprises a first portion of a metal plug and a first portion of a conductive barrier film on sidewalls of the first portion of the metal plug, and the second portion comprises a second portion of the metal plug and a second portion of the conductive barrier film on sidewalls of the second portion of the metal plug; a first top surface of the first portion of the conductive barrier film and a second top surface of the first portion of the metal plug are coplanar with each other and at a first vertical height level; and a third top surface of the second portion of the conductive barrier film is lower than a fourth top surface of the second portion of the metal plug with respect to the substrate.

According to some embodiments of the inventive concept, there is provided an integrated circuit device, including: a first fin-type active region and a second fin-type active region both extending parallel to each other in a first horizontal direction on a substrate and spaced apart from each other in a second horizontal direction crossing the first horizontal direction; a gate line extending longitudinally in the second horizontal direction on the first fin-shaped active region and the second fin-shaped active region; a source/drain region on the first fin-shaped active region and the second fin-shaped active region; and a source/drain contact pattern electrically connected to the source/drain region, wherein the source/drain contact pattern includes a first portion overlapping the first fin-type active region in a vertical direction and having a first height in the vertical direction, and a second portion overlapping the second fin-type active region in the vertical direction and having a second height in the vertical direction smaller than the first height; and the source/drain contact pattern comprises a metal plug and a conductive barrier film, the metal plug comprising a protruding top in the second portion, and the conductive barrier film in the second portion being on a sidewall of the metal plug in the second portion and comprising a first top surface lower than a top surface of the protruding top with respect to the substrate.

According to some embodiments of the inventive concept, a method of manufacturing an integrated circuit device is provided. In the method, a fin-type active region extending in a first horizontal direction on a substrate is formed. And forming a source/drain region on the fin-shaped active region. Forming a source/drain contact pattern electrically connected to the source/drain region. The source/drain contact pattern includes a first portion having a first height in a vertical direction and a second portion having a second height in the vertical direction smaller than the first height. The source/drain contact pattern includes a metal plug and a conductive barrier film, the metal plug is in the first portion and the second portion, and the conductive barrier film is on a sidewall of the metal plug in the first portion and the second portion, and the conductive barrier film in the second portion includes a first top surface lower than a top surface of the metal plug in the second portion with respect to the substrate.

According to some embodiments of the inventive concept, a method of manufacturing an integrated circuit device is provided. In the method, a fin-type active region extending in a first horizontal direction on a substrate is formed. And forming a source/drain region on the fin-shaped active region. An insulating film is formed on the source/drain regions. Forming source/drain contact holes in the insulating film to expose the source/drain regions. Forming a source/drain contact pattern in the source/drain contact hole to include a first portion and a second portion, the first portion having a first height in a vertical direction, and the second portion having a second height in the vertical direction that is less than the first height. Forming the source/drain contact pattern includes: forming a preliminary source/drain contact in the source/drain contact hole, the preliminary source/drain contact including a preliminary conductive barrier film and a preliminary metal plug; forming a mask pattern on a portion of the preliminary source/drain contact; and forming a metal plug and a conductive barrier film by etching the preliminary conductive barrier film and the preliminary metal plug using the mask pattern as an etching mask. The metal plugs are in the first and second portions, and the conductive barrier film covers sidewalls of the metal plugs in the first and second portions, and the conductive barrier film in the second portion includes a first top surface that is lower than top surfaces of the metal plugs in the second portion relative to the substrate.

According to some embodiments of the inventive concept, methods of fabricating an integrated circuit device are provided. In the method, a first fin-type active region and a second fin-type active region are formed on a substrate to extend parallel to each other in a first horizontal direction and to be spaced apart from each other in a second horizontal direction crossing the first horizontal direction. Forming a source/drain region on the first fin-shaped active region and the second fin-shaped active region to be electrically connected to the first fin-shaped active region and the second fin-shaped active region. An insulating film is formed on the source/drain regions. Forming a source/drain contact pattern to pass through the insulating film and electrically connected to the source/drain region. The source/drain contact pattern includes a first portion overlapping the first fin-type active region in a vertical direction and having a first height in the vertical direction, and a second portion overlapping the second fin-type active region in the vertical direction and having a second height in the vertical direction that is less than the first height. Forming the source/drain contact pattern includes: forming a metal plug and a conductive barrier film, the metal plug comprising a protruding top in the second portion, and the conductive barrier film being on a sidewall of the metal plug in the second portion and comprising a first top surface that is lower than an uppermost surface of the protruding top with respect to the substrate.

Drawings

Example embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a layout of an integrated circuit device according to some embodiments of the inventive concept;

FIG. 2A shows a cross-sectional view taken along lines X1-X1 'and X2-X2' in FIG. 1; FIG. 2B is a cross-sectional view taken along line Y1-Y1' of FIG. 1;

fig. 3A and 3B are enlarged sectional views of a portion corresponding to a region C1 in fig. 1, wherein fig. 3A is an enlarged sectional view of a region C2A in fig. 2A, and fig. 3B is an enlarged sectional view of a region C2B in fig. 2B;

fig. 4A and 4B are cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept;

fig. 5A and 5B are cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept;

fig. 6A and 6B are cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept;

fig. 7A and 7B are cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept;

fig. 8A is a layout of an integrated circuit device according to some embodiments of the inventive concept; FIG. 8B is a cross-sectional view taken along line X8-X8' of FIG. 8A;

fig. 9 is a cross-sectional view of an integrated circuit device according to some embodiments of the inventive concept;

fig. 10A is a layout of an integrated circuit device according to some embodiments of the inventive concept; FIG. 10B is a cross-sectional view taken along line X9-X9' in FIG. 10A; FIG. 10C is a cross-sectional view taken along line Y9-Y9' in FIG. 10A;

fig. 11A to 22B are cross-sectional views illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept, in which fig. 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A illustrate portions corresponding to cross-sections taken along lines X1-X1 ' and X2-X2 ' in fig. 1, respectively, and fig. 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate portions corresponding to cross-sections taken along lines Y1-Y1 ' in fig. 1, respectively;

fig. 23A to 23D are cross-sectional views illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept;

fig. 24A and 24B are cross-sectional views illustrating methods of fabricating integrated circuit devices according to some embodiments of the inventive concept; and

fig. 25A to 31 are sectional views illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept, in which fig. 25A, 26A, 27A, 28A, 29A, 30A, and 31 illustrate portions corresponding to a section taken along line X9-X9 'in fig. 10A, and fig. 25B, 26B, 27B, 28B, 29B, and 30B illustrate portions corresponding to a section taken along line Y9-Y9' in fig. 10A.

Detailed Description

Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals and characters denote like elements, and redundant description thereof may be omitted.

Fig. 1 is a layout of an integrated circuit device 100 according to some embodiments of the inventive concept. Fig. 2A shows a sectional view taken along line X1-X1 ' and line X2-X2 ' in fig. 1, and fig. 2B is a sectional view taken along line Y1-Y1 ' in fig. 1. Fig. 3A and 3B are enlarged sectional views of a portion corresponding to a region C1 in fig. 1, in which fig. 3A is an enlarged sectional view of a region C2A in fig. 2A, and fig. 3B is an enlarged sectional view of a region C2B in fig. 2B.

Referring to fig. 1 to 3B, the integrated circuit device 100 includes a logic cell LC formed in an area defined by a cell boundary BN on a substrate 110. The logic unit LC may include a fin field effect transistor (FinFET).

The substrate 110 has a main surface 110M extending in a horizontal direction (for example, XY plane direction). The substrate 110 may include a semiconductor material such as Si or Ge, or a compound semiconductor material such as SiGe, SiC, GaAs, InAs, or InP. The substrate 110 may include conductive regions, such as doped wells or doped structures.

Logic cell LC includes first device region RX1 and second device region RX 2. A plurality of fin-type active regions FA protruding from the substrate 110 may be formed in each of the first and second device regions RX1 and RX 2. The device isolation region DTA may be between the first device region RX1 and the second device region RX 2.

The fin-type active regions FA may extend parallel to each other in a width direction (i.e., a first horizontal direction (e.g., X direction)) of the logic cells LC. As shown in fig. 2B, an isolation film 112 may be formed in the substrate 110 between the fin-type active regions FA, and an isolation insulating film 114 may be formed in the substrate 110 in the device isolation region DTA. Each of the isolation film 112 and the isolation insulating film 114 may include, for example, an oxide film. The fin-type active region FA may protrude from the isolation film 112 to have a fin shape in the first and second device regions RX1 and RX 2.

A plurality of gate insulating films 132 and a plurality of gate lines GL are formed on the substrate 110 to extend in a height direction (i.e., a second horizontal direction (e.g., Y direction)) of the logic cells LC so as to cross the fin-type active region FA. The gate insulating film 132 and the gate line GL may cover a top surface and both sidewalls of each of the fin-type active regions FA, a top surface of the isolation film 112, and a top surface of the isolation insulating film 114. As used herein, "element a covers the surface of element B" (or similar language) may mean that element a is on and overlaps the surface of element B, but does not necessarily mean that element a completely covers the surface of element B.

A plurality of Metal Oxide Semiconductor (MOS) transistors may be formed along the gate line GL in the first and second device regions RX1 and RX 2. Each of the MOS transistors may have a three-dimensional (3D) structure in which a channel is formed on a top surface and both sidewalls of each of the fin-type active regions FA.

The dummy gate line DGL may extend along the cell boundary BN in the second horizontal direction (Y direction). The dummy gate line DGL may include the same material as the gate line GL, but may function as an electrical isolation region between the logic cell LC and another adjacent logic cell by remaining in an electrically floating state during operation of the integrated circuit device 100. The gate line GL and the plurality of dummy gate lines DGL may have the same width in the first horizontal direction (X direction) and may be arranged at a certain pitch in the first horizontal direction (X direction).

The gate insulating film 132 may include, for example, a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material having a higher dielectric constant than the silicon oxide film. The high-k dielectric film may include, for example, a metal oxide or a metal oxynitride. An interface film (not shown) may be between the fin-type active region FA and the gate insulating film 132. The interface film may include, for example, an oxide film, a nitride film, or an oxynitride film.

The gate line GL and the dummy gate line DGL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap filling metal film are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap filling metal film may include a W film or an Al film. The gate line GL and the dummy gate line DGL may include a work function metal layer. The work function metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, the gate line GL and the dummy gate line DGL may include a stack structure of TiAl C/TiN/W, TiN/TaN/TiAl C/TiN/W or TiN/TaN/TiN/TiAl C/TiN/W, but are not limited thereto.

The plurality of insulating spacers 120 may cover both sidewalls of the gate line GL and both sidewalls of the dummy gate line DGL. Each of the insulating spacers 120 may have a line shape extending in the length direction (Y direction) of the logic cell LC. The insulating spacer 120 may include, for example, a silicon nitride film, a SiOCN film, a SiCN film, or a combination thereof, but is not limited thereto.

A top surface of each of the gate line GL, the gate insulating film 132, the insulating spacer 120, and the dummy gate line DGL may be covered with an insulating cover line 140. The plurality of insulating cover lines 140 may include, for example, a silicon nitride film.

A plurality of recess regions RR may be respectively formed in the top surface of the fin-type active region FA at the side of each of the gate lines GL, and a plurality of source/drain regions SD may be respectively formed in the recess regions RR. Each of the source/drain regions SD may be between adjacent gate lines GL. The gate line GL may be separated from the source/drain region SD with the gate insulating film 132 and the insulating spacer 120 therebetween. The plurality of source/drain regions SD may include, for example, a semiconductor epitaxial layer epitaxially grown on the plurality of recess regions RR in the fin-type active region FA, or a combination of semiconductor epitaxial layers. The source/drain regions SD may include, for example, an epitaxially grown Si layer, an epitaxially grown SiC layer, or an epitaxially grown SiGe layer. The inter-gate insulating film 128 may include, for example, a silicon oxide film. In example embodiments, the source/drain regions SD may be covered with an insulating liner (not shown). The insulating liner may conformally cover the surface of each of the source/drain regions SD. The insulating liner may comprise, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO₂Or a combination thereof.

In example embodiments, the first device region RX1 may correspond to an N-channel mos (nmos) transistor region, and the second device region RX2 may correspond to a P-channel mos (pmos) transistor region. In this case, the plurality of source/drain regions SD in the first device region RX1 may include an epitaxially grown Si layer or an epitaxially grown SiC layer, and the plurality of source/drain regions SD in the second device region RX2 may include a plurality of epitaxially grown SiGe layers. As shown in fig. 2B, the source/drain regions SD in the first device region RX1 may have different shapes and sizes than the source/drain regions SD in the second device region RX 2. However, the embodiment is not limited thereto, and the plurality of source/drain regions SD in the first and second device regions RX1 and RX2 may have different shapes and sizes.

A plurality of source/drain contact patterns CAP may be formed on the source/drain regions SD. The source/drain regions SD may be connected to conductive lines (not shown) above the source/drain regions SD through source/drain contact patterns CAP. The source/drain contact pattern CAP may include a conductive barrier film 154 and a metal plug 156. The conductive barrier film 154 may cover sidewalls and a bottom surface of the metal plug 156. The metal silicide film 152 may be formed between the source/drain region SD and the source/drain contact pattern CAP. As used herein, "element a is connected to element B" (or similar language) may mean that element a is electrically connected to element B or that element a physically contacts element B.

In example embodiments, the metal silicide film 152 may include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 152 may include titanium silicide. The conductive barrier film 154 may include, for example, Ti, Ta, TiN, TaN, or a combination thereof, and the metal plug 156 may include, for example, W, Co, Cu, Ru, Mn, or a combination thereof.

Sidewalls of each of the source/drain contact patterns CAP may be covered with contact insulating spacers 150. In example embodiments, the contact insulation spacer 150 may include, for example, SiCN, SiCON, silicon nitride (SiN), or a combination thereof, but is not limited thereto.

The source/drain contact pattern CAP may have different heights according to its position. Each of the source/drain contact patterns CAP may include a first portion S1 and a second portion S2, the first portion S1 and the second portion S2 respectively having different heights in the vertical direction (Z direction), and being integrally connected to each other. As used herein, the term "portion" may be interchangeable with the term "portion".

As shown in fig. 3B, the first portion S1 of the source/drain contact pattern CAP above the fin-type active area FA may have a first height H1 in the vertical direction (Z direction), and the second portion S2 of the source/drain contact pattern CAP may have a second height H2 in the vertical direction (Z direction), the second height H2 being less than the first height H1.

In each of the source/drain contact patterns CAP, the conductive barrier film 154 and the metal plug 156 may extend on the first and second portions S1 and S2 to be included in the first and second portions S1 and S2.

In the first portion S1 of each source/drain contact pattern CAP, the top surface of the conductive barrier film 154 may be coplanar with the top surface of the metal plug 156 at a vertical height level LV 1. In the present specification, the term "height level" refers to a distance from the main surface 110M of the substrate 110 in the vertical direction (Z direction).

In the second portion S2 of each of the source/drain contact patterns CAP, the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 is lower than the vertical height level LV3 of the uppermost surface of the metal plug 156. A height difference DH1 between a vertical height level LV3 of an uppermost surface of the metal plug 156 in the second portion S2 and a vertical height level LV2 of an uppermost surface of the conductive barrier film 154 may be about 1nm to about 5nm, for example, about 2nm to about 3 nm. As used herein, "the vertical height level X of surface a is lower than the vertical height level Y of surface B" (or similar expressions) may mean that surface a is lower than surface B in the vertical direction relative to the substrate, and thus the substrate is closer to surface a in the vertical direction than surface B.

In the vertical direction (Z direction), the vertical height level LV1 of the uppermost surface of the first portion S1 may be higher than that of the gate line GL, and the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 in the second portion S2 and the vertical height level LV3 of the uppermost surface of the metal plug 156 in the second portion S2 may be lower than that of the uppermost surface of the gate line GL. In other words, in the vertical direction (Z direction), a distance from the main surface 110M of the substrate 110 to an uppermost surface of each of the first portions S1 may be greater than a distance from the main surface 110M of the substrate 110 to an uppermost surface of each of the gate lines GL, and in the vertical direction (Z direction), a distance from the main surface 110M of the substrate 110 to an uppermost surface of the second portion S2 may be smaller than a distance from the main surface 110M of the substrate 110 to an uppermost surface of each of the gate lines GL. However, the embodiments are not limited thereto. For example, an uppermost surface of each of the first and second portions S1 and S2 may be higher than an uppermost surface of each of the gate lines GL. As used herein, "the vertical height level X of surface a is higher than the vertical height level Y of surface B" (or similar expressions) may mean that surface a is higher than surface B in the vertical direction relative to the substrate, and thus the substrate is closer to surface B in the vertical direction than surface a.

In the second portion S2 of each source/drain contact pattern CAP, the metal plug 156 may include a protruding top 156P at a height level higher than the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 in the second portion S2. In the second portion S2 of each source/drain contact pattern CAP, the sidewalls of the protruding top 156P of the metal plug 156 may not be covered with the conductive barrier film 154. The protruding top 156P may protrude beyond the uppermost surface of the conductive barrier film 154 in the second portion S2, as shown in fig. 3A and 3B.

Protruding top 156P may have a flat top surface (e.g., a substantially planar top surface). In an example embodiment, an uppermost surface of the protruding top 156P may extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. However, the embodiment is not limited thereto, and various changes may be made to the shape of the protruding top 156P. Specific examples of various shapes of the protruding top 156P will be described below with reference to fig. 5A to 7B.

The insulating covered wire 140 may have different thicknesses at different positions. For example, as shown in fig. 2A, a portion of the insulated covered wire 140 between two adjacent first portions S1 may be relatively thick, and a portion of the insulated covered wire 140 between two adjacent second portions S2 may be relatively thin. A portion of the insulating cover line 140 between the first portion S1 of one source/drain contact pattern CAP and the second portion S2 of the other source/drain contact pattern CAP may have a thickness that may vary in the first horizontal direction (X direction) and decrease from the first portion S1 toward the second portion S2.

The integrated circuit device 100 may include a buried insulating film 170 and an insulating structure 180, the buried insulating film 170 covering the second portion S2 of each of the plurality of source/drain contact patterns CAP, the gate line GL and the plurality of insulating cover lines 140, and the insulating structure 180 covering a top surface of the buried insulating film 170.

The buried insulating film 170 may be in contact with a top surface of each of the plurality of second portions S2 and a top surface of each of the insulating cover lines 140. The buried insulating film 170 may include a main buried part 170M and a buried protrusion 170P. The main buried part 170M covers the top surface of the metal plug 156 included in each of the second portions S2, a portion of the plurality of contact insulation spacers 150 adjacent to the second portion S2, and the insulation cover line 140. The buried protrusion 170P protrudes from the main buried portion 170M toward the substrate 110. The buried protrusion 170P may be on the second portion S2 of each of the source/drain contact patterns CAP to contact the top surface of the conductive barrier film 154. The buried protrusion 170P may also be in contact with the sidewall of the protruding top 156P of the metal plug 156 and the sidewall of the contact insulation spacer 150. The buried protrusion 170P may fill a space (e.g., an inner space of the lower recess LR shown in fig. 19A and 19B) defined by the uppermost surface of the conductive barrier film 154, sidewalls of the protruding top 156P of the metal plug 156, and sidewalls of the contact insulating spacers 150.

The buried insulating film 170 may have a planarized top surface. The buried insulating film 170 may include a portion filling a space above the second portion S2 of each of the source/drain contact patterns CAP between the gate lines GL. The top surface of the buried insulating film 170 may be coplanar with the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156, the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156 being included in the first portion S1 of each of the source/drain contact patterns CAP, and may be substantially at the vertical height level LV 1. The buried insulating film 170 may include, for example, a silicon oxide film, SiOC, SiOCN, SiON, SiCN, SiN, or a combination thereof, but is not limited thereto.

The insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184, the etch stop film 182 and the interlayer insulating film 184 being sequentially stacked on the buried insulating film 170. The bottom surface of the etch stop film 182 may be in contact with the uppermost surface of the buried insulating film 170. The etch stop film 182 may include, for example, silicon carbide (SiC), SiN, silicon carbide doped with nitrogen (SiC: N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may include, for example, an oxide film, a nitride film, an ultra low K (ulk) film having an ultra low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a High Density Plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a Flowable Chemical Vapor Deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof.

A plurality of via contacts CAV may be respectively formed on the source/drain contact patterns CAP. Each of the via contacts CAV may pass through the insulating structure 180 and contact the top surface of the first portion S1 of the source/drain contact pattern CAP.

A plurality of gate contacts CB may be respectively formed on the gate lines GL. Each of the gate contacts CB may pass through the insulating structure 180, the buried insulating film 170, and the insulating cover line 140, and may be connected to the gate line GL. Each gate contact CB may pass through a relatively thin portion of the insulating cover line 140 and contact the top surface of the gate line GL.

Each of some gate contacts CB may contact the gate line GL at a position adjacent to the second portion S2 of the source/drain contact pattern CAP. In this case, as shown in fig. 2A and 3A, the buried protrusion 170P of the buried insulating film 170 may be between the gate line GL and the second portion S2 of the source/drain contact pattern CAP, which are adjacent to each other in the first horizontal direction (X direction), and the gate line GL and the second portion S2 of the source/drain contact pattern CAP. In other words, the gate contact CB and the second portion S2 of the source/drain contact pattern CAP may be separated from each other in the first horizontal direction (X direction) with the buried protrusion 170P of the buried insulating film 170 between the gate contact CB and the second portion S2 of the source/drain contact pattern CAP. Accordingly, a spaced distance from the conductive barrier film 154 and the metal plug 156 forming the second portion S2 to the gate line GL may be ensured by at least the buried protrusion 170P. Accordingly, even when the gate contact CB and the second portion S2 of the source/drain contact pattern CAP are formed to be adjacent to each other, an insulation margin between the gate contact CB and the source/drain contact pattern CAP can be secured, thereby reducing or preventing an undesired short circuit between the gate contact CB and the source/drain contact pattern CAP.

Each of the via contact CAV and the gate contact CB may include a buried metal film and a conductive barrier film surrounding the buried metal film. The buried metal film may include, for example, Co, Cu, W, Ru, Mn, or a combination thereof, and the conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or a combination thereof. Sidewalls of each of the via contact CAV and the gate contact CB may be covered with an insulating liner (not shown). The insulating liner layer may include, for example, a silicon nitride film, but is not limited thereto. As used herein, "element a surrounds element B" (or similar language) may mean that element a is on and partially surrounds element B, but does not necessarily mean that element a completely surrounds the surface of element B.

In the logic cell LC, the ground line VSS may be connected to the fin-type active regions FA in the first device region RX1 through some of the source/drain contact patterns CAP, and the power supply line VDD may be connected to the fin-type active regions FA in the second device region RX2 through some of the source/drain contact patterns CAP. The ground line VSS and the power line VDD may be formed at a height level higher than a top surface of each of the source/drain contact pattern CAP and the gate contact CB. Each of the ground line VSS and the power line VDD may include a conductive barrier film and a wiring conductive layer. The conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or a combination thereof. The wiring conductive layer may include, for example, Co, Cu, W, alloys thereof, or combinations thereof.

Fig. 4A and 4B are cross-sectional views of an integrated circuit device 200 according to some embodiments of the inventive concept. Fig. 4A shows a cross-sectional view of the integrated circuit device 200 taken along lines X1-X1 ' and X2-X2 ' in fig. 1, and fig. 4B shows a cross-sectional view of the integrated circuit device 200 taken along lines Y1-Y1 ' in fig. 1.

Referring to fig. 4A and 4B, the integrated circuit device 200 may be substantially the same as or similar to the integrated circuit device 100 described with reference to fig. 1-3B. However, the integrated circuit device 200 includes a plurality of conductive lines ML extending in a direction crossing the plurality of gate lines GL on the via contact portions CAV.

Some of the conductive lines ML may be connected to the source/drain regions SD through via contacts CAV and source/drain contact patterns CAP. Although not shown, the other ones of the conductive lines ML may be connected to the gate lines GL through gate contacts CB.

The conductive line ML may be formed on the substrate 110 at the same height level as the ground line VSS and the power supply line VDD. The conductive line ML may include a plurality of unidirectional wiring layers extending parallel to each other in the first horizontal direction (X direction). Each of the conductive lines ML may include a conductive barrier film and a wiring conductive layer. The conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or a combination thereof. The wiring conductive layer may include, for example, Co, Cu, W, alloys thereof, or combinations thereof.

Fig. 5A and 5B are cross-sectional views of an integrated circuit device 300 according to some embodiments of the inventive concept. Specifically, fig. 5A is an enlarged cross-sectional view of region C1 in fig. 1 taken along line X1-X1 'in fig. 1, and fig. 5B is an enlarged cross-sectional view of region C1 in fig. 1 taken along line Y1-Y1' in fig. 1.

Referring to fig. 5A and 5B, the integrated circuit device 300 may be substantially the same as or similar to the integrated circuit device 100 described with reference to fig. 1-3B. However, the source/drain contact pattern CAP of the integrated circuit device 300 includes the metal plug 356 instead of the metal plug 156. The metal plug 356 may include a protruding top 356P, the protruding top 356P being at a higher height level than the conductive barrier film 154 in the second portion S2 of the source/drain contact pattern CAP. The protruding top 356P may have a rounded corner 356C in its outer edge. The top surface portion 356T substantially in the middle of the protruding top portion 356P in the first horizontal direction (X direction) may extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. The specific configuration of the metal plug 356 is substantially the same as or similar to the specific configuration of the metal plug 156 of the integrated circuit device 100 described with reference to fig. 1-3B.

Fig. 6A and 6B are cross-sectional views of an integrated circuit device 400 according to some embodiments of the inventive concept. Specifically, fig. 6A is an enlarged cross-sectional view of region C1 in fig. 1 taken along line X1-X1 'in fig. 1, and fig. 6B is an enlarged cross-sectional view of region C1 in fig. 1 taken along line Y1-Y1' in fig. 1.

Referring to fig. 6A and 6B, the integrated circuit device 400 may be substantially the same as or similar to the integrated circuit device 100 described with reference to fig. 1-3B. However, the source/drain contact pattern CAP of the integrated circuit device 400 includes the metal plug 456 instead of the metal plug 156. The metal plugs 456 may include protruding tops 456P at a height level higher than the conductive barrier film 154 in the second portion S2 of the source/drain contact pattern CAP. The protruding top 456P may have a top surface portion 456T, the top surface portion 456T being convex in a direction away from the substrate 110. In the first horizontal direction (X direction), the top surface portion 456T of the protruding top 456P may not extend flat but extend in a curved shape. In the second horizontal direction (Y direction), the protruding top 456P may have a rounded corner 456C in an outer edge thereof. The specific configuration of metal plugs 456 may be substantially the same as or similar to the specific configuration of metal plugs 156 of integrated circuit device 100 described with reference to fig. 1-3B.

Fig. 7A and 7B are cross-sectional views of an integrated circuit device 500 according to some embodiments of the inventive concept. Specifically, fig. 7A is an enlarged cross-sectional view of region C1 in fig. 1 taken along line X1-X1 'in fig. 1, and fig. 7B is an enlarged cross-sectional view of region C1 in fig. 1 taken along line Y1-Y1' in fig. 1.

Referring to fig. 7A and 7B, the integrated circuit device 500 may be substantially the same as or similar to the integrated circuit device 100 described with reference to fig. 1-3B. However, the source/drain contact pattern CAP of the integrated circuit device 500 includes the metal plug 556 instead of the metal plug 156. The metal plugs 556 may include protruding tops 556P, the protruding tops 556P being at a higher height level than the conductive barrier film 154 in the second portion S2 of the source/drain contact pattern CAP. The protrusion top 556P may have a double peak protrusion that is convex in a direction away from the substrate 110.

Specifically, the protrusion top 556P may include a double peak protrusion including a first peak T1 and a second peak T2, the first peak T1 and the second peak T2 being convex in a direction away from the substrate 110. The recess 556D may be between the first peak T1 and the second peak T2. The opposite sidewalls of the first peak T1 of the protrusion top 556P may be symmetrical or asymmetrical with respect to the first apex P1. The opposite sidewalls of the second peak T2 may be symmetrical or asymmetrical with respect to the second vertex P2. In the vertical direction (Z direction), the height level of the first apex P1 may be equal to or similar to the height level of the second apex P2. In some embodiments, the first apex P1 and the second apex P2 may be equidistant from the substrate 110.

The protrusion top 556P may have a rounded corner 556C in an outer edge in the second horizontal direction (Y direction). The recess 556D of the protrusion top 556P may extend substantially flat in the second horizontal direction (Y direction). The specific configuration of the metal plug 556 is substantially the same as the specific configuration of the metal plug 156 of the integrated circuit device 100 described with reference to fig. 1-3B.

In the integrated circuit devices 300, 400, and 500 shown in fig. 5A through 7B, the metal plugs 356, 456, and 556 of the second portion S2 of the source/drain contact pattern CAP may include protruding tops 356P, 456P, and 556P, respectively, at a higher height level than the conductive barrier film 154 in the second portion S2, and each of the protruding tops 356P, 456P, and 556P may include rounded corners 356C, 456C, or 556C in an outer edge thereof and include a top surface portion, which may be flat (e.g., substantially planar) (e.g., top surface portion 356T), may be convex (e.g., top surface portion 456T), or may include a double peak protrusion (e.g., top surface portion of protruding top 556P) including the first peak T1 and the second peak T2. Therefore, even when each of some gate contacts CB is disposed adjacent to the second portion S2 of the source/drain contact pattern CAP, the spaced distance in the first horizontal direction (X direction) between the second portion S2 of the source/drain contact pattern CAP and the adjacent gate contact CB can be sufficiently ensured. Accordingly, even when the gate contact CB and the second portion S2 of the source/drain contact pattern CAP are arranged adjacent to each other, an insulation margin between the gate contact CB and the source/drain contact pattern CAP may be more easily ensured, thereby reducing or preventing an undesired short circuit between the gate contact CB and the source/drain contact pattern CAP.

Fig. 8A and 8B are diagrams of an integrated circuit device 600 according to some embodiments of the inventive concept, where fig. 8A is a layout of the integrated circuit device 600 and fig. 8B is a cross-sectional view taken along line X8-X8' in fig. 8A. In fig. 1 to 3B and fig. 8A and 8B, like reference numerals denote like elements, and detailed description thereof may be omitted. The integrated circuit device 600 shown in fig. 8A and 8B may include an SRAM array comprising a plurality of SRAM cells arranged in a matrix on the substrate 110.

Referring to fig. 8A and 8B, the integrated circuit device 600 includes a plurality of fin-type active areas FA and a plurality of gate lines GL, wherein the plurality of fin-type active areas FA extend parallel to each other in a first horizontal direction (X direction), and the plurality of gate lines GL extend parallel to each other in a second horizontal direction (Y direction) on the fin-type active areas FA. The transistors may be formed at respective intersections between the fin-type active area FA and the gate lines GL. The integrated circuit device 600 may include a plurality of shared contacts SC each connected to the gate line GL and the source/drain region SD.

In the integrated circuit device 600, each of the source/drain contact patterns CAP may include a conductive barrier film 154 and a metal plug 156. Each of the source/drain contact patterns CAP may include a first portion S1 and a second portion S2, the first portion S1 and the second portion S2 respectively having different heights in the vertical direction (Z direction) and integrally connected to each other. In each of the source/drain contact patterns CAP, the conductive barrier film 154 and the metal plug 156 may extend on the first and second portions S1 and S2 to be included in the first and second portions S1 and S2.

In the first portion S1 of each of the source/drain contact patterns CAP, the top surface of the conductive barrier film 154 may be coplanar with the top surface of the metal plug 156 at a vertical height level LV 61. In the second portion S2 of each of the source/drain contact patterns CAP, the vertical height level LV62 of the uppermost surface of the conductive barrier film 154 is lower than the vertical height level LV63 of the uppermost surface of the metal plug 156. A height difference between the vertical height level LV63 of the uppermost surface of the metal plug 156 in the second portion S2 and the vertical height level LV62 of the uppermost surface of the conductive barrier film 154 may be about 1nm to about 5nm, for example, about 2nm to about 3 nm.

In the second portion S2 of each of the source/drain contact patterns CAP, the metal plug 156 may include protruding tops 656P at a height level higher than the vertical height level LV62 of the uppermost surface of the conductive barrier film 154. In the second portion S2 of each of the source/drain contact patterns CAP, the sidewalls of the protruding tops 656P of the metal plugs 156 may not be covered with the conductive barrier film 154.

Similar to the protruding top 156P shown in fig. 3A and 3B, the protruding top 656P can have a flat top surface (e.g., a substantially planar top surface). However, the embodiments are not limited thereto. For example, instead of the protruding top 656P, the metal plug 156 of the integrated circuit device 600 may include a protruding top having a shape identical or similar to one of the protruding tops 356P, 456P, and 556P shown in fig. 5A-7B.

The buried insulating film 170 may cover the top surface of the second portion S2 of each of the source/drain contact patterns CAP and the top surface of the insulating cover line 140. The buried insulating film 170 may include a main buried part 170M and a buried protrusion 170P, wherein the buried protrusion 170P protrudes from the main buried part 170M toward the substrate 110. The main buried portion 170M may be in contact with the top surface of the metal plug 156 included in each of the plurality of second portions S2, a portion of the inter-gate insulating film 128, and the plurality of insulating cover lines 140. The buried protrusion 170P may be on the second portion S2 of each of the source/drain contact patterns CAP to contact the uppermost surface of the conductive barrier film 154. The buried protrusion 170P may also be in contact with the sidewalls of the protruding top 656P of the metal plug 156. The buried protrusion 170P may fill a space defined by the uppermost surface of the conductive barrier film 154 of the second portion S2, sidewalls of the protruding top 656P of the metal plug 156, and the contact insulating spacer 150.

The buried insulating film 170 may have a planarized top surface. The buried insulating film 170 may include a portion filling a space above the second portion S2 of each of the source/drain contact patterns CAP between the gate lines GL. The top surface of the buried insulating film 170 may be coplanar with the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156, the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156 being included in the first portion S1 of each of the source/drain contact patterns CAP, and may be substantially at the vertical height level LV 61.

The integrated circuit device 600 includes the metal plug 156, and the metal plug 156 includes the protruding top 656P in the second portion S2 of the source/drain contact pattern CAP. The sidewalls of the protruding top 656P may be covered with the buried protruding portion 170P of the buried insulating film 170. Accordingly, a spaced distance from the conductive barrier film 154 and the metal plug 156 forming the second portion S2 to another conductive region adjacent to the second portion S2 may be ensured by at least the buried protrusion 170P. Accordingly, an insulation margin between the second portion S2 of the source/drain contact pattern CAP and the adjacent conductive region may be secured, thereby reducing or preventing an undesired short between the second portion S2 and the adjacent conductive region and improving reliability of the integrated circuit device 600.

Fig. 9 is a cross-sectional view of an integrated circuit device 700 according to some embodiments of the inventive concept. Fig. 9 shows an enlarged cross-sectional view of a portion corresponding to the region C9 in fig. 8B.

Referring to fig. 9, the integrated circuit device 700 may be substantially the same as or similar to the integrated circuit device 600 described with reference to fig. 8A and 8B. However, the integrated circuit device 700 includes the metal plugs 756 instead of the metal plugs 156 in the source/drain contact pattern CAP. The metal plugs 756 may include protruding tops 756P at a height level higher than the conductive barrier film 154 in the second portion S2 of the source/drain contact pattern CAP. The protruding top 756P can have a rounded corner 756C in the outer edge. A top surface portion 756T substantially in the middle of the protruding top 756P in the first horizontal direction (X direction) may extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. However, the embodiments are not limited thereto. For example, the protruding top 756P may have a convex curved shape similar to the protruding top 456P described with reference to fig. 6A and 6B. In another example, similar to the protrusion top 556P described with reference to fig. 7A and 7B, the protrusion top 756P may comprise a double-peak protrusion that is convex in a direction away from the substrate 110. The specific configuration of metal plugs 756 may be substantially the same as or similar to the specific configuration of metal plugs 156 of integrated circuit device 100 described with reference to fig. 1-3B.

Fig. 10A through 10C are diagrams of an integrated circuit device 900 according to some embodiments of the inventive concept, wherein fig. 10A is a layout of the integrated circuit device 900, fig. 10B is a cross-sectional view taken along line X9-X9 'in fig. 10A, and fig. 10C is a cross-sectional view taken along line Y9-Y9' in fig. 10A.

Referring to fig. 10A-10C, the integrated circuit device 900 includes a plurality of fin-type active regions F9 and a plurality of nanosheet stacks NSS, the plurality of fin-type active regions F9 protruding from the substrate 902 and extending (e.g., longitudinally extending) in a first horizontal direction (e.g., the X-direction), and each of the plurality of nanosheet stacks NSS being separated from the underlying fin-type active region F9 in a vertical direction (the Z-direction) and facing the top surface FT of the fin-type active region F9. In the present description, the term "nanoplatelets" refers to conductive structures having a cross-section substantially perpendicular to the direction of current flow. It will be understood that the nanoplatelets comprise nanowires.

Trenches T9 defining a plurality of fin-type active regions F9 may be formed in substrate 902 and filled with isolation film 912. The substrate 902, the fin active region F9, and the isolation film 912 may be the same as or similar to the substrate 110, the fin active region FA, and the isolation film 112 shown in fig. 2A and 2B, respectively.

A plurality of gate lines 960 extend in the second horizontal direction (Y direction) on the fin-type active region F9. Each of the nanosheet stacks NSS may be above the top surface FT of one of the fin-type active regions F9 at an intersection between one of the fin-type active regions F9 and one of the gate lines 960, may face the top surface FT of one of the fin-type active regions F9, and may be at a location separate from one of the fin-type active regions F9. A plurality of nanosheet transistors may be formed on substrate 902 at respective intersections between fin-type active regions F9 and gate lines 960.

Each of the nanosheet stack NSS may include a plurality of nanosheets overlapping one another in the vertical direction (Z-direction) above the top surface FT of one of the fin-shaped active regions F9. The nanoplatelets may comprise first, second and third nanoplatelets N1, N2, N3, the first, second and third nanoplatelets N1, N2, N3 being at different vertical distances from the top surface FT of each of the fin-shaped active regions F9, respectively. As used herein, "element a overlaps element B in a vertical direction" (or similar language) may mean that there is at least one vertical line that intersects both element a and element B.

Although fig. 10A illustrates that the nanosheet stack NSS has a rectangular shape, the embodiments are not limited thereto. The nanosheet stack NSS may have various shapes in plan view depending on the shapes of the fin-type active region F9 and the gate line 960. Further, although fig. 10A, 10B, and 10C show that a plurality of nanosheet stacks NSS and a plurality of gate lines 960 are formed on one fin-type active region F9, and the nanosheet stacks NSS are arranged on the fin-type active region F9 in the first horizontal direction (X direction), the inventive concept is not limited thereto. The number of nanosheet stack NSS on one fin-type active region F9 is not particularly limited. For example, one nanosheet stack NSS may be formed on one fin-shaped active region F9. Further, although fig. 10B and 10C illustrate that each of the nanosheet stack NSS includes three nanosheets, embodiments are not limited thereto. For example, each of the nanosheet-stacked NSS may include at least two (e.g., two, four, or more) nanosheets, and the number of nanosheets included in each nanosheet-stacked NSS is not particularly limited.

Each of the first, second and third nanoplatelet N1, N2, N3 may have a channel region. In example embodiments, each of the first, second, and third nanoplate N1, N2, N3 may comprise, for example, a Si layer, a SiGe layer, or a combination thereof.

A plurality of recess regions R9 may be formed in an upper portion of the fin-type active region F9, and a plurality of source/drain regions 930 may be formed in the recess regions R9. The source/drain regions 930 may include, for example, an epitaxially grown semiconductor layer. The source/drain regions 930 may be substantially the same as or similar to the source/drain regions SD described above with reference to fig. 2A and 2B.

A gate line 960 may be on the fin-type active region F9 to cover the nanosheet stack NSS and surround each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3. Each of the gate lines 960 may include a main gate portion 960M and a plurality of sub-gate portions 960S, the main gate portion 960M extending (e.g., longitudinally extending) in a second horizontal direction (Y-direction) to cover a top surface of the nanosheet stack NSS, and the plurality of sub-gate portions 960S being integrally connected to the main gate portion 960M and between the third nanosheet N3 and the second nanosheet N2, the second nanosheet N2 and the first nanosheet N1, and the first nanosheet N1 and the fin-type active region F9, respectively. The first, second, and third nanosheets N1, N2, and N3 may have a Gate All Around (GAA) structure surrounded by the gate line 960. The gate line 960 may include, for example, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er and Pd. The metal nitride may be selected from, for example, TiN and TaN. The metal carbide may comprise, for example, TiAlC. The gate insulating film 952 may be between the nanosheet stack NSS and the gate line 960. The gate insulating film 952 may be substantially the same as or similar to the gate insulating film 132 described with reference to fig. 2A and 2B.

A metal silicide film 982 may be formed on a top surface of each of the source/drain regions 930. The metal silicide film 982 may be substantially the same as or similar to the metal silicide film 152 described with reference to fig. 2A and 2B. The metal silicide film 982 may be omitted.

Both sidewalls of each of the gate lines 960 may be covered with a plurality of outer insulating spacers 918. An outer insulating spacer 918 may be on the plurality of nanosheet stacks NSS to cover both sidewalls of the main gate portion 960M. The outer insulating spacers 918 and the source/drain regions 930 may be covered with an insulating liner 942. The outer insulating spacers 918 and insulating liner 942 may comprise, for example, SiN, SiCN,SiBN、SiON、SiOCN、SiBCN、SiOC、SiO₂Or a combination thereof. The insulating liner 942 may be omitted.

A plurality of internal insulating spacers 928 are between the third nanoplate N3 and the second nanoplate N2, between the second nanoplate N2 and the first nanoplate N1, and between the first nanoplate N1 and the fin-type active region F9. Each of both sidewalls of each of the sub-gate portions 960S may be covered with an inner insulating spacer 928, with the gate insulating film 952 between the sidewall of each sub-gate portion 960S and the inner insulating spacer 928. A plurality of inner insulating spacers 928 may be between the sub-gate portion 960S and the source/drain regions 930. In an example embodiment, the outer insulating spacer 918 and the inner insulating spacer 928 may include the same insulating material as each other. In an example embodiment, the outer insulating spacer 918 and the inner insulating spacer 928 may include insulating materials different from each other. The inner insulating spacers 928 may include, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO₂Or a combination thereof. The inner insulating spacer 928 may also include an air gap.

The insulating liner 942 may be covered with an intergate insulating film 944. The inter-gate insulating film 944 may include, for example, a silicon oxide film. The plurality of source/drain contact patterns CAP9 may be in the plurality of contact holes 980, respectively, the plurality of contact holes 980 passing through the inter-gate insulating film 944 and the insulating liner layer 942. Each of the source/drain contact patterns CAP9 may be connected to the source/drain region 930 through a metal silicide film 982. Each of the source/drain contact patterns CAP9 may include a conductive barrier film 954 and a metal plug 956. Each of the source/drain contact patterns CAP9 may include a first portion S91 and a second portion S92, the first portion S91 and the second portion S92 having different heights in a vertical direction (Z direction), and being integrally connected to each other.

In each of the source/drain contact patterns CAP9, the conductive barrier film 954 and the metal plugs 956 may extend on the first and second portions S91 and S92 to be included in the first and second portions S91 and S92.

In the first portion S91 of each of the source/drain contact patterns CAP9, the top surface of the conductive barrier film 954 may be coplanar with the top surface of the metal plug 956 at a vertical height level LV 91. In the second portion S92 of each of the source/drain contact patterns CAP9, the vertical height level LV92 of the uppermost surface of the conductive barrier film 954 is lower than the vertical height level LV93 of the uppermost surface of the metal plug 956. The height difference between the vertical height level LV93 of the uppermost surface of the metal plug 956 in the second portion S92 and the vertical height level LV92 of the uppermost surface of the conductive barrier film 954 may be about 1nm to about 5nm, for example, about 2nm to about 3 nm.

In the second portion S92 of each of the source/drain contact patterns CAP9, the metal plugs 956 may include protruding tops 956P at a height level higher than the vertical height level LV92 of the uppermost surface of the conductive barrier film 954. In the second portion S92 of each of the source/drain contact patterns CAP9, sidewalls of the protruding tops 956P of the metal plugs 956 may not be covered with the conductive barrier film 954.

Similar to the overhanging portion 156P shown in fig. 3A and 3B, the overhanging portion 956P may have a flat top surface (e.g., a substantially planar top surface). However, the embodiments are not limited thereto. For example, metal plug 956 may include a protruding top having a shape identical or similar to one of protruding tops 356P, 456P, and 556P shown in fig. 5A-7B, instead of protruding top 956P.

The conductive barrier film 954 and the metal plugs 956 forming each of the source/drain contact patterns CAP9 may be substantially the same as or similar to the conductive barrier film 154 and the metal plugs 156, respectively, which have been described with reference to fig. 2A to 3B. Each of the gate lines 960 may be covered with an insulating cover line 940. The insulating covered wire 940 may have different thicknesses at different positions. For example, the insulating cover line 940 may have a variable thickness in the first horizontal direction (X direction). The insulated covered wire 940 may be substantially the same as or similar to the insulated covered wire 140 described with reference to fig. 2A and 2B.

The buried insulating film 970 may cover the top surface of the second portion S92 of each of the source/drain contact patterns CAP9 and the top surface of the insulating cover line 940. The buried insulating film 970 may be in contact with the top surface of the second portion S92 and the top surface of the insulating cover line 940.

The buried insulating film 970 may include a main buried portion 970M and a buried protrusion 970P, the buried protrusion 970P protruding from the main buried portion 970M toward the substrate 902. The main buried portion 970M may be in contact with the top surface of the metal plug 956 included in each of the plurality of second portions S92, a portion of the insulating liner 942, a portion of the inter-gate insulating film 944, and the plurality of insulating cover lines 940. The buried protrusion 970P may be on the second portion S92 of each of the source/drain contact patterns CAP9 to contact the top surface of the conductive barrier film 954. The buried protrusion 970P may also be in contact with the sidewall of the protruding top 956P of the metal plug 956. The buried protrusion 970P may fill a space defined by the top surface of the conductive barrier film 954 of the second portion S92, the sidewalls of the protruding top 956P of the metal plug 956, and the sidewalls of the inter-gate insulating film 944.

The buried insulating film 970 may have a planarized top surface. The buried insulating film 970 may include a portion filling a space above the second portion S92 of each of the source/drain contact patterns CAP9 between the gate lines 960. The top surface of the buried insulating film 970 may be coplanar with the respective uppermost surfaces of the conductive barrier film 954 and the metal plugs 956, which are included in the first portion S91 of each of the source/drain contact patterns CAP9, and may be substantially at the vertical height level LV 91. The specific configuration of the buried insulating film 970 may be the same as or similar to the specific configuration of the buried insulating film 170 described above with reference to fig. 2A to 3B. The integrated circuit device 900 described with reference to fig. 10A to 10C includes the metal plugs 956 including the protruding tops 956P in the second portion S92 of each of the source/drain contact patterns CAP 9. The sidewall of the protrusion top 956P may be covered with a buried protrusion 970P of a buried insulating film 970. Accordingly, a spacing distance from the conductive barrier film 954 and the metal plug 956 forming the second portion S92 to another conductive region adjacent to the second portion S92 can be ensured at least by the buried protrusion 970P. Accordingly, an insulation margin between the second portion S92 of each of the source/drain contact patterns CAP9 and the adjacent conductive region may be secured, thereby reducing or preventing an undesired short circuit between the second portion S92 and the adjacent conductive region and improving the reliability of the integrated circuit device 900.

Hereinafter, methods of manufacturing integrated circuit devices according to some embodiments of the inventive concept will be described with specific examples.

Fig. 11A through 22B are cross-sectional views illustrating methods of manufacturing integrated circuit devices according to some embodiments of the inventive concepts. Fig. 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A show portions corresponding to sections taken along lines X1-X1 ' and X2-X2 ' in fig. 1, respectively, and fig. 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B show portions corresponding to sections taken along lines Y1-Y1 ' in fig. 1. Hereinafter, an example of a method of manufacturing the integrated circuit device 100 shown in fig. 1 to 3B will be described with reference to fig. 11A to 22B.

Referring to fig. 11A and 11B, a plurality of fin-type active regions FA protruding from a main surface 110M of the substrate 110 in a vertical direction (Z direction) and extending parallel to each other in a first horizontal direction (X direction) and an isolation film 112 may be formed by partially etching the substrate 110 in the first and second device regions RX1 and RX2, and the isolation film 112 covers both sidewalls of a lower portion of each of the fin-type active regions FA. The deep trench DT defining the first and second device regions RX1 and RX2 may be formed by etching a portion of the isolation film 112 and a portion of the substrate 110, and may be filled with the isolation insulating film 114. Accordingly, the deep trench DT in the device isolation region DTA may be filled with the isolation insulating film 114. In the first and second device regions RX1 and RX2, the fin-type active region FA may protrude upward from the top surface of the isolation film 112.

Referring to fig. 12A and 12B, a plurality of dummy gate structures DGS extending to cross the fin-type active region FA are formed on the isolation film 112 and the isolation insulating film 114. Each of the dummy gate structures DGS may include a dummy gate insulating film D12, a dummy gate line D14, and a dummy insulating cap D16 sequentially stacked on the fin-type active area FA. The dummy gate insulating film D12 may include, for example, silicon oxide. The dummy gate line D14 may include, for example, polysilicon. The dummy insulating capping layer D16 may include, for example, silicon nitride.

The insulating spacers 120 may be formed on each of both sidewalls of each of the dummy gate structures DGS, and a plurality of recess regions RR may be formed in an upper portion of each of the plurality of fin active regions FA by partially etching the fin active regions FA exposed at both sidewalls of each of the dummy gate structures DGS. Thereafter, a plurality of source/drain regions SD filling the recess regions RR may be formed.

The isolation film 112, the isolation insulating film 114, the source/drain region SD, and the inter-gate insulating film 128 covering the source/drain region SD may be formed between the dummy gate structures DGS. In example embodiments, before the inter-gate insulating film 128 is formed, an insulating liner (not shown) covering the source/drain regions SD may also be formed. The insulating liner may comprise, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO₂Or a combination thereof.

Referring to fig. 13A and 13B, the dummy gate line D14 is exposed by removing the insulating films around the dummy insulating capping layer D16 and the dummy insulating capping layer D16 from the resulting structure of fig. 12A and 12B using, for example, a Chemical Mechanical Polishing (CMP) process. At this time, the heights of the inter-gate insulating film 128 and the insulating spacer 120 may be reduced.

Referring to fig. 14A and 14B, a plurality of gate spaces GA are provided by removing the plurality of dummy gate lines D14 and the plurality of dummy gate insulating films D12 from the resulting structure of fig. 13A and 13B. The insulating spacers 120, the fin-type active regions FA, the isolation films 112, and the isolation insulating film 114 may be exposed through the gate spaces GA.

Referring to fig. 15A and 15B, a gate insulating film 132, a gate line GL, and an insulating cover line 140 are formed in the gate space GA of the resulting structure of fig. 14A and 14B.

In order to form the gate insulating film 132, the gate line GL and the insulating cover line 140, a plurality of gate insulating films 132 and a plurality of gate lines GL may be formed to fill the gate space GA, and then the plurality of gate insulating films 132 and the plurality of gate lines GL may be etched back to be lowered so as to fill only a lower portion of the gate space GA. During the etch-back of the gate insulating film 132 and the gate line GL, the upper portion of the insulating spacer 120 defining the gate space GA may also be removed, so that the height of the insulating spacer 120 may be reduced. Thereafter, the insulating cover line 140 may be formed to cover the top surface of each of the gate line GL, the gate insulating film 132, and the insulating spacer 120 in the gate space GA and fill the upper portion of the gate space GA.

In example embodiments, before the gate insulating film 132 is formed, an interface film (not shown) may be formed to cover a surface of each of the fin-type active regions FA exposed by the gate space GA. For example, to form the interface film, the fin-type active region FA exposed in the gate space GA may be partially oxidized.

Referring to fig. 16A and 16B, a plurality of source/drain contact holes CAH are formed through the inter-gate insulating film 128 to expose the source/drain regions SD, and contact insulating spacers 150 are formed to cover inner sidewalls of each of the source/drain contact holes CAH. To form the contact insulating spacer 150, an insulating spacer film may be formed to conformally cover inner sidewalls of each of the source/drain contact holes CAH, and then the insulating spacer film is anisotropically etched to expose the source/drain regions SD through each of the source/drain contact holes CAH. Accordingly, a plurality of contact insulating spacers 150 may be obtained, each of the plurality of contact insulating spacers 150 including a portion of the insulating spacer film remaining on the sidewalls of the source/drain contact hole CAH.

A plurality of metal silicide films 152 and a plurality of preliminary source/drain contacts RCA are formed, the plurality of metal silicide films 152 cover the source/drain regions SD in lower portions of the source/drain contact holes CAH, respectively, and the plurality of preliminary source/drain contacts RCA fill the source/drain contact holes CAH, respectively. The preliminary source/drain contact RCA may include a conductive barrier film 154 and a metal plug 156. In the present specification, the conductive barrier film 154 included in the preliminary source/drain contact RCA may be referred to as a "preliminary conductive barrier film", and the metal plug 156 included in the preliminary source/drain contact RCA may be referred to as a "preliminary metal plug".

In example embodiments, the metal silicide film 152, the conductive barrier film 154, and the metal plug 156 may be formed by performing processes described below. First, a metal liner conformally covering the source/drain regions SD may be formed in the source/drain contact holes CAH. The metal underlayer may include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, Pd, or combinations thereof. Thereafter, the conductive barrier film 154 may be formed to cover the exposed surface of the metal liner and the inner sidewalls of the source/drain contact holes CAH. The metal underlayer and the conductive barrier film 154 may be formed using, for example, Physical Vapor Deposition (PVD), CVD, or Atomic Layer Deposition (ALD). Thereafter, a heat treatment may be performed on the resulting structure including the metal underlayer and the conductive barrier film 154 to cause a reaction between the semiconductor material of the source/drain region SD and the metal of the metal underlayer, thereby forming a metal silicide film 152 covering the source/drain region SD. In example embodiments, after the metal silicide films 152 are formed, a portion of the metal underlayer may remain between each of the metal silicide films 152 and the conductive barrier film 154. In example embodiments, the entire metal underlayer may be used to form the metal silicide films 152, and thus the metal underlayer may not remain between each of the metal silicide films 152 and the conductive barrier film 154.

Thereafter, a metal film may be formed thick enough to fill the inside of each of the source/drain contact holes CAH on the resulting structure including the metal silicide film 152 and the conductive barrier film 154. The metal film may be formed using, for example, CVD, PVD, or plating. Thereafter, the metal plug 156 including the metal film remaining on the conductive barrier film 154 in each of the source/drain contact holes CAH may be formed by removing unnecessary portions of the conductive barrier film 154 and the metal film using, for example, CMP to expose the top surface of the inter-gate insulating film 128.

Referring to fig. 17A and 17B, the height of the top surface of the conductive barrier film 154 is reduced by performing an etch-back process for selectively removing a portion (e.g., an upper portion) of the conductive barrier film 154 in the resulting structure of fig. 16A and 16B. Accordingly, an upper recess UR exposing the top surface of the conductive barrier film 154 may be formed between the metal plug 156 in each of the source/drain contact holes CAH and the contact insulating spacer 150. The outer sidewall of the metal plug 156 and the inner sidewall of the contact insulation spacer 150 may be exposed through the upper recess UR.

In example embodiments, the vertical height URH of the upper recess UR exposing the top surface of the conductive barrier film 154 may be about 1nm to about 5nm, for example, about 2nm to about 3 nm.

Referring to fig. 18A and 18B, an etch stop film 160 is formed to cover a top surface of the resulting structure of fig. 17A to 17B, and a plurality of mask patterns MP may be formed on the etch stop film 160 to partially cover the preliminary source/drain contacts RCA. The mask pattern MP may be positioned to correspond to the source/drain via contact CAV in fig. 1. In some embodiments, each of the mask patterns MP may overlap with a first portion of the upper recess UR and may not overlap with a second portion of the upper recess UR, as shown in fig. 18A and 18B.

The etch stop film 160 may include a material different from the mask pattern MP. In example embodiments, the etch stop film 160 may include, for example, SiOC, SiN, or a combination thereof, and the mask pattern MP may include, for example, a silicon oxide film, a spin-on hard mask (SOH) film, a photoresist film, or a combination thereof, but the embodiment is not limited thereto.

Referring to fig. 19A and 19B, the etching stopper film 160 is etched using the mask pattern MP as an etching mask, and the exposed preliminary source/drain contact RCA is etched in a specific etching atmosphere to be lowered. Accordingly, a plurality of source/drain contact patterns CAP having different heights at different positions may be formed. Each of the source/drain contact patterns CAP may include a first portion S1 and a second portion S2, the first portion S1 and the second portion S2 having different heights in a vertical direction (Z direction), and being integrally connected to each other. The first portion S1 may include a first portion of the metal plug 156, and the second portion S2 may include a second portion of the metal plug 156. Each of the first and second portions of the metal plug 156 may be a portion of a metal film that is a monolithic or unitary film and is formed by a single process, and the first and second portions of the metal plug 156 may be connected to each other without an interface or a boundary. The first portion S1 may include a first portion of the conducting barrier film 154, and the second portion S2 may include a second portion of the conducting barrier film 154. Each of the first and second portions of the conductive barrier film 154 may be a portion of the barrier film that is a monolithic or unitary film and is formed by a single process, and the first and second portions of the conductive barrier film 154 may be connected to each other without an interface or boundary.

A specific etching atmosphere may be provided to etch the metal-containing film forming the preliminary source/drain contact RCA. In a specific etching atmosphere, the etching amount of the metal-containing film forming the preliminary source/drain contact RCA may be greater than the etching amount of the insulating film forming the plurality of insulating cover lines 140, and the etching amount of the insulating film forming the insulating cover lines 140 may be greater than 0. While each of the metal plugs 156 and the contact insulation spacers 150 is lowered by etching the exposed portions of the preliminary source/drain contacts RCA using the mask pattern MP as an etching mask, the profile of the top surface of the preliminary source/drain contacts RCA including the upper recesses UR shown in fig. 17A and 17B may be transferred downward. Accordingly, after the source/drain contact patterns CAP are formed, a lower recess LR exposing the top surface of the conductive barrier film 154 between the metal plug 156 and the contact insulation spacer 150 may be formed on the top surface of the second portion S2 of each of the source/drain contact patterns CAP. The outer sidewall of the metal plug 156 of each of the source/drain contact patterns CAP and the inner sidewall of the contact insulation spacer 150 may be exposed through the lower recess LR.

In example embodiments, the vertical height LRH of the lower recess LR exposing the top surface of the conductive barrier film 154 may be about 1nm to about 5nm, for example, about 2nm to about 3 nm.

The height of the portion of the insulating cover line 140 exposed to a specific etching atmosphere while the exposed portion of the preliminary source/drain contact RCA is etched using the mask pattern MP as an etching mask may be reduced.

In a specific etching atmosphere, the height of each of the mask pattern MP, the plurality of insulating spacers 120, and the inter-gate insulating film 128 may be reduced while forming the source/drain contact pattern CAP including the first and second portions S1 and S2.

Referring to fig. 20A and 20B, an insulating film is formed on the resultant structure of fig. 19A and 19B to have a thickness sufficient to fill the space between the mask patterns MP, and planarization is performed on the resultant structure including the insulating film to form a buried insulating film 170 including the planarized insulating film. While performing planarization until the buried insulating film 170 is obtained, an upper portion of each of the mask pattern MP, the etch stop film 160, and the source/drain contact pattern CAP is removed so that respective top surfaces of the conductive barrier film 154 and the metal plug 156 forming the first portion S1 of each of the source/drain contact pattern CAP may be coplanar with each other and may be substantially at the vertical height level LV 1.

The second portion S2 of each of the source/drain contact patterns CAP and the insulating cover line 140 may be covered with the buried insulating film 170. The buried insulating film 170 may be formed to fill a space above the second portion S2 of each of the source/drain contact patterns CAP between the gate lines GL. The buried insulating film 170 may include a buried protrusion 170P, and the buried protrusion 170P fills the lower recess LR on the top surface of the second portion S2 (see fig. 19A and 19B).

The buried insulating film 170 may have a planarized top surface (e.g., a flat or substantially thousand-sided top surface). The top surface of the buried insulating film 170 may extend substantially at the vertical height level LV1 on the same plane as the respective top surfaces of the conductive barrier film 154 and the metal plug 156 forming the first portion S1.

Referring to fig. 21A and 21B, an insulating structure 180 is formed on the resulting structure of fig. 20A and 20B. The insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184, the etch stop film 182 and the interlayer insulating film 184 being sequentially formed on the buried insulating film 170 and the source/drain contact pattern CAP.

Referring to fig. 22A and 22B, a plurality of source/drain via contacts CAV connected to the respective first portions S1 of the source/drain contact pattern CAP and a plurality of gate contacts CB connected to the plurality of gate lines GL are respectively formed.

In example embodiments, the source/drain via contact CAV and the gate contact CB may be simultaneously formed. In example embodiments, the source/drain via contact CAV and the gate contact CB may be sequentially formed using separate processes. In this case, the gate contact CB may be formed after the source/drain via contact CAV is formed, or the source/drain via contact CAV may be formed after the gate contact CB is formed.

Each of the source/drain via contacts CAV may pass through the insulating structure 180 and contact a top surface of the first portion S1 of one of the source/drain contact patterns CAP. Each of the gate contacts CB may pass through one of the interlayer insulating film 184, the etch stop film 182, the buried insulating film 170, and the insulating cover line 140 and contact a top surface of one of the gate lines GL.

Each of some gate contacts CB may contact the gate line GL in a position adjacent to the second portion S2 of the source/drain contact pattern CAP. In this case, as shown in fig. 22A, the buried protrusion 170P of the buried insulating film 170 may be between the second portion S2 of the source/drain contact pattern CAP and the gate line GL adjacent to the second portion S2 in the first horizontal direction (X direction). Accordingly, a spaced distance from the conductive barrier film 154 and the metal plug 156 forming the second portion S2 to the gate line GL may be ensured by at least the buried protrusion 170P. Accordingly, even when the gate contact CB is adjacent to the second portion S2 of the source/drain contact pattern CAP, an insulation margin between the gate contact CB and the source/drain contact pattern CAP may be secured, thereby reducing or preventing an undesired short circuit between the gate contact CB and the source/drain contact pattern CAP.

Fig. 23A to 23D are cross-sectional views illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept. Fig. 23A to 23D show, in sequential stages, sectional views of parts corresponding to sections taken along the lines X1-X1 'and X2-X2', respectively, in fig. 1. Hereinafter, another example of a method of manufacturing the integrated circuit device 100 shown in fig. 1 to 3B will be described with reference to fig. 23A to 23D.

Referring to fig. 23A, using the method described with reference to fig. 18A and 18B, an etch stop film 160 and a plurality of mask patterns MP are formed on the resultant structure obtained by performing the method for forming a plurality of preliminary source/drain contacts RCA described with reference to fig. 11A to 16B.

Referring to fig. 23B, the etch stop film 160 is etched using the mask pattern MP as an etch mask in the resulting structure of fig. 23A, thereby exposing some of the preliminary source/drain contacts RCA.

Referring to fig. 23C, an etch-back process is performed on the resulting structure of fig. 23B using the mask pattern MP as an etching mask, so that a portion of the conductive barrier film 154 in each of the exposed preliminary source/drain contacts RCA is selectively removed by the method described with reference to fig. 17A and 17B. Accordingly, the height of the top surface of the conductive barrier film 154 is reduced, and the upper recess UR is formed.

Referring to fig. 23D, a plurality of source/drain contact patterns CAP, each including a first portion S1 and a second portion S2, are formed by etching the preliminary source/drain contact RCA in the resultant structure of fig. 23C using the mask pattern MP as an etching mask by a method similar to that described with reference to fig. 19A and 19B, the first portion S1 and the second portion S2 being integrally connected to each other. A lower recess LR exposing the top surface of the conductive barrier film 154 between the metal plug 156 and the contact insulating spacer 150 may be formed on the top surface of the second portion S2 of each of the source/drain contact patterns CAP.

Thereafter, the integrated circuit device 100 shown in fig. 1 to 3B may be manufactured by performing the process described with reference to fig. 20A to 22B.

Fig. 24A and 24B are cross-sectional views illustrating methods of manufacturing integrated circuit devices according to some embodiments of the inventive concepts. Fig. 24A and 24B show, in sequential stages, sectional views of parts corresponding to sections taken along lines X1-X1 'and X2-X2', respectively, in fig. 1. Hereinafter, still another example of a method of manufacturing the integrated circuit device 100 shown in fig. 1 to 3B will be described with reference to fig. 24A and 24B.

Referring to fig. 24A, after forming an etch stop film 160 and a mask pattern MP on the resulting structure including the preliminary source/drain contact RCA formed by the method described with reference to fig. 23A and 23B, the preliminary source/drain contact RCA is etched by using the mask pattern MP as an etch mask by a method similar to the method described with reference to fig. 23D, so that the height of a portion corresponding to the second portion S2 of each of the source/drain contact patterns CAP shown in fig. 2A and 2B is reduced.

While the height of some of the preliminary source/drain contacts RCA is reduced by etching the exposed portions of the preliminary source/drain contacts RCA using the mask pattern MP as an etching mask, the profile of the top surface of each of the preliminary source/drain contacts RCA in fig. 23B may be transferred downward. Accordingly, in the portion in which the height of each of the preliminary source/drain contacts RCA is reduced, the top surface of the conductive barrier film 154 may be substantially at the same height level as the top surface of the metal plug 156.

Referring to fig. 24B, an etch-back process is performed on the resultant structure of fig. 24A using the mask pattern MP as an etch mask, so that a portion of the conductive barrier film 154 in each of the preliminary source/drain contacts RCA, which has been exposed, is selectively removed by a method similar to that described with reference to fig. 17A and 17B, thereby reducing the height of the top surface of the conductive barrier film 154 and forming the lower recess LR. Accordingly, a plurality of source/drain contact patterns CAP, each including the first and second portions S1 and S2 integrally connected to each other, may be formed.

In some embodiments, instead of performing the process described with reference to fig. 24B, the resulting structure of fig. 24B may be obtained according to the resulting structure of fig. 23B by using one-step etching of the preliminary source/drain contacts RCA while applying an etching atmosphere while etching the preliminary source/drain contacts RCA using the mask pattern MP as an etching mask in the process described with reference to fig. 24A, wherein in the etching atmosphere, the etching selectivity of each of the conductive barrier film 154 and the metal plugs 156 may be appropriately controlled. The structure shown in fig. 24B may be formed by performing a single etching process on the structure shown in fig. 23B using the mask pattern MP as an etching mask.

Thereafter, the integrated circuit device 100 shown in fig. 1 to 3B may be manufactured by performing the process described with reference to fig. 20A to 22B.

Although examples of methods of manufacturing the integrated circuit device 100 shown in fig. 1 to 3B have been described with reference to fig. 11A to 22B, 23A to 23D, and 24A and 24B, it will be understood by those skilled in the art that the integrated circuit device 200 shown in fig. 4A and 4B, the integrated circuit device 300 shown in fig. 5A and 5B, the integrated circuit device 400 shown in fig. 6A and 6B, the integrated circuit device 500 shown in fig. 7A and 7B, the integrated circuit device 600 shown in fig. 8A and 8B, the integrated circuit device 700 shown in fig. 9, the integrated circuit device 900 shown in fig. 10A to 10C, and the like may be manufactured by variously modifying and changing the methods described with reference to fig. 11A to 22B, 23A to 23D, and 24A and 24B without departing from the scope of the inventive concept, And other integrated circuit devices having various structures modified and changed based on the above-described integrated circuit devices.

In example embodiments, the process of manufacturing the integrated circuit device 100 described with reference to fig. 11A through 22B may be used to manufacture the integrated circuit device 200 shown in fig. 4A and 4B. However, after the source/drain via contact CAV and the gate contact CB are formed in the stage described with reference to fig. 22A and 22B, a process of forming the plurality of wires ML connected to the source/drain via contact CAV and the gate contact CB may also be performed.

In example embodiments, to manufacture the integrated circuit device 300 shown in fig. 5A and 5B and the integrated circuit device 400 shown in fig. 6A and 6B, the process of manufacturing the integrated circuit device 100 that has been described with reference to fig. 11A to 22B may be used. However, in the process of forming the upper recess UR described with reference to fig. 17A and 17B and/or the process of forming the lower recess LR described with reference to fig. 19A and 19B, the etching selectivity of the conductive barrier film 154 with respect to the metal plugs 156 may be controlled so that metal plugs 356 (which have rounded corners 356C in the outer edges of the protruding tops 356P as described with reference to fig. 5A and 5B) or metal plugs 456 (which have top surface portions 456T and rounded corners 456C in the protruding tops 456P as described with reference to fig. 6A and 6B) may be formed in the final structure including the lower recess LR instead of the metal plugs 156.

In an example embodiment, to manufacture the integrated circuit device 500 shown in fig. 7A and 7B, the process of manufacturing the integrated circuit device 100 already described with reference to fig. 11A to 22B may be used. However, in the process of forming the metal plug 156 described with reference to fig. 16A and 16B, the metal plug 156 may be formed to have a slit or a void at least in an inner portion thereof, and in the process of forming the upper recess UR described with reference to fig. 17A and 17B and/or the process of forming the lower recess LR described with reference to fig. 19A and 19B, the etching selectivity of the conductive barrier film 154 with respect to the metal plug 156 may be controlled such that a portion of the metal plug 156, which is relatively weak due to the slit or the void in the metal plug 156, is also etched during the etching process for forming the upper recess UR or the lower recess LR, thereby forming the metal plug 556 having a double-peak protrusion in the protruding top 556P instead of the metal plug 156 in the final structure including the lower recess LR.

Fig. 25A to 31 are sectional views illustrating a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept, in which fig. 25A, 26A, 27A, 28A, 29A, 30A, and 31 illustrate portions corresponding to a section taken along line X9-X9 'in fig. 10A, and fig. 25B, 26B, 27B, 28B, 29B, and 30B illustrate portions corresponding to a section taken along line Y9-Y9' in fig. 10A. Hereinafter, an example of a method of manufacturing the integrated circuit device 900 illustrated in fig. 10B to 10C will be described with reference to fig. 25A to 31. In fig. 1 to 10C and fig. 25A and 31, like reference numerals and characters denote like elements, and detailed descriptions thereof may be omitted.

Referring to fig. 25A and 25B, a plurality of sacrificial semiconductor layers 904 and a plurality of nanosheet semiconductor layers NS are alternately stacked on the substrate 902. The sacrificial semiconductor layer 904 may comprise a different material than the nanosheet semiconductor layer NS. In an example embodiment, the sacrificial semiconductor layer 904 may include, for example, SiGe, and the nanosheet semiconductor layer NS may include, for example, Si.

Referring to fig. 26A and 26B, a trench T9 is formed by partially etching the sacrificial semiconductor layer 904, the nanosheet semiconductor layer NS, and the substrate 902, and an isolation film 912 is formed in the trench T9. Accordingly, a fin-type active region F9 defined by the trench T9 may be formed. The stacked structure of the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS remains on the top surface FT of the fin-shaped active region F9.

Referring to fig. 27A and 27B, a plurality of dummy gate structures DGS9 are formed on the stacked structure of the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS of the resulting structure of fig. 26A and 26B, and a plurality of outer insulating spacers 918 are formed covering both sidewalls of each of the dummy gate structures DGS9, respectively. Thereafter, the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS are partially etched using the dummy gate structure DGS9 and the outer insulating spacer 918 as an etch mask such that the nanosheet semiconductor layer NS is separated into a plurality of nanosheet stacks NSs, wherein the nanosheet stacks NSs include a first nanosheet N1, a second nanosheet N2 and a third nanosheet N3. Thereafter, the fin-type active region F9 exposed between the nanosheet stacks NSS is etched, thereby forming a plurality of recess regions R9 in an upper portion of the fin-type active region F9.

Each of the dummy gate structures DGS9 may extend (e.g., longitudinally extend) in a second horizontal direction (Y-direction). Each of the dummy gate structures DGS9 may have a structure in which an insulating layer D962, a dummy gate layer D964, and a capping layer D966 are sequentially stacked. In example embodiments, the insulating layer D962 may include, for example, silicon oxide, the dummy gate layer D964 may include, for example, polysilicon, and the capping layer D966 may include, for example, silicon nitride.

Referring to fig. 28A and 28B, by partially removing the sacrificial semiconductor layer 904 exposed around the recessed regions R9 of the resulting structure of fig. 27A and 27B, a plurality of recesses (e.g., openings) are formed between the first, second and third nanoplatelets N1, N2 and N3 and the top surface FT, and a plurality of internal insulating spacers 928 filling the recesses are formed.

Referring to fig. 29A and 29B, a plurality of source/drain regions 930 are formed by epitaxially growing a semiconductor material from the exposed surface of the recess region R9 of the resultant structure of fig. 28A and 28B, an insulating liner 942 is formed to cover the resultant structure including the source/drain regions 930, an inter-gate insulating film 944 is formed on the insulating liner 942, and the top surface of the covering layer D966 is exposed by planarizing the top surface of each of the insulating liner 942 and the inter-gate insulating film 944. Thereafter, a gate space GS is provided by removing the dummy gate structure DGS9, and the sacrificial semiconductor layer 904 is removed through the gate space GS such that the gate space GS extends to spaces between the first, second and third nanoplate N1, N2 and N3 and the top surface FT.

Referring to fig. 30A and 30B, a gate insulating film 952 is formed to cover the exposed surface of each of the first, second, and third nanosheets N1, N2, N3 and the fin-type active region F9, a plurality of gate lines 960 are formed on the gate insulating film 952 to fill the plurality of gate spaces GS, and an upper portion of each of the gate lines 960 and an upper portion of each of the gate insulating film 952 and the outer insulating spacers 918 around the gate lines 960 are removed to empty the upper portion of each of the gate spaces GS. Thereafter, an upper portion of each of the gate spaces GS is filled with an insulating cover line 940. Since the planarization is performed during the formation of the gate line 960 and the insulating cover line 940, the height of each of the insulating liner 942 and the intergate insulating film 944 may be reduced.

Referring to fig. 31, a plurality of contact holes 980 exposing the source/drain regions 930 are formed by partially etching the inter-gate insulating film 944 and the insulating liner layer 942, and a metal silicide film 982 and a preliminary source/drain contact RCA9 are formed in each of the contact holes 980.

In example embodiments, the metal silicide film 982 and the preliminary source/drain contact RCA9 may be formed using the method of forming the metal silicide film 152 and the preliminary source/drain contact RCA that has been described with reference to fig. 16A and 16B.

Thereafter, a process similar to that described with reference to fig. 17A to 19B may be performed on the resultant structure of fig. 31, thereby forming a plurality of source/drain contact patterns CAP9 (see fig. 10B) according to a plurality of preliminary source/drain contacts RCA 9. At this time, the height of a portion of the insulating cover line 940 is reduced so that the insulating cover line 940 may have a variable thickness in the first horizontal direction (X direction). After that, the integrated circuit device 900 illustrated in fig. 10A to 10C can be manufactured by forming the buried insulating film 970 using the method of forming the buried insulating film 170 which has been described with reference to fig. 20A and 20B.

In the drawings, two elements shown in contact with each other without intervening elements may be in direct contact with each other.

While the present inventive concept has been particularly shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the present inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.