阅读说明：本技术 主动式x射线攻击预防装置 (Active X-ray attack prevention device ) 是由 V·杰恩 S·T·文特罗内 S·P·埃杜苏米利 J·J·埃利斯-莫纳甘 A·拉曼 于 2021-05-07 设计创作，主要内容包括：本发明涉及主动式X射线攻击预防装置。本公开涉及一种用于保护集成电路的主动式x射线攻击预防装置的金属层。具体地,本公开涉及一种结构,该结构包括：半导体材料；位于半导体材料正面上的一个或多个器件；位于一个或多个器件下方的背面图案化金属层,其被定位和构造以保护一个或多个器件免受主动入侵；以及至少一个接触,其提供穿过半导体材料到背面图案化金属层的正面的电连接。背面图案化金属层位于半导体材料和绝缘体层中的一者与晶片之间。(The present invention relates to an active X-ray attack prevention apparatus. The present disclosure relates to a metal layer for an active x-ray attack prevention device for protecting an integrated circuit. Specifically, the present disclosure relates to a structure comprising: a semiconductor material; one or more devices located on the front side of the semiconductor material; a backside patterned metal layer located below the one or more devices, positioned and configured to protect the one or more devices from active intrusion; and at least one contact providing an electrical connection through the semiconductor material to the front side of the backside patterned metal layer. A backside patterned metal layer is between the wafer and one of the semiconductor material and the insulator layer.)

1. A structure, comprising:

a semiconductor material;

one or more devices on the front side of the semiconductor material;

a backside patterned metal layer located below the one or more devices, positioned and configured to protect the one or more devices from active intrusion; and

at least one contact providing an electrical connection through the semiconductor material to the front side of the backside patterned metal layer,

wherein the backside patterned metal layer is between a wafer and one of the semiconductor material and insulator layer.

2. The structure of claim 1, wherein:

the insulator layer is located below the semiconductor material,

the wafer is located below the insulator layer,

the back side patterned metal layer is located between the insulator layer and the wafer, and

the at least one contact is provided through the insulator layer.

3. The structure of claim 1, further comprising logic circuitry connected to the backside patterned metal layer, the logic circuitry configured to detect a change in resistance in the backside patterned metal layer.

4. The structure of claim 3, wherein the logic circuit is configured to generate a tamper signal to change circuit operation in response to the detected change in resistance.

5. The structure of claim 3, wherein the logic circuit detects when at least one of the contacts has a change in resistance above a threshold resistance while the other contacts have a change in resistance below the threshold resistance.

6. The structure of claim 3, wherein the logic circuit is configured to indicate that a thermal change has occurred.

7. The structure of claim 1, wherein the at least one contact comprises a plurality of contacts along the backside patterned metal layer.

8. The structure of claim 1, wherein the backside patterned metal layer is serpentine shaped.

9. The structure of claim 1, wherein:

the wafer may include a handle wafer that is,

the semiconductor material is bulk Si, and

the backside patterned metal layer is located between the handle wafer and the bulk Si.

10. The structure of claim 9, further comprising a marker layer different from the bulk Si, wherein:

the marker layer is located on the lower side of the body Si,

the back patterned metal layer is located on the lower side of the mark layer, and

the at least one contact is a plurality of through silicon vias extending through the indicia layer and in contact with the backside patterned metal layer along a length of the backside patterned metal layer.

11. A structure, comprising:

a semiconductor material;

at least one device on the front side of the semiconductor material;

a backside patterned metal layer buried on a backside of the semiconductor material;

at least one contact connected to a front side of the backside patterned metal layer, the at least one contact extending through the semiconductor material; and

a logic circuit connected to the backside patterned metal layer via the at least one contact and configured to detect a change in resistance in the backside patterned metal layer.

12. The structure of claim 11, further comprising an insulator material underlying the semiconductor material and a wafer underlying the backside patterned metal layer.

13. The structure of claim 12, wherein the backside patterned metal layer is buried between the wafer and the insulator material.

14. The structure of claim 13, wherein the at least one contact is a plurality of contacts along a length of the backside patterned metal layer.

15. The structure of claim 11, further comprising a wafer underlying the semiconductor material, wherein the semiconductor material is a bulk semiconductor material and the backside patterned metal layer is buried between the wafer and the bulk semiconductor material.

16. The structure of claim 14, wherein the at least one contact is a plurality of Through Silicon Vias (TSVs).

17. The structure of claim 14, further comprising a silicon germanium (SiGe) material between the bulk semiconductor material and the backside patterned metal layer.

18. The structure of claim 11, wherein the backside patterned metal layer prevents a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM) from reaching the at least one device.

19. The structure of claim 11, wherein the logic circuit is configured to generate a tamper signal to alter circuit operation in response to a detected change in resistance of the backside patterned metal layer.

20. A method, comprising:

forming an insulator layer;

forming a semiconductor layer on the insulator layer;

forming a back-end-of-line (BEOL) layer on the semiconductor layer;

forming a back patterned metal layer on a back side of the insulator layer; and

a handle wafer is formed on the backside patterned metal layer.

Technical Field

The present disclosure relates to integrated circuits, and more particularly, to active x-ray attack prevention devices and methods of operation for protecting integrated circuits.

Background

When using active x-ray spectroscopy, one can observe the integrated circuit under power and voltage contrast and determine the functional state of the design. Furthermore, once the decryption step of the private key occurs, it is possible to unlock the private key of the device and use the registers of the integrated circuit for the first time. Known techniques to prevent such unlocking may include enclosure shielding, but the enclosure shielding is still susceptible to tampering. Therefore, the known technology cannot prevent the discovery of key technologies and intellectual property rights in the integrated circuit.

Disclosure of Invention

In one aspect of the disclosure, a structure comprises: a semiconductor material; one or more devices on the front side of the semiconductor material; a backside patterned metal layer located below the one or more devices, positioned and configured to protect the one or more devices from active intrusion; and at least one contact providing an electrical connection through the semiconductor material to the front side of the backside patterned metal layer. The backside patterned metal layer is located between a wafer and one of the semiconductor material and insulator layer.

In another aspect of the disclosure, a structure comprises: a semiconductor material; at least one device on the front side of the semiconductor material; a backside patterned metal layer buried on a backside of the semiconductor material; at least one contact connected to a front side of the backside patterned metal layer, the at least one contact extending through the semiconductor material; and logic circuitry connected to the backside patterned metal layer via the at least one contact and configured to detect a change in resistance in the backside patterned metal layer.

In another aspect of the disclosure, a method comprises: forming an insulator layer; forming a semiconductor layer on the insulator layer; forming a back-end-of-line (BEOL) layer on the semiconductor layer; forming a back patterned metal layer on a back side of the insulator layer; and forming a handle wafer (handle wafer) on the backside patterned metal layer.

Drawings

In the following detailed description, the present disclosure is described with reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

Fig. 1 illustrates, among other features, a body contact and corresponding fabrication process in accordance with aspects of the present disclosure.

Fig. 2 illustrates, among other features, a handle wafer and a corresponding fabrication process in accordance with aspects of the present disclosure.

Fig. 3 illustrates, among other features, a backside patterned metal layer and a corresponding fabrication process in accordance with aspects of the present disclosure.

Fig. 4 illustrates, among other features, removal of a handle wafer and a corresponding fabrication process, according to aspects of the present disclosure.

Fig. 5 illustrates a representative graph of a backside metal pattern in accordance with aspects of the present disclosure.

Fig. 6 illustrates, among other features, a bulk silicon (bulk silicon) wafer having a silicon germanium (SiGe) stack (stack) and corresponding fabrication process in accordance with aspects of the present disclosure.

Fig. 7 illustrates, among other features, back end of line (BEOL) layers and corresponding fabrication processes in accordance with aspects of the present disclosure.

Fig. 8 illustrates, among other features, a thinned wafer and a corresponding fabrication process in accordance with aspects of the present disclosure.

Fig. 9 illustrates, among other features, a backside patterned metal layer on a backside of a semiconductor material and a corresponding fabrication process in accordance with aspects of the present disclosure.

Detailed Description

The present disclosure relates to integrated circuits, and more particularly, to active x-ray attack prevention devices and methods of operation for protecting integrated circuits. More specifically, the present disclosure provides a buried patterned metal layer to prevent Scanning Electron Microscopy (SEM) from attacking the chip with backside attacks. By implementing the apparatus disclosed herein, the circuit can detect a resistance change in the buried patterned metal layer and generate a tamper signal to alter circuit operation when there is a backside attack from a Scanning Electron Microscope (SEM). Thus and advantageously, by implementing the apparatus disclosed herein, the apparatus can prevent active x-ray attacks from determining the functional state of a circuit design and from theft of critical technologies and intellectual property.

In known circuits, attacks and/or analysis of the circuit occur by scanning the back side of the chip across the die (die). The attack and/or analysis may capture the functionality of the device, which can then be reconstructed. For example, the analysis may be done by performing active and passive optical probing using photo-electro emission (PE), electro-optic frequency modulation, or laser voltage techniques. To avoid attacks and/or analyses on the circuit, charge trap logic structures may be used; however, in this type of circuit, the attack and/or analysis may occur after bypassing the charge trap device. Furthermore, the encapsulation shield may prevent attacks and/or analysis on the circuit; however, the enclosure shield is easily tampered with. In contrast, the present invention provides a buried metal layer for generating a tamper signal to alter circuit operation in the presence of a backside attack from a SEM. In particular, the present disclosure includes a buried metal layer that prevents x-rays from passing through to the functional circuitry.

In an embodiment of the present disclosure, an integrated circuit includes active and passive devices formed on the front side of a wafer. In addition, a patterned metal is buried between the buried oxide layer (BOX) and the wafer. Contacts in the integrated circuit provide electrical connections from the patterned metal to the front side of the wafer. Further, the integrated circuit includes a logic circuit that detects the resistance change in the patterned metal and generates a tamper signal to alter the circuit operation. Advantageously, the present disclosure prevents x-ray penetration to the chip while using bulk contact with buried patterned metal or backside patterned metal. The integrated circuit detects any change in resistance of the buried patterned metal or the backside patterned metal that is indicative of tampering to remove the buried metal.

The devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. Generally, however, methods and tools are used to form structures having micron and nanometer scale dimensions. The methods (i.e., techniques) for fabricating the devices of the present disclosure have been employed in accordance with Integrated Circuit (IC) technology. These structures are built on a wafer, for example, and are realized in a film of material that is patterned by means of a photolithographic process on top of the wafer. Specifically, the fabrication of the device uses three basic building blocks: (i) depositing a material film on a substrate; (ii) applying a patterned mask on top of the film by lithographic imaging; and (iii) etching the film selective to the mask.

Figure 1 shows, among other features, a body contact and corresponding manufacturing process. The structure 100 of fig. 1 may represent a semiconductor-on-insulator (SOI) technology. More specifically, in fig. 1, structure 100 includes a substrate 115, and substrate 115 includes silicon-on-insulator (SOI) technology. In SOI technology, the substrate 115 includes a semiconductor material 120 bonded or attached to an insulating layer 130, and the insulating layer 130 is bonded to a handle wafer 140. Semiconductor material 120 may be bonded to insulating layer 130 using wafer bonding techniques and/or other suitable methods. In an embodiment, handle wafer 140 and semiconductor material 120 may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, GaAs, InAs, InP, and other group III/V or II/VI compound semiconductors. Insulating layer 130 may also be formed by any suitable process, such as separation by implanted oxygen (SIMOX), oxidation, deposition, and/or other suitable processes. Insulator layer 130 comprises any suitable material including silicon oxide, sapphire, or other suitable insulating material and/or combinations thereof. Exemplary insulator layer 130 may be a buried oxide layer (BOX). In an embodiment, the depth of the semiconductor material 120 and the insulator layer 130 is about 100 nanometers; however, other dimensions are also contemplated herein.

Still referring to fig. 1, device 160 is formed within semiconductor material 120 or on semiconductor material 120. Device 160 may be an active or passive device. For example, the device 160 may be a transistor, a resistor, a capacitor, a combination thereof, and the like. Back end of line (BEOL) layers 110 are deposited on the semiconductor material 120 by a conventional deposition process, such as a Chemical Vapor Deposition (CVD) process. In an embodiment, the BEOL layers 110 are whole back end of line stacks (stacks) that include a stack of vias and metal for wiring including inductors, resistors, and capacitors.

Fig. 1 also shows a plurality of contacts 150 formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, a resist formed over the BEOL layer 110 is exposed to energy (light) to form a pattern (opening). One or more trenches extending into the handle wafer 140 are formed in the BEOL layers 110, the semiconductor material 120, and the insulating layer 130 through the openings in the resist using an etching process having selective chemistry, such as Reactive Ion Etching (RIE). In another embodiment, one or more trenches extending through the semiconductor material 120 and the insulating layer 130 into the handle wafer 140 are formed in a front-end-of-line (FEOL) process through openings in the resist using an etching process with selective chemistry, such as Reactive Ion Etching (RIE). After the resist is removed by a conventional oxygen ashing process or other known strippers, a metal material may be deposited within these trenches to form a plurality of contacts 150, such as body contacts. In embodiments, the metallic material may be aluminum or tungsten (e.g., WSi) or copper, among other materials, deposited by any conventional deposition process (e.g., a CVD process). Any residual material on the surface of the BEOL layer 110 may be removed by a conventional Chemical Mechanical Polishing (CMP) process.

In fig. 2, a temporary handle wafer 170 is attached to the BEOL layers 110 by a conventional bonding process. For example, the temporary handle wafer 170 may be bonded to the BEOL layers 110 by contact bonding or thermocompression bonding. Contact bonding uses a liquid curable adhesive layer coated on a carrier wafer; and the hot pressing process includes heating and applying heat and mechanical pressure to the two connectors.

In fig. 3, the structure of fig. 2 is flipped over, e.g., inverted, and the handle wafer 140 is removed by conventional processes including mechanical polishing, debonding, or other known processes. Removal of handle wafer 140 exposes insulator layer 130 (i.e., the BOX layer) and body contact 150. A backside patterned metal layer 180 (i.e., a buried patterned metal layer 180) is formed on the exposed backside of the insulator layer 130 (i.e., BOX layer), the backside patterned metal layer 180 being in contact with the body contact 150. In particular, the pattern of backside patterned metal layer 180 has dimensions that prevent SEM from detecting devices above the pattern.

In an embodiment, the metal material of the backside patterned metal layer 180 may be deposited by conventional deposition methods, and then a patterning process (e.g., photolithography and etching) is performed to form different patterns. Handle wafer 190 is attached or deposited over backside patterned metal layer 180 by conventional techniques, as described herein and well known to those skilled in the art, and therefore need not be described further.

In fig. 4, the temporary handle wafer 170 is removed by conventional debonding techniques. For example, debonding may be provided by mechanical forces, such as cleaving, and may also be provided by other debonding techniques that are well known to those of ordinary skill in the art and therefore require no further explanation for a complete understanding of the present disclosure.

By implementing the processes described herein, a backside patterned metal layer 180 is provided between the insulator layer 130 (i.e., the BOX layer 130) and the handle wafer 190. Integrated circuit 100 in fig. 4 does not require through-silicon vias (TSVs). Furthermore, in fig. 4, the buried patterned metallization layer with body contacts 150 (i.e., the backside patterned metal layer 180) may be connected to logic circuitry (which may be represented by any of the devices 160). Logic circuit 160 may be used to detect any tampering of backside patterned metal layer 180. For example, any attempt to remove handle wafer 190 and backside patterned metal layer 180 may result in the logic measuring a higher resistance, which triggers a tamper signal. The logic circuit 160 for detecting the change in resistance may be of any known circuit design.

Fig. 5 shows a representative graph of the backside metal pattern. In fig. 5, the back metal pattern 180 includes body contacts 150, and the body contacts 150 are placed at different distances and positions of the back metal pattern 180 to measure the resistance of the back patterned metal layer 180. In the pattern of fig. 5, the backside patterned metal layer 180 is a serpentine (serpentine) pattern. Other patterns are also contemplated herein. The pattern should preferably shield the device and its function from attacks. For example, the pattern may be a spiral configuration of concentric shapes (e.g., circular, rectangular, octagonal, etc.), different shapes (e.g., circular, rectangular, octagonal, etc.), and the spacing or interval between adjacent lines may be sized to prevent backside monitoring. In this way, the backside patterned metal layer 180 will prevent X-rays from penetrating the backside of the handle wafer 190, and any tampering with the patterning will change the resistance of the backside patterned metal layer 180. The change in resistance will be a warning of tampering, at which time the device may be deactivated.

In further embodiments, the serpentine shape may have multiple sensing taps (taps) (e.g., body contacts 150) along the length of the serpentine structure. Thus, the integrated circuit (i.e., integrated circuit 100) cannot be bypassed using the external resistor. In addition, a series of these serpentine (or other shaped) patterned metal structures may be added to the chip to prevent local attacks. In still other embodiments, to compensate for resistance changes as a function of temperature (i.e., relative to hacking attempts), several resistors may be used for comparison. For example, if all of the resistances of these resistors increase (within a known tolerance), it is most likely due to thermal variations rather than hacking/tampering attempts. However, if at least one of these resistors increases beyond a known tolerance while the other resistors remain stable or only increase within a known tolerance, it is most likely due to a hacking/tampering attempt, rather than to thermal variations.

Fig. 6-9 illustrate a Through Silicon Via (TSV) method with backside metal according to aspects of the present disclosure. In fig. 6, the structure 100a comprises a bulk silicon wafer 305, the bulk silicon wafer 305 having a silicon germanium (SiGe) stack 320 grown thereon. In particular, the SiGe material 320 may be 10-20% Ge and 80-90% Si. The SiGe material 320 may be 100 nanometers or more thick to serve as a marker layer (e.g., etch stop layer), the bulk wafer 310 may be about 100 microns; however, other dimensions are contemplated herein. In an embodiment, the semiconductor material 310 is deposited (e.g., grown) on the SiGe material 320. In an embodiment, the semiconductor material 310 may be a single crystal Si material; although other semiconductor materials as described herein are also contemplated. In further embodiments, the SiGe stack 320 may be removed by performing an etch based on the final wafer thickness.

In fig. 7, a back end of line (BEOL) layer 110 is deposited on a semiconductor material 310 by a conventional deposition process, such as a CVD process. In an embodiment, the BEOL layers 110 are whole back-end stacks that include stacks of metal and vias for wiring including inductors, resistors, and capacitors. Furthermore, the device 160 is formed on a semiconductor material 310 surrounded by the BEOL layers 110. Device 160 may be an active or passive device as described herein.

Fig. 7 also illustrates a plurality of through-silicon via (TSV) contacts 330 formed by conventional photolithography, etching, and deposition methods, which are well known to those skilled in the art, and therefore further explanation is not necessary to understand the present disclosure. The TSV contacts 330 may extend through the BEOL layers 110, the semiconductor material 310, the SiGe material 320 into the wafer 305. As an example, the TSV 330 may have a depth of about 100 microns; however other dimensions are also contemplated herein.

In fig. 8, the wafer 305 is thinned to the depth of the SiGe material 320. The SiGe material 320 may act as an etch stop due to the material selectivity between the wafer 305 and the SiGe material 320. In fig. 9, after the SiGe material 320 is removed, the TSV 330 is exposed, and a backside patterned metal layer 180 (and wafer 190) is formed on the backside of the semiconductor material 310, wherein the backside patterned metal layer 180 is in electrical contact with the TSV contact 330.

In an alternative embodiment, the SiGe material 320 may remain on the semiconductor material 310, as representatively illustrated by the dashed lines in fig. 9. In this embodiment, a backside patterned metal layer 180 (i.e., a buried patterned metal layer 180) is formed on the backside of the SiGe material 320 in electrical contact with the TSV contacts 330. In any embodiment and as previously described, the metallization on the wafer backside will prevent scanning electron microscope/transmission electron microscope (SEM/TEM) electrons from reaching the device 160.

Active x-ray attack prevention devices may be utilized in system-on-a-chip (SoC) technology for metal layers. It will be understood by those skilled in the art that an SoC is an integrated circuit (also referred to as a "chip") that integrates all of the components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, the SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. Therefore, socs are becoming the dominant force in the mobile computing (e.g., smartphone) and edge computing markets. Socs are also commonly used in embedded systems and the internet of things.

The above structure and method are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having a plurality of unpackaged chips), as a die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnections and/or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product (e.g., a motherboard) or (b) an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The description of the various embodiments of the present disclosure has been presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.