阅读说明：本技术 一种可扩展的超导量子芯片的封装盒 (Extensible superconducting quantum chip packaging box ) 是由 王浩华 宋超 刘武新 郭秋江 宋紫璇 任文慧 王震 李贺康 张鹏飞 董航 张叙 于 2020-06-30 设计创作，主要内容包括：本发明公开了一种可扩展的超导量子芯片的封装盒,该封装盒包括：底座和盖板；所述底座内挖有两个凹槽,用于放置同轴线和超导量子芯片,所述用于放置同轴线的凹槽侧面设置有纵向的多排孔阵列,用于安装同轴线来进行微波信号传输,同轴线在靠近超导量子芯片的一端做特殊处理,作为与超导量子芯片的性能管脚连接的信号层电极；所述盖板与底座挖有凹槽的一面对应,并与其紧密贴合。本发明通过纵向第三个维度将量子芯片上的信号引出去,在不扩大所述底座尺寸的前提下容纳更多的信号层电极,有效地节省了空间,更利于超导量子比特的集成化；所述同轴线和所述底座以及盖板可以根据需求使用不同的材料,所述材料的选择具有很大的自由度。(The invention discloses an extensible packaging box of a superconducting quantum chip, which comprises: a base and a cover plate; two grooves are dug in the base and used for placing a coaxial line and a superconducting quantum chip, a longitudinal multi-row hole array is arranged on the side face of the groove for placing the coaxial line and used for installing the coaxial line to transmit microwave signals, and the coaxial line is specially processed at one end close to the superconducting quantum chip and is used as a signal layer electrode connected with a performance pin of the superconducting quantum chip; the cover plate corresponds to one surface of the base with the groove and is tightly attached to the base. The invention leads out the signal on the quantum chip through the third longitudinal dimension, and accommodates more signal layer electrodes on the premise of not enlarging the size of the base, thereby effectively saving space and being more beneficial to the integration of superconducting quantum bits; the coaxial line and the base and cover plate can be made of different materials according to requirements, and the materials are selected with great freedom.)

1. An expandable superconducting quantum chip package, comprising: a base and a cover plate; two grooves are dug in the base and are respectively used for placing the coaxial line and the superconducting quantum chip; the two grooves are both positioned in the center of the base, and the groove for placing the superconducting quantum chip is positioned below the groove for placing the coaxial line; the side surface of the groove for placing the coaxial line is provided with a longitudinal multi-row hole array for installing the coaxial line to transmit microwave signals; the number of the longitudinal multi-row hole arrays can be expanded and is determined according to the number of bits on the superconducting quantum chip; the coaxial line is cut at one end close to the superconducting quantum chip and is used as a signal layer electrode connected with a performance pin of the superconducting quantum chip; the cover plate corresponds to one surface of the base with the groove and is tightly attached to the base.

2. The scalable superconducting quantum chip package of claim 1, wherein the cover plate covers the base, and the groove in the base and the cover plate cooperate to form a sealed cavity structure.

3. The scalable superconducting quantum chip package of claim 2, wherein the coaxial line passes through the longitudinal multi-row hole array and extends into the sealed cavity from the outside, and after a cutting process is performed on the end of the coaxial line close to the superconducting quantum chip, the inner metal core is exposed and forms a plane with the outer metal and the intermediate medium layer of the coaxial line.

4. The scalable superconducting quantum chip packaging box according to claim 1, wherein the base has a groove for placing the superconducting quantum chip therein, and the depth of the groove is 0.2-1.0 mm.

5. The scalable superconducting quantum chip package box according to claim 1, wherein countersunk threaded holes are formed in the upper and lower surfaces of the base for compressing the coaxial lines.

6. The scalable superconducting quantum chip package of claim 1, wherein the base and the cover are made of a material with superconducting properties at mK temperature, such as aluminum, niobium, indium, tantalum, tin, or vanadium, and the central metal and the outer metal of the coaxial line are also made of a material with superconducting properties at mK temperature, so as to effectively isolate the superconducting quantum chip from the external environment, shield the external environment from noise, reduce energy loss, and better maintain the coherence of qubits on the chip.

Technical Field

The invention relates to the technical field of quantum chip packaging, in particular to an extensible superconducting quantum chip packaging box.

Background

In the scheme of realizing the superconducting quantum computation, effective control and reading of the superconducting quantum chip by using an external circuit are necessary steps. The circuit size of the superconducting quantum chip is in the micrometer scale, and the size of the external circuit is in the millimeter or centimeter scale, so that how to safely and efficiently switch the circuit of the quantum chip and the external circuit becomes a crucial problem. The superconducting quantum chip packaging box is a first-stage device for realizing connection of a superconducting quantum chip and an external circuit, and how to connect various performance pins of the superconducting quantum chip with corresponding external circuits becomes one of design problems in the industry.

Expanding the number of qubits on a chip is a necessary way to achieve quantum computation, and corresponding to the increase in the number of bits on a chip, the number of performance pins also increases. Therefore, how to connect the pins on the chip with the external circuit in the smallest space possible becomes a problem to be considered. In addition, the status of qubits in a quantum chip is very fragile and susceptible to interference from the environment and decoherence if not effectively protected.

Although the conventional PCB packaging technology is easy to achieve a high integration level, it cannot shield noise from external environment well and introduces loss. Another packaging technique typically installs connectors on the sides of the enclosure to establish the connection between the chip circuitry and the external circuitry, and the very limited area of the sides of the enclosure and the size of the connectors limit the number of connectors that can be installed, wasting a lot of space on the sample and enclosure. With the increasing number of quantum bits, the low-efficiency connection mode is difficult to expand and realize high-density wiring, so that a new packaging mode is required to realize high-integration and expandable quantum chip connection.

Disclosure of Invention

The invention aims to provide an extensible packaging box of a superconducting quantum chip aiming at the defects of the prior art.

The purpose of the invention is realized by the following technical scheme: an expandable superconducting quantum chip package, comprising: a base and a cover plate; two grooves are dug in the base and are respectively used for placing the coaxial line and the superconducting quantum chip; the two grooves are both positioned in the center of the base, and the groove for placing the superconducting quantum chip is positioned below the groove for placing the coaxial line; the side surface of the groove for placing the coaxial line is provided with a longitudinal multi-row hole array for installing the coaxial line to transmit microwave signals; the number of the longitudinal multi-row hole arrays can be expanded and is determined according to the number of bits on the superconducting quantum chip; the coaxial line is cut at one end close to the superconducting quantum chip and is used as a signal layer electrode connected with a performance pin of the superconducting quantum chip; the cover plate corresponds to one surface of the base with the groove and is tightly attached to the base.

Further, when the cover plate covers the base, the groove in the base and the cover plate are matched to form a sealed cavity structure.

Furthermore, the coaxial line penetrates through the longitudinal multi-row hole array and extends into the sealed cavity from the outside, and after one end of the coaxial line close to the superconducting quantum chip is subjected to cutting treatment, the inner metal needle core is exposed and forms a plane with the outer metal and the middle medium layer of the coaxial line.

Furthermore, the inside recess that is used for placing superconductive quantum chip of base, the degree of depth range is 0.2 ~ 1.0 mm.

Furthermore, countersunk threaded holes are formed in the upper surface and the lower surface of the base and used for compressing the coaxial lines.

Furthermore, the base and the cover plate are made of materials with superconducting properties at the mK temperature level, such as aluminum, niobium, indium, tantalum, tin or vanadium, and the central metal and the outer metal of the coaxial line are also made of materials with superconducting properties at the mK temperature level, so that the superconducting quantum chip can be effectively isolated from the external environment, the noise of the external environment is shielded, the energy loss is reduced, and the coherence of the quantum bit on the chip is better maintained.

The invention has the following benefits: according to the extensible encapsulation box of the superconducting quantum chip, signals on the quantum chip are led out through the third longitudinal dimension, more signal layer electrodes are accommodated on the premise that the size of the base is not enlarged, the space is effectively saved, and integration of superconducting quantum bits is facilitated; the coaxial line and the base and the cover plate can be made of different materials according to requirements, and the materials are selected with great freedom.

Drawings

Fig. 1a is a schematic front structure diagram of a quantum chip packaging box according to an embodiment of the present invention;

fig. 1b is a schematic back structure diagram of a quantum chip packaging box according to an embodiment of the invention;

fig. 2a is a schematic view of a near-sighted structure of a base without a chip of a quantum chip packaging box according to an embodiment of the invention;

FIG. 2b is a schematic view of a close-up structure of a base of a chip placed in a quantum chip packaging box according to an embodiment of the present invention;

FIG. 2c is a schematic cross-sectional view of the packaging box of the embodiment of the invention after being packaged in a superconducting quantum chip;

element number description: 100. a cover plate; 101. countersunk through holes; 102. a base; 103. a coaxial line; 104. a countersunk threaded hole in the lower surface of the base; 105. a countersunk threaded hole in the upper surface of the base; 106. a threaded hole; 107. a groove for placing a coaxial line is arranged in the base; 108. a groove for placing a chip in the base; 109. a signal layer electrode; 110. a superconducting quantum chip.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. It should be noted that, in the drawings and the description, the same reference numerals are used for the same parts. Implementations not depicted or described in the drawings are of a form known to those of ordinary skill in the art. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

The invention provides an extensible packaging box of a superconducting quantum chip, which comprises: a base and a cover plate; two grooves are dug in the base and used for containing the coaxial line and the superconducting quantum chip respectively, the grooves used for containing the superconducting quantum chip are formed in the base, and the depth range is 0.2-1.0 mm. The two grooves are both positioned in the center of the base, and the groove for placing the superconducting quantum chip is positioned below the groove for placing the coaxial line; the side surface of the groove for placing the coaxial line is provided with a longitudinal multi-row hole array for installing the coaxial line to transmit microwave signals, and the upper surface and the lower surface of the base are provided with countersunk threaded holes for compressing the coaxial line; the number of the longitudinal multi-row hole arrays can be expanded and is determined according to the number of bits on the superconducting quantum chip; the coaxial line penetrates through the longitudinal multi-row hole array and extends into the sealed cavity from the outside, one end of the coaxial line close to the superconducting quantum chip is subjected to cutting treatment, so that an internal metal needle core is exposed, and a plane is formed by the coaxial line, the external metal of the coaxial line and the intermediate medium layer and serves as a signal layer electrode connected with a performance pin of the superconducting quantum chip; the cover plate corresponds to one surface of the base, which is dug with the groove, and is tightly attached to the base, and when the cover plate covers the base, the groove in the base and the cover plate are matched to form a sealed cavity structure.

The base and the cover plate are made of materials with superconductivity at the mK temperature magnitude, and can be made of aluminum, niobium, indium, tantalum, tin or vanadium, the central metal and the outer metal of the coaxial line are also made of materials with superconductivity at the mK temperature magnitude, the superconducting quantum chip can be effectively isolated from the external environment, noise of the external environment is shielded, energy loss is reduced, and coherence of quantum bits on the chip is better maintained.

The architecture of the embodiments of the present invention relies on the encapsulation of superconducting quantum chips, and fig. 1a and 1b provide the actual structure of the encapsulation box of a superconducting quantum chip. Fig. 1a is a front view and fig. 1b is a bottom view of a quantum chip package. The package of superconducting quantum chips comprises a cover plate 100 and a base plate 102. The cover plate 100 and the base plate 102 cooperate to form a sealed cavity structure.

As shown in fig. 1a, the cover plate 100 and the base plate 102 are both cylindrical in shape, and the diameters of the cover plate 100 and the base plate 102 are the same, as an example. Coaxial line 103 extends through the side wall of base 102 into the sealed cavity. The cover plate 100 has 4 countersunk through holes 101, the base plate 102 has 4 threaded holes 106 on the upper surface in fig. 2a, and the countersunk through holes 101 and the threaded holes 106 are mechanically connected to allow the cover plate 100 and the base plate 102 to be tightly fitted.

As shown in fig. 1b, the lower surface of the base 102 has three circles of countersunk screw holes 104 from inside to outside, into which screws can be inserted to press the coaxial wires 103. At the same time, the upper surface of the base 102 in fig. 2a also has three circles of countersunk threaded holes 105 from inside to outside, which are also used for placing screws to compress the coaxial line 103. The coaxial line 103 is fixed by pressing the coaxial line 103 up and down.

Fig. 2a is a schematic view of a close-up structure of a packaging box of a superconducting quantum chip without a chip base. Two grooves are provided in the base 102. As an example, the groove 107 for placing the coaxial line in the base is a square groove, and the inner wall is sloped in the longitudinal direction. The side of the groove 107 penetrates through the outer wall of the base 102 through a longitudinal three-row hole array for inserting the coaxial line 103. The section of the coaxial line 103 extending into the groove 107 is cut to expose the inner metal needle core, and forms a plane with the outer metal and the middle medium layer of the coaxial line, and the plane is used as a signal layer electrode 109 connected with a performance pin of the quantum chip. The groove 108 for placing the chip in the base is a square groove, and the depth of the groove 108 is 1.0 mm.

Fig. 2b is a schematic structural diagram of the superconducting quantum chip placed on the base of fig. 2a, and the superconducting quantum chip 110 is placed on the groove 108.

As shown in fig. 2c, a longitudinal three-row hole array is arranged on the side of the base 102, and a groove 107 for placing a coaxial line is arranged through the outer wall and the inner part of the base 102. The coaxial line 103 extends into the groove 107 through the longitudinal three-row hole array, and the extended end is cut to be used as a signal layer electrode 109 to be connected with a performance pin on the quantum chip. The signal layer electrodes are distributed in three longitudinal rows by means of three longitudinal rows of hole arrays, the external transmission quantity of quantum chip signals is expanded on the basis that the size of the base is not changed, the space is effectively saved, and the quantum chip array substrate is more integrated.

By way of example, the material used for the cover plate 100 and base plate 102 is aluminum 6061-T6. The material used for the central metal and the outer metal of coaxial line 103 is niobium.

The above-described embodiments are intended to illustrate rather than to limit the invention, and any modifications and variations of the present invention are within the spirit of the invention and the scope of the appended claims.