阅读说明：本技术 数据及电力隔离屏障 (Data and power isolation barrier ) 是由 D·B·拉贾帕克沙 R·施佩利希 A·S·卡马特 V·德瓦拉詹 W·拉伊 于 2020-06-24 设计创作，主要内容包括：一种半导体封装包含具有初级绕组(L1)及次级绕组(L2)的变压器(T1)。所述初级绕组(L1)具有第一及第二端子以及一对抽头。所述次级绕组(L2)具有第一及第二端子以及一对抽头。所述半导体封装包含第一及第二数据传送电路(110、140)、电桥(120)及整流器(130)。所述第一数据传送电路(110)耦合到所述初级绕组(L1)的所述对抽头。所述第二数据传送电路(140)耦合到所述次级绕组(L2)的所述对抽头。所述电桥(120)耦合到所述初级绕组(L1)的所述第一及第二端子。所述整流器(130)耦合到所述次级绕组(L2)的所述第一及第二端子。(A semiconductor package includes a transformer (T1) having a primary winding (L1) and a secondary winding (L2). The primary winding (L1) has first and second terminals and a pair of taps. The secondary winding (L2) has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits (110, 140), a bridge (120), and a rectifier (130). The first data transmitting circuit (110) is coupled to the pair of taps of the primary winding (L1). The second data transfer circuit (140) is coupled to the pair of taps of the secondary winding (L2). The bridge (120) is coupled to the first and second terminals of the primary winding (L1). The rectifier (130) is coupled to the first and second terminals of the secondary winding (L2).)

1. A semiconductor package, comprising:

a transformer having a primary winding and a secondary winding, the primary winding having first and second terminals and a pair of taps, and the secondary winding having first and second terminals and a pair of taps;

a first data transfer circuit coupled to the pair of taps of the primary winding;

a second data transfer circuit coupled to the pair of taps of the secondary winding;

a bridge coupled to the first and second terminals of the primary winding; and

a rectifier coupled to the first and second terminals of the secondary winding.

2. The semiconductor package of claim 1, further comprising:

a first die including the first data transfer circuit and the bridge; and

a second die including the rectifier and the second data transfer circuit.

3. The semiconductor package of claim 2, further comprising a third die including the transformer.

4. The semiconductor package of claim 1, further comprising:

a first die including the first data transfer circuit and the bridge; and

a second die including the transformer.

5. The semiconductor package of claim 1, wherein:

the first data transfer circuit includes a first modulator and a first oscillator, the first modulator configured to modulate a first data input signal using a first clock signal from the first oscillator; and

the bridge includes first, second, third, and fourth transistors and a first controller coupled to the first, second, third, and fourth transistors.

6. The semiconductor package of claim 5, wherein the first controller is configured to operate the first, second, third, and fourth transistors at a first frequency, and the first clock signal from the first oscillator has a second frequency different from the first frequency.

7. The semiconductor package of claim 6, wherein the second frequency is at least ten times the first frequency.

8. The semiconductor package of claim 5, wherein:

the second data transmitting circuit includes a second modulator and a second oscillator, the second modulator configured to modulate a second data input signal using a second clock signal from the second oscillator.

9. The semiconductor package of claim 8, wherein:

the first data transfer circuit includes a first demodulator configured to demodulate a data signal generated on the primary winding; and is

The second data transmitting circuit includes a second demodulator configured to demodulate a data signal generated on the secondary winding.

10. An apparatus, comprising:

a transformer having a primary winding and a secondary winding, the primary winding having first and second terminals and a center tap, and the secondary winding having first and second terminals and a center tap, the center tap of the primary winding being coupled to a supply voltage node, and the center tap of the secondary winding providing an isolated ground;

a first data transfer circuit coupled to the first and second terminals of the primary winding;

a second data transfer circuit coupled to the first and second terminals of the secondary winding;

a transformer driver coupled to the first and second terminals of the primary winding; and

a rectifier having first and second rectifier inputs and a rectifier output, the first rectifier input coupled to the first terminal of the secondary winding and the second rectifier input coupled to the second terminal of the secondary winding.

11. The apparatus of claim 10, further comprising a voltage regulator having a voltage regulator input and a voltage regulator output, the voltage regulator input coupled to the rectifier output and the voltage regulator output providing an isolated output voltage.

12. The apparatus of claim 11, further comprising:

a first die including the first data transfer circuit and the transformer driver; and

a second die including the rectifier and the second data transfer circuit.

13. The apparatus of claim 12, wherein the second die also includes the voltage regulator.

14. The apparatus of claim 10, wherein the transformer driver comprises a push-pull circuit.

15. The apparatus of claim 10, wherein:

the first data transfer circuit includes a first transmitter, a first capacitor, and a second capacitor;

the first transmitter has first and second transmitter outputs;

the first capacitor is coupled between the first transmitter output and the first terminal of the primary winding; and is

The second capacitor is coupled between the second transmitter output and the second terminal of the primary winding.

16. A circuit, comprising:

a modulator having an input and an output;

an oscillator coupled to the input of the modulator;

a transmitter having an input and first and second outputs, the input of the transmitter coupled to the output of the modulator;

a transformer driver having first and second terminals configured to be coupled to terminals of a transformer;

a first capacitor coupled between the first output of the transmitter and the first terminal of the transformer driver; and

a second capacitor coupled between the second output of the transmitter and the second terminal of the transformer driver.

17. The circuit of claim 16, further comprising a receiver having first and second inputs and an output, the first input of the receiver being coupled to the first output of the transmitter and the second input of the receiver being coupled to the second output of the transmitter.

18. The circuit of claim 17, further comprising:

a filter having an input and an output, the input of the filter coupled to the output of the receiver; and

a demodulator having an input coupled to the output of the filter.

19. The circuit of claim 16, wherein the transformer driver includes:

a first transistor coupled to the first capacitor; and

a second transistor coupled to the second capacitor.

20. A circuit, comprising:

a modulator having an input and an output;

an oscillator coupled to the input of the modulator;

a transmitter having an input and first and second outputs, the input of the transmitter coupled to the output of the modulator;

a first capacitor having first and second terminals, the first terminal of the first capacitor being coupled to the first output of the transmitter, and the second terminal of the first capacitor being configured to be coupled to a first terminal of a transformer;

a second capacitor having first and second terminals, the first terminal of the second capacitor being coupled to the second output of the transmitter, and the second terminal of the second capacitor being configured to be coupled to a second terminal of the transformer; and

a rectifier having first and second rectifier inputs and an output, the first rectifier input coupled to the second terminal of the first capacitor and the second rectifier input coupled to the second terminal of the second capacitor.

21. The circuit of claim 20, further comprising a voltage regulator having an input, the input of the voltage regulator being coupled to the output of the rectifier.

Background

Some circuits benefit from isolation of power and data nodes of the circuit from other circuits and power nodes. For example, sensitive circuits in power tools or other types of high voltage machines benefit from isolation of such circuits from the AC (alternating current) power line.

Disclosure of Invention

In one example, a semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transmission circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

In yet another example, an apparatus includes a transformer, first and second data transfer circuits, a transformer driver, and a rectifier. The transformer has primary and secondary windings. The primary winding has first and second terminals and a center tap. The secondary winding has first and second terminals and a center tap. The center tap of the primary winding is coupled to a supply voltage node. The center tap of the secondary winding provides an isolated ground. The first data transfer circuit is coupled to the first and second terminals of the primary winding. The second data transmission circuit is coupled to the first and second terminals of the secondary winding. The transformer driver is coupled to the first and second terminals of the primary winding. The rectifier has first and second rectifier inputs and a rectifier output. The first rectifier input is coupled to the first terminal of the secondary winding. The second rectifier input is coupled to the second terminal of the secondary winding.

In yet another example, a circuit includes a modulator, an oscillator, a transmitter, a transformer driver, and first and second capacitors. The modulator has an input and an output. The oscillator is coupled to the input of the modulator. The transmitter has an input and first and second outputs. The input of the transmitter is coupled to the output of the modulator. The transformer driver has first and second terminals configured to be coupled to terminals of a transformer. The first capacitor is coupled between the first output of the transmitter and the first terminal of the transformer driver. The second capacitor is coupled between the second output of the transmitter and the second terminal of the transformer driver.

In another example, a circuit includes a modulator, an oscillator, a transmitter, a transformer driver, first and second capacitors, and a rectifier. The modulator has an input and an output. The oscillator is coupled to the input of the modulator. The transmitter has an input and first and second outputs. The input of the transmitter is coupled to the output of the modulator. The first capacitor has first and second terminals, wherein the first terminal of the first capacitor is coupled to the first output of the transmitter and the second terminal of the first capacitor is configured to be coupled to a first terminal of a transformer. The second capacitor has first and second terminals, wherein the first terminal of the second capacitor is coupled to the second output of the transmitter and the second terminal of the second capacitor is configured to be coupled to a second terminal of the transformer. The rectifier has first and second rectifier inputs and an output. The first rectifier input is coupled to the second terminal of the first capacitor, and the second rectifier input is coupled to the second terminal of the second capacitor.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

fig. 1 illustrates an example of an isolation circuit.

Fig. 2 illustrates a three-die device implementing the isolation circuit of fig. 1.

Fig. 3 illustrates another example of an isolation circuit.

Fig. 4 shows an example transformer driver usable in the isolation circuit of fig. 3.

Fig. 5 illustrates a multi-die implementation of the isolation circuit of fig. 3.

Fig. 6 illustrates another multi-die implementation of the isolation circuit of fig. 3.

Detailed Description

Some isolation barrier implementations include separate isolation barriers for data and power. Thus, one isolation barrier is used to isolate the data inputs and outputs of the circuit from external data connections, and another isolation barrier is used to isolate power. When separate isolation barriers are used for data and power, size and cost increase. In an example, one isolation barrier is used for both data and power. In this example, the data is modulated onto the same isolation channel as used for power isolation.

Fig. 1 shows an example of an isolation circuit 100. In this example, the isolation circuit 100 includes data transfer circuits 110 and 140, a bridge 120, a transformer T1, and a rectifier 130. The data path through the illustrated isolation circuit 100 is bi-directional. Thus, the DATA transfer circuit 110 includes a DATA input 95 that can receive incoming DATA (DATA IN 91) to be transferred through the isolation circuit 100 and output as output DATA (DATA OUT 94) via the DATA output 98 of the DATA transfer circuit 140. Similarly, the DATA transfer circuit 140 includes a DATA input 97 that can receive incoming DATA (DATA IN 93) to be transferred through the isolation circuit 100 and output as output DATA (DATA OUT 91) via the DATA output 96 of the DATA transfer circuit 110. A bridge 120 coupled to the primary winding L1 of transformer T1 receives an input voltage (VCC1) and a rectifier 130 coupled to the secondary winding L2 of transformer T1 provides an isolated output voltage VISO. VISO is galvanically isolated from VCC1 and GND 1. Transformer T1 is used to isolate both data and power.

The data transmission circuit 110 includes a data serializer 111, a modulator 112, an oscillator 113, a Transmitter (TX)114, a Receiver (RX)115, a band pass filter 116, a demodulator 117, a data deserializer 118, and capacitors C1 and C2. The data input 95 of the data transmission circuit 110 is an input to a data serializer 111. The output of the data serializer 111 is coupled to one input of the modulator 112. In one example, modulator 112 is a mixer. An oscillator 113 is coupled to another input of the modulator 112. An output of modulator 112 is coupled to an input of transmitter 114. The transmitter 114 has a positive output 150 and a negative output 151. The positive output 150 of the transmitter 114 is coupled to one terminal of a capacitor C1 and the positive input 152 of the receiver 115. The negative output 151 of the transmitter 114 is coupled to one terminal of a capacitor C2 and the negative input 153 of the receiver 115. An output of receiver 115 is coupled to an input of bandpass filter 116, and an output of bandpass filter 116 is coupled to an input of demodulator 117. The output of demodulator 117 is coupled to the input of DATA deserializer 118, and the output of the DATA deserializer provides DATA OUT 91.

Bridge 120 includes transistors PP0, PP1, PN0, and PN 1. In the configuration shown, the bridge 120 comprises a full bridge. In the example of fig. 1, PP0 and PP1 comprise p-type metal oxide semiconductor field effect transistors (PMOS), and PN0 and PN1 comprise n-type metal oxide semiconductor field effect transistors (NMOS). Different types of transistors may be used for other implementations. The sources of PP0 and PP1 are coupled together at node N1. Node N1 is also coupled to the input voltage node to receive an input voltage VCC 1. The drains of PP1 and PN1 are coupled together at node N2. The drains of PP0 and PN0 are coupled together at node N3. The sources of PN1 and PN0 are coupled together at ground node (GND 1). The controller 122 generates control signals 123, 124, 125, and 126 for the gates of the respective PP1, PP0, PN1, and PN0, as shown. Primary winding L1 has terminals 160 and 161. Terminal 160 is coupled to node N2, and terminal 161 is coupled to node N3.

In operation, controller 122 causes PP1 and PN0 to be simultaneously on (while PN0 and PN1 are off) and conversely causes PP0 and PN1 to be simultaneously on (while PP1 and PN0 are off). When both PP1 and PN0 are on, the VCC1 voltage is applied to terminal 160 of the primary winding L1, and ground GND1 is applied to terminal 161 of the primary winding. Conversely, when both PP0 and PN1 are on, the VCC1 voltage is applied to terminal 161 of the primary winding L1, and ground GND1 is applied to terminal 160 of the primary winding. Thus, the switching waveform is applied to the terminal of the primary winding L1 at the switching frequency (Fs) set by the controller 122.

Secondary winding L2 includes terminals 162 and 163 coupled to rectifier 130. Rectifier 130 comprises a full wave bridge rectifier including diodes D1 through D4. The cathodes of D1 and D2 are coupled together at node N4. The voltage at node N4 is the isolated output voltage VISO. The anode of D1 is coupled to cathode D3 at node N5, and the anode of D2 is coupled to cathode D4 at node N6. The anodes of D3 and D4 are coupled together and provide an isolated ground node (GISO). GISO is galvanically isolated from GND1 and VCCI. Terminal 162 of secondary winding L2 is coupled to node N6, and terminal 163 of the secondary winding is coupled to node N5. A capacitor C3 is coupled between terminals 162 and 163 across secondary winding L2.

The data transfer circuit 140 has an architecture similar to that of the data transfer circuit 140. The data transfer circuit 140 includes a data serializer 141, a modulator 142, an oscillator 143, a transmitter 144, a receiver 145, a band pass filter 146, a demodulator 147, a data deserializer 148, and capacitors C4 and C5. The data input 93 of the data transmission circuit 140 is an input to the data serializer 141. The output of the data serializer 141 is coupled to one input of the modulator 142. In one example, modulator 142 is a mixer. An oscillator 143 is coupled to another input of the modulator 142. An output of the modulator 142 is coupled to an input of a transmitter 144. The transmitter 144 has a positive output 170 and a negative output 171. The positive output 170 of the transmitter 144 is coupled to one terminal of a capacitor C4 and the positive input 172 of the receiver 145. The negative output 171 of the transmitter 144 is coupled to one terminal of a capacitor C5 and the negative input 173 of the receiver 145. An output of the receiver 145 is coupled to an input of a band pass filter 146, and an output of the band pass filter 146 is coupled to an input of a demodulator 147. An output of the demodulator 147 is coupled to an input of a DATA deserializer 148, and an output of the DATA deserializer provides DATA OUT 94.

The controller 122 turns the transistors PP0, PP1, MN0, and PN1 on and off as described above to generate a switching waveform across the primary winding L1 of the transformer T1. The capacitor C3 across the secondary winding L2 of the transformer helps set the resonant frequency of the secondary side of the transformer to be approximately the same as the switching frequency Fs of the switching waveform applied to the primary winding L1. By setting the resonant frequency equal to Fs, a large amount of power is transferred across the transformer to produce the isolated output voltage VISO. In one example, Fs is in the range of 20MHz to 100MHz (e.g., 25 MHz). The switching frequency may also be significantly less than 25MHz (e.g., 200KHz), but the size of the transformer would need to be increased (compared to Fs of 25 MHz). In one implementation, transformer T1 is fabricated on a semiconductor die (as illustrated by the example of fig. 3 and described below). If transformer T1 is forced to be significantly larger due to the use of small Fs (e.g., 200KHz), it may become infeasible to fabricate the transformer on a semiconductor die. If T1 is too large to be fabricated on a semiconductor die, T1 may be provided as an external device (i.e., outside the die containing the other components shown in FIG. 1).

Data is also magnetically transferred through the same isolation transformer T1 as the power. The DATA serializer 111 converts the DATA IN 90 from a parallel format to a serial format, represented IN FIG. 1 as Serial DATA (SD). In one example, the data serializer 111 may include a multiplexer. The frequency of SD is increased by modulator 112. The oscillator 113 generates a clock with a frequency significantly greater than the switching frequency Fs of the bridge 120. In one example, the frequency of oscillator 113 is 10 times, 20 times, etc. Fs. For example, if Fs is 25MHz, the frequency of oscillator 113 may be 250MHz or 500 MHz. Thus, the output signal from modulator 113 is a modulated version of SD and is shown as SDMOD.

The primary winding L1 of transformer T1 has a pair of taps 180 and 181 between external terminals 160 and 161. The taps may be positioned so as to divide the primary winding into three portions. For example, the taps may be positioned to divide the primary winding into three equal portions. Capacitor C1 is coupled to tap 180 and capacitor C2 is coupled to tap 181. By coupling the data transfer circuit 110 to the center taps 180, 181 of L1 instead of the terminals 160, 162 of L1, it is ensured that the data transfer circuit 110 will not be coupled to a low impedance load — if terminals 160 and 161 are used, the data transfer circuit 110 will experience a low impedance load through the transistors of the bridge 120 when the opposite transistor pair is flipped between VCC1 and GND 1. Similarly, the secondary winding L2 of transformer T1 also has a pair of center taps 190 and 191. Capacitor C4 is coupled to tap 190 and capacitor C5 is coupled to tap 191.

SDMOD is provided by transmitter 150 to taps 180, 181 of primary winding L1. Corresponding signals (at the same frequency as the SDMOD) are generated on taps 190, 192 of secondary winding L2 and provided to receiver 145. The receiver provides the received signal to a band pass filter 146, the center frequency of the band pass filter 146 being approximately centered on the carrier frequency of the received data signal to attenuate noise at higher and lower frequencies. The demodulator 147 then demodulates the DATA signal back to its original DATA rate, and the DATA deserializer 148 converts the serial signal back to a parallel format as DATA OUT 94.

Data transferred in the opposite direction through the isolation circuit 100 is processed in much the same manner as described. DATA serializer 141 converts DATA IN 93 to serial format and modulator 142 modulates the serial DATA signal to a higher frequency (significantly higher than Fs) using oscillator 143. The higher frequency modulated data signals are provided to taps 190 and 191 of the secondary winding and corresponding data signals are generated on taps 180 and 181 of the primary winding. The receiver 115 receives a higher frequency data signal. The bandpass filter 116 filters it and the demodulator 117 converts the higher frequency data signal back to its original data rate. The DATA deserializer 118 converts the recovered DATA signal back into a parallel format as DATA OUT 91.

Fig. 2 illustrates an example of a semiconductor package (also referred to as a "chip") 200 that includes the isolation circuit 100. The semiconductor package 200 in this example includes three dice 220, 230, and 240. All three dice 220, 230, and 240 are encapsulated by molding compound 210 to form a single semiconductor package. Each die has a different portion of the isolation circuit 100 of fig. 1. Die 220 includes data transfer circuitry 110 and bridge 120. Die 230 includes transformer T1. Die 240 includes rectifier 130 and data transfer circuit 140.

Fig. 3 shows another example of an isolation circuit 300. In this example, isolation circuit 300 includes data transfer circuits 310 and 350, transformer driver 320, transformer T2, rectifier 330, and voltage regulator 340 (e.g., a low dropout voltage regulator). As with the isolation circuit 100, the data path through the isolation circuit 300 is bidirectional. Thus, the DATA transfer circuit 310 includes a DATA input 395, which can receive incoming DATA (DATA IN 301) to be transferred through the isolation circuit 300 and output as output DATA (DATA OUT 304) via the DATA output 398 of the DATA transfer circuit 350. Similarly, the DATA transfer circuit 350 includes a DATA input 397 that may receive incoming DATA (DATA IN 303) to be transferred through the isolation circuit 300 and output as output DATA (DATA OUT 302) via a DATA output 396 of the DATA transfer circuit 310.

Transformer T2 includes a primary winding L3 and a secondary winding L4. The primary winding L3 has opposing terminals 380 and 381, and the secondary winding L4 has opposing terminals 333 and 384. Each winding of the transformer T2 is tapped centrally. Primary winding L3 includes a center tap 382 and secondary winding L4 includes a center tap 385. A center tap 382 of primary winding L3 receives input voltage VIN. The output of voltage regulator 340 provides an isolation Voltage (VISO) that is galvanically isolated from VIN. The center tap 385 of secondary winding L4 is connected to isolation Ground (GISO), which is galvanically isolated from the ground reference on the primary side of transformer T2.

The data transmitting circuit 310 includes a data serializer 311, a modulator 312, an oscillator 313, a transmitter 314, a receiver 315, a band-pass filter 316, a demodulator 317, a data deserializer 318, and capacitors C31 and C32. The data input 395 of the data transmission circuit 310 is an input to the data serializer 311. The output of the data serializer 311 is coupled to one input of a modulator 312. In one example, modulator 312 is a mixer. An oscillator 313 is coupled to another input of the modulator 312. An output of the modulator 312 is coupled to an input of a transmitter 314. Emitter 314 has a positive output 370 and a negative output 371. The positive output 370 of the transmitter 314 is coupled to one terminal of a capacitor C31 and the positive input 372 of the receiver 315. A negative output 371 of transmitter 314 is coupled to one terminal of capacitor C32 and a negative input 373 of receiver 315. An output of the receiver 315 is coupled to an input of a band pass filter 316, and an output of the band pass filter 316 is coupled to an input of a demodulator 317. The output of demodulator 317 is coupled to the input of DATA deserializer 318, and the output of the DATA deserializer provides DATA OUT 302.

Transformer driver 320 is coupled across primary winding L3 of transformer T2 (e.g., to terminals 380 and 381). In one example (as will be illustrated in fig. 4 and described below), the transformer driver 320 is configured to operate as a "push-pull" converter.

Rectifier 330 is coupled across (i.e., connected to terminals 383 and 384) the secondary winding L4 of transformer T2. In the example shown in fig. 3, rectifier 330 includes zener diodes Z1 and Z2. The anode of Z1 is coupled to terminal 383 of secondary winding L4 and the anode of Z2 is coupled to terminal 384 of the secondary winding. The cathodes of Z1 and Z2 are coupled together at node N31 and to the input of the voltage regulator 340. The voltage at node N31 is isolated from VIN and the ground reference for VIN and is further converted to an isolated output voltage VISO by voltage regulator 340.

The data transfer circuit 350 has an architecture similar to that of the data transfer circuit 310. The data transfer circuit 350 includes a data serializer 351, a modulator 352, an oscillator 353, a transmitter 354, a receiver 355, a band pass filter 356, a demodulator 357, a data deserializer 358, and capacitors C33 and C34. The data input 303 of the data transmission circuit 350 is an input to the data serializer 351. The output of the data serializer 351 is coupled to one input of the modulator 352. In one example, modulator 352 is a mixer. An oscillator 353 is coupled to another input of the modulator 352. An output of the modulator 352 is coupled to an input of a transmitter 354. The transmitter 354 has a positive output 374 and a negative output 375. The positive output 374 of the transmitter 354 is coupled to one terminal of a capacitor C33 and the positive input 376 of the receiver 355. The negative output 375 of the transmitter 354 is coupled to one terminal of a capacitor C34 and the negative input 377 of the receiver 355. The output of receiver 355 is coupled to the input of bandpass filter 356, and the output of bandpass filter 356 is coupled to the input of demodulator 357. The output of demodulator 357 is coupled to the input of DATA deserializer 358, and the output of the DATA deserializer provides DATA OUT 304.

Fig. 4 shows an example implementation of transformer driver 320. In this example, transformer driver 320 includes transistors M1 and M2 and controller 409. M1 and M2 include NMOS transistors, but may include other types of transistors. The controller 409 is coupled to the gates of M1 and M2 and provides control signals to the respective gates. The controller 409 turns on M1 and M2 in reverse so that both M1 and M2 are not turned on at the same time. Thus, M1 turns on when M2 turns off, and then M2 turns on when M1 turns off. Each cycle includes a period of time when neither transistor is on. When one of M1 and M2 is turned on, VIN is applied between the center tap 382 and ground, with current flowing from the center tap 381 to the drain of the turned on transistor. The voltage is reversed across the non-conductive half of primary winding L3 to maintain volt-second balance, thereby generating 2 VIN across primary winding L3 between terminals 380 and 381. The same voltage is generated across each corresponding half of secondary winding L4, but scaled by a factor of N (the turns ratio of transformer T2).

Returning to fig. 3, data transfer circuit 310 is coupled to terminals 380 and 381 of the primary winding L3 of transformer T2, and data transfer circuit 350 is coupled to terminals 383 and 384 of the secondary winding. More specifically, C31, C32, C33, and C34 are coupled to respective terminals 380, 381, 383, and 384. Data to be transmitted across the transformer T2 is synchronized with the operation of the transformer driver 320 so that when the corresponding transistor M1/M2 (fig. 4) coupled to the respective transformer terminal is turned off, the output of the transmitter provides a data signal to that terminal. For example, when M1 (which is coupled to terminal 380) is off, transmitter output 370 (which is also coupled to terminal 380 through capacitor C31) provides its data signal to terminal 380. Transformer driver 320 has power transistors M1 and M2, which turn on and off at a relatively low frequency (e.g., 300 KHz). When the gate of M1 of fig. 4 is 0V, controller 409 in fig. 4 may signal the emitter (via control signal 411). At this point, the transmitter may drive a high frequency RF signal to terminal 380.

The transformer secondary terminals 383 and 384 swing between the + ve and-ve voltages (e.g., +6V and-6V) around the GISO, while node N31 is at a constant output voltage (e.g., 6V minus one diode drop, or the voltage of N31 is approximately 5.5V). When terminal 383 is at the-ve potential diode, Z1 is reverse biased and terminal 383 is at a relatively high impedance. At this point, RF signal 413 may be coupled between terminals 383 (and 384) and transmitter 354. This can be illustrated in the picture by showing the connections between 383, 384 and the emitters. While coordination between the transmitter and the transformer driver 320 may improve the efficiency of the communication, in some implementations, coordination between the transmitter and the transformer driver is not present — the transmitter may keep transmitting high frequency signals and when the transformer is at high impedance (e.g., every alternating cycle) it will naturally couple to the transformer.

Fig. 5 illustrates an example in which the isolation circuit 300 is fabricated as three separately packaged devices-die 410, die 420, and transformer T2. Each die 410, 420 has a different portion of the isolation circuit 300 of figure 3. Die 410 includes data transfer circuitry 310 and transformer driver 320. Die 420 includes rectifier 330, voltage regulator 340, and data transfer circuit 350. Alternatively, the components of dies 410 and 420 may be fabricated on a single die with transformer T2 packaged separately.

Fig. 6 illustrates an example in which isolation circuit 300 is fabricated as four separately packaged devices-die 410, die 510, die 520, and transformer T2. Each die 410, 510, and 520 has a different portion of the isolation circuit 300 of figure 3. Die 410 includes data transfer circuitry 310 and transformer driver 320. Die 510 includes rectifier 330. Die 520 includes voltage regulator 340 and data transfer circuit 350.

The term "coupled" is used throughout this specification. The terms may cover a connection, communication, or signal path capable of performing a functional relationship consistent with the description herein. For example, in a first example, device a is coupled to device B if device a generates a signal to control device B to perform an action, or in a second example, device a is coupled to device B through intermediary component C if intermediary component C does not substantially alter the functional relationship between device a and device B such that device B is controlled by device a via the control signal generated by device a.

Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.