阅读说明：本技术 一种半导体器件及其可靠性验证方法 (Semiconductor device and reliability verification method thereof ) 是由 陈治中 廖童佳 王华辉 史波 于 2019-11-05 设计创作，主要内容包括：本申请所提供的一种半导体器件及其可靠性验证方法,该半导体器件包括：至少两个芯片、框架以及引脚,其中,所述框架为具有至少两个格子的格子结构,每个所述格子内均设置有一个所述芯片,所述引脚包括第一引脚和第二引脚,所述第一引脚与框架相连,所述第二引脚通过导线与格子内的芯片连接；本申请可以同时将多种塑封料塑封在同一个器件,一个器件验证了多种塑封料,增加塑封料与芯片验证组合方式,对于任何一种芯片与各种塑封料匹配情况可以同步验证,并且可以同时验证多种芯片漏电情况,通过不同组合来验证长期漏电增长问题,使得研发周期、成本和效率方面具有更好的研发竞争力。(The application provides a semiconductor device and a reliability verification method thereof, wherein the semiconductor device comprises: the chip packaging structure comprises at least two chips, a frame and pins, wherein the frame is of a lattice structure with at least two lattices, one chip is arranged in each lattice, the pins comprise first pins and second pins, the first pins are connected with the frame, and the second pins are connected with the chips in the lattices through wires; this application can be simultaneously with multiple plastic packaging material plastic envelope in same device, multiple plastic packaging material has been verified to a device, increases plastic packaging material and chip verification combination mode, can verify in step to any kind of chip and various plastic packaging material matching conditions to can verify multiple chip electric leakage condition simultaneously, verify long-term electric leakage through different combinations and increase the problem, make have better research and development competitiveness in the aspect of research and development cycle, cost and efficiency.)

1. A semiconductor device, comprising:

at least two chips, a frame, and pins, wherein,

the frame is a lattice structure with at least two lattices, one chip is arranged in each lattice,

the pins comprise a first pin and a second pin, the first pin is connected with the frame, and the second pin is connected with the chip in the grid through a wire.

2. The semiconductor device of claim 1, wherein the bottom of the chip is connected to the frame and the top of the chip is connected to the second lead by a wire.

3. The semiconductor device according to claim 1, wherein the frame has a two-row four-column lattice structure, and eight chips are respectively disposed in eight lattices of the frame.

4. The semiconductor device of claim 1, wherein the chips in the lattice are of the same or different model.

5. The semiconductor device according to claim 1, further comprising a mold section for packaging each of the chips in the lattice.

6. The semiconductor device according to claim 5, wherein the molding part is formed by filling or injecting the same or different molding materials into each of the cells, respectively.

7. The semiconductor device according to claim 1, wherein the frame comprises a bottom plate for carrying a chip, side plates surrounding the bottom plate, and spacers for forming the lattice, both ends of the spacers are connected to the side plates, respectively, and one side of the spacer is connected to the bottom plate.

8. The semiconductor device of claim 1, wherein the frame is a one-piece stamped and formed frame copper frame.

9. A method for plastic packaging of a semiconductor device according to any of claims 1-8, comprising the steps of:

processing the frame into a lattice structure having at least two lattices to form a plurality of independent chip bonding areas;

welding the chip on the frame;

welding the first pin on the frame, and connecting the lead wires of each chip in the lattice of the frame with the second pin;

and respectively carrying out glue pouring or injection molding on the plurality of chip welding areas.

10. A method of verifying reliability for a semiconductor device according to any one of claims 1 to 8, comprising:

taking a first pin of the semiconductor device as a common cathode, and applying a forward voltage to the first pin;

respectively taking second pins of the semiconductor device as anodes to receive output signals, wherein the output signals are respectively leakage information of corresponding chips;

and feeding back the leakage trend of the semiconductor device through the leakage information.

Technical Field

The application relates to the technical field of plastic packaging, in particular to a semiconductor device and a reliability verification method thereof.

Background

At the present research and development stage, for a plastic package device, the matching condition of a plastic package material and a chip is verified through an HTRB reliability experiment, the matching verification can be performed only through one plastic package material of injection molding or glue pouring, and the matching condition of one chip and the plastic package material can only be verified singly. Moreover, long-term electric leakage growth verification cannot be detected through the existing experimental analysis means, and the fundamental reason of electric leakage growth cannot be checked and verified, so that the research and development cost is high, and the verification period is long.

Therefore, a semiconductor device, a plastic packaging method and a reliability verification method are needed to solve the problems that the matching condition of the chip and various plastic packaging materials and the leakage condition of various chips cannot be verified simultaneously.

Disclosure of Invention

Aiming at the defects of the prior art, the application provides a semiconductor device, a plastic packaging method and a reliability verification method, and aims to solve the problems that the matching condition of a chip and various plastic packaging materials cannot be verified synchronously and the long-term leakage growth verification cannot be detected by the conventional experimental analysis means in the prior art.

In order to solve the above technical problem, in a first aspect, the present application provides a semiconductor device, including:

at least two chips, a frame, and pins, wherein,

the frame is a lattice structure with at least two lattices, one chip is arranged in each lattice,

the pins comprise a first pin and a second pin, the first pin is connected with the frame, and the second pin is connected with the chip in the grid through a wire.

Preferably, the bottom of the chip is connected with the frame, and the top of the chip is connected with the second pin through a wire.

Preferably, the frame is a two-row and four-column lattice structure, and the eight chips are respectively arranged in the eight lattices of the frame.

Preferably, the frame is a two-row and four-column lattice structure, and the chips in the lattice are of the same or different types. Preferably, the package structure further comprises a plastic package part for packaging each chip in the grid.

Preferably, the plastic package part is formed by respectively filling glue into each of the cells or injecting the same or different plastic package materials.

Preferably, the frame includes a bottom plate for carrying the chip, side plates surrounding the bottom plate, and a spacer for forming the lattice, both ends of the spacer are connected to the side plates, respectively, and one side of the spacer is connected to the bottom plate.

Preferably, the frame is a copper frame formed by integral stamping and forming.

In a second aspect, the present application provides a method for plastic packaging of a semiconductor device, comprising the steps of:

processing the frame into a lattice structure having at least two lattices to form a plurality of independent chip bonding areas;

welding the chip on the frame;

welding the first pin on the frame, and connecting the lead wires of each chip in the lattice of the frame with the second pin;

and respectively carrying out glue pouring or injection molding on the plurality of chip welding areas.

Preferably, the bottom of the chip is connected with the frame, and the top of the chip is connected with the second pin through a wire.

Preferably, the frame is a two-row and four-column lattice structure, and eight chips are respectively welded in eight lattices of the frame.

Preferably, a chip of the same or different type is welded in each grid of the frame.

Preferably, the same or different plastic packaging materials are poured or injected in the chip welding area.

Preferably, the frame includes a bottom plate for carrying the chip, side plates surrounding the bottom plate, and a spacer for forming the lattice, both ends of the spacer are connected to the side plates, respectively, and one side of the spacer is connected to the bottom plate.

Preferably, the frame is a copper frame formed by integral stamping and forming.

In a third aspect, the present application provides a reliability verification method for the above semiconductor device, including:

taking a first pin of the semiconductor device as a common cathode, and applying a forward voltage to the first pin;

respectively taking second pins of the semiconductor device as anodes to receive output signals, wherein the output signals are respectively leakage information of corresponding chips;

and feeding back the leakage trend of the semiconductor device through the leakage information.

Compared with the prior art, the method has the following beneficial effects:

1. compared with the traditional scheme, the chip packaging method has the advantages that each chip is independently opened by designing the special frame, various chips and plastic packaging materials can be simultaneously packaged in the same device, and the problem of one-time plastic packaging of the chips is solved.

2. On the basis of chip independence, multiple plastic packaging materials can be matched, one device verifies multiple plastic packaging materials, the combination mode of the plastic packaging materials and chip verification is increased, the verification of the matching degree of the plastic packaging materials and the chip in the original packaging scheme is kept, the advantages are added, the period and the cost for verifying the matching of the plastic packaging materials and the chip are greatly reduced, and the research and development efficiency is improved;

3. this application has adopted special frame to verify the technique in HTRB reliability experiment, can verify in step to any kind of chip and various plastic-sealed materials matching condition to can verify multiple chip electric leakage condition simultaneously, solve the matching condition of chip and different plastic-sealed materials and multiple chip electric leakage condition verification problem, provide one kind and verify long-term electric leakage and increase research means, have instructive direction to the research and development, shorten research and development cycle, greatly reduced research and development cost.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a semiconductor device provided in the prior art;

fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

fig. 3 is a flowchart of a method for plastic packaging a semiconductor device according to an embodiment of the present disclosure;

fig. 4 is a flowchart of plastic HTRB verification of a semiconductor device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The noun explains:

HTRB: high temperature reverse Bias test, i.e. a reverse voltage of 80% is continuously provided under High temperature (the ambient temperature of the acid-washed chip is 125 ℃, the ambient temperature of the glass passivated chip is 150 ℃, and the ambient temperature of the schottky chip is 100 ℃). The reverse leakage current of the test specimens is required to be stable over a range of values over long periods of operation (48/96/168 hours). In the development stage, HTRB (high temperature reverse bias) is generally used to verify the reliability of the device and detect the leakage information of the device, thereby verifying the matching degree between the molding compound and the chip.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device provided in the prior art, the semiconductor device including:

the chip comprises two chips and a frame, wherein three pins are led out of the frame, the two chips are respectively welded in the frame, and the two chips are respectively connected with the two pins through leads.

When the conventional semiconductor device is used for an HTRB experiment, a pin connected to a chip, namely a pin 1 and a pin 2 in fig. 1, is used as a semi-anode to receive an output signal, the other pin is used as a common cathode to apply a forward voltage, the output signal is leakage information of the corresponding chip, and the leakage trend of the whole HTRB experiment process is judged according to the leakage condition. Because the existing semiconductor device can only be matched and verified with the chip in the existing semiconductor device through injection molding or glue pouring of one plastic packaging material, synchronous verification of matching conditions of various chips and various plastic packaging materials cannot be realized, and electric leakage conditions of various chips cannot be verified at the same time.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device 200 according to an embodiment of the present disclosure, where the semiconductor device includes:

at least two chips 201, a frame 202, and pins 203, wherein,

the frame 202 is a lattice structure having at least two lattices, one chip 201 being disposed in each of the lattices,

the leads 203 include a first lead 203A and a second lead 203B, the first lead 203A is connected to the frame 202, and the second lead 203B is connected to the chip 201 in the grid through a wire 204.

Specifically, the first lead 203A is a common cathode lead and is directly connected to the frame 202, the second lead 203B is separated from the frame 202, and the second lead 203B is connected to the chip 201 in the grid through a wire 204. The first lead 203A can be led out from the middle position of the frame and connected with the frame 202, and the second lead 203B is led out from the chip 201 in each grid of the frame through a wire 204 and is not connected with the frame 202.

Based on the above embodiment, as a preferred embodiment, the bottom of the chip is connected to the frame, and the top of the chip is connected to the second pin through a wire.

Specifically, chip business turn over signal is in the bottom and the top of chip, and the welding of chip bottom is on copper frame, and the chip top need be with the pin of pin connection, and the chip just can normally input and output signal like this to carry out chip output signal's collection through the second pin, realize follow-up through HTRB reliability experiment verify multiple chip electric leakage increase problem and chip and various plastic-envelope material matching condition verify.

Based on the above embodiment, as a preferred embodiment, the frame has a two-row and four-column lattice structure, and eight chips are respectively disposed in eight lattices of the frame.

Specifically, when the frame 202 is a two-row and four-column lattice structure, the first pins 203A, that is, the pins 9, are led out from the middle positions of the copper frame 202, and eight second pins 203B, that is, the pins 1, 2, 3, 4, 5, 6, 7, and 8, are led out from the frame positions of each lattice, and the eight second pins 203B are all connected with the chip 201 inside the lattice through the wires 204.

Based on the above embodiment, as a preferred embodiment, the frame 202 is a two-row and four-column lattice structure, and the chips 201 in the lattice are of the same or different models.

Based on the above embodiment, as a preferred embodiment, the semiconductor device further includes a mold sealing portion for sealing each of the chips in the lattice.

Based on the above embodiment, as a preferred embodiment, the plastic package part is formed by respectively filling glue or injecting the same or different plastic packages into each grid.

Based on the above embodiment, as a preferred embodiment, the frame 202 includes a bottom plate for carrying a chip, side plates surrounding the bottom plate, and spacers for forming the grid, two ends of the spacers are respectively connected to the side plates, and one side of the spacer is connected to the bottom plate.

Based on the above embodiment, as a preferred embodiment, the frame 202 is a copper frame formed by integral stamping.

Referring to fig. 3, fig. 3 is a flowchart illustrating a method for molding a semiconductor device according to an embodiment of the present disclosure, where the method 300 includes:

s301: stamping the frame to form a grid structure with two rows and multiple columns to form a plurality of independent chip welding areas;

s302: welding the chip on the frame;

s303: welding the first pin on the frame, and connecting the lead wires of each chip in the lattice of the frame with the second pin;

s304: and respectively performing glue pouring or injection molding on the plurality of chip welding areas in the injection molding of the packaging process.

Based on the above embodiment, as a preferred embodiment, the frame has a two-row and four-column lattice structure, and eight chips are respectively soldered in eight lattices of the frame.

Based on the above embodiment, as a preferred embodiment, one chip of the same or different type is soldered in each cell of the frame.

Based on the above embodiment, as a preferred embodiment, the same or different molding compounds are poured or injected in the chip bonding area.

Based on the above embodiment, as a preferred embodiment, the frame includes a bottom plate for carrying a chip, side plates surrounding the bottom plate, and spacers for forming the grid, two ends of the spacers are respectively connected to the side plates, and one side of the spacer is connected to the bottom plate.

Based on the above embodiment, as a preferred embodiment, the frame is a copper frame formed by integral stamping and forming.

Referring to fig. 4, fig. 4 is a flowchart of a method for verifying reliability of a semiconductor device according to an embodiment of the present application, where the method 400 includes:

s401: taking a first pin of the semiconductor device as a common cathode, and applying a forward voltage to the first pin;

s402: respectively taking second pins of the semiconductor device as anodes to receive output signals, wherein the output signals are respectively leakage information of corresponding chips;

s403: and feeding back the leakage trend of the semiconductor device through the leakage information.

Specifically, when the first pin of the semiconductor device is used as a common cathode, a forward voltage of 600V may be applied thereto, and a voltage signal output from the second pin of the semiconductor device may be received, so as to obtain leakage information of a corresponding chip according to a voltage value output from the second pin connected to different chips.

The main material of the chip is Si, and the surface of the chip is provided with a layer of Si oxide layer SiO₂Due to the presence of Si and SiO₂SiO 2 (m) is₂And the impurities in the plastic packaging material can have movable electrons under the action of an electric field, and the movable electrons form leakage current under the action of the electric field after being electrified, so that the leakage phenomenon of the chip is caused. The leakage that occurs at which level cannot be detected independently in the chip. Through the special frame of the proposal, the chip, Si and SiO are respectively encapsulated in each independent chip welding area₂Laminated sheet of SiO₂The chip and the plastic package material sheet (namely, the plastic package material sheet is directly fed to the pin lead) are subjected to an HTRB experiment for 1000 hours, the four online leakage conditions are detected simultaneously, the whole leakage trend is analyzed, and the leakage current can be verified on which layer, so that the leakage distribution condition can be researched.

In addition, the matching condition of the chip and the plastic packaging material is verified by detecting a leakage signal of the device through an HTRB experiment. The HTRB equipment can detect the leakage condition on line, such as continuous rising of the leakage, which indicates that the chip is not matched with the plastic package material. Through moulding plastics different types of plastic packaging material at different check, to same style chip, can verify multiple plastic packaging material and chip matching condition simultaneously.

Specifically, referring to fig. 2, the semiconductor device may be soldered to chips of different models, the same or different plastic packages are filled with glue or injected into a plurality of cells of the frame, and by combining the output signals of the pins 1 to 8 at will, matching conditions between any one chip and various plastic packages can be obtained, and leakage conditions of multiple chips can be verified at the same time.

Therefore, multiple plastic packaging materials can be simultaneously packaged in the same device, one device verifies multiple plastic packaging materials, and verification combination of the plastic packaging materials and the chip is increased, so that the period and cost for verifying the matching of the plastic packaging materials and the chip are greatly reduced, the research and development efficiency is improved, the advantages of the original packaging scheme on the verification of the matching degree of the plastic packaging materials and the chip are maintained, and the research and development competitiveness is better in the aspects of the research and development period, the cost and the efficiency; this application has adopted special frame to verify the technique in HTRB reliability experiment, can verify in step to any kind of chip and various plastic envelope material matching conditions to can verify multiple chip electric leakage condition simultaneously, verify long-term electric leakage through different combinations and increase the problem, provide one kind and verify long-term electric leakage and increase research means, have instructive direction to the development, the research and development cycle shortens, simultaneously greatly reduced cost.

The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system provided by the embodiment, the description is relatively simple because the system corresponds to the method provided by the embodiment, and the relevant points can be referred to the method part for description.

The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.