阅读说明：本技术 具有中介层桥的层叠封装 (Package-on-package with interposer bridge ) 是由 崔福奎 于 2020-07-10 设计创作，主要内容包括：具有中介层桥的层叠封装。一种层叠封装包括设置在封装基板上的下半导体芯片、包括通孔的中介层桥以及上半导体芯片。上半导体芯片具有彼此相反的第一边缘和第二边缘。上半导体芯片包括位于第一边缘和第二边缘之间的第一区域、第三区域和连接区域。上半导体芯片还包括将设置在第一区域和第三区域上的多个焊盘彼此连接的再分布层图案。再分布层图案延伸到连接区域上。(A package on package with an interposer bridge. A stacked package includes a lower semiconductor die, an interposer bridge including vias, and an upper semiconductor die disposed on a package substrate. The upper semiconductor chip has a first edge and a second edge opposite to each other. The upper semiconductor chip includes a first region, a third region and a connection region between a first edge and a second edge. The upper semiconductor chip further includes a redistribution layer pattern connecting the plurality of pads disposed on the first and third areas to each other. The redistribution layer pattern extends onto the connection area.)

1. A package on package, comprising:

a lower semiconductor chip disposed on the package substrate;

an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip, and including a through-hole; and

an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole,

wherein the upper semiconductor chip includes:

a first edge and a second edge opposite to each other;

a first region located between the first edge and the second edge;

a second region located between the first region and the first edge;

a third region located between the first region and the second edge;

a first connection region overlapping the through-hole;

a first power supply pad and a first signal pad disposed on the first region;

a second power supply pad disposed on the second region;

a third power supply pad disposed on the third region;

a first redistribution layer pattern connected to the first signal pad to extend onto the first connection region; and

a second redistribution layer pattern connecting the third power supply pad, the first power supply pad, and the second power supply pad to each other to extend onto the first connection area, and including a first extension extending from the third area to reach the first area,

wherein a width of the first extension is greater than a width of the first redistribution layer pattern.

2. The package on package of claim 1, wherein the second redistribution layer pattern further comprises:

a second extension having a width greater than a width of the first redistribution layer pattern and extending from the first region onto the first connection region; and

a third extension having a width less than a width of the second extension and connecting the first extension to the second extension.

3. The package on package of claim 1, wherein the second redistribution layer pattern is longer than the first redistribution layer pattern.

4. The package on package of claim 1, wherein the upper semiconductor chip further comprises:

a first ground pad disposed on the first region and on an opposite side of the first signal pad from the first power supply pad;

a second ground pad disposed on the second region;

a third ground pad disposed on the third region; and

a third redistribution layer pattern configured to connect the first, second, and third ground pads to each other and extend onto the first connection area, the third redistribution layer pattern configured to include an extension extending from the third area onto the first area and having a width greater than a width of the first redistribution layer pattern and configured to be located on an opposite side of the first redistribution layer pattern from the second redistribution layer pattern.

5. The package on package of claim 1, wherein the second region of the upper semiconductor chip is disposed to be spaced apart from the first region such that a distance between the second region and the first edge is smaller than a distance between the second region and the first region.

6. The package on package of claim 1, wherein the package is a single package,

wherein the third region of the upper semiconductor chip is spaced apart from the first region such that a distance between the third region and the second edge is smaller than a distance between the third region and the first region; and is

Wherein the third region of the upper semiconductor chip is located on an opposite side of the first region from the second region.

7. The package on package of claim 1, wherein the first region and the third region of the upper semiconductor chip overlap with the lower semiconductor chip.

8. The package on package of claim 1, wherein the first connection region of the upper semiconductor chip is spaced apart from the first region such that a distance between the first connection region and the first edge is smaller than a distance between the first connection region and the first region.

9. The package on package of claim 1, further comprising:

a first inner connector disposed between the interposer bridge and the first connection region of the upper semiconductor chip to electrically connect the via to the first redistribution layer pattern and the second redistribution layer pattern extending onto the first connection region; and

first support bumps disposed between the lower semiconductor chip and the upper semiconductor chip to support the upper semiconductor chip.

10. The package on package of claim 1, wherein the lower semiconductor chip comprises:

a third edge and a fourth edge opposite to each other;

a fourth region located between the third edge and the fourth edge;

a fifth region located between the fourth region and the third edge;

a sixth region located between the fourth region and the fourth edge;

a second connection region disposed adjacent to the third edge such that a distance between the second connection region and the third edge is less than a distance between the second connection region and the fourth region;

a fourth power supply pad and a second signal pad disposed on the fourth region;

a fifth power supply pad disposed on the fifth region;

a sixth power supply pad disposed on the sixth region;

a fourth redistribution layer pattern connected to the second signal pad to extend onto the second connection area; and

a fifth redistribution layer pattern connecting the sixth power supply pad, the fourth power supply pad, and the fifth power supply pad to each other to extend onto the second connection area.

11. The package on package of claim 10,

wherein the fifth redistribution layer pattern comprises a fourth extension extending from the sixth area to reach the fourth area; and is

Wherein a width of the fourth extension is greater than a width of the fourth redistribution layer pattern.

12. The package on package of claim 10, further comprising:

a second inner connector disposed between the package substrate and the second connection region of the lower semiconductor chip; and

second support bumps disposed between the package substrate and the lower semiconductor chip and between the fourth edge of the lower semiconductor chip and the second inner connectors.

13. The package on package of claim 1, wherein the interposer bridge further comprises a silicon substrate through which the via passes vertically.

14. A package on package, comprising:

a lower semiconductor chip disposed on the package substrate;

an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip, and including a through-hole; and

an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole,

wherein the upper semiconductor chip includes:

a first edge and a second edge opposite to each other;

a first region located between the first edge and the second edge;

a second region located between the first region and the first edge;

a third region located between the first region and the second edge;

a connection region overlapping the through-hole;

a first redistribution layer pattern extending from the first region through the second region onto the connection region; and

a second redistribution layer pattern configured to extend from the third area, across the first area and the second area, onto the connection area, and configured to have a length greater than a length of the first redistribution layer pattern,

wherein a width of at least a portion of the second redistribution layer pattern is greater than a width of the first redistribution layer pattern.

15. The package on package of claim 14,

wherein the upper semiconductor chip further includes a plurality of chip pads disposed on the first region, the second region, and the third region; and is

Wherein the second redistribution layer pattern extends to connect the plurality of chip pads to each other.

16. The package on package of claim 14, wherein the second region of the upper semiconductor chip is disposed to be spaced apart from the first region such that a distance between the second region and the first edge is smaller than a distance between the second region and the first region.

17. The package on package of claim 14,

wherein the third region of the upper semiconductor chip is spaced apart from the first region such that a distance between the third region and the second edge is smaller than a distance between the third region and the first region; and is

Wherein the third region of the upper semiconductor chip is located on an opposite side of the first region from the second region.

18. The package on package of claim 14, wherein the connection region of the upper semiconductor chip is spaced apart from the first region such that a distance between the connection region and the first edge is smaller than a distance between the connection region and the first region.

19. The package on package of claim 14, further comprising:

a first inner connector disposed between the interposer bridge and the connection region of the upper semiconductor chip to electrically connect the via to the first redistribution layer pattern and the second redistribution layer pattern extending onto the connection region; and

support bumps disposed between the lower semiconductor chip and the upper semiconductor chip to support the upper semiconductor chip.

20. A package on package, comprising:

a lower semiconductor chip disposed on the package substrate;

an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip, and including a through-hole; and

an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole,

wherein the upper semiconductor chip includes:

a first edge and a second edge opposite to each other;

a first region located between the first edge and the second edge;

a third region located between the first region and the second edge;

a first connection region overlapping the through-hole;

a first redistribution layer pattern extending from the first region onto the connection region; and

a second redistribution layer pattern configured to extend from the third area, through the first area, and onto the connection area,

wherein a width of at least a portion of the second redistribution layer pattern is greater than a width of the first redistribution layer pattern.

Technical Field

Embodiments of the present disclosure relate generally to packaging technology and, more particularly, to a package on package with an interposer bridge.

Background

Recently, techniques for incorporating multiple semiconductor chips into a single package have been developed to provide a fast semiconductor package with a large capacity memory. For example, a plurality of semiconductor chips may be two-dimensionally arranged on the same plane to provide a single semiconductor package having a planar stacked structure. The planar stack structure may result in an increase in the planar area and size of the semiconductor package. Therefore, much effort has been focused on stacking a plurality of semiconductor chips three-dimensionally in a limited planar area to reduce the size of the semiconductor package. That is, advanced techniques for vertically stacking a plurality of semiconductor chips have been proposed to provide a compact semiconductor package.

Disclosure of Invention

According to an embodiment, a stack package includes: a lower semiconductor chip disposed on the package substrate; an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip and configured to include a through-hole; and an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole. The upper semiconductor chip includes first and second edges opposite to each other, a first region between the first and second edges, a second region between the first and second regions, a third region between the first and second edges, a first connection region overlapping the via hole, first and first power pads disposed on the first region, a second power pad disposed on the second region, a third power pad disposed on the third region, a first redistribution layer pattern connected to the first signal pad to extend onto the first connection region, and a second redistribution layer pattern connecting the first, second, and third power pads to each other and extending onto the first connection region. The second redistribution layer pattern includes a first extension extending from the third area to reach the first area. The width of the first extension portion is greater than the width of the first redistribution layer pattern.

According to another embodiment, a stack package includes: a lower semiconductor chip disposed on the package substrate; an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip and configured to include a through-hole; and an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole. The upper semiconductor chip includes: a first edge and a second edge opposite to each other; a first region located between the first edge and the second edge; a second region located between the first region and the first edge; a third region located between the first region and the second edge; a connection region overlapping the through-hole; a first redistribution layer pattern extending from the first region through the second region onto the connection region; and a second redistribution layer pattern configured to extend from the third area, across the first area and the second area, and onto the connection area, and configured to have a length greater than a length of the first redistribution layer pattern. A width of at least a portion of the second redistribution layer pattern is greater than a width of the first redistribution layer pattern.

According to another embodiment, a stack package includes: a lower semiconductor chip disposed on the package substrate; an interposer bridge disposed on the package substrate to be spaced apart from the lower semiconductor chip and including a through hole; and an upper semiconductor chip disposed on the lower semiconductor chip to extend onto the interposer bridge and electrically connected to the package substrate through the via hole. The upper semiconductor chip may include: a first edge and a second edge opposite to each other; a first region located between the first edge and the second edge; a third region located between the first region and the second edge; a first connection region overlapping the through-hole; a first redistribution layer pattern extending from the first region onto the connection region; and a second redistribution layer pattern configured to extend from the third area, through the first area, and onto the connection area. A width of at least a portion of the second redistribution layer pattern may be greater than a width of the first redistribution layer pattern.

Drawings

Fig. 1 is a cross-sectional view illustrating a package on package according to an embodiment.

Fig. 2 is a plan view illustrating an interposer bridge of the package-on-package shown in fig. 1.

Fig. 3 is a plan view illustrating a chip pad array of an upper semiconductor chip included in the package on package of fig. 1.

Fig. 4 is a plan view illustrating a redistribution layer pattern array of an upper semiconductor chip included in the stack package of fig. 1.

Fig. 5 is an enlarged view of a portion of fig. 4.

Fig. 6 is a plan view illustrating a cell matrix region of an upper semiconductor chip included in the package on package of fig. 1.

Fig. 7 is a plan view illustrating a redistribution layer pattern of a lower semiconductor chip and an array of chip pads M4 included in the stack package of fig. 1.

Fig. 8 is a cross-sectional view illustrating signal paths of the package on package shown in fig. 1.

Fig. 9 is a cross-sectional view illustrating a package on package according to another embodiment.

Fig. 10 is a block diagram illustrating an electronic system employing a memory card including at least one of the package-on-package according to an embodiment.

Fig. 11 is a block diagram illustrating another electronic system including at least one of the package-on-package according to an embodiment.

Detailed Description

Terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to those of ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definition. Unless defined otherwise, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments belong.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to limit the elements themselves or to imply a particular order.

It will also be understood that when an element or layer is referred to as being "on," "over," "under," or "outside" another element or layer, it can be directly in contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between" or "adjacent" and "directly adjacent").

Spatially relative terms, such as "under", "lower", "above", "upper", "top", "bottom", and the like, may be used to describe a relationship of an element and/or feature to another element and/or feature (e.g., as shown in the figures). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The package on package may correspond to a semiconductor package, and the semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor die. Semiconductor chips or semiconductor dies can be obtained by separating a semiconductor substrate such as a wafer into pieces using a dicing process. The semiconductor chip may correspond to a memory chip, a logic chip, or an Application Specific Integrated Circuit (ASIC) chip. The memory chip may include a Dynamic Random Access Memory (DRAM) circuit, a Static Random Access Memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a Magnetic Random Access Memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The semiconductor package may be used in a communication system such as a mobile phone, an electronic system associated with biotechnology or healthcare, or a wearable electronic system. The semiconductor package may be applicable to the internet of things (IoT).

Like reference numerals refer to like elements throughout the specification. Even if a reference number is not mentioned or described with reference to one figure, the reference number may also be mentioned or described with reference to another figure. In addition, even if a reference numeral is not shown in one drawing, it may be mentioned or described with reference to another drawing.

Fig. 1 is a cross-sectional view showing a package on package 10 according to an embodiment.

Referring to fig. 1, a stack package 10 may be configured to include a package substrate 100, a lower semiconductor chip 200, an upper semiconductor chip 300, and an interposer bridge 400. In addition, a molding layer 500 may be provided to protect the lower semiconductor chip 200, the upper semiconductor chip 300, and the interposer bridge 400. The molding layer 500 may be provided by forming an encapsulation material on the package substrate 100 to cover the lower semiconductor chip 200, the upper semiconductor chip 300, and the interposer bridge 400. The molding layer 500 may include an Epoxy Molding Compound (EMC) material.

The package substrate 100 may have a first surface 101 and a second surface 102 opposite to each other. The lower semiconductor chip 200, the upper semiconductor chip 300, and the interposer bridge 400 may be disposed on the first surface 101 of the package substrate 100, and the external connector 190 for connecting the stack package 10 to an external device may be disposed on the second surface 102 of the package substrate 100. The external connectors 190 may be connection members such as solder balls. The package substrate 100 may be an interconnection member for electrically connecting the lower semiconductor chip 200 and the upper semiconductor chip 300 to an external electronic system or an external module. The package substrate 100 may be, for example, a Printed Circuit Board (PCB).

The lower semiconductor chip 200 may be a memory semiconductor chip such as a DRAM chip. The upper semiconductor chip 300 may be a memory semiconductor chip such as a DRAM chip. The upper semiconductor chip 300 may be a semiconductor chip having a function different from that of the lower semiconductor chip 200. Alternatively, the lower semiconductor chip 200 and the upper semiconductor chip 300 may have the same function. The lower semiconductor chip 200 and the upper semiconductor chip 300 may be semiconductor chips having the same configuration.

The lower semiconductor chip 200 may be disposed on the first surface 101 of the package substrate 100. The interposer bridge 400 may be disposed on the first surface 101 of the package substrate 100 to be laterally spaced apart from the lower semiconductor chip 200 by a certain distance. The upper semiconductor chip 300 may be disposed to vertically overlap the lower semiconductor chip 200 and the interposer bridge 400. The upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200 to be laterally offset with respect to the lower semiconductor chip 200 such that a portion of the upper semiconductor chip 300 vertically overlaps the lower semiconductor chip 200. The upper semiconductor chip 300 may extend onto the interposer bridge 400 such that another portion of the upper semiconductor chip 300 vertically overlaps the interposer bridge 400.

Fig. 2 is a plan view illustrating an interposer bridge 400 of the package on package 10 shown in fig. 1.

Referring to fig. 1 and 2, the interposer bridge 400 may be configured to include a silicon substrate 410 and vias 420. The through-hole 420 may correspond to a through-silicon-via (TSV) that substantially penetrates the silicon substrate 410 in a vertical direction. The via 420 may be formed to include a conductive material such as copper (Cu). Since the through-holes 420 correspond to TSVs, the number of the through-holes 420 provided in the silicon substrate 410 having a limited planar area can be maximized. For example, the through-hole 420 may be formed to include several tens to several hundreds of through-holes. In order to increase the number of the through holes 420 provided in the silicon substrate 410, the through holes 420 may be arranged in at least two rows parallel to the length direction of the silicon substrate 410.

The interposer bridge 400 may correspond to an interconnection member that electrically connects the upper semiconductor chip 300 to the package substrate 100. The upper semiconductor chip 300 may be electrically connected to the package substrate 100 through the via 420 of the interposer bridge 400. The interposer bridge 400 may also serve as a support member that supports the upper semiconductor chip 300 together with the lower semiconductor chip 200. The interposer bridge 400 may be provided in chip form or die form including a silicon substrate 410 provided with vias 420. The interposer bridge 400 may be coupled to the package substrate 100 through a third connector 630. The third connector 630 may be a connection member having a bump form. The interposer bridge 400 may be bonded to the package substrate 100 by attaching the bumps to the vias 420 of the interposer bridge 400 and by bonding the bumps to the package substrate 100.

Fig. 3 is a plan view illustrating an array M1 of chip pads of an upper semiconductor chip 300 included in the package on package 10 of fig. 1.

Referring to fig. 1 and 3, the upper semiconductor chip 300 may include a first edge 301 and a second edge 302 opposite to each other. The upper semiconductor chip 300 may further include a surface 303 defined by a first edge 301 and a second edge 302. The surface 303 of the upper semiconductor chip 300 may include a first region 311, a second region 312, a third region 313, and a first connection region 314. The first region 311, the second region 312, the third region 313, and the first connection region 314 may be set as separate regions spaced apart from each other.

The first region 311 of the upper semiconductor chip 300 may be located between the first edge 301 and the second edge 302. The first region 311 of the upper semiconductor chip 300 may be located at a central position spaced apart from the first and second edges 301 and 302 by the same distance. When the upper semiconductor chip 300 is a memory chip, the first region 311 of the upper semiconductor chip 300 may be defined as a peripheral region where peripheral circuits of the memory chip are disposed.

The second region 312 of the upper semiconductor chip 300 may be located between the first region 311 and the first edge 301. The second region 312 of the upper semiconductor chip 300 may be disposed to be spaced apart from the first region 311 and the first edge 301. The distance between the second region 312 and the first edge 301 may be smaller than the distance between the second region 312 and the first region 311.

The third region 313 of the upper semiconductor chip 300 may be located between the first region 311 and the second edge 302. The third region 313 of the upper semiconductor chip 300 may be disposed to be spaced apart from the first region 311 and the second edge 302. The distance between the third region 313 and the second edge 302 may be less than the distance between the third region 313 and the first region 311. The third region 313 of the upper semiconductor chip 300 may be located on the opposite side of the first region 311 from the second region 312.

The upper semiconductor chip 300 may include chip pads disposed on the surface 303, and the chip pads disposed on the surface 303 may serve as connection terminals for electrically connecting the upper semiconductor chip 300 to another component. The chip pad may be disposed on all of the first, second, and third regions 311, 312, and 313. The chip pads disposed on the surface 303 may include power supply pads for applying a power supply voltage to the upper semiconductor chip 300, signal pads for transmitting various signals to the upper semiconductor chip 300, and ground pads for applying a ground voltage to the upper semiconductor chip 300.

The first power supply pad 321 of the chip pad may be disposed on the first region 311 of the upper semiconductor chip 300. The first power supply pads 321 may be arranged along a length direction of the first region 311. In the plan view of fig. 3, the length direction of the first region 311 may be substantially perpendicular to a line extending from the first edge 301 toward the second edge 302. Other first power supply pads 321S may be additionally arranged in the first region 311 along the length direction of the first region 311. In this case, the first power supply pads 321 may be arranged in a first row parallel to the length direction of the first region 311, and the other first power supply pads 321S may be arranged in a second row spaced apart from and parallel to the first row.

The first ground pad 331 of the chip pad may be disposed on the first region 311 of the upper semiconductor chip 300. The first ground pads 331 may be arranged along a length direction of the first region 311. Other first ground pads 331S may be additionally arranged in the first region 311 along the length direction of the first region 311. In this case, the first ground pads 331 may be arranged in a first row parallel to a length direction of the first region 311, and the other first ground pads 331S may be arranged in a second row spaced apart from and parallel to the first row.

The first signal pad 341 of the chip pads may be disposed on the first region 311 of the upper semiconductor chip 300. The first signal pads 341 may be arranged along a length direction of the first region 311. Other first signal pads 341S may be additionally arranged in the first region 311 along the length direction of the first region 311. In this case, the first signal pads 341 may be arranged in a first row parallel to the length direction of the first region 311, and the other first signal pads 341S may be arranged in a second row spaced apart from and parallel to the first row.

The first power supply pad 321, the first signal pad 341, and the first ground pad 331 may be repeatedly arranged along the length direction of the first region 311 in the order of the first power supply pad 321, the first signal pad 341, and the first ground pad 331. Each of the first power supply pads 321 may be disposed between two adjacent first signal pads 341 arranged along the length direction of the first region 311. Each of the first ground pads 331 may be disposed between two adjacent first signal pads 341 arranged along a length direction of the first region 311.

Among the first power supply pad 321, the first signal pad 341, and the first ground pad 331 disposed adjacent to each other along the length direction of the first region 311, the first ground pad 331 may be disposed on the opposite side of the first signal pad 341 from the first power supply pad 321. Among the first power supply pad 321, the first signal pad 341, and the first ground pad 331 disposed adjacent to each other along the length direction of the first region 311, the first power supply pad 321 and the first ground pad 331 may be disposed at both sides of the first signal pad 341, respectively. Accordingly, since the first power supply pad 321, the first signal pad 341, and the first ground pad 331 are disposed adjacent to each other along the length direction of the first region 311, a routing distance between the data signal, the power supply voltage signal, and the ground voltage signal may be reduced to improve the operation speed of the upper semiconductor chip 300.

The second power supply pad 322 of the chip pad may be disposed on the second region 312 of the upper semiconductor chip 300. The second power pads 322 may be arranged along the length direction of the second region 312. In the plan view of fig. 3, the length direction of the second region 312 may be substantially perpendicular to a line extending from the first edge 301 toward the second edge 302.

The second ground pad 332 may also be disposed on the second region 312 of the upper semiconductor chip 300. The second ground pads 332 may be arranged along a length direction of the second region 312.

The third power supply pad 323 of the chip pad may be disposed on the third region 313 of the upper semiconductor chip 300. The third power supply pads 323 may be arranged along a length direction of the third region 313. In the plan view of fig. 3, the length direction of the third region 313 may be substantially perpendicular to a line extending from the first edge 301 toward the second edge 302.

The third ground pad 333 may also be disposed on the third region 313 of the upper semiconductor chip 300. The third ground pads 333 may be aligned along a length direction of the third region 313.

The first connection region 314 may be defined as a portion of the surface 303 of the upper semiconductor chip 300. The first connection region 314 of the upper semiconductor chip 300 may be a region to which the via 420 of the interposer bridge 400 is connected. The first connection region 314 of the upper semiconductor chip 300 may be a region overlapping with the via 420 of the interposer bridge 400. Since the via 420 of the interposer bridge 400 is connected to the connection region 314 of the upper semiconductor chip 300, the upper semiconductor chip 300 may be stacked on the lower semiconductor chip 200 to be laterally offset with respect to the lower semiconductor chip 200 such that a portion of the upper semiconductor chip 300 (including the connection region 314) laterally protrudes from a side surface of the lower semiconductor chip 200. The first region 311 and the third region 313 of the upper semiconductor chip 300 may overlap with the lower semiconductor chip 200.

The first connection region 314 of the upper semiconductor chip 300 may be disposed to be spaced apart from the first region 311 such that a distance between the first connection region 314 and the first edge 301 is smaller than a distance between the first connection region 314 and the first region 311. The first connection region 314 of the upper semiconductor chip 300 may be disposed adjacent to the first edge 301 such that a distance between the first connection region 314 and the first edge 301 is smaller than a distance between the first connection region 314 and the second region 312. Although not shown in the drawings, the first connection region 314 of the upper semiconductor chip 300 may be disposed to overlap the second region 312.

Fig. 4 is a plan view illustrating a redistribution layer pattern array M2 of the upper semiconductor chip 300 included in the stack package 10 of fig. 1. Fig. 5 is an enlarged view of a portion of fig. 4.

Referring to fig. 1, 4, and 5, the upper semiconductor chip 300 may include a redistribution layer pattern disposed on the surface 303. The redistribution layer pattern may be a conductive pattern for electrically extending the chip pad to the first connection region 314.

A first redistribution layer pattern 350 of the redistribution layer patterns may be connected to the first signal pad 341 and may extend onto the first connection region 314. The first redistribution layer pattern 350 may be a conductive pattern extending from the first region 311 through the second region 312 to reach the first connection region 314.

The second redistribution layer pattern 360 of the redistribution layer patterns may be a conductive pattern connecting the first power supply pad 321, the second power supply pad 322, and the third power supply pad 323 to each other and extending onto the first connection area 314. The second redistribution layer pattern 360 may be a conductive pattern extending from the third region 313 through the first region 311 and the second region 312 to reach the first connection region 314. Thus, the second redistribution layer pattern 360 of length L1 may be longer than the first redistribution layer pattern 350 of length L2. The second redistribution layer pattern 360 may be a conductive pattern extending to connect the first, second, and third power supply pads 321, 322, and 323 disposed on the respective first, second, and third areas 311, 312, and 313 to each other.

The third redistribution layer pattern 370 of the redistribution layer patterns may be a conductive pattern connecting the first, second, and third ground pads 331, 332, and 333 to each other and extending onto the first connection area 314. The third redistribution layer pattern 370 may be a conductive pattern extending from the third region 313 through the first region 311 and the second region 312 to reach the first connection region 314. Accordingly, the third redistribution layer pattern 370 may be longer than the first redistribution layer pattern 350.

Each of the second redistribution layer patterns 360 may include a first extension 361 extending from the third area 313 to reach the first area 311. The first extension 361 of the second redistribution layer pattern 360 may cover at least one of the third power supply pads 323 and may be electrically connected to the at least one third power supply pad 323. Each of the second redistribution layer patterns 360 may further include a second extension 362 extending from the first area 311 to the first connection area 314 through the second area 312. The second extension portion 362 of the second redistribution layer pattern 360 may cover at least one of the second power supply pads 322 and may be electrically connected to the at least one second power supply pad 322.

The second extension portion 362 of the second redistribution layer pattern 360 may include a first contact area 362-1 in the first connection area 314. The first contact area 362-1 of the second extension portion 362 of each second redistribution layer pattern 360 may correspond to a portion to which one of the first inner connectors 610 is coupled. The first female connector 610 may be a bump. The first inner connector 610 may be disposed between the first connection region 314 of the upper semiconductor chip 300 and the through-hole 420 to electrically connect the through-hole 420 of the interposer bridge 400 to the first contact region 362-1 of the second extension 362.

Each of the second redistribution layer patterns 360 may further include a third extension 363 connecting one of the second extensions 362 to one of the first extensions 361. Widths W1, W2 of the first and second extensions 361 and 362 of the second redistribution layer pattern 360 may be greater than a width W3 of the third extension 363. The third extension 363 may be a conductive line having a width W3 less than the widths W1, W2 of the first and second extensions 361 and 362. Each of the second redistribution layer patterns 360 may further include a first overlap 364 overlapping one of the first power supply pads 321 disposed on the first region 311, and a width W4 of the first overlap 364 may be greater than a width W3 of the third extension 363 to completely cover the first power supply pad 321.

Each first redistribution layer pattern 350 may include a second overlap 354 covering one of the first signal pads 341 disposed on the first region 311. Each first redistribution layer pattern 350 may further include a second contact pad 352 disposed on the first contact region 314. The second contact pad 352 may be coupled to one of the first inner connectors 610. Each first redistribution layer pattern 350 may further include an extension 351 connecting the second contact pad 352 to the second overlap 354.

The second redistribution layer pattern 360 may extend to be longer than the first redistribution layer pattern 350. The second redistribution layer pattern 360 may extend from the first connection region 314 to reach the third region 313, thereby having a relatively high resistance value and a relatively high resistance value. At least a portion of each of the second redistribution layer patterns 360 may be formed to be wider than the first redistribution layer pattern 350. For example, the first and second extensions 361 and 362 of the second redistribution layer pattern 360 may be formed to be wider than the width W8 of the extension 351 of the first redistribution layer pattern 350. Accordingly, due to the presence of the first and second extending portions 361 and 362 of the second redistribution layer pattern 360, the resistance value and the resistance value of the second redistribution layer pattern 360 may be reduced. Accordingly, the first and second extending portions 361 and 362 of the second redistribution layer pattern 360 may offset or suppress an increase in resistance and impedance values of the second redistribution layer pattern 360 due to a longer length of the second redistribution layer pattern 360. As a result, the first extension 361 and the second extension 362 of the second redistribution layer pattern 360 may provide an effect of improving a power transmission network.

Each of the third redistribution layer patterns 370 may include a fifth extension 371 extending from the third region 313 to reach the first region 311. The fifth extension 371 of the third redistribution layer pattern 370 may cover at least one of the third ground pads 333 and may be electrically connected to the at least one third ground pad 333. Each of the third redistribution layer patterns 370 may further include a sixth extension 372 extending from the first area 311 to the first connection area 314 through the second area 312. The sixth extension 372 of the third redistribution layer pattern 370 may cover at least one of the second ground pads 332 and may be electrically connected to the at least one second ground pad 332.

The sixth extension portion 372 of the third redistribution layer pattern 370 may include a third contact area 372-1 in the first connection area 314. The third contact area 372-1 of the sixth extension 372 of each third redistribution layer pattern 370 may correspond to a portion to which one of the first inner connectors 610 is bonded.

Each of the third redistribution layer patterns 370 may further include a seventh extension 373 connecting one of the sixth extensions 372 to one of the fifth extensions 371. The widths W5, W6 of the fifth and sixth extension portions 371, 372 of the third redistribution layer pattern 370 may be greater than the width W7 of the seventh extension portion 373.

At least a portion of each of the third redistribution layer patterns 370 may be formed to be wider than the first redistribution layer pattern 350. For example, the fifth and sixth extensions 371 and 372 of the third redistribution layer pattern 370 may be formed to be wider than the extension 351 of the first redistribution layer pattern 350.

As described above, the third redistribution layer pattern 370 may be formed to have substantially the same shape as the second redistribution layer pattern 360. The third redistribution layer pattern 370 may be disposed on an opposite side of the first redistribution layer pattern 350 from the second redistribution layer pattern 360, among the first redistribution layer pattern 350, the second redistribution layer pattern 360, and the third redistribution layer pattern 370 adjacent to each other.

Referring again to fig. 1, the upper semiconductor chip 300 may further include a first dielectric layer 391 and a second dielectric layer 392 covering a surface 303 corresponding to a surface of the chip body 300B of the upper semiconductor chip 300. A first dielectric layer 391 may be provided to protect the surface 303 of the chip body 300B. The second dielectric layer 392 may cover the redistribution layer patterns (350, 360, and 370 of fig. 4) to electrically insulate the redistribution layer patterns from each other.

The upper semiconductor chip 300 may be coupled to the through-hole 420 of the interposer bridge 400 by the first inner connector 610. The first connection region 314 of the upper semiconductor chip 300 may be closer to the first edge 301 than the second edge 302 and may be coupled to the first inner connector 610. Accordingly, a portion of the upper semiconductor chip 300 adjacent to the second edge 302 may be supported by the first support bump 640.

The first support bumps 640 may be disposed between the lower semiconductor chip 200 and the upper semiconductor chip 300 to balance the upper semiconductor chip 300 and prevent the upper semiconductor chip 300 from being tilted. The first support bumps 640 may be substantially the same conductive bumps as the first internal connector 610. Alternatively, the first support bump 640 is not necessarily formed of a conductive material. Accordingly, the first support bump 640 may be an insulation bump or an insulation ball formed of an insulation material (e.g., a polymer material or a resin material). The first support bumps 640 may be bonded to the surface of the second dielectric layer 392 of the upper semiconductor chip 300.

Fig. 6 is a plan view illustrating a cell matrix area array M3 of the upper semiconductor chip 300 included in the package on package 10 of fig. 1.

Referring to fig. 1, 4, 5 and 6, a first core region 316 may be disposed between a first region 311 and a first edge 301 of the upper semiconductor chip 300, and a second core region 317 may be disposed between the first region 311 and a second edge 302 of the upper semiconductor chip 300. When the upper semiconductor chip 300 is a memory chip, each of the first core region 316 and the second core region 317 may be a region in which memory cells 319 are arranged. The first region 311 of the upper semiconductor chip 300 may be a peripheral region provided with a peripheral circuit for controlling the memory unit 319. Each of the first core area 316 and the second core area 317 may be an area in which a plurality of cell matrix areas 318 are disposed. The cell matrix region 318 may correspond to a memory bank (memory bank). The layout shown in fig. 6 may be only an example of the upper semiconductor chip 300. Typically, 16 banks may be arranged in a row, and 32 banks may be disposed in the first core area. Each memory cell 319 disposed in the cell matrix region 318 may include a transistor and a capacitor.

The first power supply pad 321 disposed on the first region 311 of the upper semiconductor chip 300 may be disposed to apply a power supply voltage to the first memory cell 319-1 located in the first cell matrix region 318-1 disposed adjacent to the first region 311. The second power supply pad 322 disposed on the second region 312 of the upper semiconductor chip 300 may be configured to apply a power supply voltage to the second memory cell 319-2 located in the second cell matrix region 318-2 disposed between the second region 312 and the first edge 301.

Since the second memory cell 319-2 receives the power supply voltage from the second power supply pad 322 located in the second region 312, a voltage drop across the power supply line between the second power supply pad 322 and the second memory cell 319-2 may be reduced as compared to a case where the second memory cell 319-2 receives the power supply voltage from the first power supply pad 321 located in the first region 311. That is, since the second memory cell 319-2 receives a power supply voltage from the second power supply pad 322 located in the second region 312 between the first cell matrix region 318-1 and the second cell matrix region 318-2, the power supply voltage applied to the second memory cell 319-2 can be maximized.

As described with reference to fig. 3, the second power supply pad 322 and the third power supply pad 323 may be uniformly disposed even in the second region 312 and the third region 313 except for the first region 311 corresponding to the peripheral region. Accordingly, the level of the power supply voltage applied to all the memory cells 319 of the upper semiconductor chip 300 can be maximized.

Fig. 7 is a plan view illustrating a redistribution layer pattern of the lower semiconductor chip 200 and an array of chip pads M4 included in the stack package 10 of fig. 1.

Referring to fig. 1 and 7, the lower semiconductor chip 200 may include a redistribution layer pattern and a chip pad having substantially the same layout as the redistribution layer pattern and the chip pad of the upper semiconductor chip 300. The lower semiconductor chip 200 may have a third edge 201 and a fourth edge 202 opposite to each other, and may have a surface 203 defined by the third edge 201 and the fourth edge 202.

The surface 203 of the lower semiconductor chip 200 may include a fourth region 211, a fifth region 212, a sixth region 213, and a second connection region 214. The fourth region 211, the fifth region 212, the sixth region 213, and the second connection region 214 may be set as separate regions spaced apart from each other. The fourth region 211 of the lower semiconductor chip 200 may be located between the third edge 201 and the fourth edge 202. The fourth region 211 located at the central region between the third edge 201 and the fourth edge 202 of the lower semiconductor chip 200 may be a peripheral region of the memory chip. The fifth region 212 of the lower semiconductor chip 200 may be located between the fourth region 211 and the third edge 201. The sixth region 213 of the lower semiconductor chip 200 may be located between the fourth region 211 and the fourth edge 202. The distance between the second connection region 214 and the third edge 201 may be smaller than the distance between the second connection region 214 and the fifth region 212.

The fourth power supply pad 221 and the second signal pad 241 may be disposed on the fourth region 211 of the lower semiconductor chip 200. The fifth power supply pad 222 may be disposed on the fifth region 212 of the lower semiconductor chip 200. The sixth power supply pad 223 may be disposed on the sixth region 213 of the lower semiconductor chip 200.

The fourth redistribution layer pattern 250 may be connected to the second signal pad 241 and may extend onto the second connection area 214. The fourth redistribution layer pattern 250 may have substantially the same shape as the first redistribution layer pattern (350 of fig. 4) of the upper semiconductor chip (300 of fig. 4) and may be arranged in the same manner as the first redistribution layer pattern 350.

The fifth redistribution layer pattern 260 may be disposed to connect the fourth, fifth, and sixth power supply pads 221, 222, and 223 to each other and extend onto the second connection area 214. The fifth redistribution layer pattern 260 may have substantially the same shape as the second redistribution layer pattern (360 of fig. 4) of the upper semiconductor chip (300 of fig. 4) and may be arranged in the same manner as the second redistribution layer pattern 360. The layout of array M4 of the pattern shown in FIG. 7 may be substantially the same as the layout of array M2 rotated 180 degrees shown in FIG. 4. That is, if the layout of array M2 shown in FIG. 4 is rotated 180 degrees such that the reference angle C1 of the layout of array M2 is located at the reference angle C2 of the layout of array M4 shown in FIG. 7, the rotated layout of array M2 shown in FIG. 4 may be substantially the same as the layout of array M4 shown in FIG. 7.

A width W9 of the fourth extension portion 263 of the fifth redistribution layer pattern 260 may be greater than a width W10 of the fourth redistribution layer pattern 250. The fourth extension part 263 of the fifth redistribution layer pattern 260 may be a conductive pattern extending from the sixth area 213 to reach the fourth area 211.

The ground pad 230 may also be disposed on the fourth, fifth and sixth regions 211, 212 and 213. The sixth redistribution layer pattern 270 may be disposed to connect the ground pads 230 located in the fourth, fifth, and sixth areas 211, 212, and 213 to each other, and extend onto the second connection area 214. The sixth redistribution layer pattern 270 may have substantially the same shape as the third redistribution layer pattern (370 of fig. 4) of the upper semiconductor chip (300 of fig. 4) and may be arranged in the same manner as the third redistribution layer pattern 370.

Referring again to fig. 1, the second inner connector 620 may be disposed between the lower semiconductor chip 200 and the package substrate 100 to overlap the second connection region 214 of the lower semiconductor chip 200. The second inner connector 620 may be a connection member electrically connecting the lower semiconductor chip 200 to the package substrate 100. The second inner connector 620 may be formed of the same conductive bumps as the first inner connector 610.

The second inner connector 620 may be disposed to overlap the second connection region 214 adjacent to the third edge 201 of the lower semiconductor chip 200. The second support bump 650 may be additionally disposed between a portion of the lower semiconductor chip 200 and the package substrate 100 to balance the lower semiconductor chip 200 and prevent the lower semiconductor chip 200 from being tilted. The second support bumps 650 may be disposed closer to the fourth edge 202 of the lower semiconductor chip 200 than the second inner connectors 620. That is, the distance between the fourth edge 202 of the lower semiconductor chip 200 and the second support bump 650 may be smaller than the distance between the fourth edge 202 of the lower semiconductor chip 200 and the second inner connector 620. Similar to the first support bumps 640, the second support bumps 650 may be dummy bumps such as insulation bumps.

Fig. 8 is a cross-sectional view illustrating signal paths of the package on package 10 shown in fig. 1.

Referring to fig. 8, the upper semiconductor chip 300 of the package on package 10 may communicate with an external device (not shown) through a first signal path including the first redistribution layer pattern 350, the interposer bridge 400, and the first external connector 190-1 of the package substrate 100. The lower semiconductor chip 200 of the stack package 10 may communicate with an external device through a second signal path including the fourth redistribution layer pattern 250 and the second outer connector 190-2 of the package substrate 100. The first and second external connectors 190-1 and 190-2 may constitute the external connectors 190 to which electric signals are independently applied. The upper and lower semiconductor chips 300 and 200 may communicate with an external device through the first and second signal channels functioning independently.

Fig. 9 is a cross-sectional view illustrating a package on package 20 according to another embodiment. In fig. 9, the same reference numerals as used in fig. 1 denote the same elements.

Referring to fig. 9, the package on package 20 may be configured to include a lower semiconductor chip 1200 and an upper semiconductor chip 300 sequentially stacked on a package substrate 100. The upper semiconductor chip 300 may be configured to include the second redistribution layer pattern 360 shown in fig. 1 and 4. The lower semiconductor chip 1200 may not include any redistribution layer pattern, such as the fifth redistribution layer pattern (260 of fig. 1), except for the lower semiconductor chip (200 of fig. 1) of the stack package (10 of fig. 1) according to the embodiment. Accordingly, the fourth inner connectors 1620, which electrically connect the lower semiconductor chip 1200 to the package substrate 100, may be directly connected or bonded to the chip pads 1220 of the lower semiconductor chip 1200. The chip pad 1220 of the lower semiconductor chip 1200 may be disposed on all of the first, second, and third regions 1211, 1212, and 1213.

Fig. 10 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of the package-on-package according to an embodiment. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may comprise at least one of a package on package according to an embodiment.

The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data is read out or stored data is stored in response to a read/write request from the host 7830.

Fig. 11 is a block diagram illustrating an electronic system 8710 including at least one of the stacked packages according to an embodiment. The electronic system 8710 may include a controller 8711, an input/output unit 8712, and a memory 8713. The controller 8711, the input/output unit 8712, and the memory 8713 may be coupled to each other by a bus 8715 that provides a path for data movement.

In an embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one of a stack package according to an embodiment of the present disclosure. The input/output unit 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands, etc. to be executed by the controller 8711.

The memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 can also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be wired or wireless in type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If electronic system 8710 is a device capable of performing wireless communication, electronic system 8710 may be used in a communication system using a technology of CDMA (code division multiple access), GSM (global system for mobile communication), NADC (north american digital cellular), E-TDMA (enhanced time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband internet).

The concepts disclosed above in connection with some embodiments. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Accordingly, the embodiments disclosed in this specification should not be considered in a limiting sense, but rather should be considered in an illustrative sense. The scope of the concept is not limited to the description above but is defined by the claims which follow, and all different features which come within the range of equivalents are to be construed as being included therein.

Cross Reference to Related Applications

The present application claims priority from korean application No.10-2019-0143816, filed 11.11.2019, which is incorporated herein by reference in its entirety.