阅读说明：本技术 半导体存储器装置和该半导体存储器装置的制造方法 (Semiconductor memory device and method of manufacturing the same ) 是由 崔康植 于 2020-07-22 设计创作，主要内容包括：一种半导体存储器装置和该半导体存储器装置的制造方法。该半导体存储器装置包括：基板,其包括外围电路；栅极层叠结构,其设置在基板上并且包括单元阵列区域以及从单元阵列区域延伸的阶梯区域；沟道结构,其穿过栅极层叠结构的单元阵列区域；存储器层,其围绕沟道结构的侧壁；第一接触插塞,其穿过栅极层叠结构的阶梯区域；以及绝缘结构,其围绕第一接触插塞的侧壁,以使第一接触插塞与栅极层叠结构绝缘。(A semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes: a substrate including a peripheral circuit; a gate stack structure disposed on a substrate and including a cell array region and a stepped region extending from the cell array region; a channel structure passing through the cell array region of the gate stack structure; a memory layer surrounding sidewalls of the channel structure; a first contact plug passing through a stepped region of the gate stack structure; and an insulating structure surrounding sidewalls of the first contact plug to insulate the first contact plug from the gate stack structure.)

1. A semiconductor memory device, the semiconductor memory device comprising:

a substrate including a peripheral circuit;

a gate stack structure disposed on the substrate and including a cell array region and a stepped region extending from the cell array region;

a channel structure passing through the cell array region of the gate stack structure;

a memory layer surrounding sidewalls of the channel structure;

a first contact plug passing through the stepped region of the gate stack structure; and

an insulating structure surrounding sidewalls of the first contact plug to insulate the first contact plug from the gate stack structure.

2. The semiconductor memory device according to claim 1, further comprising:

a discharge impurity region formed in the substrate;

a transistor included in the peripheral circuit;

a first lower contact plug connected to the discharge impurity region;

a second lower contact plug connected to the transistor;

a first semiconductor pattern disposed between the gate stack structure and the substrate and extending to overlap the first lower contact plug; and

a second semiconductor pattern disposed between the gate stack structure and the substrate and overlapping the second lower contact plug.

3. The semiconductor memory device according to claim 2, wherein the channel structure extends into the first semiconductor pattern.

4. The semiconductor memory device according to claim 3, wherein the first semiconductor pattern comprises:

a first semiconductor layer surrounding a lower portion of the channel structure;

a second semiconductor layer extending along a bottom surface of the gate stack structure and surrounding the channel structure; and

a channel coupling pattern disposed between the first semiconductor layer and the second semiconductor layer and contacting the channel structure,

wherein each of the first semiconductor layer and the channel coupling pattern comprises a doped semiconductor layer.

5. The semiconductor memory device according to claim 2, wherein the first contact plug passes through the second semiconductor pattern to contact the second lower contact plug.

6. The semiconductor memory device according to claim 5, wherein the second semiconductor pattern comprises a first semiconductor layer, a first protective layer, a sacrificial layer, a second protective layer, and a second semiconductor layer surrounding the first contact plug and sequentially stacked on one another.

7. The semiconductor memory device according to claim 2, further comprising:

a first vertically doped semiconductor pattern formed on a sidewall of the first semiconductor pattern; and

a second vertically doped semiconductor pattern formed on sidewalls of the second semiconductor pattern.

8. The semiconductor memory device according to claim 7, wherein the first vertically doped semiconductor pattern overlaps the first lower contact plug.

9. The semiconductor memory device according to claim 2, wherein a width of the second semiconductor pattern is larger than a width of the first contact plug.

10. The semiconductor memory device according to claim 1, further comprising:

a transistor included in the peripheral circuit, wherein the transistor does not overlap with the gate stack structure;

a lower contact plug connected to the transistor;

a semiconductor pattern overlapping the lower contact plug;

a dummy stacked structure including an interlayer insulating layer and a sacrificial layer alternately stacked on each other on the semiconductor pattern; and

a second contact plug passing through the dummy stacked structure and the semiconductor pattern to contact the lower contact plug.

11. The semiconductor memory device according to claim 10, further comprising a vertically doped semiconductor pattern formed on a sidewall of the semiconductor pattern.

12. The semiconductor memory device according to claim 10, wherein a width of the semiconductor pattern is larger than a width of the second contact plug.

13. The semiconductor memory device of claim 1, wherein the insulating structure comprises a dummy memory layer, wherein the dummy memory layer and the memory layer comprise a same material.

14. The semiconductor memory device according to claim 13, wherein the insulating structure further comprises an oxide layer disposed between the dummy memory layer and the first contact plug.

15. The semiconductor memory device according to claim 1, further comprising:

a support pillar passing through the stepped region of the gate stack structure, wherein the support pillar and the channel structure comprise a same material; and

a dummy memory layer surrounding sidewalls of the support pillars, wherein the dummy memory layer and the memory layer comprise a same material.

16. The semiconductor memory device according to claim 1, wherein the gate stack structure includes an interlayer insulating layer and a conductive pattern alternately stacked on each other.

17. A method of manufacturing a semiconductor memory device, the method comprising:

forming a preliminary structure including a first semiconductor pattern and a second semiconductor pattern separated from each other by an insulating layer;

forming a stacked structure on the preliminary structure, the stacked structure including interlayer insulating layers and sacrificial layers alternately stacked on top of each other;

forming a channel hole and a first contact hole through the stacked structure, wherein the channel hole overlaps the first semiconductor pattern, and wherein the first contact hole overlaps the second semiconductor pattern;

forming a memory layer on a surface of each of the channel hole and the first contact hole;

filling the channel hole with a channel structure;

forming a first contact plug in the first contact hole, wherein the first contact plug passes through the memory layer and the second semiconductor pattern in the first contact hole; and

the sacrificial layer is replaced with a conductive pattern,

wherein the conductive pattern surrounds the channel structure and the first contact plug with the memory layer interposed between each of the conductive patterns and each of the channel structure and the first contact plug.

18. The method of claim 17, wherein the step of forming the preliminary structure comprises the steps of:

sequentially laminating a first semiconductor layer, a sacrificial laminated structure, and a second semiconductor layer on a substrate including a first lower contact plug connected to a discharge impurity region and a second lower contact plug connected to a transistor;

etching the first semiconductor layer, the sacrificial stacked structure, and the second semiconductor layer to form the first semiconductor pattern overlapping the first lower contact plug and the second semiconductor pattern overlapping the second lower contact plug; and

filling the etched regions of the first semiconductor layer, the sacrificial stacked structure, and the second semiconductor layer with the insulating layer.

19. The method of claim 18, further comprising the steps of:

removing the sacrificial stack structure of the first semiconductor pattern to expose the memory layer in the channel hole;

removing the exposed region of the memory layer to expose the channel structure; and

forming a channel coupling pattern contacting the channel structure between the first semiconductor layer and the second semiconductor layer of the first semiconductor pattern,

wherein each of the first semiconductor layer and the channel coupling pattern comprises a doped semiconductor layer.

20. The method of claim 18, further comprising the steps of: forming a vertically doped semiconductor pattern on a sidewall of each of the first and second semiconductor patterns.

21. The method of claim 17, wherein the laminated structure comprises a stepped structure, and

wherein the first contact hole passes through the stepped structure of the stacked structure.

22. The method of claim 17, wherein the stacked structure comprises a stepped structure overlapping the first semiconductor pattern, and

wherein, the method also comprises the following steps:

forming a dummy hole penetrating the stepped structure and overlapping the first semiconductor pattern by using a process of forming the channel hole and the first contact hole;

forming a dummy memory layer on a surface of the dummy hole by using the step of forming the memory layer; and

filling the dummy hole with a support pillar by using the step of filling the channel hole with the channel structure, wherein the support pillar and the channel structure comprise the same material.

23. The method of claim 17, further comprising the steps of: forming an oxide layer on the memory layer in the first contact hole before forming the first contact plug,

wherein the first contact plug passes through the oxide layer.

24. The method of claim 17, wherein a width of the first contact hole is smaller than a width of the second semiconductor pattern.

25. The method of claim 17, wherein the preliminary structure further includes a third semiconductor pattern separated from the first and second semiconductor patterns by the insulating layer, and

wherein the step of replacing the sacrificial layer with the conductive pattern is controlled such that a portion of each of the sacrificial layers overlapping with the third semiconductor pattern remains.

26. The method of claim 25, further comprising the steps of:

forming a second contact hole penetrating the stacked structure and overlapping the third semiconductor pattern by using a process of forming the channel hole and the first contact hole; and

forming a second contact plug in the second contact hole by using the step of forming the first contact plug in the first contact hole.

27. The method of claim 26, wherein a width of the second contact hole is smaller than a width of the third semiconductor pattern.

Technical Field

Various embodiments relate generally to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same.

Background

A semiconductor memory device may include a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array may include a plurality of memory cells, and the peripheral circuit may be configured to perform various operations of the memory cells.

A plurality of memory cells may be arranged three-dimensionally to form a three-dimensional semiconductor memory device. In the three-dimensional semiconductor memory device, gates of memory cells may be coupled to a plurality of word lines stacked on a substrate. In order to increase the integration density of the three-dimensional semiconductor memory device, the number of word lines stacked on top of each other may be increased. The more word lines are stacked on top of each other, the more complicated the manufacturing process of the semiconductor memory device may become.

Disclosure of Invention

According to one embodiment, a semiconductor memory device may include: a substrate including a peripheral circuit; a gate stack structure disposed on a substrate and including a cell array region and a stepped region extending from the cell array region; a channel structure passing through the cell array region of the gate stack structure; a memory layer surrounding sidewalls of the channel structure; a first contact plug passing through a stepped region of the gate stack structure; and an insulating structure surrounding sidewalls of the first contact plug to insulate the first contact plug from the gate stack structure.

According to one embodiment, a method of manufacturing a semiconductor memory device may include: forming a preliminary structure including a first semiconductor pattern and a second semiconductor pattern separated from each other by an insulating layer; forming a stacked structure including interlayer insulating layers and a sacrificial layer alternately stacked on one another on the preliminary structure; forming a channel hole and a first contact hole through the stacked structure; forming a memory layer on a surface of each of the channel hole and the first contact hole; filling the channel hole with a channel structure; forming a first contact plug in the first contact hole; and replacing the sacrificial layer with a conductive pattern. The trench hole may overlap the first semiconductor pattern, and the first contact hole may overlap the second semiconductor pattern. The first contact plug may pass through the memory layer and the second semiconductor pattern in the first contact hole. The conductive patterns may surround the channel structures and the first contact plugs with the memory layer interposed between each of the conductive patterns and each of the channel structures and the first contact plugs.

Drawings

Fig. 1 is a schematic diagram showing a configuration of a semiconductor memory device according to an embodiment;

fig. 2 is a diagram illustrating a cell array region and a staircase region of a semiconductor memory device according to an embodiment;

FIGS. 3A to 3C are sectional views taken along the lines I-I ', II-II ' and III-III ' shown in FIG. 2;

fig. 4 is a cross-sectional view showing a part of a semiconductor memory device according to an embodiment;

FIG. 5A is a diagram illustrating a memory string according to one embodiment, and FIG. 5B is a diagram illustrating a memory layer according to one embodiment;

fig. 6 is a sectional view showing a lower structure of a semiconductor memory device according to an embodiment;

fig. 7 is a flowchart schematically showing a method of manufacturing a semiconductor memory device according to an embodiment;

fig. 8A to 8C are sectional views showing one embodiment with respect to step ST1 shown in fig. 7;

fig. 9A to 9J are sectional views showing one embodiment with respect to step ST3 shown in fig. 7;

fig. 10A to 10K are sectional views showing one embodiment with respect to step ST5 shown in fig. 7;

FIGS. 11A to 11C are sectional views showing one embodiment with respect to step ST7 shown in FIG. 7;

fig. 12A, 12B, 13, 14A and 14B are sectional views showing one embodiment of a process performed after step ST7 shown in fig. 7;

fig. 15 is a block diagram showing a configuration of a memory system according to an embodiment; and

fig. 16 is a block diagram illustrating a configuration of a computing system according to an embodiment.

Detailed Description

The specific structural or functional descriptions disclosed herein are merely exemplary for purposes of describing illustrative embodiments in accordance with the present disclosure. Embodiments may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

Various embodiments relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device capable of simplifying a manufacturing process of the semiconductor memory device.

Fig. 1 is a schematic diagram showing a configuration of a semiconductor memory device according to an embodiment.

Referring to fig. 1, the semiconductor memory device may include a peripheral circuit and a memory cell array disposed on a substrate 201 shown in fig. 6, the substrate 201 including a first region a1 and a second region a 2. The first region a1 may be defined as a region overlapping the gate stack structure GST forming the memory cell array. The second region a2 may be defined as a region not overlapping the gate stack structure GST.

Although not shown in fig. 1, the peripheral circuits may include a row decoder, a page buffer, control logic, and the like. The row decoder, page buffer and control logic may include a transistor TR. A first group of transistors among the transistors TR included in the peripheral circuit may be disposed in the second region a2 of the substrate. The second group of transistors among the transistors TR included in the peripheral circuit may be disposed in the first region a1 of the substrate and may overlap the gate stack structure GST. The gate 213 of each transistor TR may be disposed in an active region ACT defined in the substrate. Junctions JN serving as a source and a drain of each transistor TR shown in fig. 6 may be formed in the active region ACT at opposite sides of the gate 213.

The gate stack structures GST may be spaced apart from each other by the slit SI. Each gate stack structure GST may include a cell array region CAR and a stepped region STA. The stepped region STA may extend from the cell array region CAR. According to one embodiment, each of the gate stack structures GST may include two or more cell array regions CAR and a stepped structure STA disposed between adjacent cell array regions CAR. However, the implementation is not limited thereto. For example, the stepped structure STA of each gate stack structure GST may be disposed at an edge of the gate stack structure GST corresponding to the stepped structure STA.

The stepped structure STA may include a first contact area CA1 and a second contact area CA 2. The stepped structure of the gate stack structure GST may be coupled to a gate contact plug GCT shown in fig. 2, which is disposed in the first contact area CA1 corresponding to the stepped structure. The stepped structure of the gate stack structure GST may be penetrated by the first contact plug PCT1 shown in fig. 2, the first contact plug PCT1 being disposed in the second contact region CA2 corresponding to the stepped structure.

The cell array region CAR may include a plurality of word lines WL shown in fig. 5A and select lines SSL and DSL shown in fig. 5A coupled to the memory string. The memory string may be coupled to a bit line BL disposed on the gate stack structure GST.

According to one embodiment, the transistor TR disposed in the second region a2 may overlap the dummy stack structure disposed at the same level as the gate stack structure GST. According to one embodiment, the dummy lamination structure may be omitted.

Fig. 2 is a diagram illustrating a cell array region CAR and a staircase region STA of a semiconductor memory device according to an embodiment.

Referring to fig. 2, the channel structure CH may penetrate the cell array region CAR of the gate stack structure GST. The cell array region CAR of the gate stack structure GST may extend in the first direction D1 and the second direction D2. The channel structure CH may extend in a third direction D3 orthogonal to a plane extending in the first direction D1 and the second direction D2. According to one embodiment, the first direction D1, the second direction D2, and the third direction D3 may correspond to an x-axis, a y-axis, and a z-axis of a cartesian coordinate system.

The memory layer 81 may surround a sidewall of each channel structure CH. The channel structure CH may be disposed in the gate stack structure GST corresponding to the channel structure. The channel structure CH may be arranged in a zigzag shape. The array of channel structures is not limited thereto. In one embodiment, the array of channel structures CH may form a matrix structure. Each channel structure CH may have one of various cross-sectional shapes including, but not limited to, a circle, an ellipse, a polygon, or a square.

The channel structures CH may be disposed at opposite sides of the upper slit USI formed in the gate stack structure GST. The upper slits USI and the slits SI may extend in the first direction D1 and the third direction D3.

The stepped structure STA of the gate stack structure GST may include a first contact region CA1 coupled to the gate contact plug GCT and a second contact region CA2 penetrated by the first contact plug PCT1, as described with reference to fig. 1. The semiconductor memory device may further include a support pillar SP passing through the stepped region STA of the gate stack structure GST.

Each of the gate contact plug GCT, the support post SP, and the first contact plug PCT1 may have one of various sectional shapes including, but not limited to, an oval shape, a polygonal shape, or a square shape. The arrangement of the gate contact plugs GCT, the support pillars SP, and the first contact plugs PCT1 is not limited to the embodiment shown in fig. 2, but may be variously changed. In a plane extending in the first and second directions D1 and D2, an area of each of the support columns SP and the first contact plugs PCT1 may be larger than an area of each of the channel structures CH.

The gate contact plug GCT may overlap the stepped region STA and may extend in the third direction D3. The first insulation structure IS1 may surround a sidewall of each of the first contact plugs PCT 1. Each of the first contact plugs PCT1 may be insulated from the gate stack structure GST by a first insulation structure IS 1. The first dummy memory layer 81d1 may surround the sidewall of each support post SP. The first dummy memory layer 81d1 may comprise the same material as the memory layer 81.

Fig. 3A to 3C are sectional views taken along the lines I-I ', II-II ', and III-III ' shown in fig. 2.

Referring to fig. 3A to 3C, the gate stack structure GST may include interlayer insulating layers 41 and 63 and conductive patterns CP1 to CPn alternately stacked on each other, where n is a natural number. The conductive patterns CP1 through CPn may be stacked to be spaced apart from each other in the third direction D3 by the interlayer insulating layer 41 or 63 disposed therebetween. The conductive patterns CP 1-CPn may include various conductive materials, such as doped semiconductors, metals, and conductive metal nitrides. Each of the conductive patterns CP1 through CPn may include one conductive material or two or more conductive materials. The interlayer insulating layers 41 and 63 may include a silicon oxide layer.

Each channel structure CH passing through the gate stack structure GST may be spaced apart from the conductive patterns CP1 through CPn by the memory layer 81. Each of the support pillars SP passing through the gate stack structure GST may be spaced apart from the conductive patterns CP1 to CPn by the first dummy memory layer 81d 1.

Each of the support pillars SP may include the same material as that of each of the channel structures CH. According to one embodiment, each of the channel structure CH and the support pillars SP may include a channel layer 83, a core insulation pattern 85, and a capping pattern (capping pattern) 91. The channel layer 83 may be formed on the memory layer 81 or the first dummy memory layer 81d1 corresponding to the channel layer 83, and may include a semiconductor material. For example, the channel layer 83 may include silicon. The channel layer 83 of each channel structure CH may serve as a channel of the memory string. The core insulation pattern 85 and the capping pattern 91 may fill a central region of the channel layer 83. The core insulating pattern 85 may include an oxide. The capping pattern 91 may be disposed on the core insulating pattern 85 and may have a sidewall surrounded by an upper end of the channel layer 83. The capping pattern 91 may include a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. For example, the capping pattern 91 may include a doped silicon layer. According to one embodiment, the core insulating pattern 85 may be omitted, and the channel layer 83 may fill a central region of the memory layer 81 or the first dummy memory layer 81d1 corresponding to the channel layer 83.

One gate stack structure GST may be separated from another gate stack structure GST adjacent thereto by a slit SI. In the third direction D3, the depth of the upper slit USI passing through the upper portion of the gate stack structure GST may be less than the depth of the slit SI. According to one embodiment, the upper slit USI may be deep enough to pass through at least the uppermost conductive pattern CPn of the conductive patterns CP1 through CPn. However, the embodiment is not limited thereto. For example, the upper slit USI may pass through one or more conductive patterns sequentially disposed under the nth conductive pattern CPn. The conductive pattern (e.g., CPn) penetrated by the upper slit USI may be divided into selection lines. The conductive pattern used as the word line WL shown in fig. 5A may not be penetrated by the upper slit USI.

The first contact plug PCT1 may pass through the stepped structure of the gate stack structure GST. The first insulating structure IS1 surrounding each of the first contact plugs PCT1 may include a second dummy memory layer 81d2, the second dummy memory layer 81d2 including the same material as the memory layer 81. The first insulation structure IS1 may further include an oxide layer 95 disposed between the second dummy memory layer 81d2 and the first contact plug PCT1 corresponding to the second dummy memory layer 81d 2.

Each of the channel structure CH, the support post SP, and the first contact plug PCT1 may be formed in a hole passing through the gate stack structure GST. According to one embodiment, the hole may have a structure in which a lower hole and an upper hole are coupled together. A lower hole may be defined as a portion passing through the first stacked structure G1 forming a lower portion of the gate stacked structure GST, and an upper hole may be defined as a portion passing through the second stacked structure G2 forming an upper portion of the gate stacked structure GST. The interlayer insulating layers 41 and 63 may be divided into a first interlayer insulating layer 41 included in the first stacked structure G1 and a second interlayer insulating layer 63 included in the second stacked structure G2. The conductive patterns CP1 to CPn may include a first group of conductive patterns (CP1 to CPk) included in the first stacked structure G1 and a second group of conductive patterns (CPk +1 to CPn) included in the second stacked structure G2, where k is a natural number less than n. The lower holes may be deep enough to pass through the first stacked structure G1 and the upper holes may be deep enough to pass through the second stacked structure G2. The etching process for forming each of the lower and upper holes may be easier than the etching process for forming the holes having a depth passing through both the first and second stacked structures G1 and G2. When the lower hole and the upper hole are formed as described above, respectively, an undercut region (undercut region) may be defined at a boundary between the lower hole and the upper hole. The embodiment is not limited to the structure in which the undercut region is defined at the boundary between the lower hole and the upper hole, and the sidewall of each of the channel structure CH, the support post SP, and the first contact plug PCT1 may be substantially flat.

The conductive patterns CP1 to CPn of the gate stack structure GST may be coupled to the gate contact plug GCT. The gate contact plugs GCT may be coupled to portions of the conductive patterns CP1 through CPn, respectively, which form a stepped structure, and may extend in the third direction D3.

The ridge (rise) defined by the stepped structure may be covered by a gap-filling insulating structure. The gap-filling insulating structure may include a first gap-filling insulating layer 50 covering the bumps defined by the first stacked structure G1 and a second gap-filling insulating layer 68 covering the bumps defined by the second stacked structure G2. The gap-fill insulating structure and the gate stack structure GST may be covered by an upper insulating layer 99. The channel structure CH may extend through the upper insulating layer 99. Each of the support pillars SP, the gate contact plugs GCT, and the first contact plugs PCT1 may pass through the upper insulating layer 99 and the first and second gap filling insulating layers 50 and 68 of the gap filling insulating structure.

The gate stack structure GST may be disposed on the semiconductor patterns 20A and 20B separated from each other by the insulating layer 35. The semiconductor patterns 20A and 20B may include a first semiconductor pattern 20A and a second semiconductor pattern 20B.

Each of the first and second semiconductor patterns 20A and 20B may include a first semiconductor layer 21 and a second semiconductor layer 29. The second semiconductor layer 29 may be spaced apart from the first semiconductor layer 21 and may extend along a bottom surface of the gate stack structure GST. The first semiconductor pattern 20A may include a channel coupling pattern 121 disposed between the first semiconductor layer 21 and the second semiconductor layer 29 corresponding to the first semiconductor pattern 20A, and each of the second semiconductor patterns 20B may include a sacrificial stacked structure SA disposed between the first semiconductor layer 21 and the second semiconductor layer 29. The sacrificial stacked structure SA may include a first protective layer 23, a sacrificial layer 25, and a second protective layer 27 sequentially stacked on the first semiconductor layer 21.

The first semiconductor layer 21 and the channel coupling pattern 121 may include n-type or p-type impurities. According to one embodiment, the channel coupling pattern 121 including the n-type impurity and the first semiconductor layer 21 may be used for a GIDL erase method for performing an erase operation by using a Gate Induced Drain Leakage (GIDL). According to one embodiment, the channel coupling pattern 121 including the p-type impurity and the first semiconductor layer 21 may be used for a well erase method for performing an erase operation by supplying a hole. The second semiconductor layer 29 may be an undoped semiconductor layer or a doped semiconductor layer including the same type of impurities as the first semiconductor layer 21 and the channel coupling pattern 121. The sacrificial layer 25 may include a material having a different etch rate from the first and second protective layers 23 and 27 to selectively etch the sacrificial layer 25. For example, the sacrificial layer 25 may include an undoped silicon layer. Each of the first protective layer 23 and the second protective layer 27 may include an oxide layer.

The first semiconductor pattern 20A may extend to overlap the slit SI and the channel structure CH. The slit SI may pass through the second semiconductor layer 29 of the first semiconductor pattern 20A. An oxide layer 125 may be formed between the slit SI and the first semiconductor pattern 20A.

The first semiconductor pattern 20A may extend to overlap the support post SP. The first semiconductor pattern 20A may overlap a portion of the stepped structure penetrated by the support post SP.

The channel structure CH and the support post SP may extend into the first semiconductor pattern 20A. According to one embodiment, the channel structure CH and the support columns SP may extend into the first semiconductor layer 21 of the first semiconductor pattern 20A.

The memory layer 81 may be divided into a first memory pattern P1 and a second memory pattern P2. The first memory pattern P1 may be disposed between the channel structure CH corresponding to the first memory pattern P1 and the first semiconductor layer 21 of the first semiconductor pattern 20A, and the second memory pattern P2 may be disposed between the channel structure CH corresponding to the second memory pattern P2 and the gate stack structure GST.

The first dummy memory layer 81d1 may be divided into a first dummy pattern P1d and a second dummy pattern P2 d. The first dummy pattern P1d may be disposed between the support pillar SP corresponding to the first dummy pattern P1d and the first semiconductor layer 21 of the first semiconductor pattern 20A, and the second dummy pattern P2d may be disposed between the support pillar SP corresponding to the second dummy pattern P2d and the gate stack structure GST.

The first semiconductor layer 21 of the first semiconductor pattern 20A may surround a lower portion of each channel structure CH and a lower portion of each support post SP. The second semiconductor layer 29 of the first semiconductor pattern 20A may extend along the bottom surface of the gate stack structure GST to surround the channel structure CH and the support pillars SP. The channel coupling pattern 121 may extend between the first and second memory patterns P1 and P2 to contact the channel structure CH. The channel coupling pattern 121 may extend between the first dummy pattern P1d and the second dummy pattern P2d to contact the support pillars SP.

The first contact plug PCT1 may penetrate the second semiconductor pattern 20B. The width of each of the second semiconductor patterns 20B may be greater than the width of the first contact plug PCT 1. The first semiconductor layer 21, the first protective layer 23, the sacrificial layer 25, the second protective layer 27, and the second semiconductor layer 29 of each of the second semiconductor patterns 20B may surround the first contact plug PCT 1. Each of the first contact plugs PCT1 may pass through the first insulation structure IS1 and may extend farther than the first insulation structure IS 1.

The first vertically doped semiconductor pattern 31A may be formed on sidewalls of the first semiconductor pattern 20A, and the second vertically doped semiconductor pattern 31B may be formed on sidewalls of each of the second semiconductor patterns 20B. The first and second vertically doped semiconductor patterns 31A and 31B may include n-type or p-type impurities. According to one embodiment, the first and second vertically doped semiconductor patterns 31A and 31B may include the same type of impurities as the first semiconductor layer 21.

The semiconductor patterns 20A and 20B may be disposed on the lower insulating layer 10 penetrated by the lower contact plugs 11A and 11B. The lower contact plugs 11A and 11B may include a first lower contact plug 11A coupled to the first semiconductor pattern 20A and a second lower contact plug 11B coupled to the first contact plug PCT 1.

The first semiconductor pattern 20A and the first vertically doped semiconductor pattern 31A may overlap the first lower contact plug 11A, and each of the first contact plugs PCT1 and each of the second semiconductor patterns 20B may overlap the second lower contact plug 11B. Each of the first contact plugs PCT1 may pass through the second semiconductor pattern 20B to contact the second lower contact plug 11B.

Fig. 4 is a cross-sectional view illustrating a portion of a semiconductor memory device according to an embodiment. The portion of the semiconductor memory apparatus shown in fig. 4 may overlap the second region a2 shown in fig. 1.

Referring to fig. 4, the lower insulating layer 10 and the insulating layer 35 described with reference to fig. 3A to 3C may extend to overlap the second region a2 described with reference to fig. 1.

The lower contact plug passing through the lower insulating layer 10 may further include a third lower contact plug 11C. The semiconductor patterns divided by the insulating layer 35 may further include a third semiconductor pattern 20C.

The third semiconductor pattern 20C may include the same material as the second semiconductor pattern 20B shown in fig. 3B. The third semiconductor pattern 20C may include a first semiconductor layer 21, a first protective layer 23, a sacrificial layer 25, a second protective layer 27, and a second semiconductor layer 29 sequentially stacked on one another. The third semiconductor pattern 20C may overlap the third lower contact plug 11C. The third vertically doped semiconductor pattern 31C may be formed on sidewalls of the third semiconductor pattern 20C. The third vertically doped semiconductor pattern 31C may include the same type of impurities as the first semiconductor layer 21.

The third semiconductor pattern 20C and the third vertically doped semiconductor pattern 31C may be covered by the dummy stacked structure DST. The dummy stacked structure DST may include dummy interlayer insulating layers 41d and 63d and sacrificial layers 43 and 61 alternately stacked on the third semiconductor pattern 20C and the third vertically doped semiconductor pattern 31C. The dummy interlayer insulating layers 41d and 63d may include the same material as the interlayer insulating layers 41 and 63 described with reference to fig. 3A to 3C, and the dummy interlayer insulating layer 41d may be disposed at the same level as the interlayer insulating layer 41 and the dummy interlayer insulating layer 63d may be disposed at the same level as the interlayer insulating layer 63. The sacrificial layers 43 and 61 may be disposed at the same level as the conductive patterns CP1 through CPn described with reference to fig. 3A through 3C, respectively. The sacrificial layers 43 and 61 may include a material having a different etching rate from the dummy interlayer insulating layers 41d and 63d to selectively etch the sacrificial layers 43 and 61. For example, each of the sacrificial layers 43 and 61 may include a nitride layer.

The second contact plug PCT2 may penetrate the dummy stack structure DST and the third semiconductor pattern 20C. The second contact plug PCT2 may be extended to contact the third lower contact plug 11C.

The second insulating structure IS2 may surround the sidewall of the second contact plug PCT 2. The second insulating structure IS2 may include the same material as the first insulating structure IS1 described with reference to fig. 3B. According to one embodiment, the second insulating structure IS2 may include a third dummy memory layer 81d3 having the same material as the memory layer 81 shown in fig. 3A and 3B, and an oxide layer 95 disposed between the third dummy memory layer 81d3 and the second contact plug PCT 2.

The second contact plug PCT2 may be formed in a hole passing through the dummy stack structure DST. The hole may be formed by a forming process through a lower hole of the lower stacked structure 40 forming a lower portion of the dummy stacked structure DST and by a forming process through an upper hole of the upper stacked structure 60 forming an upper portion of the dummy stacked structure DST. According to this embodiment, an undercut region may be defined at the boundary between the lower hole and the upper hole. Embodiments are not limited to a structure in which an undercut region is defined at a boundary between a lower hole and an upper hole, and a sidewall of the second contact plug PCT2 may be substantially flat. The embodiment is not limited to the method of manufacturing the hole through the formation process of the lower hole and the formation process of the upper hole.

The upper insulating layer 99 described with reference to fig. 3A to 3C may extend to cover the dummy stack structure DST and may be penetrated by the second contact plug PCT 2. The width of the third semiconductor pattern 20C may be greater than that of the second contact plug PCT 2.

The first, second, and third lower contact plugs 11A, 11B, and 11C and the first and second contact plugs PCT1 and PCT2 shown in fig. 3A to 3C and 4 may include various conductive materials capable of transmitting electrical signals.

Fig. 5A is a diagram illustrating a memory string according to an embodiment, and fig. 5B is a diagram illustrating a memory layer according to an embodiment.

Referring to fig. 5A, a memory string may be coupled to a plurality of word lines WL and select lines SSL and DSL. The select lines SSL and DSL may include at least one source select line SSL and at least one drain select line DSL. The word line WL may be disposed between the source select line SSL and the drain select line DSL. A source select line SSL may be coupled to the gate of the source select transistor, a drain select line DSL may be coupled to the gate of the drain select transistor, and a word line WL may be coupled to the gate of the memory cell.

The conductive patterns CP1 to CPn described with reference to fig. 3A to 3C may form a source select line SSL, a word line WL, and a drain select line DSL. According to one embodiment, among the conductive patterns CP1 to CPn, the first conductive pattern CP1 adjacent to the first semiconductor pattern 20A may serve as a source select line SSL, and the nth conductive pattern CPn disposed farthest from the first semiconductor pattern 20A may serve as a drain select line DSL. A conductive pattern between the source select line SSL and the drain select line DSL may serve as a word line WL. According to one embodiment, one or more conductive patterns sequentially disposed above the first conductive pattern CP1 may be used as another source selection line, and one or more conductive patterns sequentially disposed below the nth conductive pattern CPn may be used as another drain selection line.

According to the above-described structure, a drain select transistor may be formed at an intersection of the drain select line DSL and the channel structure CH, a source select transistor may be formed at an intersection of the source select line SSL and the channel structure CH, and a memory cell may be formed at an intersection of the word line WL and the channel structure CH. The memory cells may be coupled in series between the source select transistor and the drain select transistor by the channel layer 83 of the channel structure CH. The source select transistor may be coupled to the channel coupling pattern 121 of the first semiconductor pattern 20A through the channel layer 83. The capping pattern 91 of the channel structure CH may serve as a junction of the drain select transistor.

The memory layer 81 may extend between each of the first semiconductor layer 21 and the second semiconductor layer 29 of the first semiconductor pattern 20A and the channel structure CH. As shown in fig. 5B, each of the first and second memory patterns P1 and P2 of the memory layer 81 may include a tunneling insulating layer TI, a data storage layer DL, and a blocking insulating layer BI.

Fig. 5B shows a cross section of the memory layer 81 surrounding the channel layer 83.

Referring to fig. 5B, the central region of the memory layer 81 may be filled with the channel layer 83, the core insulation pattern 85, and the capping pattern 91 shown in fig. 5A. The tunneling insulation layer TI of the memory layer 81 may surround the channel layer 83, the data storage layer DL of the memory layer 81 may surround the tunneling insulation layer TI, and the blocking insulation layer BI of the memory layer 81 may surround the data storage layer DL.

The data storage layer DL may include a material layer capable of storing data changed by using Fowler-Nordheim tunneling. The data storage layer DL may include various materials, such as a charge trapping layer. The charge trapping layer may include a nitride layer. The embodiment is not limited thereto, and the data storage layer DL may include a phase change material, nanodots, or the like. The blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunneling insulating layer TI may include a silicon oxide layer that enables charge tunneling.

Each of the first dummy memory layer 81d1 shown in fig. 3A, the second dummy memory layer 81d2 shown in fig. 3B, and the third dummy memory layer 81d3 shown in fig. 4 may include the same material layers as the above-described tunneling insulating layer TI, data storage layer DL, and blocking insulating layer BI.

Fig. 6 is a sectional view showing a lower structure LS of a semiconductor memory device according to an embodiment.

Referring to fig. 6, a lower structure LS may be disposed between a substrate 201 including a first region a1 and a second region a2 and a lower insulating layer 10 penetrated by first, second, and third lower contact plugs 11A, 11B, and 11C.

The lower structure LS may include a plurality of transistors TR, discharge impurity regions DCI, and an interconnect structure 221. A plurality of transistors TR may be formed on the active region. The active region and the discharge impurity region DCI may be separated from each other by an isolation layer 203 formed in the substrate 201. The interconnection structure 221 may be connected to the transistor TR and the discharge impurity region DCI. The discharge impurity region DCI and the transistor TR may be covered by an insulating layer lamination structure 220 in which two or more insulating layers are laminated, and the interconnection structure 221 may pass through the insulating layer lamination structure 220.

The discharge impurity region DCI may be formed in the substrate 201. The discharge impurity region DCI may be connected to the first lower contact plug 11A via an interconnect structure 221 corresponding to the discharge impurity region DCI. The discharging impurity region DCI may be provided to discharge the charges accumulated in the first semiconductor pattern 20A.

Each transistor TR may include a gate insulating layer 211, a gate electrode 213, and a junction JN. The gate insulating layer 211 and the gate electrode 213 of each transistor TR may be stacked on the active region. The junction JN of the transistor TR may be formed by implanting n-type or p-type impurities into the active regions protruding at opposite sides of the corresponding gate electrode 213.

Each of the first contact plugs PCT1 passing through the stepped region STA of the gate stack structure GST may be connected to the transistor TR via the second lower contact plug 11B and the interconnection structure 221.

The transistors disposed in the second region a2 of the transistors TR may be connected to the second contact plug PCT2 passing through the dummy stack structure DST via the interconnect structure 221 and the third lower contact plug 11C corresponding to the transistors disposed in the second region a 2.

Fig. 7 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

Referring to fig. 7, the method of manufacturing the semiconductor memory device may include a step ST1 of forming a preliminary structure, a step ST3 of forming a stacked structure, a step ST5 of forming a channel structure, a support pillar, and a contact plug, and a step ST7 of forming a channel coupling pattern.

The substrate including the lower structure and the lower contact plug may be formed before performing step ST 1. The lower structure may include the lower structure LS described with reference to fig. 6, and the lower contact plugs may include the first, second, and third lower contact plugs 11A, 11B, and 11C described with reference to fig. 3A to 3C, 4, and 6. In step ST1, a preliminary structure may be formed on the substrate including the lower structure and the lower contact plug.

In step ST3, the stacked structure may be formed to have a stepped structure and may be penetrated by a channel hole, a dummy hole, and a contact hole. According to one embodiment, step ST3 may include forming a first step structure that forms a lower portion of the stacked structure and forming a second step structure that forms an upper portion of the stacked structure. However, the embodiment is not limited thereto. According to one embodiment, step ST3 may include stacking a plurality of material layers as high as the height of the target stacked structure, and forming the stepped structure by etching the plurality of material layers.

Step ST5 may include forming a memory layer on sidewalls of each of the channel hole, the dummy hole, and the contact hole, forming a channel structure and a support pillar in the channel hole and the dummy hole, respectively, and forming a contact plug in the contact hole. Thus, each of the channel structure, the support pillar, and the contact plug may be surrounded by the memory layer.

Step ST7 may include partially exposing sidewalls of the channel structure and forming a channel coupling pattern contacting the exposed sidewalls of the channel structure.

Hereinafter, a method of manufacturing a semiconductor memory device according to one embodiment is described with reference to fig. 8A to 8C, 9A to 9J, 10A to 10K, 11A to 11C, 12A, 12B, 13, 14A, and 14B. The following figures are cross-sectional views of the structure according to the manufacturing steps. The following figures are sectional views taken along the lines I-I ', II-II ', and III-III ' and corresponding to the second region a 2. The following figures illustrate one embodiment of a method for fabricating a semiconductor memory device including the structure illustrated in fig. 3A through 3C and 4.

Fig. 8A to 8C are sectional views showing one embodiment regarding step ST1 shown in fig. 7.

Referring to fig. 8A, before step ST1 is performed, lower contact plugs 311A, 311B, and 311C passing through the lower insulating layer 300 may be formed on the substrate 201 including the lower structure LS shown in fig. 6. The lower contact plugs 311A, 311B, and 311C may include various conductive materials capable of transmitting electrical signals.

The lower contact plugs 311A, 311B, and 311C may include a first lower contact plug 311A, a second lower contact plug 311B, and a third lower contact plug 311C. The first lower contact plug 311A may be connected to the discharged impurity region DCI shown in fig. 6. The second and third lower contact plugs 311B and 311C may be respectively connected to corresponding ones of the transistors TR of the peripheral circuit shown in fig. 6.

Referring to fig. 8B, step ST1 may include forming preliminary first, second, and third semiconductor patterns 320a1, 320B, and 320C separated from each other.

The preliminary first semiconductor pattern 320a1 may overlap the first lower contact plug 311A, the second semiconductor pattern 320B may overlap the second lower contact plug 311B, and the third semiconductor pattern 320C may overlap the third lower contact plug 311C. An edge of the preliminary first semiconductor pattern 320a1 may overlap the first lower contact plug 311A. The width of the second semiconductor pattern 320B may be greater than that of the second lower contact plug 311B, and the second semiconductor pattern 320B may protrude toward opposite sides of the second lower contact plug 311B. The third semiconductor pattern 320C may have a width greater than that of the third lower contact plug 311C, and the third semiconductor pattern 320C may protrude toward opposite sides of the third lower contact plug 311C.

The step of forming the preliminary first, second, and third semiconductor patterns 320a1, 320B, and 320C may include: sequentially stacking a first semiconductor layer 321, a sacrificial stacked structure 305, and a second semiconductor layer 329 on the lower insulating layer 300 to cover the first, second, and third lower contact plugs 311A, 311B, and 311C; and etching the first semiconductor layer 321, the sacrificial stacked structure 305, and the second semiconductor layer 329.

The first semiconductor layer 321 may include n-type or p-type impurities. The sacrificial stack structure 305 may include a first protective layer 323, a sacrificial layer 325, and a second protective layer 327 sequentially stacked on one another. The sacrificial layer 325 may include a material having a different etching rate from the first and second protective layers 323 and 327 to selectively etch the sacrificial layer 325, and the first and second protective layers 323 and 327 may include a material capable of protecting the first and second semiconductor layers 321 and 329 when the sacrificial layer 325 is etched. For example, the sacrificial layer 325 may comprise an undoped silicon layer. Each of the first protective layer 323 and the second protective layer 327 may include an oxide layer. The second semiconductor layer 329 may include an undoped semiconductor layer or a doped semiconductor layer including n-type or p-type impurities. At least one of the first protective layer 323, the second protective layer 327, and the second semiconductor layer 329 may be omitted.

Referring to fig. 8C, step ST1 may include forming first, second and third vertically doped semiconductor patterns 331A, 331B and 331C on sidewalls of the preliminary first, second and third semiconductor patterns 320a1, 320B and 320C, respectively. The first, second, and third vertically doped semiconductor patterns 331A, 331B, and 331C may include the same impurities as the first semiconductor layer 321 described with reference to fig. 8B.

Step ST1 may include filling spaces between the preliminary first, second, and third semiconductor patterns 320a1, 320B, and 320C with an insulating layer 335.

A preliminary structure including preliminary first, second, and third semiconductor patterns 320a1, 320B, and 320C overlapping the first, second, and third lower contact plugs 311A, 311B, and 311C, respectively, and separated from each other by the insulating layer 335 may be formed through the process described above with reference to fig. 8A through 8C.

Fig. 9A to 9J are sectional views showing one embodiment regarding step ST3 shown in fig. 7.

Referring to fig. 9A, step ST3 may include forming a first stacked structure 340 on the preliminary structure. The first stacked structure 340 may include first interlayer insulating layers 341 and first sacrificial layers 343 alternately stacked on each other. The first interlayer insulating layer 341 may include a first material layer, and the first sacrificial layer 343 may include a second material layer. The second material layer may include an insulating material having a different etch rate from the first material layer to selectively etch the second material layer. For example, the first material layer may include an oxide layer, and the second material layer may include a nitride layer.

Referring to fig. 9B, step ST3 may include etching the first stacked structure 340 to form a first stepped structure SW 1.

Referring to fig. 9C, step ST3 may include forming a first gap-fill insulating layer 350 covering the first stepped structure SW1 shown in fig. 9B. The bump defined by the first stepped structure SW1 may be covered by the first gap filling insulating layer 350.

Referring to fig. 9D, step ST3 may include forming lower holes 351A to 351D. The lower holes 351A to 351D may be simultaneously formed. The lower holes 351A to 351D may include a first lower hole 351A, a second lower hole 351B, a third lower hole 351C, and a fourth lower hole 351D.

The first lower hole 351A may pass through the first laminate structure 340 and may extend into the preliminary first semiconductor pattern 320a 1. The first lower hole 351A may pass through the second semiconductor layer 329, the second protective layer 327, the sacrificial layer 325, and the first protective layer 323 of the preliminary first semiconductor pattern 320a1, and may extend into the first semiconductor layer 321.

The second lower hole 351B may pass through the first stepped structure SW1 covering the first stepped structure SW1 shown in fig. 9B and under the first gap filling insulating layer 350, or may pass through a portion of the first stacked structure 340 adjacent to the first stepped structure SW 1. The second lower hole 351B may pass through the second semiconductor layer 329, the second protective layer 327, the sacrificial layer 325, and the first protective layer 323 of the preliminary first semiconductor pattern 320a1, and may extend into the first semiconductor layer 321.

The third lower hole 351C may pass through a portion of the first stacked structure 340 overlapping the second semiconductor pattern 320B. The third lower hole 351C may pass through the first gap-filling insulating layer 350 on the portion of the first stepped structure SW1 and the portion of the first stepped structure SW1 shown in fig. 9B. The third lower hole 351C may pass through the second semiconductor layer 329, the second protective layer 327, the sacrificial layer 325, and the first protective layer 323 of the second semiconductor pattern 320B, and may extend into the first semiconductor layer 321. The width of the third lower hole 351C may be less than the width of the second semiconductor pattern 320B.

The fourth lower hole 351D may pass through a portion of the first stacked structure 340 overlapping the third semiconductor pattern 320C. The fourth lower hole 351D may pass through the second semiconductor layer 329, the second protective layer 327, the sacrificial layer 325, and the first protective layer 323 of the third semiconductor pattern 320C, and may extend into the first semiconductor layer 321. The fourth lower hole 351 may have a width smaller than that of the third semiconductor pattern 320.

When an etching process of forming the first, second, third, and fourth lower holes 351A, 351B, 351C, and 351D is performed, each of the preliminary first, second, and third semiconductor patterns 320a, 320B, and 320C may serve as an etch stop layer.

Referring to fig. 9E, step ST3 may include filling the first lower hole 351A, the second lower hole 351B, the third lower hole 351C, and the fourth lower hole 351D with a vertical sacrificial layer 353. The vertical sacrificial layer 353 may include a material having a different etch rate from the first material layer and the second material layer described above with reference to fig. 9A to selectively remove the vertical sacrificial layer 353. According to one embodiment, the vertical sacrificial layer 353 may include a metal, such as tungsten.

Referring to fig. 9F, step ST3 may include forming a second stacked structure 360 on the first stacked structure 340 having the first stepped structure penetrated by the vertical sacrificial layer 353 and covered by the first gap-fill insulating layer 350. The second stacked structure 360 may include second sacrificial layers 363 and second interlayer insulating layers 361 alternately stacked on each other. The second interlayer insulating layer 361 may include the first material layer described with reference to fig. 9A, and the second sacrificial layer 363 may include the second material layer described with reference to fig. 9A.

Referring to fig. 9G, step ST3 may include etching the second stacked structure 360 to form a second stepped structure SW 2. A portion of the second stacked structure 360 overlapping the first stepped structure SW1 may be removed, and the first stepped structure SW1 may not overlap the second stacked structure 360 having the second stepped structure SW 2.

Referring to fig. 9H, step ST3 may include forming a second gap filling insulating layer 368 covering the second stepped structure SW2 shown in fig. 9G. The bump defined by the second stepped structure SW2 may be covered by a second gap filling insulating layer 368. Subsequently, a first mask layer 371 may be formed to cover the second gap filling insulating layer 368 and the second stacked structure 360. The first mask layer 371 may include a nitride layer.

Referring to fig. 9I, step ST3 may include forming upper holes 373A to 373D. The upper holes 373A to 373D may be formed simultaneously. The upper holes 373A to 373D may include a first upper hole 373A coupled to the first lower hole 351A, a second upper hole 373B coupled to the second lower hole 351B, a third upper hole 373C coupled to the third lower hole 351C, and a fourth upper hole 373D coupled to the fourth lower hole 351D.

The first upper hole 373A, the second upper hole 373B, the third upper hole 373C, and the fourth upper hole 373D may be formed by etching the first mask layer 371, the second stacked structure 360, and the second gap filling insulating layer 368 to expose the vertical sacrificial layer 353. The first upper hole 373A may pass through the second stacked structure 360. The second upper hole 373B may pass through the second stepped structure SW2 shown in fig. 9G, or may pass through the second gap filling insulating layer 368 overlapping the first stepped structure SW1 shown in fig. 9G. The third upper hole 373 may pass through the second stepped structure of the second stacked structure 360 overlapping the third lower hole 351C, or may pass through the second gap-filling insulating layer 368 overlapping the third lower hole 351C. The fourth upper hole 373 may pass through a portion of the second stacked structure 360 overlapping the fourth lower hole 351D.

Referring to fig. 9J, step ST3 may include removing the vertical sacrificial layer 353 shown in fig. 9I through the first upper hole 373A, the second upper hole 373B, the third upper hole 373C, and the fourth upper hole 373D shown in fig. 9I. Accordingly, the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD may be opened.

The channel hole HA may be defined by coupling the first lower hole 351A to the first upper hole 373A shown in fig. 9I, and the first semiconductor layer 321 of the preliminary first semiconductor pattern 320a1 may be exposed. The dummy hole HB may be defined by coupling the second lower hole 351B to the second upper hole 373B shown in fig. 9I, and the first semiconductor layer 321 of the preliminary first semiconductor pattern 320a1 may be exposed. The first contact hole HC may be defined by coupling the third lower hole 351C to the third upper hole 373C shown in fig. 9I, and the first semiconductor layer 321 of the second semiconductor pattern 320B may be exposed. The second contact hole HD may be defined by coupling the fourth lower hole 351D to the fourth upper hole 373D shown in fig. 9I, and the first semiconductor layer 321 of the third semiconductor pattern 320C may be exposed.

The stepped stacked structure 379 having the stepped structure and penetrated by the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD may be formed by the process described above with reference to fig. 9A to 9J. The channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD may be formed such that the channel hole HA and the dummy hole HB overlap the preliminary first semiconductor pattern 320a1, the first contact hole HC overlaps the second semiconductor pattern 320B, and the second contact hole HD overlaps the third semiconductor pattern 320C.

Fig. 10A to 10K are sectional views showing one embodiment regarding step ST5 shown in fig. 7.

Referring to fig. 10A, step ST5 may include forming a memory layer 381 on a surface of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, forming a channel layer 383 on the memory layer 381, and filling a central region of the channel layer 383 with a core insulating layer 385.

The memory layer 381 may be formed by sequentially stacking the blocking insulating layer BI, the data storage layer DL, and the tunneling insulating layer TI described with reference to fig. 5B. The memory layer 381 may be simultaneously formed on the surfaces of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD.

According to one embodiment, the channel layer 383 may be conformally formed on the memory layer 381, and the core insulating layer 385 may be formed by filling a central region of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, which is not filled with the channel layer 383, with a flowable material layer, and then by hardening the flowable material layer. The flowable material layer may include Polysilazane (PSZ).

Referring to fig. 10B, step ST5 may include removing an upper end of the core insulating layer 385 shown in fig. 10A to define a hollow portion HP at an upper end of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD. Accordingly, a core insulation pattern 385P opening an upper end of the channel layer 383 may be defined.

Subsequently, step ST5 may include forming a doped semiconductor layer 391L to fill the hollow portion HP. The doped semiconductor layer 391L may include at least one of an n-type impurity and a p-type impurity.

Referring to fig. 10C, step ST5 may include planarizing the doped semiconductor layer 391L shown in fig. 10B to expose the first mask layer 371. Accordingly, a cap pattern 391 surrounded by an upper end of the channel layer 383 may be formed.

Through the processes described with reference to fig. 10A to 10C, the channel structure 380A may be formed in the channel hole HA, and the support column 380B may be formed in the dummy hole HB, and the first dummy channel structure 380C and the second dummy channel structure 380D may be formed in the first contact hole HC and the second contact hole HD, respectively. According to an embodiment, each of the channel structure 380A, the support pillar 380B, the first dummy channel structure 380C, and the second dummy channel structure 380D may include a channel layer 383, a core insulating pattern 385P, and a capping pattern 391.

Although not shown in fig. 10C, according to an embodiment, the capping pattern 391 may be omitted, and each of the channel structure 380A, the support pillar 380B, the first dummy channel structure 380C, and the second dummy channel structure 380D may include a channel layer 383 filling a central region of the memory layer 381.

Referring to fig. 10D, step ST5 may include forming a second mask layer 393 extending to cover the channel structures 380A and the support pillars 380B on the first mask layer 371. The second mask layer 393 may be etched to expose the first dummy channel structure 380C and the second dummy channel structure 380D shown in fig. 10C.

Subsequently, step ST5 may include removing the cover pattern 391 illustrated in fig. 10C from each of the first contact hole HC and the second contact hole HD through an etching process using the second mask layer 393 as an etching barrier. Accordingly, the core insulation pattern 385 may be exposed. When the capping pattern 391 is etched, the upper end of the channel layer 383 shown in fig. 10C may be removed from the first and second contact holes HC and HD, and a portion of the channel layer 383 may remain.

Referring to fig. 10E, step ST5 may include removing the core insulating pattern 385P shown in fig. 10D from each of the first and second contact holes HC and HD through an etching process using the second mask layer 393 as an etch barrier.

Referring to fig. 10F, step ST5 may include removing the channel layer 383P shown in fig. 10E from each of the first and second contact holes HC and HD through an etching process using the second mask layer 393 as an etch barrier. Accordingly, the memory layer 381 formed along the surface of each of the first and second contact holes HC and HD may be exposed.

Referring to fig. 10G, step ST5 may include forming an oxide layer 395 on the memory layer 381 exposed on a surface of each of the first and second contact holes HC and HD. Oxide layer 395 can be formed to compensate for the insulating properties of memory layer 381. According to one embodiment, the formation of oxide layer 395 may be omitted.

Referring to fig. 10H, step ST5 may include forming a first contact hole extension EA coupled to the first contact hole HC and a second contact hole extension EB coupled to the second contact hole HD.

The first contact hole extension EA may pass through the memory layer 381 and the oxide layer 395 of the bottom surface of the first contact hole HC and pass through the first semiconductor layer 321 of the second semiconductor pattern 320B to expose the second lower contact plug 311B. The second contact hole extension EB may pass through the memory layer 381 and the oxide layer 395 of the bottom surface of the second contact hole HD and pass through the first semiconductor layer 321 of the third semiconductor pattern 320 to expose the third lower contact plug 311C. Hereinafter, the memory layer and the oxide layer remaining in each of the first and second contact holes HC and HD may be referred to as a dummy memory layer 381P and an oxide layer pattern 395P.

Referring to fig. 10I, step ST5 may include forming a first contact plug 397A filling the first contact hole HC and the first contact hole extension EA and a second contact plug 397B filling the second contact hole HD and the second contact hole extension EB.

The first and second contact plugs 397A and 397B may include various conductive materials capable of transmitting electrical signals. The first contact plug 397A may contact the second lower contact plug 311B, and the second contact plug 397B may contact the third lower contact plug 311C. When the first and second contact plugs 397A and 397B are formed, the second mask layer 393 illustrated in fig. 10H may be removed.

Referring to fig. 10J, after forming the first and second contact plugs 397A and 397B, the first mask layer 371 shown in fig. 10I may be removed.

Referring to fig. 10K, the region from which the first mask layer is removed may be filled with a first upper insulating layer 399. The first upper insulating layer 399 may surround the upper ends of the channel structure 380A, the support columns 380B, the first contact plug 397A, and the second contact plug 397B.

As described above with reference to fig. 10A to 10I, the dummy memory layer 381P surrounding each of the first and second contact plugs 397A and 397B may be formed through a process of forming the memory layer 381 surrounding the channel structure 380A. The dummy memory layer 381P may serve as an insulating structure to insulate the first and second contact plugs 397A and 397B.

Fig. 11A to 11C are sectional views showing one embodiment regarding step ST7 shown in fig. 7.

Referring to fig. 11A, an upper slit may be formed, an isolation insulating layer 401 filling the upper slit may be formed, and a second upper insulating layer 411 may be formed on the first upper insulating layer 399 before step ST7 is performed. The second upper insulating layer 411 may extend to cover the channel structure 380A, the support pillars 380B, the first contact plugs 397A, and the second contact plugs 397B shown in fig. 10K. The upper slit may correspond to the upper slit USI shown in fig. 2 and 3C.

Step ST7 may include forming a slit 413 through the second upper insulating layer 411, the first upper insulating layer 399, and the stepped layered structure 379. The slits 413 may extend into the preliminary first semiconductor pattern 320a 1. The slits 413 may pass through the second semiconductor layer 329 of the preliminary first semiconductor pattern 320a 1. The slits 413 may extend into the sacrificial layer 325 of the preliminary first semiconductor pattern 320a 1. The sacrificial layer 325 may be exposed through the bottom surface of the slit 413.

Referring to fig. 11B, step ST7 may include removing the sacrificial layer 325 of the preliminary first semiconductor pattern 320a1 shown in fig. 11A to expose the memory layer through the slits 413, and dividing the memory layer into first and second memory patterns 381P1 and 381P2 by removing the exposed memory layer. When an etching process for removing the memory layer is performed, the first and second protective layers 323 and 327 of the preliminary first semiconductor pattern 320a1 shown in fig. 11A may be removed to expose the first and second semiconductor layers 321 and 329 of the preliminary first semiconductor pattern 320a 1.

Hereinafter, a space disposed between the first and second semiconductor layers 321 and 329 and extending between the first and second memory patterns 381P1 and 381P2 may be defined as a horizontal space 415. The horizontal space 415 may expose the channel layer 383 of the channel structure 380A.

Referring to fig. 11C, step ST7 may include filling the horizontal space 415 shown in fig. 11B with a trench coupling pattern 421. The channel coupling pattern 421 may contact the first and second semiconductor layers 321 and 329 and the channel layer 383. The channel coupling pattern 421 may include n-type impurities or p-type impurities.

The channel coupling pattern 421 may be formed by a selective growth method, for example, a Selective Epitaxial Growth (SEG) method using at least one of the first and second semiconductor layers 321 and 329 and the channel layer 383 as a seed layer. According to one embodiment, the channel coupling pattern 421 may be formed by a non-selective method, for example, a Chemical Vapor Deposition (CVD) method.

The first semiconductor pattern 320a2 including the first semiconductor layer 321, the second semiconductor layer 329, and the channel coupling pattern 421 may be formed through the process described above with reference to fig. 11A to 11C.

Fig. 12A, 12B, 13, 14A and 14B are sectional views illustrating one embodiment of a process performed after step ST7 shown in fig. 7.

Fig. 12A and 12B are sectional views showing that the first sacrificial layer 343 described with reference to fig. 9A and the second sacrificial layer 363 described with reference to fig. 9F are replaced with conductive patterns.

Referring to fig. 12A, an oxide layer 425 may be formed on the surface of the first semiconductor pattern 320a2 through the slits 413. The oxide layer 425 may be formed by oxidizing a portion of the first semiconductor pattern 320a 2.

Subsequently, the first sacrificial layer and the second sacrificial layer adjacent to the slit 413 may be selectively removed. Hereinafter, the region where the first sacrificial layer and the second sacrificial layer are removed may be referred to as a gate region 431. The gate region 431 may be defined between respective layers of the first and second interlayer insulating layers 341 and 361.

Referring to fig. 12B, after the gate regions 431 shown in fig. 12A are opened, the gate regions 431 may be filled with conductive patterns 433, respectively.

The step of forming the conductive pattern 433 may include: forming a barrier metal layer extending along the surface of the gate region 431; forming a conductive layer on the barrier metal layer thick enough to fill the gate region 431; and etching the barrier metal layer and the conductive layer to be separated into the conductive pattern 433. Accordingly, a gate stack structure 430 including the first and second interlayer insulating layers 341 and 361 and the conductive pattern 433 disposed between respective layers of the first and second interlayer insulating layers 341 and 361 that are adjacent to each other may be formed.

Fig. 13 is a cross-sectional view of the end portion of the first semiconductor pattern 320a2 formed through the process described above with reference to fig. 11A through 11C, the stepped structure of the gate stack structure 430 formed through the process described above with reference to fig. 12A and 12B, and the first and second sacrificial layers 343 and 363 which remain and form the dummy stack structure 440.

Referring to fig. 13, the first vertical doping pattern 331A may remain on sidewalls of the first semiconductor pattern 320a 2.

The gate stack structure 430 may surround the channel structure 380A, the support pillar 380B, and the first contact plug 397A. The support pillars 380B and the first contact plugs 397A may pass through the stepped structure of the gate stack structure 430 covered by the first and second gap-filling insulating layers 350 and 368. The conductive pattern 433 of the gate stack structure 430 may surround the channel structure 380A, and a portion of the conductive pattern 433 forming a stepped structure of the gate stack structure 430 may surround the support pillar 380B and the first contact plug 397A.

The channel coupling pattern 421 of the first semiconductor pattern 320a2 may not only extend between the first and second memory patterns 381P1 and 381P2 but also extend to contact the channel layer 383 of the support post 380B. Accordingly, the memory layer surrounding the support pillars 380B may be divided into first dummy patterns 381P1d and second dummy patterns 381P2 d. The support columns 380B may be insulated from the conductive patterns 433 by the second dummy patterns 381P2 d.

The first contact plug 397A may be insulated from the conductive pattern 433 by the dummy memory layer 381P. Therefore, according to one embodiment, even when a barrier structure for preventing the conductive pattern 433 from being formed around the first contact plug 397A is not additionally formed, the operation characteristics of the semiconductor memory device may be ensured. Accordingly, the semiconductor memory device according to one embodiment may prevent process difficulties and defects due to a manufacturing process of forming a barrier structure.

When the gate stack structure 430 is formed, some of the first and second sacrificial layers 343 and 363, which are disposed in the second region a2, may not be replaced with the conductive pattern 433, but may remain, and the second region a2 is spaced farther from the slit 413 shown in fig. 12A to 12B than the first region a1 shown in fig. 2. The first and second sacrificial layers 343 and 363 and the first and second interlayer insulating layers 341 and 361 remaining in the second region a2 may form a dummy stacked structure 440. The dummy stack structure 440 may overlap the third semiconductor pattern 320C and may surround the second contact plug 397B.

Fig. 14A and 14B are sectional views illustrating the formation of the bit line contact plug 451, the gate contact plug 453, the first upper contact plug 455, and the second upper contact plug 457.

Referring to fig. 14A, upper contact holes 441, 443, 445, and 447 may be formed through at least one of the second upper insulating layer 411, the first upper insulating layer 399, the second gap-filling insulating layer 368, and the first gap-filling insulating layer 350. The support columns 380B may be covered with the second upper insulating layer 411 without being exposed to the outside.

The upper contact holes 441, 443, 445, and 447 may include: a first upper contact hole 441 exposing the capping pattern 391 of the channel structure 380A; second upper contact holes 443 exposing corresponding ones of the conductive patterns 433; a third upper contact hole 445 exposing the first contact plug 397A; and a fourth upper contact hole 447 exposing the second contact plug 397B. The second upper contact hole 443 may overlap the stepped structure, and may expose the conductive pattern 433 corresponding to the second upper contact hole 443.

Referring to fig. 14B, after each of the first, second, third, and fourth upper contact holes 441, 443, 445, and 447 is filled with a conductive material, the surface of the conductive material may be planarized. Accordingly, the bit line contact plug 451, the gate contact plug 453, the first upper contact plug 455, and the second upper contact plug 457 may be formed.

The bit line contact plug 451 may be coupled to the channel structure 380A, the gate contact plug 453 may be coupled to the conductive pattern 433 corresponding to the gate contact plug 453, the first upper contact plug 455 may be coupled to the first contact plug 397A, and the second upper contact plug 457 may be coupled to the second contact plug 397B.

Subsequently, processes subsequent to the processes of forming the bit line contact plug 451, the gate contact plug 453, the first upper contact plug 455, and the second upper contact plug 457 may be performed, for example, forming the bit line BL shown in fig. 1. The bit line BL may be coupled to the bit line contact plug 451.

FIG. 15 is a block diagram illustrating a memory system 1100 according to one embodiment.

Referring to fig. 15, a memory system 1100 may include a memory device 1120 and a memory controller 1110.

Memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include: a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a stepped structure; a contact plug passing through the stepped structure of the gate stack structure; and an insulating structure surrounding the contact plug.

The memory controller 1110 may be configured to control the memory device 1120, and may include a Static Random Access Memory (SRAM)1111, a Central Processing Unit (CPU)1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may serve as an operation memory for the CPU 1112, the CPU 1112 may perform a general control operation for data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol of a host accessing the memory system 1100. Further, the error correction block 1114 may detect and correct errors included in data read from the memory device 1120, and the memory interface 1115 may perform an interface connection with the memory device 1120. In addition, the memory controller 1110 may further include a Read Only Memory (ROM) for storing code data interfacing with the host.

The memory system 1100 having the above-described configuration may be a Solid State Drive (SSD) or a memory card in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) via one of a variety of interface protocols including, but not limited to, Universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

Fig. 16 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment.

Referring to FIG. 16, computing system 1200 may include a CPU 1220, Random Access Memory (RAM)1230, user interface 1240, modem 1250, and memory system 1210 electrically coupled to system bus 1260. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, an image processor, a mobile DRAM, and the like may be further included.

Memory system 1210 may include a memory device 1212 and a memory controller 1211. Memory device 1212 may include: a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a stepped structure; a contact plug passing through the stepped structure of the gate stack structure; and an insulating structure surrounding the contact plug.

According to the present disclosure, the manufacturing process may be simplified by forming the contact hole using a channel hole forming process.

According to the present disclosure, an insulating structure capable of insulating a contact plug disposed in a contact hole from a conductive pattern of a gate stack structure may be formed through a memory layer forming process, so that a manufacturing process may be simplified.

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2019-.