阅读说明：本技术 半导体结构及其制造方法 (Semiconductor structure and manufacturing method thereof ) 是由 陈明发 陈宪伟 陈洁 于 2020-09-24 设计创作，主要内容包括：提供一种半导体结构及一种半导体结构的制造方法。所述半导体结构包括集成电路组件、在侧向上包封集成电路组件的侧壁的绝缘层、设置在绝缘层及集成电路组件上的重布线结构、以及与重布线结构相对地耦合到集成电路组件的背侧的翘曲控制部分。重布线结构电连接到集成电路组件。翘曲控制部分包括衬底、设置在衬底与集成电路组件之间的图案化介电层、以及嵌入在图案化介电层中且与集成电路组件电隔离的金属图案。(A semiconductor structure and a method of fabricating a semiconductor structure are provided. The semiconductor structure includes an integrated circuit component, an insulating layer laterally encapsulating sidewalls of the integrated circuit component, a redistribution structure disposed on the insulating layer and the integrated circuit component, and a warpage-controlling portion coupled to a backside of the integrated circuit component opposite the redistribution structure. The rerouting structure is electrically connected to the integrated circuit assembly. The warpage-controlling portion includes a substrate, a patterned dielectric layer disposed between the substrate and the integrated circuit component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the integrated circuit component.)

1. A semiconductor structure, comprising:

an integrated circuit component;

an insulating layer laterally encapsulating sidewalls of the integrated circuit assembly;

a rewiring structure disposed on the insulating layer and the integrated circuit assembly, the rewiring structure being electrically connected to the integrated circuit assembly; and

a warp control portion coupled to a backside of the integrated circuit assembly opposite the rerouting structure, the warp control portion comprising:

a substrate;

a patterned dielectric layer disposed between the substrate and the integrated circuit component; and

a metal pattern embedded in the patterned dielectric layer and electrically isolated from the integrated circuit component.

Technical Field

Embodiments of the present invention relate to a semiconductor structure and a method of fabricating the same, and more particularly, to a semiconductor structure including a warpage-controlling portion and a method of fabricating the same.

Background

The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, these improvements in integration density come from the ever-decreasing minimum feature size (minimum feature size), which enables more components to be integrated into a given area. Technological advances in Integrated Circuit (IC) design have produced one generation and another, where each generation of ICs is smaller and more complex than the previous generation. Examples of the semiconductor device package type include a three-dimensional integrated circuit (3 DIC). These relatively new types of semiconductor packaging technologies face manufacturing challenges.

Disclosure of Invention

In accordance with some embodiments, a semiconductor structure includes an Integrated Circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage-controlling portion coupled to a backside of the IC component opposite the redistribution structure. The rerouting structure is electrically connected to the IC assembly. The warpage-controlling portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.

According to some alternative embodiments, a semiconductor structure includes an Integrated Circuit (IC) portion and a warpage-controlling portion attached to the IC portion. The IC part includes an IC package embedded in the insulating layer, and a rewiring structure provided on the IC package and the insulating layer, wherein a bonding connector of the IC package is bonded to a bonding connector of the rewiring structure, and a contact area of the bonding connector of the IC package at a bonding interface of the IC package and the rewiring structure is substantially equal to a surface area of the bonding connector of the rewiring structure. The warpage-controlling portion includes a first substrate and a first metal pattern embedded in a first dielectric layer. The first metal pattern is interposed between the first substrate and the IC portion.

According to some alternative embodiments, a method of fabricating a semiconductor structure includes at least the following steps. Forming an Integrated Circuit (IC) portion and forming the IC portion includes analyzing a warpage characteristic of the IC portion. Forming the warpage-controlling portion based on the warpage characteristics of the IC portion and forming the IC portion includes forming a metal pattern in an opening of a patterned dielectric layer over the substrate. The IC portion is flattened by bonding the IC portion to the warpage-controlling portion.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1E show schematic cross-sectional views of an Integrated Circuit (IC) portion at various stages of fabrication, according to some embodiments.

Fig. 2A-2B illustrate schematic warp profiles of an IC portion, according to some embodiments.

Fig. 3A-3B illustrate schematic outline diagrams of an IC portion according to some embodiments.

Fig. 4A-4B show schematic cross-sectional views of a warpage-controlling portion at various stages of fabrication, according to some embodiments.

Figure 5 illustrates a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage-controlling portion, in accordance with some embodiments.

Fig. 6 illustrates a schematic top view of the warp control portion of fig. 5 according to some embodiments.

Fig. 7A-7B illustrate schematic views of the assembly of a semiconductor structure according to some embodiments.

Figure 8 illustrates a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage-controlling portion, in accordance with some embodiments.

Fig. 9A-9B show schematic top views of the warp control portion of fig. 8 with different configurations according to some embodiments.

Fig. 10-11 show schematic cross-sectional views of variations of semiconductor structures according to some embodiments.

Figure 12 illustrates a schematic cross-sectional view of an application of a semiconductor structure according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below …", "below …", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another element or feature for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

Other features and processes may also be included. For example, test structures may be included to facilitate proof testing of three-dimensional (3D) packages or 3DIC devices. The test structure may include, for example, test pads (test pads) formed in a redistribution layer or on a substrate to enable testing of 3D packages or 3DIC devices, use of probes and/or probe cards (probe cards), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies (known good die) to improve yield and reduce cost.

Embodiments of the present disclosure are discussed in the context of semiconductor fabrication, and in particular, in the context of forming three-dimensional (3D) semiconductor structures. The 3D semiconductor structure includes an Integrated Circuit (IC) portion and a warpage control portion bonded to the IC portion. By configuring the warpage-controlling portion, warpage of the 3D semiconductor structure can be effectively reduced. Some variations of embodiments are discussed. It should be understood that the drawings are diagrammatic and not to scale in all figures. Throughout the various figures and illustrative embodiments, the same or similar reference numbers refer to the same or similar components.

Fig. 1A-1E show schematic cross-sectional views of an Integrated Circuit (IC) portion at various stages of fabrication, according to some embodiments. Referring to fig. 1A, a rewiring structure 110 is formed over a temporary carrier TC. The temporary carrier TC may comprise any suitable material that provides mechanical support to the structure formed thereon in subsequent processing. Thereafter, once the fabrication process is complete, the temporary carrier TC may be removed from the resulting structure. For example, the temporary carrier TC includes glass, ceramic, metal, silicon, or the like. In some embodiments, the rewiring structure 110 is formed over the temporary carrier TC, with an adhesive layer (not shown) sandwiched between the rewiring structure 110 and the temporary carrier TC. For example, the bonding layer is a light-to-heat conversion (LTHC) film that reduces or loses its tackiness when exposed to a radiation source, such as Ultraviolet (UV) light or laser light. Therefore, in order to remove the temporary carrier TC in a subsequent process, Ultraviolet (UV) light or external energy may be applied to the adhesive layer to easily remove the temporary carrier TC and the adhesive layer from the resulting structure. Other suitable adhesive layers such as Die Attach Film (DAF) may be used, and the removal process of the temporary carrier TC may include a mechanical peel-off process (mechanical peel-off process), a grinding process (grinding process), or an etching process (etching process) and may include an additional cleaning process (cleaning process). In other embodiments, the adhesive layer is omitted.

The rewiring structure 110 may include one or more conductive features 114 (e.g., conductive lines, vias, and pads) formed in one or more dielectric layers 112. The dielectric layer 112 of the redistribution structure 110 may comprise silicon oxide, silicon nitride, low-k dielectric (e.g., carbon-doped oxide), ultra-low-k dielectric (e.g., porous carbon-doped silicon dioxide), combinations thereof, or the like, and the dielectric layer 112 of the redistribution structure 110 may be formed by processes such as Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), Atomic Layer Deposition (ALD), or any other suitable deposition method. The conductive features 114 of the rewiring structure 110 may be formed of a metal such as aluminum, copper, tungsten, titanium, an alloy, or a combination thereof, and the conductive features 114 of the rewiring structure 110 may be formed by patterning and metallization techniques or other suitable deposition methods.

In some embodiments, the bottommost dielectric layer 112b is deposited over the temporary carrier TC, and then the bottommost layer 114b of the conductive feature 114 is deposited over the bottommost dielectric layer 112 b. Next, an intermediate dielectric layer 112m is formed on the bottommost dielectric layer 112b to cover the bottommost layer of the conductive feature 114, wherein portions of the bottommost layer 114b of the conductive feature 114 are exposed in an accessible manner through the opening of the intermediate dielectric layer 112 m. Then, an intermediate layer 114m of the conductive feature 114 is formed in the opening of the intermediate dielectric layer 112m and the intermediate layer 114m of the conductive feature 114 extends to the top surface of the intermediate dielectric layer 112 m. The steps of forming the interlayer dielectric layer 112m and the interlayer 114m of the conductive feature 114 may be repeated based on circuit design requirements.

Subsequently, a topmost dielectric layer 112t is formed on the intermediate dielectric layer 112m to cover the intermediate layer 114m of the conductive feature 114, and then a topmost layer 114t of the conductive feature 114 is formed in the opening of the topmost dielectric layer 112 t. The topmost layer 114t of the conductive feature 114 may be formed by a damascene process, such as single damascene or dual damascene, or other suitable process. In some embodiments, the topmost layer 114t of the conductive features 114 serves as a bonding connector and the topmost dielectric layer 112t serves as a bonding dielectric. For example, at least a portion of the topmost layer 114t of the conductive feature 114 is in physical and electrical contact with the middle layer 114m of the conductive feature 114. In some embodiments, the portion of the topmost layer 114t of the conductive feature 114 is a dummy connection and may be electrically floating. In some embodiments, the semiconductor die are bonded together in a hybrid bonding process using the topmost layer 114t of conductive features 114 and the topmost dielectric layer 112 t.

Referring to fig. 1B, a plurality of Integrated Circuit (IC) assemblies 120 are bonded to the rerouting structure 110. It should be noted that although two IC assemblies 120 are shown, the number of IC assemblies 120 is not limited in this disclosure. The types of IC components 120 may be the same or may be different. For example, the respective IC components 120 include logic circuitry, processing circuitry, storage circuitry, bias circuitry, reference circuitry, and/or the like. In some embodiments, the IC assembly 120 is referred to as a die or chip that is singulated from a device wafer.

In some embodiments, each IC device 120 includes a semiconductor substrate 122 and an interconnect structure 124 formed on the semiconductor substrate 122. The semiconductor substrate 122 may include circuitry (not shown) formed in a front-end-of-line (FEOL) process, and the interconnect structure 124 may be formed in a back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 124 includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate 122 and an inter-metal dielectric (IMD) layer formed over the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of low-K dielectric materials such as phosphosilicate Glass (PSG), borophosphosilicate Glass (BPSG), SiOxCy, Spin-On-Glass (Spin-On-Glass), Spin-On-Polymer (Spin-On-Polymer), silicon carbon materials, compounds thereof, composites thereof, combinations thereof, or the like. The ILD and IMD layers may include any suitable number of dielectric material layers without limitation thereto.

For example, the semiconductor substrate 122 includes a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, other support substrates (e.g., quartz, glass, etc.), combinations thereof, or the like, which may be doped or undoped. In some embodiments, the semiconductor substrate 122 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure, etc.), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (alinium arsenide, AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (galnas), indium gallium phosphide (galnas), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. In some embodiments, an alloy SiGe is formed over a silicon substrate. In other embodiments, the SiGe substrate is strained.

In some embodiments, a die attach film DAF is disposed on the back side 122b of the semiconductor substrate 122. For example, the die attach film DAF is provided before bonding the IC assembly 120 to the rerouting structure 110. Alternatively, the die attach film DAF is omitted. In some embodiments, a plurality of semiconductor devices 123, represented by a square, are formed on the front side 122a of the semiconductor substrate 122, and the interconnect structure 124 may interconnect the semiconductor devices 123. For example, the semiconductor device 123 may be or include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.) or other suitable electrical components. For example, the interconnect structure 124 includes a dielectric layer 1241 formed over the semiconductor substrate 122 and interconnect circuitry 1242 embedded in the dielectric layer 1241. Interconnect 1242 may include conductive lines, conductive pads, vias, etc. The material of interconnect circuit 1242 may comprise copper or copper alloy, but other conductive materials (e.g., aluminum, silver, gold, and combinations thereof) may also be used. In some embodiments, two or more layers of conductive lines of interconnect circuit 1242 are vertically interconnected through vias of interconnect circuit 1242. The interconnect circuit 1242 embedded in the dielectric layer 1241 may be electrically coupled to the semiconductor device 123 formed in the semiconductor substrate 122 and/or on the semiconductor substrate 122.

In some embodiments, the interconnect structure 124 includes a bond connector 1243 embedded in a dielectric layer 1241. For example, bond connections 1243 are formed using a damascene process (e.g., single damascene or dual damascene) or other suitable technique. In some embodiments, the portion of the dielectric layer 1241 in which the bond connector 1243 is embedded serves as a bonding dielectric. The bonding surface of the dielectric layer 1241 may be substantially flush with the bonding surface of the bonding connection 1243. For example, at least a portion of the bonding connection 1243 is in physical and electrical contact with the interconnect circuitry 1242. In some embodiments, portions of the bond connections 1243 are dummy connections and may be electrically floating. In some embodiments, the interconnect structure 124 of the IC device 120 is in physical and electrical contact with the redistribution structure 110. The bonding of the IC assembly 120 to the redistribution structure 110 is achieved, for example, by a bonding mechanism (joint bonding mechanism) that bonds the dielectric layer 1241 and the topmost dielectric layer 112t together, and furthermore, the respective bond connectors 1243 are aligned with and bonded together with the topmost layers 114t of the conductive features 114. In some embodiments, the bond connector 1243 is in direct contact with the topmost layer 114t of the conductive feature 114, wherein the contact area of the bond connector 1243 at the bonding interface IF of the topmost layer 114t of the conductive feature 114 and the bond connector 1243 is substantially equal to the surface area of the topmost layer 114t of the conductive feature 114. For example, the contact area of the bond connector 1243 is substantially aligned with the contact area of the topmost layer 114t of the conductive feature 114 at the bond interface 1F.

In some embodiments in which both the dielectric layer 1241 and the topmost dielectric layer 112t are oxide materials, an oxide-oxide bond is formed between the dielectric layer 1241 and the topmost dielectric layer 112 t. In embodiments where both bond connections 1243 and 114t are formed of copper, the copper in the bond connections 1243 and 114t form a copper-copper bond. Thus, the IC device 120 and the redistribution structure 110 are hybrid bonded (hybrid bonded) via the bonding connection 1243 disposed in the topmost portion of the interconnect structure 124 of the IC device 120 and the topmost layer 114t of the conductive features 114 of the redistribution structure 110. For example, at least portions of the connection portions of the bonding connections (1243 and 114t) provide vertical electrical connections between the IC component 120 and the rerouting structure 110. In some embodiments, the bonding may be performed on a die-to-wafer level. Alternatively, the bonding may be performed on a wafer level (wafer level) where the rewiring structure 110 and the IC component 120 are in wafer form and bonded together, and then the bonded structure is singulated into individual packages.

Referring to fig. 1C, an insulating layer 130 is formed on the rewiring structure 110 to cover the IC assembly 120 at least in a lateral direction. For example, the insulating layer 130 is formed on the topmost dielectric layer 112t of the redistribution structure 110 and the insulating layer 130 extends along the sidewalls 120s of the IC assembly 120. The insulating layer 130 may fill gaps between adjacent IC assemblies 120, and the adjacent IC assemblies 120 may be spatially separated from each other by the insulating layer 130. In some embodiments, insulating layer 130 may comprise silicon oxide, silicon nitride, and/or Tetraethoxysilane (TEOS). In some embodiments, the insulating layer 130 may be formed by CVD, PECVD, ALD, or similar processes. In some embodiments, the insulating layer 130 may be referred to as a "gap fill oxide". In some other embodiments, the insulating layer 130 includes a molding compound, a molding underfill, a resin (e.g., an epoxy), or the like. Other suitable insulating materials that may provide a degree of protection to the IC assembly 120 may be used.

In some embodiments, a Chemical Mechanical Polishing (CMP) step may be next employed to planarize the top surface 130a of the insulating layer 130. In some embodiments, the die attach film DAF disposed on the back side 122b of the semiconductor substrate 122 is covered at least laterally by the insulating layer 130. For example, the top surface 130a of the insulating layer 130 is substantially flush with the top surface Dt of the die attach film DAF. In some embodiments, a bonding layer (such as indicated by reference numeral 15 in fig. 4) is optionally formed over the IC assembly 120 and the insulating layer 130. In some embodiments, the bonding layer is in physical contact with the top surface 130a of the insulating layer 130 and the top surface Dt of the die attach film DAF. Alternatively, the die attach film DAF is omitted and the top surface 130a of the insulating layer 130 may be substantially flush with the back side 122b of the semiconductor substrate 122.

Referring to fig. 1D and 1E, the temporary carrier TC is removed to expose the bottommost dielectric layer 112b of the redistribution structure 110, and then electrical connections are formed on the redistribution structure 110 opposite the IC component 120. For example, portions of the bottommost dielectric layer 112b are removed using photolithography and etching techniques or other suitable removal processes to form the openings 112 o. The opening 112o of the bottommost dielectric layer 112b may contactably expose at least a portion of the bottommost layer 114b of the conductive feature 114. Next, a conductive material may be formed in the opening 112o of the bottommost dielectric layer 112b and patterned on the surface of the bottommost dielectric layer 112b, thereby forming a via 142 in the opening 112o of the bottommost dielectric layer 112b and a contact pad 144 on the surface of the bottommost dielectric layer 112 b. For example, contact pad 144 and via 142 connected to contact pad 144 are electrically connected to bottommost dielectric layer 112 b. In some embodiments, contact pads 144 include under-bump metal (UBM) patterns for further electrical connections.

In some embodiments, a passivation layer 146 is optionally formed on the bottommost dielectric layer 112b to provide a degree of protection for the underlying structures. The passivation layer 146 can be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations of these materials, or other suitable dielectric materials. The passivation layer 146 may be formed by a process such as CVD, although any suitable process may be utilized. For example, passivation layer 146 includes an opening that exposes at least a portion of contact pad 144 in an accessible manner.

Subsequently, a plurality of conductive terminals 150 are formed in the openings of the passivation layer 146, and the plurality of conductive terminals 150 may be in physical and electrical contact with the contact pads 144 exposed through the passivation layer 146. In some embodiments, the respective conductive terminals 150 are metal posts 152 with solder caps 154 formed thereon. In some embodiments, the conductive terminals 150 comprise controlled collapse chip connection (C4) bumps and/or may comprise materials such as solder, tin, or other suitable materials (e.g., silver, lead-free tin, copper, etc.). Other terminal structures may be used, such as Ball Grid Array (BGA) balls, micro-bumps, and/or the like. Thus, the IC portion 10A of the semiconductor structure is fabricated. The above examples are provided for illustrative purposes only, and other embodiments may utilize fewer or additional components in the IC portion.

Fig. 2A-2B illustrate schematic warp profiles of IC portions according to some embodiments, and fig. 3A-3B illustrate schematic profile views of IC portions according to some embodiments. For purposes of illustration, the warp profile of an IC portion may be schematic and exaggerated in all figures and details of the IC portion are not shown. Referring to fig. 2A to 2B and fig. 1E, as a result of the manufacturing process, the IC portion 10A shown in fig. 1E may be warped. For example, warpage may occur due to mismatch of Coefficient of Thermal Expansion (CTE) between materials, application of heat, temperature fluctuations, and/or the like. It is understood that warpage of the structure may adversely affect electrical performance of devices/circuits formed in IC portion 10A and warpage issues may affect subsequent processing and/or product reliability.

The bending (bowing) of IC portion 10A causes bonding surface BS (e.g., the surface opposite conductive terminal 150) to lie on the curved plane. In some embodiments, IC portion 10A has a concave warpage (i.e., smiling face contour) in which bonding surface BS of IC portion 10A curves upward as shown in fig. 2A. In some other embodiments, IC portion 10A has a convex warpage (i.e., a crying face contour) in which joining surface BS of IC portion 10A curves downward as shown in fig. 2B. In some embodiments, at high temperatures (e.g., a bonding temperature of about 250 degrees celsius), the height difference H1 in bonding surface BS of IC portion 10A may be about 80 μm or less than 80 μm. In the example described above, the warpage of the IC portion may be symmetrical. Due to the complex semiconductor processing, IC portion 10A may exhibit more complex warpage, rather than a simple convex warpage or a simple concave warpage.

Referring to fig. 3A-3B, in some embodiments, some areas of IC portion 10A exhibit convex warpage, some other areas of IC portion 10A exhibit concave warpage, wherein a portion of engagement surface BS may curve upward and another portion of engagement surface BS may curve downward. In some embodiments, IC portion 10A may have an asymmetric warpage. As shown in fig. 3A and 3B, respectively, various factors may cause warpage when IC portion 10A is at room temperature (e.g., about 25 degrees celsius) and when IC portion 10A is exposed to high temperatures (e.g., about 250 degrees celsius or greater than 250 degrees celsius).

In some embodiments, at room temperature, the warpage condition encountered is that the corner regions of IC portion 10A bend downward as shown by arrow A1, while the central region of IC portion 10A protrudes upward as shown by arrow A2. The warp direction may vary from the central region to the corner regions. In some embodiments, under high temperature conditions, IC portion 10A may have an irregular warp profile, as shown in fig. 7B. The warpage encountered may be such that the corner regions of IC portion 10A bend upward as indicated by arrow a2, while the central region of IC portion 10A is recessed downward as indicated by arrow a 1.

The curved face of the IC portion 10A makes it difficult to bond all of the conductive terminals 150 to respective contact pads of another package assembly (not shown) because some of the conductive terminals 150 will not contact respective contact pads of the package assembly. This can lead to cold welding (cold joint) between the conductive terminals 150 and the contact pads of the package assembly and the cold welding can lead to defective semiconductor structures and reduce the yield of semiconductor fabrication. In some embodiments, to reduce and/or eliminate warpage of IC portion 10A, a warpage control portion is bonded to IC portion 10A for warpage management. Details of which will be discussed below.

Fig. 4A-4B show schematic cross-sectional views of a warpage-controlling portion at various stages of fabrication, according to some embodiments. Referring to fig. 4A, a first dielectric layer 220 is formed over a substrate 210. For example, the substrate 210 is a silicon substrate. In some embodiments, substrate 210 may comprise another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multi-layered substrates or gradient substrates may be used. In some embodiments, substrate 210 is made of glass, ceramic, metal, or other suitable material having a degree of rigidity.

In some embodiments, the first dielectric layer 220 is an oxide layer. In some embodiments, the first dielectric layer 220 may be formed of a non-organic material such as silicon oxide, undoped silicate glass, silicon oxynitride, and the like. Other suitable dielectric materials may also be used (e.g., polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), combinations of these materials, or the like). For example, the interface between the substrate 210 and the first dielectric layer 220 may be silicon-to-silicon, silicon-to-oxide, oxide-to-oxide, or any other covalent bonding mechanism. The thickness 210t of the substrate 210 and the thickness 220t of the first dielectric layer 220 may be varied to control the degree of warpage of the warpage-controlling portion, as will be explained later in other embodiments.

Referring to fig. 4B, a second dielectric layer 222 and a metal pattern 224A embedded in the second dielectric layer 222 are formed on the first dielectric layer 220. In some embodiments, the dielectric material is formed by a suitable fabrication technique, such as spin-on coating, CVD, PECVD, lamination, or other suitable deposition process, and then portions of the dielectric material are removed using photolithography and/or etching, laser drilling, or other suitable removal process to form the second dielectric layer 222 with openings. The second dielectric layer 222 may be referred to as a patterned dielectric layer.

The first dielectric layer 220 and the second dielectric layer 222 may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations thereof, and the like. In other embodiments, the first dielectric layer 220 and/or the second dielectric layer 222 may be made of a polymer such as polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), a combination of these materials, or the like. In some embodiments, both the first dielectric layer 220 and the second dielectric layer 222 are oxide, and an etch stop layer (not shown) is sandwiched between the first dielectric layer 220 and the second dielectric layer 222.

Next, a metal pattern 224A may be formed in the opening of the second dielectric layer 222. For example, a seed layer is conformally formed on the second dielectric layer 222 and a conductive material (e.g., copper alloy, aluminum alloy, or a combination thereof) is filled in the openings using plating or other suitable process. A planarization process (e.g., CMP, mechanical polishing, etc.) may be performed such that the top surface of the second dielectric layer 222 is substantially flush with the top surface of the metal pattern 224A. In some embodiments, the additional second dielectric layer 222 and the additional metal pattern 224A may be repeatedly formed to control the degree of warpage of the warpage-controlling portion, as will be described later in connection with fig. 9A to 10. The metal pattern 224A may include sloped sidewalls or vertical sidewalls, depending on the process requirements. The specific configuration of the metal pattern 224A is based on the warpage characteristics of the IC portions to be bonded, and details regarding the configuration of the metal pattern 224A will be described later in other embodiments.

In some embodiments, a bonding layer (e.g., 15 as labeled in fig. 5) is optionally formed on the second dielectric layer 222 and the metal pattern 224A. For example, if a bonding layer is formed during fabrication of IC portion 10A, no bonding layer may be formed on second dielectric layer 222 and metal pattern 224A. If the bonding layer is not present in IC portion 10A, a bonding layer formation process is performed on second dielectric layer 222 and metal pattern 224A. In some embodiments, a bonding layer is formed in both IC portion 10A and warpage-controlling portion 20A. Thus, the warpage-controlling portion 20A of the semiconductor structure is fabricated.

Figure 5 illustrates a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage-controlling portion, in accordance with some embodiments. Referring to fig. 5, a semiconductor structure S1 including an IC portion 10A and a warpage-controlling portion 20A stacked on each other is provided. For example, the IC portion 10A and the warpage-controlling portion 20A are bonded together by, for example, a thermal bonding process, a gluing process, a pressure bonding process, a combination thereof, or other types of bonding processes. In some embodiments, the IC portion 10A and the warpage-controlling portion 20A are bonded together with the bonding layer 15 interposed therebetween. For example, the bonding layer 15 is an oxide-based dielectric layer for forming an oxide-to-oxide bond (oxide fusion bond) with another portion in a subsequent process. An anneal process may be performed after the bonding process to increase the bonding strength between the IC portion 10A and the warpage-controlling portion 20A. In other embodiments, the bonding layer 15 is an adhesive layer or a glue layer for physical attachment. For example, the bonding layer 15 includes a die attach film that may be made of epoxy resin (epoxy resin), phenol resin (phenol resin), acrylic rubber (acrylic rubber), silica filler (silica filler), a combination thereof, or the like.

In some embodiments, the bottom surface 15b of the bonding layer 15 is in physical contact with the second dielectric layer 222 and the metal pattern 224A of the warpage-controlling portion 20A. The metal pattern 224A of the warpage-controlling portion 20A may be electrically isolated by a dielectric material. For example, the sidewalls of the metal pattern 224A are covered by the second dielectric layer 222, the bottom surface of the metal pattern 224A is covered by the first dielectric layer 220, and the top surface of the metal pattern 224A is covered by the bonding layer 15. The metal pattern 224A of the warpage-controlling portion 20A may electrically float in the semiconductor structure S1. The metal pattern 224A may be referred to as a dummy pattern or a dummy conductive feature. In some embodiments, top surface 15a of bonding layer 15 is connected to IC portion 10A. For example, the insulating layer 130 and the die attach film DAF substantially flush with the insulating layer 130 are in physical contact with the top surface 15a of the bonding layer 15. In some embodiments in which the die attach film DAF is omitted, the top surface 15a of the bonding layer 15 is in physical contact with the insulating layer 130 and the semiconductor substrate 122 of the IC assembly 120.

In some embodiments, the bonding of IC portion 10A to warpage-controlling portion 20A may be performed at the wafer level, after which the resulting structure is singulated to form respective semiconductor structures S1. For example, singulation involves cutting through successive layers such as the passivation layer 146, the redistribution structure 110, the insulating layer 130, the bonding layer 15, the second dielectric layer 222, the first dielectric layer 220, and the substrate 210. Thus, after singulation, the sidewalls of these successive layers may be substantially flush with each other.

In some embodiments, one of the functions of the warpage-controlling portion 20A is to control the warpage of the IC portion 10A. As described above, IC portion 10A may experience warpage due to several factors (e.g., CTE mismatch, excessive thermal stress, temperature fluctuations, and/or the like). As is known, warpage of IC portions can adversely affect electrical performance. In addition, low planarity (or severe warpage) of the IC portion can stress the packaged IC components and interfere with the singulation process. By attaching the warpage-controlling portion 20A to the IC portion 10A, the problem of warpage of the IC portion 10A can be solved. For example, warpage control portion 20A bonded to IC portion 10A has an inherent stress (intrinsic stress) that can warp IC portion 10A in a direction opposite to the existing warpage direction, thus compensating for the existing warpage. In some embodiments, warped IC portion 10A is planarized by bonding to warp control portion 20A prior to being sawed into respective semiconductor structures S1 to enable proper sawing and good package planarity (planarity).

Fig. 6 illustrates a schematic top view of the warp control portion of fig. 5 according to some embodiments. Referring to fig. 5 and 6, the metal pattern 224A may include a plurality of first features 2241 formed in the openings of the second dielectric layer 222. For example, the first features 2241 are arranged in an array. In some embodiments, the first features 2241 are arranged in a linear array. Alternatively, the first features 2241 are arranged, for example, in a non-linear manner, a curvilinear manner, a geometrically sequential manner, or other uniformly distributed manner. In other embodiments, the first features 2241 are arranged, for example, in a uniformly distributed manner, in a random manner, or in another irregularly distributed manner.

Although the first features 2241 shown in the top view are all rectangular in shape, it should be understood that in other embodiments, the first features 2241 may have any shape, such as circular, oval, triangular, square, cross, polygonal, combinations of these shapes, and the like. In some embodiments, the first features 2241 include dummy metal vias, dummy metal lines, and/or dummy metal pads. The respective first features 2241 may be spatially separated from each other. For example, the first features 2241 are not electrically connected and may be isolated from each other. In some embodiments, metal lines of a particular linewidth W have a certain amount of linespacing S therebetween. The first features 2241 may be designed with distributed lines and line spacing to meet design rules and provide a desired warping effect and degree. In some embodiments, the line width W of the respective first feature 2241 is about 15 μm or may be less than 15 μm. For example, the line width W is in the range of about 0.3 μm to about 15 μm. In some embodiments, the line spacing S of adjacent first features 2241 is at least 0.3 μm or greater than 0.3 μm.

In some embodiments, the first features 2241 are formed according to design rules, where the spacing S between metal lines is varied to achieve a desired global pattern density (global pattern density). For example, the global pattern density ranges from about 10% to about 80%. In some embodiments, the first features 2241 are laid out in a process window where the local pattern density is in the range of about 10% to about 90%. In some embodiments, the density difference between process windows is substantially equal to or less than 40%, wherein the respective process windows may have a length and width of 250 μm by 250 μm. It should be understood that the dimensions described herein are examples only, and that dimensions set forth herein may be changed if different formation techniques are used or if simulation results show that different dimensions are preferred.

The formation of the first features 2241 may increase or decrease stress by redistributing local stress to particular regions of the warp control portion 20A. For example, first feature 2241 is located in an area selected to more effectively control warpage of IC portion 10A. In some embodiments, the warp control portion 20A includes a first region R1 and a second region R2 surrounding the first region R1. First features 2241 may be distributed within first region R1, and first region R1 may correspond to an area of IC assembly 120 in IC portion 10A. For example, the forward projection area of each IC component 120 may substantially overlap with the corresponding first region R1. In other embodiments, the forward projection area of the IC component 120 partially overlaps the first region R1. Alternatively, the front projection area of the IC package 120 is completely offset from the first region R1. The distribution area of first region R1 may be determined based on the warpage profile to counteract or compensate for an unintended warpage of IC portion 10A. Details regarding the warpage control will be set forth later in other embodiments.

In some embodiments, metal pattern 224A includes at least one second feature 2242 disposed within second region R2. For example, the second region R2 is a boundary region of the warp control portion 20A in the top view. For example, the first features 2241 are confined to a first region R1 corresponding to the IC component 120, and the second features 2242 in a second region R2 are located at the periphery of the warp control portion 20A. The first and second features 2241 and 2242 may not have electrical functionality in the semiconductor structure S1 and may not be electrically connected to an overlying IC portion 10A. In some embodiments, the second feature 2242 is formed from the same conductive material as the first feature 2241, and the second feature 2242 may be formed substantially simultaneously with the formation of the first feature 2241. In some embodiments, a plurality of second features 2242 are disposed in a diagonal arrangement in the second region R2. Other arrangements may be used to form the second feature 2242.

In some embodiments, second feature 2242 may serve as an alignment marker, such that second feature 2242 may be referred to as an alignment feature. The second features 2242 may be formed into a blank area on the warp control section 20A inside the dicing lane (not shown) so that the second features 2242 remain in the warp control section 20A after singulation. In some embodiments, the second features 2242 may be formed in an edge region that overlaps a cut lane (not shown) such that the second features 2242 are cut through and partially remain in the warp control portion 20A after singulation. In other embodiments, the second feature 2242 may be formed in an area outside of the cut lane (not shown) such that the second feature 2242 is removed after singulation. The second feature 2242 used as an alignment mark may be a geometric shape (e.g., triangular, rectangular, square, cross, circular, oval, polygonal) or any suitable shape. The second feature 2242 shown is not intended to be limiting, as the second feature 2242 may have any number, shape, or size. It should be understood that the metal pattern 224A shown in fig. 5 to 6 is only an example and should not limit the scope of the present disclosure.

Fig. 7A-7B illustrate schematic views of the assembly of a semiconductor structure according to some embodiments. It should be noted that the degree of warpage shown in fig. 7A to 7B is exaggerated and details of the IC portion are omitted for illustrative purposes. Referring to fig. 7A, a semiconductor structure S1 includes an IC portion 10A and a warpage-controlling portion 20A. In some embodiments, IC portion 10A exhibits a concave warpage (i.e., a smiling face profile) and warpage control portion 20A can be fabricated with a predetermined convex warpage (i.e., a crying face profile) to counteract internal stresses that cause the concave warpage of IC portion 10A, thereby reducing manufacturing defects.

In some embodiments, the warpage characteristics of IC portion 10A are determined prior to bonding. For example, the height difference H1 (shown in fig. 2A to 2B) in the bonding surface BS of the IC part 10A is estimated by simulation or experiment. In some embodiments, warp simulation is performed based on the design of IC portion 10A to generate a contour map (contour map) of a warp contour (warp profile). By analyzing the warpage of the IC portion 10A, the configuration of the warpage-controlling portion 20A can be estimated. For example, the pattern density, line width, and line spacing of the metal pattern of the warpage-controlling portion 20A may depend on the degree of warpage to be compensated. In some embodiments, the warpage of the warpage-controlling portion 20A may be achieved by forming a dielectric material (e.g., the first dielectric layer 220 and/or the second dielectric layer 222 shown in fig. 3B) on the substrate 210, wherein the dielectric material has an inherent stress that provides a desired warpage effect and degree. In some embodiments, the thickness of substrate 210 may be determined based on the warpage characteristics of IC portion 10A to allow fine-tuning of the warpage control of IC portion 10A.

Referring to fig. 7B, the semiconductor structure S1 includes an IC portion 10A and a warpage-controlling portion 20A. In some embodiments, IC portion 10A exhibits a convex warpage (i.e., a crying face profile) and warpage control portion 20A may have a concave warpage (i.e., a smiling face profile), such that the bonding of IC portion 10A and warpage control portion 20A may achieve the flatness requirements of the semiconductor structure. As described above, the configuration of the warp control portion 20A may vary based on the warp profile. In some embodiments, the simulated warpage characteristics of IC portion 10A are used to determine an expected degree of warpage for engaging warpage control portion 20A of IC portion 10A.

For example, the metal pattern filling the opening of the second dielectric layer may have the effect of inducing concave warpage. The greater pattern density of the metal pattern of the warp control portion 20A may result in a greater warp compensation effect. The pattern density may be considered as the density of the first features occupying the area of the warp control portion in the top view. The pattern density may be a ratio of an area occupied by the first features in the first region with respect to a total area of the warpage-controlling portion. The dielectric material formed on the substrate 210, such as the first dielectric layer 220 and/or the second dielectric layer 222 shown in fig. 3B, may be selected to cause a concave or convex warpage of the warpage-controlling portion 20A. In some embodiments, the dielectric material of the warpage-controlling portion 20A is selected to mitigate the bending force provided by the metal pattern 224A of the warpage-controlling portion 20A. In some embodiments, the warpage-controlling portion 20A having thicker dielectric materials is susceptible to warpage from stresses applied by these dielectric materials. In some embodiments, the thickness of the substrate 210 is varied to control the warpage of the warpage-controlling portion 20A. For example, the concavity (concavity) of the warp control portion 20A is reduced using the thicker substrate 210.

In the above example, the warpage of the IC portion 10A may be symmetrical, and the warpage-controlling portion 20A may also be symmetrical. In some embodiments, IC portion 10A exhibits a more complex warpage profile due to complex semiconductor processing. In such an embodiment, the warped IC portion 10A may be simulated and analyzed. The warpage compensation can be customized based on simulation results (e.g., the three-dimensional profile diagrams shown in fig. 3A-3B) to form a warpage control portion 20A having a particular configuration corresponding to the warped IC portion. Therefore, the warpage of the IC portion 10A is compensated by the internal stress planned in advance by the warpage-controlling portion 20A, thereby preventing the warpage of the semiconductor structure S1 as a whole.

Fig. 8 shows a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage-controlling portion according to some embodiments, and fig. 9A-9B show schematic top views of the warpage-controlling portion in fig. 8 having different configurations according to some embodiments. Like reference numerals are used to refer to like elements throughout the various figures and exemplary embodiments of the present disclosure.

Referring to fig. 8, semiconductor structure S2 includes IC portion 10B and warpage-controlling portion 20B attached to IC portion 10B. Semiconductor structure S2 may be similar to semiconductor structure S1 illustrated in fig. 5. Differences between semiconductor structure S1 and semiconductor structure S2 include the single IC assembly 120 being disposed in semiconductor structure S2 and the topmost layer 114t ' of the conductive features 114 ' of the re-wiring structure 110 ' being modified accordingly. Also, the number of IC components 120 is not limited in this disclosure and the examples are for illustrative purposes only.

The warpage-controlling portion 20B may be similar to the warpage-controlling portion 20A of the semiconductor structure S1 set forth in fig. 5, except that the configuration of the metal pattern 224B is modified. For example, referring to fig. 8 and 9A, the warp control portion 20B includes a first region R1, third and fourth regions R3 and R4 at opposite sides of the first region R1, and a second region R2 surrounding the first region R1, the third region R3, and the fourth region R4. The first features 2241 may be distributed within a first region R1 corresponding to a region of the IC assembly 120 in the IC portion 10B.

The metal pattern 224B may further include a plurality of third features 2243 distributed within the third region R3 and a plurality of fourth features 2244 distributed within the fourth region R4. The third feature 2243 and the fourth feature 2244 may be generated by a rule-based process. In some embodiments, the pattern density of the first features 2241 in the first region R1 is less dense than the pattern density of the third features 2243 in the third region R3. In some embodiments, the pattern density of the first features 2241 in the first region R1 is also less dense than the pattern density of the fourth features 2244 in the fourth region R4. In some embodiments, the pattern density of the third features 2243 is substantially the same as the pattern density of the fourth features 2244. Alternatively, the pattern density of the third features 2243 in the third regions R3 may be denser or sparser than the pattern density of the fourth features 2244 in the fourth regions R4.

Referring to fig. 9B with respect to fig. 8, another configuration of the warp control portion 20C is provided. For example, the pattern density of the first features 2241 in the first region R1 is denser than the pattern density of the third features 2243 in the third region R3. In some embodiments, the pattern density of the first features 2241 in the first region R1 is also denser than the pattern density of the fourth features 2244 in the fourth region R4. In some embodiments, the pattern density of the third features 2243 is substantially the same as the pattern density of the fourth features 2244. Alternatively, the pattern density of the third features 2243 in the third regions R3 may be denser or sparser than the pattern density of the fourth features 2244 in the fourth regions R4. In other embodiments, the pattern density of the first features 2241 in the first region R1 is between the pattern density of the third features 2243 and the pattern density of the fourth features 2244. For example, the pattern density of the first features 2241 in the first region R1 is denser than the pattern density of the third features 2243 in the third region R3, but sparser than the pattern density of the fourth features 2244 in the fourth region R4. Alternatively, the pattern density of the first features 2241 in the first region R1 may be less dense than the pattern density of the third features 2243 in the third region R3, but denser than the pattern density of the fourth features 2244 in the fourth region R4.

The second features 2242 may be distributed within the second region R2, and in a top view, the second region R2 may be a boundary region of the warp control portion 20B. In some embodiments, the second feature 2242' serves as an alignment mark and may be disposed beside the fourth region R4 and the third region R3. For example, in top view, the second feature 2242' is disposed at the middle of the perimeter of the warp control portion 20C. Although the second feature 2242' is shown as a cross-shaped indicia, it should be understood that the second feature in other embodiments may have any shape and should not limit the scope of the present disclosure. It is understood that the characteristics (e.g., density, size, shape, arrangement, etc.) of the metal patterns (224B, 224C) shown herein are merely examples and may be varied if other types of IC portions are to be joined.

Fig. 10 and 11 show schematic cross-sectional views of variations of semiconductor structures according to some embodiments. Like reference numerals are used to refer to like elements throughout the various figures and exemplary embodiments of the present disclosure. Referring to fig. 10, semiconductor structure S3 includes IC portion 10A and warpage-controlling portion 20D attached to IC portion 10A. The semiconductor structure S3 may be similar to the semiconductor structure S1 illustrated in fig. 5, except that the warpage-controlling portion 20D of the semiconductor structure S3 includes a plurality of metal patterns stacked on one another. For example, after forming metal pattern 224A in second dielectric layer 222 as described in fig. 4B, additional dielectric layer 226 and additional metal pattern 228 are subsequently formed over dielectric layer 222 and metal pattern 224A. The formation process of the additional dielectric layer 226 and the additional metal pattern 228 may be similar to the formation process of the second dielectric layer 222 and the metal pattern 224A, and therefore, for brevity, the description is not repeated. For example, as the number of dielectric layers and metal patterns formed over substrate 210 increases, the bending force provided by these layers results in significant warpage of warpage-controlling portion 20D. The number of additional dielectric layers 226 and additional metal patterns 228 depends on the design of the warpage control portion 20D and the IC portion 10A to be bonded.

In some embodiments, the pattern distribution of the additional metal pattern 228 may be different from the pattern distribution of the underlying metal pattern 224A. In some other embodiments, the additional metal pattern 228 has a pattern distribution similar to or the same as the pattern distribution of the underlying metal pattern 224A. Any combination of pattern distribution types of the various metal patterns may be used. The additional metal pattern 228 may or may not be in physical contact with the underlying metal pattern 224A. In some embodiments, the additional metal pattern 228 and the underlying metal pattern 224A are staggered from each other. For example, the metal pattern 224A and the additional metal pattern 228 are electrically isolated from each other. The thickness of the additional dielectric layer 226 may be adjusted to apply the appropriate counteracting stress. In some embodiments, metal pattern 224A is replaced with metal pattern 224B or 224C as described in connection with fig. 8, 9A, and 9B. In some embodiments, IC portion 10A is replaced with IC portion 10B, as shown in connection with fig. 8. It should be understood that the IC portion may be replaced with other types of devices, such as system on integrated circuit (SoIC) devices, system on a chip (SoC), package structures, or the like.

Referring to fig. 11, semiconductor structure S4 includes IC portion 10A and warpage-controlling portion 20E attached to IC portion 10A. Semiconductor structure S4 may be similar to semiconductor structure S3 illustrated in fig. 5, except for the configuration of warp control portion 20E. For example, the warp control portion 20E includes a first level T1 and a second level T2 joined to the first level T1. The configuration of the first level T1 may be similar to the configuration of the warp control portion 20A set forth in fig. 4B. Second level T2 may be joined to first level T1 opposite IC portion 10A. The bonding of the first level T1 and the second level T2 may include adhesive bonding, fusion bonding through oxide-to-oxide bonding, bonding through an adhesive medium such as benzocyclobutene (BCB), and the like. In some embodiments, the second level T2 is bonded to the substrate 210 of the first level T1 by a bonding layer 16. The material of bonding layer 16 may be similar to the material of bonding layer 15 and will not be described again for brevity.

The second level T2 may include a substrate 310, a first dielectric layer 320 formed on the substrate 310, a second dielectric layer 322 formed on the first dielectric layer 320, a first metal pattern 324 embedded in the second dielectric layer 322, a third dielectric layer 326 formed on the second dielectric layer 322, and a second metal pattern 328 embedded in the third dielectric layer 326. Substrate 310 may be similar to substrate 210. In some embodiments, the substrate 210 of the first tier T1 is composed of a different material than the substrate 310 of the second tier T2. In some embodiments, substrate 210 and substrate 310 may have different thicknesses. The substrate 210 may be thicker or thinner than the substrate 310, the thickness of which may depend on the warpage to be compensated for. The stack of dielectric layers (e.g., 320, 322, and 326) and the bonding layer 16 may be sandwiched between the substrate 210 of the first level T1 and the substrate 310 of the second level T2. The materials and thicknesses of the stack of dielectric layers (e.g., 320, 322, and 326) and bonding layer 16 may vary based on warpage design requirements. The first metal pattern 324 may be similar to the metal pattern (224A, 224B, or 224C). The second metal pattern 328 may be similar to the additional metal pattern 228. In some embodiments, the configuration of the second level T2 may be similar to the configuration of the warp control portion 20D set forth in fig. 10. Other configurations may be used as long as the warp control portion 20E applies an appropriate counteracting stress.

Figure 12 illustrates a schematic cross-sectional view of an application of a semiconductor structure according to some embodiments. Referring to fig. 12, a component assembly SC is provided that includes a first component C1 and a second component C2 disposed over the first component C1. The first component C1 may be or include an interposer (interposer), a package substrate, a Printed Circuit Board (PCB), a printed wiring board (printed wiring board), and/or other carrier capable of carrying an integrated circuit. The second component C2 may be or include a semiconductor structure S5.

For example, semiconductor structure S5 includes IC portion 10C and warp control portion 20A attached to IC portion 10C. In some embodiments, IC portion 10C includes a carrier die L1 and a die stack L2 stacked on carrier die L1 and electrically connected to carrier die L1. In some embodiments, carrier die L1 may be configured to perform read, program, erase, and/or other operations, and die stack L2 may be a memory stack including memory dies stacked on top of each other and programmed by carrier die L1. For example, the carrier die may be or may include a system on chip (SoC), a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other type of IC component. Die stack L2 may include a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Synchronous Dynamic Random Access Memory (SDRAM) die, a NAND flash memory die (NAND flash die), or other types of IC components.

In some embodiments, the carrier die L1 includes a semiconductor substrate 410 having a semiconductor device formed thereon, a redistribution structure 420 disposed over a front side 410a of the semiconductor substrate 410 to electrically connect to the semiconductor device, a plurality of Through Substrate Vias (TSVs) 430 penetrating through the semiconductor substrate 410 to electrically connect to the redistribution structure 420, a bonding dielectric layer 442 disposed on a back side 410b of the semiconductor substrate 410, and a plurality of bonding pads 440 embedded in the bonding dielectric layer 442 and electrically connected to the TSVs 430. The conductive terminals 150 are formed on the re-wiring structure 420 opposite to the semiconductor substrate 410.

The die stack L2 includes multiple levels (e.g., M1-M4) stacked on top of each other, where each level may include IC components (e.g., 520, 620) laterally covered by an insulating layer 130. The IC components in the overlying level are in physical and electrical contact with the IC components in the underlying level. The IC assembly 620 at the topmost level M4 is attached to the warpage-controlling portion 20A by the bonding layer 15. The IC assembly 620 may be similar to the IC assembly 120. The bottom-most IC component 520 may be similar to the IC component 620 at the top-most level M4, except that the IC component 520 includes through-substrate vias (TSVs) 522. For example, a respective TSV 522 of the IC component 520 penetrates through the semiconductor substrate 122 to make physical and electrical contact with the interconnect structure 124. In some embodiments, the bond dielectric layer 442 is sandwiched between adjacent levels (e.g., M1 and M2, M2 and M3, or M3 and M4). A plurality of bond pads 440 may be embedded in each of the bond dielectric layers 442 to physically and electrically connect to the TSV 522 of the IC component 520 at an underlying level and also to the bond connection 1243 of the interconnect structure 124 at an overlying level. It should be understood that a four-tier stack (four-tier stack) is provided for illustrative purposes, and other embodiments may utilize fewer or additional tiers in the die stack.

It should be noted that IC portion 10C and warpage control portion 20A may be replaced with any of the IC portions and warpage control portions discussed above. The second module C2 mounted on the first module C1 may be similar to the semiconductor structure described above (e.g., S1, S2, S3, S4). For example, one or more of the semiconductor structures described above may be electrically coupled to first component C1 through a plurality of terminals CT. The terminal CT may be a conductive terminal 150. In the case of processing, the temperature rises, causing the terminal CT to deform and bond to a contact pad (not shown) of the first component C1. By using the warpage control portion, the bonded package components (C1 and C2) may not be warped. In some embodiments, a bottom fill layer UF is formed between the gaps of the first and second components C1 and C2 to cover the terminals CT at least laterally. Alternatively, the underfill UF is omitted.

In some other embodiments, the second module C2 mounted on the first module C1 may be an integrated fan-out (InFO) package including at least one semiconductor structure (e.g., S1 through S5) packaged therein. For example, the second component C2 includes a plurality of semiconductor structures (e.g., any combination of semiconductor structures S1-S5) arranged side-by-side and surrounded by a package encapsulant (not shown; e.g., molding compound). Other packaging techniques may be used to form the component assembly SC and are not limited in this disclosure. For example, the component assembly SC is formed using a Wafer Level Packaging (WLP), a chip-on-wafer-on-substrate (CoWoS) process, a chip-on-chip-on-substrate (CoCoS) process, or the like. The component assembly SC may be part of an electronic system such as a computer (e.g., a high performance computer), a computing device used in conjunction with an artificial intelligence system, a wireless communication device, a computer-related peripheral device, an entertainment device, and the like. It should be noted that other electronic applications are also possible.

According to some embodiments, a semiconductor structure comprises: an Integrated Circuit (IC) assembly, an insulating layer laterally encapsulating sidewalls of the IC assembly, a redistribution structure disposed on the insulating layer and the IC assembly, and a warpage control portion coupled to a backside of the IC assembly opposite the redistribution structure. The rerouting structure is electrically connected to the IC assembly. The warpage-controlling portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.

In some embodiments, the semiconductor structure further comprises a bonding layer coupling the warpage-controlling portion to the integrated circuit component and the insulating layer. In some embodiments, the warpage-controlling portion further comprises an oxide layer interposed between the substrate and the patterned dielectric layer. In some embodiments, the metal pattern of the warpage-controlling portion is located within a distribution area beneath an area of the integrated circuit component, the metal pattern of the warpage-controlling portion including alignment features disposed in a border area surrounding the distribution area. In some embodiments, a bonding connector of the integrated circuit component is bonded to a bonding connector of the rewiring structure, a bonding dielectric layer of the integrated circuit component laterally overlying the bonding connector of the integrated circuit component being bonded to a bonding dielectric layer of the rewiring structure laterally overlying the bonding connector of the rewiring structure. In some embodiments, the metal pattern of the warpage-controlling portion includes a plurality of first features distributed in a first region underlying a region of the integrated circuit component and a plurality of second features distributed in a second region underlying a region of the insulating layer, wherein a pattern distribution density of the plurality of first features is sparser than the plurality of second features. In some embodiments, the metal pattern of the warpage-controlling portion includes a plurality of first features distributed in a first region underlying a region of the integrated circuit component and a plurality of second features distributed in a second region underlying a region of the insulating layer, wherein a pattern distribution density of the plurality of first features is denser than the plurality of second features. In some embodiments, the warpage-controlling portion further includes an additional substrate, an additional patterned dielectric layer disposed between the substrate and the additional substrate, an additional metal pattern embedded in the additional patterned dielectric layer, and a bonding layer coupling the additional patterned dielectric layer and the additional metal pattern to the substrate.

According to some alternative embodiments, a semiconductor structure includes an Integrated Circuit (IC) portion and a warpage-controlling portion attached to the IC portion. The IC part includes an IC package embedded in the insulating layer, and a rewiring structure provided on the IC package and the insulating layer, wherein a bonding connector of the IC package is bonded to a bonding connector of the rewiring structure, and a contact area of the bonding connector of the IC package at a bonding interface of the IC package and the rewiring structure is substantially equal to a surface area of the bonding connector of the rewiring structure. The warpage-controlling portion includes a first substrate and a first metal pattern embedded in a first dielectric layer. The first metal pattern is interposed between the first substrate and the IC portion.

In some embodiments, the semiconductor structure further comprises a bonding layer interposed between the warpage-controlling portion and the integrated circuit portion. In some embodiments, the first metal pattern is substantially flush with the first dielectric layer. In some embodiments, the first metal pattern is electrically floating in the warpage-controlling portion. In some embodiments, the first metal pattern of the warpage-controlling portion is located within a distribution region that overlaps a forward projection area of the integrated circuit component, the first metal pattern of the warpage-controlling portion being electrically isolated. In some embodiments, the first metal pattern of the warpage-controlling portion includes first features and second features, wherein the first features are distributed within a distribution area overlapping a front projection area of the integrated circuit component, and the second features are distributed outside the distribution area and have a pattern distribution density denser than that of the first features. In some embodiments, the first metal pattern of the warpage-controlling portion includes first features and second features, wherein the first features are distributed within a distribution area overlapping with a forward projection area of the integrated circuit component, and the second features are distributed outside the distribution area and have a pattern distribution density that is sparse than a pattern distribution density of the first features. In some embodiments, the warpage-controlling portion further includes a second substrate, a second metal pattern embedded in a second dielectric layer and sandwiched between the first substrate and the second substrate, and a bonding layer coupling the second dielectric layer and the second metal pattern to the first substrate.

According to some alternative embodiments, a method of fabricating a semiconductor structure includes at least the following steps. Forming an Integrated Circuit (IC) portion, and forming the IC portion includes analyzing a warpage characteristic of the IC portion. Forming the warpage control portion based on warpage characteristics of the IC portion, the forming the IC portion including forming a metal pattern in an opening of the patterned dielectric layer over the substrate. The IC portion is flattened by bonding the IC portion to the warpage-controlling portion.

In some embodiments, forming the metal pattern includes forming a plurality of first features in a first region and forming a plurality of second features in a second region other than the first region, wherein the first region is located under a die of the integrated circuit portion, a pattern density of the plurality of first features in the first region being less dense than a pattern density of the plurality of second features in the second region. In some embodiments, forming the metal pattern includes forming a plurality of first features in a first region and forming a plurality of second features in a second region other than the first region, wherein the first region underlies a die of the integrated circuit portion, a pattern density of the plurality of first features in the first region being denser than a pattern density of the plurality of second features in the second region. In some embodiments, forming the integrated circuit portion includes bonding a die to a redistribution structure, wherein each of the bonding connectors of the die is bonded to one of the bonding connectors of the redistribution structure and forming an insulating layer over the redistribution structure to cover the die.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[ description of symbols ]

10A, 10B, 10C: IC part

15. 16: bonding layer

15a, 130a, Dt: top surface

15 b: bottom surface

20A, 20B, 20C, 20D, 20E: warp control section

110. 420: heavy wiring structure

112: dielectric layer

112 b: bottom dielectric layer

112m, and (2): intermediate dielectric layer

112 o: opening of the container

112 t: topmost dielectric layer

114: conductive features

114 b: the bottom layer

114 m: intermediate layer

114 t: top most layer/joint connection

114 t': the topmost layer

120. 620: integrated Circuit (IC) assembly

120 s: side wall

122. 410: semiconductor substrate

122a, 410 a: front side

122b, 410 b: back side

123: semiconductor device with a plurality of transistors

124: internal connection structure

130: insulating layer

142: perforation

144: contact pad

146: passivation layer

150: conductive terminal

152: metal column

154: solder coping

210: substrate

210 t: thickness of

220: a first dielectric layer

220 t: thickness of

222. 322: dielectric layer/second dielectric layer

224A, 224B, 224C: metal pattern

226: additional dielectric layer

228: additional metal pattern

310: substrate

320: dielectric layer/first dielectric layer

324: a first metal pattern

326: dielectric layer/third dielectric layer

328: second metal pattern

430. 522: substrate Via (TSV)

440: bonding pad

442: bonding dielectric layers

520: IC module

1241: dielectric layer

1242: interconnection circuit

1243: joint connector

2241: first characteristic

2242. 2242': second characteristic

2243: third characteristic

2244: fourth characteristic

A1, A2: arrow head

BS: joining surfaces

C1: first assembly

C2: second assembly

CT: terminal with a terminal body

DAF: tube core laminating film

H1: height difference

IF: bonding interface

L1: carrier die

L2: die stacking

M1, M2, M3, M4: hierarchy level

R1: first region

R2: second region

R3: third zone

R4: fourth zone

S: line spacing

S1, S2, S3, S4, S5: semiconductor structure

SC: component assembly

T1: first level

T2: second level

TC: temporary carrier

UF: underfill layer

W: line width