阅读说明：本技术 一种芯片封装体及其制程方法和电子装置 (Chip package, manufacturing method thereof and electronic device ) 是由 霍佳仁 宋关强 江京 刘建辉 于 2020-09-25 设计创作，主要内容包括：本申请公开了一种芯片封装体及其制程方法和电子装置,其中,该芯片封装体包括：图案化的金属基材板；芯片,设置在金属基材板上；第一绝缘层,覆盖在芯片和金属基材板上,其中,第一绝缘层中设置有通孔以裸露出部分的金属基材板和芯片；图案化的第一导电层,设置在第一绝缘层上和通孔内,以使芯片藉由第一导电层而连接至金属基材板。通过上述方式,本申请中的芯片封装体能够实现芯片的双面散热,且结构较为简单,电气路径和散热路径短,具有优异的低阻特性和散热效果,能够实现芯片封装体的小型化和轻薄化。(The application discloses a chip packaging body, a manufacturing method thereof and an electronic device, wherein the chip packaging body comprises: a patterned metal substrate sheet; a chip disposed on the metal base plate; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.)

1. A chip package, comprising:

a patterned metal substrate sheet;

a chip disposed on the metal base plate;

a first insulating layer covering the chip and the metal base plate, wherein a through hole is provided in the first insulating layer to expose a portion of the metal base plate and the chip;

a patterned first conductive layer disposed on the first insulating layer and within the via such that the chip is connected to the metal substrate board by the first conductive layer.

2. The chip package of claim 1,

a patterned second conductive layer is further arranged between the first insulating layer and the overlapped part of the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.

3. The chip package of claim 1,

the metal substrate board with still be provided with the third conducting layer between the part that the chip overlaps, the chip passes through the third conducting layer with the laminating of metal substrate board.

4. The chip package of claim 1,

the chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface, far away from the first insulating layer, of the metal substrate board.

5. The chip package of claim 1,

the chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.

6. The chip package of claim 1,

the surface area of one side of the through hole facing the metal base material plate is smaller than the surface area of one side of the through hole far away from the metal base material plate.

7. A manufacturing method of a chip package is characterized by comprising the following steps:

arranging a chip on the metal substrate plate;

forming a first insulating layer on the metal base plate on which the chip is disposed to cover the chip and the metal base plate;

patterning the first insulating layer to form a patterned first insulating layer, wherein a through hole is provided in the patterned first insulating layer to expose a portion of the metal base material plate and the chip;

forming a first conductive layer on the patterned first insulating layer, wherein the first conductive layer is filled in the through hole;

patterning the first conductive layer to form a patterned first conductive layer;

patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

8. The process of claim 7, wherein after the step of forming a first insulating layer on the metal substrate plate provided with the chip to cover the chip and the metal substrate plate, the step of patterning the first insulating layer to form a patterned first insulating layer, wherein the step of providing a through hole in the patterned first insulating layer to expose a portion of the metal substrate plate and the chip further comprises:

forming a second conductive layer on the first insulating layer;

the patterning the first insulating layer to form a patterned first insulating layer, wherein the patterning the first insulating layer has a through hole provided therein to expose a portion of the metal substrate board and the chip, and the patterning includes:

patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein through holes are provided in the patterned first insulating layer and the patterned second conductive layer to expose portions of the metal base board and the chip;

the step of forming a first conductive layer on the patterned first insulating layer and filling the through hole with the first conductive layer includes:

forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, wherein the first conductive layer is filled in the through hole;

the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer comprises:

patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

9. The process of claim 7, wherein the step of disposing the chip on the metal substrate comprises:

forming a third conductive layer on the metal base material plate;

and arranging a chip on the third conductive layer.

10. The process of claim 7, wherein the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises, after the step of patterning the metal substrate plate:

forming a conductive metal layer on a surface of the patterned metal substrate board remote from the first insulating layer.

11. The process of claim 7, wherein the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises, after the step of patterning the metal substrate plate:

and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

12. An electronic device comprising the chip package according to any one of claims 1-6.

Technical Field

The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip package, a method for manufacturing the chip package, and an electronic device.

Background

In recent years, with the application of Mosfet (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as Mosfet) and IGBT (Insulated Gate Bipolar Transistor) power modules to almost all power industry products, corresponding power devices are steadily developing in the direction of high performance, high speed, small volume and multi-chip connection packaging.

However, conventional wire bonding and double-sided copper interconnect processes and process methods have been increasingly difficult to meet the requirements of high performance, fast speed, small volume, multi-chip connection packaging and modularization of power devices. The power semiconductor packaging process needs to be developed towards a more excellent packaging mode of a PLFO (sheet level Fan out) process.

Disclosure of Invention

The application provides a chip package, a manufacturing method thereof and an electronic device, which are used for solving the problem that the chip package in the prior art cannot achieve the technical effects of miniaturization, lightness and thinness and excellent electrical and heat dissipation characteristics.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a chip package, wherein the chip package includes: a patterned metal substrate sheet; a chip disposed on the metal base plate; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer.

And a patterned second conductive layer is arranged between the overlapped parts of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.

And a third conducting layer is also arranged between the overlapped part of the metal substrate plate and the chip, and the chip is attached to the metal substrate plate through the third conducting layer.

The chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface, far away from the first insulating layer, of the metal substrate board.

The chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.

Wherein the surface area of the side of the through hole facing the metal base plate is smaller than the surface area of the side far away from the metal base plate.

In order to solve the above technical problem, the present application adopts another technical solution: a method for manufacturing a chip package is provided, wherein the method comprises: arranging a chip on the metal substrate plate; forming a first insulating layer on the metal base plate provided with the chip to cover the chip and the metal base plate; patterning the first insulating layer to form a patterned first insulating layer, wherein through holes are formed in the patterned first insulating layer to expose portions of the metal substrate plate and the chip; forming a first conductive layer on the patterned first insulating layer, wherein the first conductive layer is filled in the through hole; patterning the first conductive layer to form a patterned first conductive layer; the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

Wherein, after the step of forming a first insulating layer on the metal substrate board provided with the chip to cover the chip and the metal substrate board, patterning the first insulating layer to form a patterned first insulating layer, wherein the step of providing a through hole in the patterned first insulating layer to expose a portion of the metal substrate board and the chip further comprises: forming a second conductive layer on the first insulating layer; patterning the first insulating layer to form a patterned first insulating layer, wherein the step of providing a through hole in the patterned first insulating layer to expose a portion of the metal base plate and the chip comprises: patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein through holes are arranged in the patterned first insulating layer and the patterned second conductive layer to expose parts of the metal substrate plate and the chip; forming a first conductive layer on the patterned first insulating layer, wherein the step of filling the through hole with the first conductive layer comprises: forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, wherein the first conductive layer is filled in the through hole; the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer comprises: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

Wherein the step of providing the chip on the metal base material plate specifically includes: forming a third conductive layer on the metal base material plate; and arranging a chip on the third conductive layer.

Wherein the step of patterning the metal substrate plate to form the patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises: and forming a conductive metal layer on the surface of the patterned metal substrate plate far away from the first insulating layer.

Wherein the step of patterning the metal substrate plate to form the patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises: and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chip package as defined in any one of the above.

The beneficial effect of this application is: unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate sheet; a chip disposed on the metal base plate; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application;

FIG. 2 is a schematic structural diagram of a second embodiment of a chip package according to the present application;

FIG. 3 is a schematic structural diagram of a third embodiment of a chip package according to the present application;

FIG. 4 is a schematic structural diagram of a fourth embodiment of a chip package according to the present application;

fig. 5 is a schematic structural diagram of a fifth embodiment of the chip package of the present application;

fig. 6 is a schematic structural diagram of a sixth embodiment of a chip package according to the present application;

FIG. 7a is a schematic flow chart illustrating a method of fabricating a chip package according to a first embodiment of the present invention;

FIGS. 7 b-7 g are schematic structural diagrams of an embodiment corresponding to S710-S760 in FIG. 7 a;

FIG. 8a is a flow chart illustrating a method of fabricating a chip package according to a second embodiment of the present invention;

FIGS. 8 b-8 f are schematic structural diagrams of an embodiment corresponding to S830-S870 in FIG. 8 a;

FIG. 9a is a flow chart illustrating a third embodiment of a method for fabricating a chip package according to the present invention;

FIGS. 9 b-9 c are schematic structural diagrams of an embodiment corresponding to S910-S920 in FIG. 9 a;

FIG. 10a is a flow chart illustrating a fourth embodiment of a method for fabricating a chip package according to the present invention;

FIG. 10b is a schematic diagram illustrating an embodiment corresponding to S1070 of FIG. 10 a;

FIG. 11a is a flow chart illustrating a fifth embodiment of a method for fabricating a chip package according to the present invention;

FIG. 11b is a schematic diagram illustrating an embodiment corresponding to S1170 of FIG. 11 a;

fig. 12 is a schematic structural diagram of an embodiment of an electronic device according to the present application.

Detailed Description

In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application.

In the present embodiment, the chip package includes the patterned metal base plate 11, the chip 21, the first insulating layer 31, and the patterned first conductive layer 41. The chip 21 is disposed on the metal substrate 11, the first insulating layer 31 covers the chip 21 and the metal substrate 11, and a through hole is formed in the first insulating layer 31 to expose a portion of the metal substrate 11 and the chip 21, and further, a first conductive layer 41 is further formed in the through hole and on the first insulating layer 31, so that the chip 21 can be electrically connected to the metal substrate 11 through the first conductive layer 41, and finally, a pin of the chip package is formed, so that the chip package has a short electrical path and a short heat dissipation path, and has excellent low resistance and heat dissipation effects.

The number of the through holes in the first insulating layer 31 includes at least two, at least one through hole is disposed above the chip 21, at least another through hole is correspondingly disposed on the metal substrate 11, and the at least two through holes are electrically connected to each other through the first conductive layer 41 covering the inside of each through hole. And a portion of the structure corresponding to the metal substrate plate 11 under the at least two through holes may serve as a package pin of the chip package to electrically connect with an external device or other chips.

The patterning of the metal substrate 11 and the first conductive layer 41 is correspondingly set to be suitable for the logic circuit to be implemented by the chip 21, and different chip pins correspond to different patterned electrical paths, and the patterning can be performed by chemical etching or ion etching.

Alternatively, the material of the metal substrate 11 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 31 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 41 is one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 21 in the chip package can realize double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having more excellent heat dissipation characteristics.

Alternatively, the surface area of the through hole provided in the first insulating layer 31 on the side facing the metal base plate 11 may be set to be smaller than the surface area on the side away from the metal base plate 11, that is, the bottom areas of the two sides of the through hole may be set to be different, and the through hole may also penetrate through the metal base plate 11.

Alternatively, the edge portions of the first insulating layer 31 corresponding to the respective through holes may be inclined edges having at least two different inclination angles, or may be arranged in any reasonable structural style such as an arc-shaped curved surface, a wavy curved surface, and the like.

Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate sheet; a chip disposed on the metal base plate; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package according to a second embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in the present application in fig. 1 in that the chip package further includes a patterned second conductive layer 51, wherein the second conductive layer 51 is disposed between the overlapping portions of the first insulating layer 31 and the first conductive layer 41.

In the present embodiment, the second conductive layer 51 is disposed on the portion of the first insulating layer 31 not opened with the through hole, and the chip 21 is connected to the second conductive layer 51 through the first conductive layer and finally connected to the metal substrate 11.

The material used for the second conductive layer 51 is also selected from one of copper, aluminum, gold, silver, tin, lead, and their alloys or metal-filled organics, which is not limited in this application.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip package according to a third embodiment of the present application. This embodiment differs from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further comprises a third conductive layer 61, wherein the third conductive layer 61 is disposed between the portion where the metal substrate plate 11 and the chip 21 overlap.

In the present embodiment, the third conductive layer 61 is first disposed on the metal substrate 11, and the chip 21 is correspondingly disposed on the third conductive layer 61, wherein the chip 21 can be tightly attached to the metal substrate 11 through the third conductive layer 61.

Alternatively, the third conductive layer 61 may be a layer of conductive adhesive with adhesive property, i.e. an adhesive with certain conductivity after being cured or dried, such as one of silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive and carbon-based conductive adhesive, or adhesive alloy, such as one of copper, aluminum, gold, silver and their alloy or metal-filled organic matter, wherein the chip 21 and the metal substrate 11 can be reliably connected together and an effective conductive path can be formed through the third conductive layer 61.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a chip package according to a fourth embodiment of the present application. This embodiment differs from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further comprises a conductive metal layer 71, wherein the conductive metal layer 71 is disposed on the surface of the metal substrate board 11 away from the first insulating layer 31, i.e. the conductive metal layer 71 is disposed on the surface of the metal substrate board 11 on the other side where the chip 21 is disposed.

In the embodiment, the material of the conductive metal layer 71 is the same as the metal substrate 11, and is selected from one of copper, aluminum, gold, silver and their alloys or metal-filled organic substances, and is a thickened and stacked arrangement for the metal substrate 11, so as to ensure that the finally formed patterned metal substrate 11, i.e. the corresponding pins of the chip package, have more reliable strength without being easily bent or broken.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a chip package according to a fifth embodiment of the present application. This embodiment is different from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further includes a second insulating layer 81, wherein the second insulating layer 81 covers the first conductive layer 41 and the partially exposed first insulating layer 31.

In the embodiment, the patterned first insulating layer 31 is partially exposed and is not completely covered by the first conductive layer 41, wherein the second insulating layer 81 is further disposed in the chip package to cover the first conductive layer 41 and the partially exposed first insulating layer 31, so as to effectively protect the first conductive layer 41 from being damaged by an external force, thereby preventing a logic circuit of a corresponding pin of the chip package from being unable to be effectively implemented due to the external force.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a chip package according to a sixth embodiment of the present application.

Optionally, in an embodiment, the chip package specifically includes: a patterned metal base plate 11, a chip 21, a first insulating layer 31, a patterned first conductive layer 41, a patterned second conductive layer 51, a third conductive layer 61, a conductive metal layer 71, and a second insulating layer 81.

Wherein, the third conductive layer 61 is disposed on the patterned metal substrate 11, the chip 21 is disposed on the third conductive layer 61, the first insulating layer 31 covers the chip 21 and the metal substrate 11, and the patterned second conductive layer 51 is further disposed on the first insulating layer 31, wherein through holes are disposed in the first insulating layer 31 and the second conductive layer 51 to expose portions of the metal substrate 11 and the chip 21, and the patterned first conductive layer 41 is disposed on the second conductive layer 51 and in the through holes, so that the chip 21 can be connected to the patterned second conductive layer 51 and the patterned metal substrate 11 through the patterned first conductive layer 41 to form pins of the chip package, thereby making the chip package have a shorter electrical path and a heat dissipation path, and having excellent low resistance characteristics and a heat dissipation effect.

The conductive metal layer 71 is disposed on the surface of the metal substrate 11 away from the first insulating layer 31, and the conductive metal layer 71 is a thickened and stacked layer on the metal substrate 11 to ensure the patterned metal substrate 11 to be finally formed, i.e., the corresponding pins of the chip package have more reliable strength and are not easily bent or broken. The second insulating layer 81 covers the first conductive layer 41 and the partially exposed second conductive layer 51 to effectively protect the first conductive layer 41 and the second conductive layer 51 from being damaged by external force, so as to prevent the logic circuit of the corresponding pin of the chip package from being unable to be effectively realized due to the external force.

Alternatively, the material of the metal substrate 11 and the conductive metal layer 71 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 31 and the second insulating layer 81 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, the material of the first conductive layer 41 and the second conductive layer 51 may be one selected from copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, and the third conductive layer 61 may be one of silver-based conductive paste, gold-based conductive paste, copper-based conductive paste, and carbon-based conductive paste, or adhesive alloy, such as one of copper, aluminum, gold, silver, and their alloys or metal-filled organics, so that the chip 21 in the chip package can realize double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having more excellent heat dissipation characteristics.

Alternatively, the surface area of the through hole provided in the first insulating layer 31 on the side facing the metal base plate 11 may be set to be smaller than the surface area on the side away from the metal base plate 11, that is, the bottom areas of the two sides of the through hole may be set to be different, while in other embodiments, the bottom areas of the two sides of the through hole may also be set to be the same, and the through hole may also penetrate through the metal base plate 11, which is not limited in this application.

Optionally, the insulating material used for the second insulating layer 81 is different from the insulating material used for the first insulating layer 31, and the thermal conductivity of the insulating material used for the second insulating layer 81 is better than that of the insulating material used for the first insulating layer 31, that is, the thermal conductivity of the second insulating layer 81 is higher than that of the first insulating layer 31, so that after the first conductive layer 41 and the second conductive layer 51 are coated, the chip 21 can achieve a better heat dissipation effect through the second insulating layer 81.

Optionally, a solder resist insulating layer is further provided on a side of the chip 21 remote from the metal base board 11 to allow only the first conductive layer 41 to be connected to a position corresponding to the pad on the side of the chip 21. The bonding pad is a copper layer portion exposed by a side of the chip 21 that needs to be soldered to electrically connect with an external device, and a non-bonding pad on the side of the chip 21 is provided as a solder resist insulating layer.

Optionally, the outermost layer of the chip package, that is, the outer side of the conductive metal layer 71 and the second insulating layer 81, is further provided with an insulating cover material of any one of reasonable colors, such as black, green or yellow, so as to make the appearance of the chip package more ornamental.

Alternatively, the edge portions of the metal substrate 11 corresponding to the corresponding grooves and the structure of the remaining portions after etching may be beveled edges having at least two different angles of inclination, or may be arranged in any reasonable structural pattern such as an arc-shaped curved surface, a wavy curved surface, and the like.

Alternatively, there may be a void at a position where the metal base plate 11 is connected to the first conductive layer 41, or inside the first conductive layer 41, and the void is further filled with an insulating resin to prevent the entry of air and/or water molecules.

Optionally, the patterned gap on the side of the metal substrate 11 away from the chip 21 is filled with an insulating envelope material of any reasonable color, such as black, green or yellow, to make the appearance of the chip package more ornamental.

Alternatively, the chip package has a plurality of metal base plates 11 and insulating layers disposed in respective stacks, and the interconnection of the plurality of metal base plates 11 is realized by a plurality of conductive layers in respective through holes.

Optionally, a solder ball is further disposed on a side of the metal substrate 11 or the conductive metal layer 71 away from the chip 21 to electrically connect with an external device.

Optionally, a side of the chip package away from the metal substrate board 11 is further connected with a power module device, such as one or more of any reasonable power devices, such as a resistor, a capacitor, a transistor, etc., through the first conductive layer 41.

Optionally, at least two chips 21 are disposed on a side surface of the metal substrate 11 close to the chip 21, and the at least two chips 21 may be electrically connected through the metal substrate 11 and the first conductive layer 41, or the at least two chips 21 are independent from each other and are not electrically connected, which is specifically set by a user according to a circuit logic that the user needs to achieve.

Based on the general inventive concept, the present application further provides a method for manufacturing a chip package, please refer to fig. 7 a-7 g, wherein fig. 7a is a schematic flow chart of a first embodiment of the method for manufacturing a chip package according to the present application, and fig. 7 b-7 g are schematic structural diagrams of an embodiment corresponding to S710-S760 in fig. 7 a. The embodiment comprises the following steps:

s710: a chip is provided on the metal base plate.

Specifically, as shown in fig. 7b, in one embodiment, the chip 21 is first disposed on the provided metal base plate 11.

S720: a first insulating layer is formed on the metal base plate provided with the chip so as to cover the chip and the metal base plate.

Specifically, as shown in fig. 7c, in one embodiment, after the chip 21 is disposed on the metal substrate plate 11, a first insulating layer 31 is further formed on the metal substrate plate 11 to completely cover the chip 21 and the metal substrate plate 11.

S730: and patterning the first insulating layer to form a patterned first insulating layer, wherein a through hole is arranged in the patterned first insulating layer to expose part of the metal substrate plate and the chip.

Specifically, as shown in fig. 7d, in an embodiment, the first insulating layer 31 is formed by printing, pressing, spraying, and further a plurality of through holes are formed in the first insulating layer 31 by laser drilling or chemical etching and penetrate the surfaces of the metal substrate 11 and the chip 21 to expose portions of the metal substrate 11 and the chip 21.

S740: and forming a first conductive layer on the patterned first insulating layer, wherein the through hole is filled with the first conductive layer.

Specifically, as shown in fig. 7e, in an embodiment, after a through hole is formed in the patterned first insulating layer 31 and part of the metal substrate 11 and the chip 21 are exposed, a first conductive layer 41 is further fabricated on the first insulating layer 31 by printing, pressing, spraying, chemical plating, chemical deposition, or other processing methods, and the first conductive layer 41 is filled on the surface inside the through hole to achieve corresponding connection between the chip 21 and the metal substrate 11.

S750: the first conductive layer is patterned to form a patterned first conductive layer.

Specifically, as shown in fig. 7f, in one embodiment, the first conductive layer 41 is patterned by chemical etching or ion etching to form a patterned first conductive layer 41.

S760: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

Specifically, as shown in fig. 7g, in one embodiment, after the first conductive layer 41 is formed and patterned on the first insulating layer 31 and in the through hole, which are patterned and cover the chip 21 and the metal substrate 11, the first conductive layer 41 is patterned, and the metal substrate 11 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11. It can be understood that the chip 21 can be connected to the patterned metal substrate plate 11 through the patterned first conductive layer 41 in the through hole and on the first insulating layer 31, wherein the patterning process performed on the first insulating layer 31, the first conductive layer 41 and the metal substrate plate 11 is an adaptive setting made for achieving the electrical connection between the chip 21 and the metal substrate plate 11 and the logic circuit to be achieved, so as to finally constitute the leads of the chip package.

Alternatively, the material of the metal substrate 11 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organic substances, the material of the first insulating layer 31 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 41 is one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organic substances, so that the chip in the chip package can realize double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having more excellent heat dissipation characteristics.

Different from the prior art, the method for manufacturing the chip package in the present application includes: arranging a chip on the metal substrate plate; forming a first insulating layer on the metal base plate provided with the chip to cover the chip and the metal base plate; patterning the first insulating layer to form a patterned first insulating layer, wherein through holes are formed in the patterned first insulating layer to expose portions of the metal substrate plate and the chip; forming a first conductive layer on the patterned first insulating layer, wherein the first conductive layer is filled in the through hole; patterning the first conductive layer to form a patterned first conductive layer; the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer. In this way, the chip package who obtains in this application can be through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole and dispel the heat, thereby make this chip can realize two-sided heat dissipation, and the structure is comparatively simple, electric route and heat dissipation path are short, have more excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package, and the mode of adopting two-way preparation also makes the process of its whole processing procedure technology can be compatible with the technology of PCB equipment completely, thereby have efficient and the characteristics of high batchization degree, with low costs.

Referring to fig. 8a to 8f, fig. 8a is a flow chart illustrating a method for manufacturing a chip package according to a second embodiment of the present invention, and fig. 8b to 8f are schematic structural diagrams illustrating an embodiment corresponding to S830-S870 in fig. 8 a. It can be understood that the method for manufacturing the chip package in this embodiment is a flowchart illustrating a detailed implementation of the method for manufacturing the chip package in fig. 7a, and includes the following steps:

s810 and S820 in fig. 8a are the same as S710 and S720 in fig. 7a, respectively, and please refer to fig. 7a and the related description thereof, which are not repeated herein, and at S820, after the step of forming the first insulating layer on the metal substrate board provided with the chip to cover the chip and the metal substrate board, the method further includes the following steps:

s830: a second conductive layer is formed on the first insulating layer.

Specifically, as shown in fig. 8b, in one embodiment, after the chip 21 is disposed on the metal substrate 11, and the first insulating layer 31 is formed on the metal substrate 11 on which the chip 21 is disposed to cover the chip 21 and the metal substrate 11, a second conductive layer 51 is further formed on the first insulating layer 31.

S840: and patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein through holes are arranged in the patterned first insulating layer and the patterned second conductive layer to expose parts of the metal substrate plate and the chip.

Specifically, as shown in fig. 8c, in one embodiment, the first insulating layer 31 and the second conductive layer 51 formed on the first insulating layer 31 are patterned to obtain the patterned first insulating layer 31 and the patterned second conductive layer 51, and the first insulating layer 31 and the patterned second conductive layer 51 are formed and covered on the chip 21 and the metal substrate 11 provided with the chip 21, and a plurality of through holes are further formed in the first insulating layer 31 and the second conductive layer 51 by laser drilling or chemical etching and penetrate the surfaces of the metal substrate 11 and the chip 21 to expose portions of the metal substrate 11 and the chip 21.

S850: and forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, wherein the through hole is filled with the first conductive layer.

Specifically, as shown in fig. 8d, in one embodiment, through holes are provided in the patterned first insulating layer 31 and the second conductive layer 51, and part of the metal substrate 11 and the chip 21 are exposed, and further, the first conductive layer 41 is fabricated on the first insulating layer 31 and the second conductive layer 51, and the first conductive layer 41 is filled in the through holes formed in the first insulating layer 31, so as to realize corresponding connection between the chip 21 and the metal substrate 11.

S860: the first conductive layer is patterned to form a patterned first conductive layer.

Specifically, as shown in fig. 8e, in one embodiment, the first conductive layer 41 is patterned by chemical etching or ion etching to form a patterned first conductive layer 41, and in other embodiments, the second conductive layer 51 may be further patterned to form a vertically uniform patterned first conductive layer 41 and a patterned second conductive layer 51.

S870: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

Specifically, as shown in fig. 8f, in one embodiment, when the first conductive layer 41 is formed on the first insulating layer 31 and the patterned second conductive layer 51 which are patterned and cover the chip 21 and the metal substrate 11, and the first conductive layer 41 is also filled in the through hole in the first insulating layer 31, the first conductive layer 41 is subjected to patterning treatment, and the metal substrate 11 is further subjected to patterning treatment by chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11. It can be understood that the chip 21 can be connected to the patterned metal substrate board 11 through the patterned first conductive layer 41 in the through hole and on the first insulating layer 31 and the second conductive layer 51, wherein the patterning process performed on the first insulating layer 31, the second conductive layer 51, the first conductive layer 41 and the metal substrate board 11 is an adaptive setting made for achieving the electrical connection between the chip 21 and the metal substrate board 11 and the logic circuit to be achieved, so as to finally form the leads of the chip package.

Referring to fig. 9a to 9c, fig. 9a is a flow chart illustrating a method for manufacturing a chip package according to a third embodiment of the present invention, and fig. 9b to 9c are structural diagrams illustrating an embodiment corresponding to S910 to S920 in fig. 9 a. It is understood that the method for manufacturing the chip package in this embodiment is a flowchart illustrating another detailed implementation of the method for manufacturing the chip package in fig. 7a, and includes the following steps:

s930, S940, S950, S960, and S970 in fig. 9a are respectively the same as S720, S730, S740, S750, and S760 in fig. 7a, and refer to fig. 7a and the related text description, which are not repeated herein, and the step of disposing the chip on the metal substrate plate specifically includes:

s910: a third conductive layer is formed on the metal base material plate.

Specifically, as shown in fig. 9b, in one embodiment, a third conductive layer 61 is formed on the metal substrate 11.

S920: and arranging a chip on the third conductive layer.

Specifically, as shown in fig. 9c, in one embodiment, after the third conductive layer 61 is formed on the metal substrate 11, the chip 21 is attached to the third conductive layer 61, wherein the third conductive layer 61 may be a conductive adhesive with adhesive property, i.e. an adhesive with certain conductivity after being cured or dried, such as one of silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive and carbon-based conductive adhesive, or an adhesive alloy, such as one of copper, aluminum, gold, silver and their alloys or metal-filled organic substances, so that the chip 21 and the metal substrate 11 can be more reliably connected together by disposing the chip 21 on the third conductive layer 61 to form an effective conductive path.

Referring to fig. 10a to 10b, fig. 10a is a flowchart illustrating a fourth embodiment of a method for manufacturing a chip package according to the present application, and fig. 10b is a schematic structural diagram illustrating an embodiment corresponding to S1070 in fig. 10 a. The process flow of the chip package in this embodiment and fig. 7a is a schematic flow chart of another detailed implementation of the method for manufacturing a chip package, which includes the following steps:

s1010, S1020, S1030, S1040, S1050, and S1060 in fig. 10a are respectively the same as S710, S720, S730, S740, S750, and S760 in fig. 7a, and refer to fig. 7a and the related description thereof for details, which are not repeated herein, but the step of patterning the metal substrate plate to form a patterned metal substrate plate at S1060, so that the step of connecting the chip to the patterned metal substrate plate through the patterned first conductive layer, further includes the following steps:

s1070: and forming a conductive metal layer on the surface of the patterned metal substrate plate far away from the first insulating layer.

Specifically, as shown in fig. 10b, in one embodiment, when the first conductive layer 41 is formed and patterned on the patterned first insulating layer 31 covering the chip 21 and the metal substrate 11 and in the corresponding through hole, the first conductive layer 41 is subjected to patterning treatment, and the metal substrate 11 is further subjected to patterning treatment by chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11, and after the chip 21 is connected to the patterned metal substrate 11 by the patterned first conductive layer 41, a conductive metal layer 71 is further formed and formed on the surface of the patterned metal substrate 11 away from the first insulating layer 31. In other embodiments, the first conductive layer 41 may be formed on the first insulating layer 31 and the corresponding through holes, which are patterned and covered on the chip 21 and the metal substrate 11, and the first conductive layer 41 is patterned, then a conductive metal layer 71 is formed on the surface of the metal substrate 11 away from the first insulating layer 31, and then the metal substrate 11 and the conductive metal layer 71 are patterned to form the patterned first conductive layer 41, the metal substrate 11, and the conductive metal layer 71, so that the chip 21 is connected to the patterned metal substrate 11 through the patterned first conductive layer 41.

The material used for the conductive metal layer 71 is the same as the metal substrate 11, and is selected from one of copper, aluminum, gold, silver and their alloys or metal-filled organic matters, and is a thickened and laminated arrangement for the metal substrate 11, so as to ensure that the finally formed patterned metal substrate 11 is not easily bent and broken, that is, to ensure that the corresponding pins of the chip package have more reliable strength.

Referring to fig. 11 a-11 b, fig. 11a is a schematic flow chart illustrating a fifth embodiment of a method for manufacturing a chip package according to the present application, and fig. 11b is a schematic structural view illustrating an embodiment corresponding to S1170 of fig. 11 a. The process flow of the chip package in this embodiment and fig. 7a is a schematic flow chart of another detailed implementation of the method for manufacturing a chip package, which includes the following steps:

s1110, S1120, S1130, S1140, S1150 and S1160 in fig. 11a are respectively the same as S710, S720, S730, S740, S750 and S760 in fig. 7a, and refer to fig. 7a and the related text description thereof, which are not repeated herein, but after the step of patterning the metal substrate plate to form the patterned metal substrate plate at S1160, so that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer, the method further includes the following steps:

s1170: and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

Specifically, as shown in fig. 11b, in one embodiment, when the first conductive layer 41 is formed on the first insulating layer 31 patterned and covering the chip 21 and the metal base material plate 11 and in the corresponding through hole, the first conductive layer 41 is subjected to patterning treatment, and the metal base material plate 11 is further subjected to patterning treatment by a chemical etching or ion etching method, to form the patterned first conductive layer 41 and the metal base plate 11, and after connecting the chip 21 to the patterned metal base plate 11 via the patterned first conductive layer 41, a second insulation 81 is further formed on the first conductive layer 41 and the partially exposed first insulation layer 31, to cover the first conductive layer 41 and a portion of the exposed first insulating layer 31, so as to effectively protect the first conductive layer 41 from being damaged by external force, therefore, the logic circuit of the corresponding pin of the chip packaging body is prevented from being incapable of being effectively realized due to the action of external force.

Based on the general inventive concept, the present application further provides an electronic device, please refer to fig. 12, and fig. 12 is a schematic structural diagram of an embodiment of the electronic device according to the present application. The electronic device 1200 includes any one of the chip packages 1210 described above.

Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate sheet; a chip disposed on the metal base plate; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.