阅读说明：本技术 半导体结构 (Semiconductor structure ) 是由 傅安教 黄柏翔 徐玮泽 薛琇文 张盟昇 于 2020-09-25 设计创作，主要内容包括：本公开提供一种半导体结构。其包括一第一薄层、第二薄层及第三薄层,第一薄层包含第一介电层以及多个第一金属特征,其中第一金属特征包括第一区域中的第一组第一金属特征以及第二区域中的第二组第一金属特征,第一组第一金属特征具有第一图案密度,而第二组第一金属特征具有大于第一图案密度的第二图案密度。上述半导体结构还包括一第二薄层,被设置于第一薄层上,第二薄层包括接触第一组第一金属特征的多个第一通孔。上述半导体结构还包括一第三薄层,被设置于第二薄层上,第三薄层包括一熔丝元件,其中上述熔丝元件具有在第一区域中的第一厚度,第一厚度小于上述熔丝元件在第二区域中的第二厚度。(The present disclosure provides a semiconductor structure. The first thin layer includes a first dielectric layer and a plurality of first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, the first set of first metal features has a first pattern density, and the second set of first metal features has a second pattern density greater than the first pattern density. The semiconductor structure further includes a second layer disposed on the first layer, the second layer including a plurality of first vias contacting the first set of first metal features. The semiconductor structure further includes a third layer disposed on the second layer, the third layer including a fuse element, wherein the fuse element has a first thickness in the first region that is less than a second thickness of the fuse element in the second region.)

1. A semiconductor structure, comprising:

a first layer comprising a first dielectric layer and a plurality of first metal features, wherein the first metal features comprise a first set of first metal features in a first region and comprise a second set of first metal features in a second region, the second region being separated from the first region along a first direction, wherein the first set of first metal features has a first pattern density and the second set of first metal features has a second pattern density, the second pattern density being greater than the first pattern density;

a second layer disposed on the first layer, the second layer including a plurality of first vias contacting the first set of first metal features; and

a third layer disposed on the second layer, the third layer including a fuse element, wherein the fuse element has a first thickness in the first region that is less than a second thickness in the second region.

Technical Field

The present disclosure relates to fuse structures and methods of forming the same, and more particularly, to electrical fuses (efuses) in semiconductor devices and methods of forming the same.

Background

In the semiconductor industry, fuse elements are widely used for various purposes as features in integrated circuits, such as for memory repair, analog resistance trimming (trimming), and chip identification. For example, by replacing defective memory cells on a chip with redundant cells on the same chip, the manufacturing yield of the memory can be significantly improved. Fuses broken by a laser beam are called laser fuses, and fuses broken by current or blowing (blowing) are called electronic fuses (electrical fuses or e-fuses). By selectively blowing fuses in an integrated circuit having multiple potential uses, a versatile integrated circuit design can be economically manufactured and adapted for various special uses.

Electronic fuses may be introduced in the design of integrated circuits, where the fuses are selectively blown, for example, by a sufficient current to cause electromigration or melting of the fuse link, thereby creating a more resistive path or open circuit. In some applications, the cross-sectional area of the fuse element (i.e., the width of the fuse element) may be adjusted to vary the current density through the fuse element, and thus the current required to blow the fuse. Current electronic fuse designs lack the ability to adjust the thickness of the fuse element because the fuse element is formed in the metallization layer of the device. Accordingly, there is a need for an underlying layout design for an electronic fuse structure that overcomes the deficiencies of the prior art.

Disclosure of Invention

It is an object of the present disclosure to provide a semiconductor structure to solve at least one of the above problems.

Embodiments of the present disclosure provide a semiconductor structure comprising a first thin layer comprising a first dielectric layer and a plurality of first metal features, wherein the first metal features comprise a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set of first metal features has a first pattern density and the second set of first metal features has a second pattern density, the second pattern density being greater than the first pattern density. The semiconductor structure further includes a second layer disposed on the first layer, the second layer including a plurality of first vias contacting the first set of first metal features. The semiconductor structure further includes a third layer disposed on the second layer, the third layer including a fuse element, wherein the fuse element has a first thickness in the first region that is less than a second thickness of the fuse element in the second region.

The embodiment of the disclosure provides a method for forming a semiconductor structure. The forming method comprises providing a semiconductor substrate; forming a first thin layer on the semiconductor substrate, comprising: forming a first dielectric layer; depositing a plurality of first metal features having a first pattern density in a first region; depositing a plurality of dummy pattern metal features having a second pattern density in the second area, wherein the second pattern density is greater than the first pattern density; and performing a chemical mechanical polishing process on the first thin layer to dig into a top surface of the previous thin layer in the second region such that a first height of the first thin layer in the first region is greater than a second height of the first thin layer in the second region; and forming a fuse element on the first thin layer, the fuse element including a first thickness in the first region, the first thickness being less than a second thickness in the second region.

The embodiment of the present disclosure provides a semiconductor structure, including a semiconductor substrate; a fuse region formed on the semiconductor substrate, the fuse region including a plurality of dummy pattern metal features having a first pattern density; a contact region formed on the semiconductor substrate adjacent to the fuse region, the contact region including a plurality of metal features having a second pattern density, wherein the second pattern density is less than the first pattern density; and a fuse element formed in the fuse region and the contact region, wherein a first thickness of the fuse element in the fuse region is greater than a second thickness of the fuse element in the contact region.

Drawings

For a more complete understanding of embodiments of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.

Fig. 1A is a top view of an electronic fuse structure, according to an embodiment of the disclosure.

FIG. 1B is a cross-sectional view of the electronic fuse of FIG. 1A along line 1B.

Fig. 2A is an electronic fuse structure according to other embodiments of the present disclosure.

Fig. 2B is a cross-sectional view of the electronic fuse of fig. 2A along line 2B.

Figure 3 is a flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 4A-4D are cross-sectional views of the semiconductor structure of fig. 2B at various stages during fabrication.

The reference numbers are as follows:

100 semiconductor structure

102 base layer

104 fuse structure

106 fuse element

108 contact pad

116 dummy conductive features

1B line segment

CR contact area

FR fuse region

110 first ILD layer

112 metal features

114 etch stop layer

120 second ILD layer

122 through hole

Dummy pattern metal features 124

128 top surface

130 top surface

132 surface of

134 top surface

T1, T2 thickness

Mx, Vx, Mx-1 thin layer

200 semiconductor structure

126 dummy pattern metal features

T3, T4 thickness

2B line segment

300 method

302 to 310 blocks

304a to 304d are squares

H1 first height

H2 second height

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description recites a first feature formed on or over a second feature, it may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that direct contact between the first and second features is not provided. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms, such as "below …," "below," "…," "above," and the like, to facilitate describing the relationship of one element or feature to another element or feature in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. The device may be turned to a different orientation (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly.

The making and using of embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

Embodiments will be described with respect to an electronic fuse structure in a semiconductor chip. Other embodiments contemplate applications in which it is desirable to use an electronic fuse structure.

Fig. 1A depicts a semiconductor structure 100 having a base layer 102. The base layer 102 may include one or more thin layers of the semiconductor structure 100, such as a semiconductor substrate, a contact etch stop layer, an inter-layer dielectric (ILD) layer, a conductive layer, and an interconnect layer. The semiconductor substrate may comprise a single or compound semiconductor substrate having active elements such as transistors formed thereon. The substrate may be formed of silicon, silicon germanium, or the like.

Alternatively, the semiconductor substrate may be made of some other suitable elemental semiconductor, such as diamond or germanium; made of a suitable compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or from a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenide phosphide (gaas), or indium gallium phosphide (ga llium indium phosphide).

The semiconductor substrate may also include various doped regions, such as n-wells and p-wells. In some embodiments, the semiconductor substrate may include a buried (buried) dielectric material layer for isolation formed by a suitable technique, such as the technique known as separation by implanted oxygen (SIMOX).

The semiconductor substrate may have a uniform composition or may include various thin layers. These thin layers may have similar or dissimilar compositions, and in various embodiments, some thin layers have non-uniform compositions to induce device strain (strain) and thereby tune the performance of the device. The semiconductor substrate may include an epitaxial layer, such as an epitaxial semiconductor layer of a bulk (bulk) semiconductor wafer, formed on the top surface. In various embodiments, the semiconductor substrate comprises one or more epitaxially grown semiconductor materials. For example, a silicon layer is epitaxial on a silicon wafer. In another embodiment, the silicon germanium layer is epitaxial on a silicon wafer. In yet another embodiment, silicon and silicon germanium are alternatively epitaxial on a silicon wafer. In some embodiments, suitable deposition processes for epitaxial growth include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), high-density plasma CVD (HDP-CVD), Physical Vapor Deposition (PVD), and/or other suitable deposition processes. Any of these techniques may be used to grow semiconductor layers having any composition, including graded compositions.

The semiconductor structure 100 may also include a fuse structure 104, the fuse structure 104 includes a fuse element 106, the fuse element 106 is at least partially disposed in the fuse region FR, the fuse element 106 is connected to a pad (pad) or a plug (plug)108, and the pad or plug 108 is at least partially disposed in the contact region CR. As used herein, the fuse region FR and the contact region CR may refer only to regions of the fuse structure 104, and not to specific elements within the fuse structure 104. In some other embodiments, the fuse region FR may be specifically referred to as the fuse element 106. The fuse structure 104 may be formed of a metal such as copper, or a metal such as nickel silicide (NiSi), titanium silicide (TiSi)₂) Cobalt silicide (CoSi)_x) Platinum silicide (PtSi)₂) And the like, a silicon-doped polysilicon (polycide). The contact pad 108 may be formed of copper, tungsten, metal, or the like, and may also include a diffusion barrier (diffusion barrier layer) of the liner contact pad 108, which is formed of TiN, TaN, or the like, for example. In some embodiments, the width of fuse element 106Much smaller than the width of the contact pad 108. In one or more embodiments, the contact pads 108 may include one or more via (via) structures filled with metal plugs. The semiconductor structure 100 may additionally include dummy conductive features 116 disposed on the sides of the fuse element 106 for limiting the formation of the fuse element 106 for improved manufacturing, including better pattern density and pattern geometry. The fuse element 106 and the dummy conductive feature 116 are formed simultaneously, for example, using metal lines in the same metal layer (thin layer Mx). Accordingly, the fuse element 106 and the dummy conductive feature 116 are at the same level and comprise the same conductive material, such as copper, aluminum, other suitable conductive materials, or combinations thereof.

Fig. 1B is a cross-sectional view along line 1B of the semiconductor structure 100 of fig. 1A. As shown in fig. 1B, the substrate layer 102 includes a first ILD layer 110, the first ILD layer 110 having metal features 112 formed in the contact regions CR and having dummy pattern metal features 124 formed in the fuse regions FR.

In some embodiments, the first ILD layer 110 may be formed of silicon dioxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the first ILD layer 110 may comprise any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectric material, or combinations thereof. In some embodiments, the first ILD layer 110 comprises a low-k dielectric material (having a dielectric constant less than that of silicon oxide). The formation of the first ILD layer 110 may include deposition and Chemical Mechanical Polishing (CMP) to provide a planar top surface 128.

In some embodiments, the metal features 112 and the dummy pattern metal features 124 may be formed of any suitable conductive material, such as Cu, Co, Ru, W, Mo, Ni, Cr, Ir, Pt, Rh, Ta, Ti, Al, TaN, TiN, a compound or other suitable conductive material or combination thereof. In some embodiments, the deposition of the metal features 112 and dummy pattern metal features 124 may use PVD, CVD, ALD, electroplating (electroplating), ELD, or other suitable deposition process or combination thereof.

It will be appreciated that the metal features 112 may form a thin layer Mx-1. As shown in fig. 1B, the metal features 112 may be aligned along the x-direction. In other words, the height in the z-direction of the top surface 128 and the bottom surface of a first metal feature 112 may be approximately equal to the height in the z-direction of the top surface 128 and the bottom surface of each other metal feature 112. Similarly, the dummy pattern metal features 124 may also be aligned along the x-direction. In some embodiments, the line width, line spacing, and pattern density included in the dummy pattern metal features 124 may be approximately equal to the line width, line spacing, and pattern density of the metal features 112. In such embodiments, the duty ratio of the fuse region FR may be approximately equal to the duty ratio of the contact region CR. The duty ratio is defined as the ratio of the pattern size to the distance between adjacent patterns. In other words, the duty ratio is defined as the ratio of the line segment width to the pitch of the metal lines. In these embodiments, the CMP dishing effect (dishing effect) may be approximately equal between the fuse region FR and the contact region CR. In other words, after CMP, the metal features 112 and the dummy pattern metal features 124 may have approximately equal recess depths regardless of the recess, so that the resulting fuse element 106 includes a uniform starting depth or a flat bottom surface (surface 132) and has a uniform thickness in the fuse region FR and the contact region CR.

In some embodiments, the etch stop layer 114 may be formed on the top surface 128 of the first ILD layer 110, the metal features 112, and the dummy pattern metal features 124. The fuse structure 104 may include a second ILD layer 120 formed on the thin layer Mx-1. The second ILD layer 120 may be combined with materials and methods associated with the first ILD layer 110 without limitation. As shown in fig. 1B, the second ILD layer 120 may conform to the top surface 128 of the metal feature 112. The fuse structure 104 may be formed on the etch stop layer 114. The contact pad 108 may include a via 122 formed in the second ILD layer 120. As used herein, via 122 may include a via trench structure filled with a metal plug therein. The vias 122 may be in electrical contact with the metal features 112 of the thin layer Mx-1. It will be understood that via 122 may form a thin layer Vx.

In some embodiments, the etch stop layer 114 may be formed of SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, or combinations thereof. In some embodiments, etch stop layer 114 may be deposited by plasma enhanced cvd (pecvd) or other suitable deposition process. In some embodiments, the vias 122 may be formed of a conductive material comprising a metal, and may comprise aluminum, copper, aluminum/silicon/copper alloys, cobalt, nickel, titanium, tungsten, platinum, ruthenium, silver, gold, rhodium, molybdenum, cadmium, zinc, and alloys, compounds, or combinations thereof.

The vias 122 can be formed by any suitable deposition method, such as PVD, CVD, ALD, plating (e.g., electroplating), or combinations thereof. In some embodiments, the vias 122 may include a barrier layer. The barrier layer may include a conductive material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and may be formed using a CVD process such as PECVD. In some embodiments, the via 122 may include a seed layer (seed layer). The seed layer may be deposited by PVD, ALD, or CVD and may be formed of tungsten, copper, or copper alloys. In some embodiments, the vias 122 may be deposited on a seed layer.

Fuse structure 104 may also include a fuse element 106 formed on thin layer Vx. Fuse element 106 may be in electrical contact with via 122 of thin layer Vx. It will be understood that fuse element 106 may be formed in a thin layer Mx. As shown in fig. 1B, the fuse element 106 may conform to the top surface (surface 132) of the second ILD layer 120 and the via 122. In one or more embodiments, the fuse element 106 may extend longitudinally (length wise) in the x-direction. In some embodiments, the first width of the fuse element 106 in the contact region CR may be greater than the second width in the fuse region FR along the y-direction. In one or more embodiments, the fuse element 106 may have a fixed thickness in the z-direction. Thus, as shown, the thickness T1 in the fuse region FR may be approximately equal to the thickness T2 in the contact region CR. In some embodiments, the overall metal thickness of the fuse element 106 may be increased relative to conventional fuse structures. In some embodiments, the local metal thickness may be increased relative to conventional fuse structures, such as thickness T1. In some embodiments, the thickness, width, and length of the fuse element 106 may be scaled according to the scaling of critical dimension (critical dimension) of the integrated circuit. In some embodiments, the increased overall metal thickness of the fuse element 106 or the increased local metal thickness of the fuse element 106 in the fuse region FR may provide increased current flow and/or increased current density through the fuse region FR relative to conventional fuse structures, which may make the fuse element 106 more susceptible to burning out compared to conventional fuse structures having a relatively lower metal thickness (e.g., conventional fuses that do not have dummy pattern metal features 124 inserted into the fuse region). In some examples, conventional fuse structures include a concave bottom surface in the fuse region, such that the fuse element is thinner in the fuse region. In some embodiments without vias 122, fuse element 106 may be more easily blown or burned out in contact region CR than fuse region FR. However, in the drawn embodiment including the via 122, the fuse element 106 is more easily burned out in the fuse region FR than in the contact region CR.

Fig. 2A depicts a semiconductor structure 200 according to other embodiments. The semiconductor structure 200 may be combined with similar structures from the semiconductor structure 100 without limitation.

The semiconductor structure 200 includes dummy pattern metal features 126. In some embodiments, the dummy pattern metal features 126 may be formed of any suitable conductive material, such as Cu, Co, Ru, W, Mo, Ni, Cr, Ir, Pt, Rh, Ta, Ti, Al, TaN, TiN, a compound, or other suitable conductive material, or combinations thereof. In some embodiments, the dummy pattern metal features 126 may be deposited using PVD, CVD, ALD, electroplating, ELD, or other suitable deposition process or combination thereof.

In some embodiments, the dummy pattern metal features 126 may include line widths that are greater than the line widths of the metal features 112 and the dummy pattern metal features 124. In some embodiments, the dummy pattern metal features 126 may comprise a pattern density that is greater than the pattern density of the metal features 112 and the dummy pattern metal features 124. In some embodiments, the line width, line spacing, and pattern density of the dummy pattern metal features 126 may be greater than the line width, line spacing, and pattern density of the metal features 112 and the dummy pattern metal features 124. In some embodiments, at least a subset of the line width, line spacing, and pattern density of the dummy pattern metal features 126 is greater than a subset of the line width, line spacing, and pattern density of the metal features 112 and dummy pattern metal features 124. For example, the line spacing and pattern density of dummy pattern metal features 126 is greater than the line spacing and pattern density of metal features 112 and dummy pattern metal features 124. In these embodiments, the load ratio Df of the fuse region FR is larger than the load ratio Dc of the contact region CR, or Df/Dc is larger than 1. In some examples, the ratio of duty ratios Df/Dc is between 1.5 and 2. When the ratio Df/Dc is not large enough, the corresponding dishing effect is not sufficient to cause a sufficient height difference to effectively increase the current density. When the ratio Df/Dc is too large, dummy pattern metal features 126 will be too close together or even clustered together, leading to undesirable stress and delamination (delamination) problems. The ratio Df/Dc is adjusted to enhance current density without causing other problems, such as delamination. The semiconductor structure 200 comprising the thin layer Mx-1 according to any of the embodiments described above, having a larger line width, a larger line spacing, a larger pattern density, or having a larger line width, a larger line spacing and a larger pattern density in the fuse region FR, may modify the loading effect (CMP dishing effect) such that the CMP dishing effect is increased in the fuse region FR compared to the contact region CR. In such embodiments, the CMP dishing effect in the fuse region FR may be greater than the CMP dishing effect in the contact region CR. In other words, after CMP, the top surfaces 128 of the metal features 112 may have a greater height in the z-direction than the height of the top surfaces 130 of the dummy pattern metal features 126. That is, the dummy pattern metal features 126 may include a greater penetration depth than the metal features 112 due to more penetration of the dummy pattern metal features 126 in the fuse region FR. In some embodiments, the resulting fuse element 106 may include a non-uniform starting depth or a curved bottom surface (surface 132) and a non-uniform thickness in the fuse region FR compared to the contact region CR. In some embodiments, the resulting fuse element 106 includes a convex bottom surface.

As shown in fig. 2B, the fuse element 106 may have a non-uniform thickness in the z-direction. In some embodiments, as shown, the thickness T3 in the fuse region FR is greater than the thickness T4 in the contact region CR. In some embodiments, the thickness T3 of the fuse element 106 in the semiconductor structure 200 may exceed the thickness T1 of the fuse element 106 in the semiconductor structure 100. In some embodiments, the overall metal thickness of the fuse element 106 is further increased relative to the semiconductor structure 100. In some embodiments, the local metal thickness (e.g., thickness T3) may be increased relative to semiconductor structure 100. In some embodiments, the increased overall metal thickness of the fuse element 106 or the increased local metal thickness of the fuse element 106 in the fuse region FR provides increased current flow and/or increased current density through the fuse region FR, which may make the fuse element 106 more susceptible to burning compared to a semiconductor structure having a relatively lower metal thickness (e.g., a bottom surface with a concave surface). In some embodiments, the current drawn by the fuse element 106 of the semiconductor structure 200 is greater than 25%, or in a range between 25% and 35%, relative to a fuse element of a semiconductor structure formed by current methods.

In some embodiments described above, fuse element 106 having thickness T3 may be due to a change in the underlying metal environment (e.g., a thin Mx-1 layer) as compared to conventional approaches. As shown in fig. 2B, the height in the z-direction of the top surface 130 of the dummy pattern metal features 126 in the fuse region FR and the top surface 130 of the first ILD layer 110 may be lower than the height of the top surface 128 of the metal features 112 in the contact region CR. On the other hand, the bottom surfaces of the dummy pattern metal features 126 in the fuse region FR and the bottom surfaces of the metal features 112 in the contact region CR may be aligned with each other along the x-direction. In other words, the height in the z-direction of the bottom surface of the dummy pattern metal feature 126 may be approximately equal to the height in the z-direction of the bottom surface of the metal feature 112 in the contact region CR.

As shown in fig. 2B, the second ILD layer 120 may conform to the top surfaces 128, 130 of the metal features 112, the first ILD layer 110, and the dummy pattern metal features 126. Accordingly, the second ILD layer 120 may form a concave structure at least in the fuse region FR because the dummy pattern metal features 126 in the underlying fuse region FR and the top surface 130 of the first ILD layer 110 are lower in height than the metal features 112 in the contact region CR and the top surface 128 of the first ILD layer 110. In some embodiments, the height of the top surface (surface 132) of the second ILD layer 120 in the z-direction may move along the x-direction from the contact region CR all the way down to at or near the center of the fuse region FR. In some embodiments, the height of the top surface (surface 132) of the second ILD layer 120 may decrease gradually or continuously as shown.

As shown in fig. 2B, the fuse element 106 may conform to the top surface (surface 132) of the second ILD layer 120. Accordingly, the fuse element 106 may be formed on the bottom surface (surface 132) of the convex surface contacting the top surface (surface 132) of the concave surface of the second ILD layer 120 in the fuse region FR. In some embodiments, the top surface 134 of the fuse element 106 in the fuse region FR may be higher than the top surface of the fuse element 106 in the contact region CR. In such embodiments, the height of the top surface 134 in the z-direction may increase continuously such that the thickness T3 of the fuse element 106 may be greatest near the center of the fuse element 106 along the x-direction. In some embodiments, the fuse element 106 may be symmetrical in each direction. In some other embodiments, the top surface 134 of the fuse element 106 may be planar in the x-y plane due to the CMP process applied thereto. However, it should be understood that the thickness T3 may still exceed the thickness T4 in the contact region CR of the semiconductor structure 200 and the thickness T1 in the fuse region FR of the semiconductor structure 100.

Fig. 3 is a flow chart illustrating a method 300 for fabricating the semiconductor structure 200 according to an embodiment of the present disclosure. Fig. 4A-4D are cross-sectional views of the semiconductor structure of fig. 2B at various stages during fabrication. Referring also to fig. 3 and 4A, the method 300 begins at block 302, where the semiconductor substrate is provided at block 302. In some embodiments, the semiconductor substrate may be formed prior to forming the base layer 102. In such embodiments, the semiconductor substrate may be disposed below the base layer 102. At block 304, the method 300 proceeds to forming a first thin layer 102 (thin layer Mx-1, also referred to as base layer 102) on the semiconductor substrate, the first thin layer having a first metal line 112 (also referred to as metal feature 112) in contact with the contact pad 108 in the contact region CR and having a dummy pattern metal feature in the fuse region FR. When the duty ratio of the dummy pattern metal feature inserted in the fuse region is greater than the duty ratio of the metal feature 112 in the contact region (as shown in fig. 2B), the first thin layer has a first height H1 in a first region CR (also referred to as a contact region CR) and a second height H2 smaller than the first height H1 in a second region FR (also referred to as a fuse region FR), wherein the first height H1 and the second height H2 are measured in the z-direction. The relative height difference (H1-H2)/H1 may range from about 25% to about 35%. When the dummy pattern metal features inserted into the fuse region have the same loading ratio as the metal features 112 in the contact region (as shown in fig. 1B), the first height H1 and the second height H2 may be approximately equal to each other.

Block 304 of method 300 may include various sub-steps, including blocks 304a through 304 d. At block 304a, the method 300 proceeds to provide a design layout including first metal features 112 (also referred to as metal features 112) in the first region CR, the first metal features 112 having a first pattern density. At block 304b, the method 300 proceeds to modify the design layout by adding dummy pattern metal features 126 into the second region FR, wherein the dummy pattern metal features 126 have a second pattern density that is greater than the first pattern density. At block 304c, the method 300 proceeds to form the first thin layer 102 according to the modified design layout, including depositing the first metal feature 112 and the dummy pattern metal feature 126 in the first dielectric layer 110 (also referred to as the first ILD layer 110). The first thin layer 102 includes a flat top surface 128. As shown in fig. 4A, the flat top surface 128 is marked by dashed lines. In some embodiments, in the semiconductor structure 200, the first dielectric layer 110 may be deposited on underlying thin layers, such as one or more semiconductor substrates, contact etch stop layers, interlayer dielectric layers, conductive layers, and interconnect layers. In some embodiments, the first dielectric layer 110 may be bulk (bulk) deposited, followed by patterning and etching to form one or more contact trenches in the contact region CR and one or more dummy trenches in the fuse region FR. Thereafter, the first metal feature 112 may be deposited in the contact trench and the dummy pattern metal feature 126 may be deposited in the dummy trench using PVD, CVD, ALD, electroplating, ELD, or other suitable deposition process, or a combination thereof. In some embodiments, the planar top surface 128 may be formed by performing a CMP operation after depositing the first metal features 112 and the dummy pattern metal features 126.

At block 304d, the method 300 proceeds to perform a CMP process on the first layer to dig into the top surface 128 of the first layer in the second region FR, and the dug top surface 130 is formed by causing a dishing effect at block 304 d. In some embodiments, the parameters of the CMP process may be selected to increase the dishing effect in the second region FR relative to the first region CR. In some embodiments, each step of CMP may use a different CMP process with different process parameters, including one or more of the following: different turntable (turn table) rotation speeds, top ring (top ring) rotation speeds, head down force (or substrate-to-pad) force), slurry (slurry) composition, slurry pH, slurry additives, slurry selectivity, temperature, and polishing time. In some embodiments, the slurry may be an oxidizing slurry that includes an oxidizing agent to oxidize material on the surface to be removed. In some embodiments, the oxidizing agent may include hydrogen peroxide. In some embodiments, the slurry may have an acidic pH (pH < 7) to selectively remove acid soluble components. In some other embodiments, the slurry may have an alkaline pH (pH > 7) to selectively remove alkali soluble (base soluble) components. In some other embodiments, the slurry may have a neutral pH (pH 7). In some embodiments, the slurry may include additives such as one or more of silica, surfactants, and metal corrosion inhibitors. In some embodiments, the paste may selectively remove material in the fuse region FR relative to the contact region CR. In some embodiments, the dummy pattern metal features 126 may be dug into a second height H2 that is less than the first height H1.

Referring also to fig. 3 and 4B, at block 306, the method 300 proceeds to form a second thin layer (layer Vx) on the first thin layer 102, the second thin layer including a second dielectric layer 120 (also referred to as a second ILD layer 120) conforming to the top surface 130 into which the first thin layer 102 is dug. In some embodiments, the second dielectric layer 120 may be conformably deposited on the top surface 130 such that the contour of the dug-in top surface 130 is transferred to the top surface (surface 132) of the second dielectric layer 120. In some embodiments, the etch stop layer 114 may be deposited prior to forming the second dielectric layer 120. In such embodiments, the etch stop layer 114 may be conformally deposited on the dug-in top surface 130.

Referring also to fig. 3 and 4C, at block 308, the method 300 proceeds to form first vias 122 (also referred to as vias 122) in contact with the first metal features 112 in the first region CR, wherein each of the first vias 122 is in electrical contact with a corresponding first metal feature 112 and further in electrical contact with the overlying fuse element 106. In some embodiments, the second dielectric layer 120 may be patterned and etched to form one or more via trenches in the contact region CR. Thereafter, a conductive material may be deposited on the second dielectric layer 120 to fill the via trench to form the first via 122. In some embodiments, the conductive material may be deposited using PVD, CVD, ALD, electroplating, ELD, or other suitable deposition process or combination thereof. Thereafter, a CMP process may be applied to remove excess conductive material and re-expose the top surface (surface 132) of the second dielectric layer 120.

Referring also to fig. 3 and 4D, at block 310, the method 300 proceeds to form the fuse element 106 (thin layer Mx) on the second thin layer, the fuse element 106 having a first thickness T4 in the first region CR and a second thickness T3 greater than the first thickness T4 in the second region FR. In some embodiments, the relative difference between thickness T3 and thickness T4 is expressed as (T3-T4)/T4, which may be between about 20%And about 30%. In some embodiments, the fuse element 106 may be made of a material such as copper or other suitable metal, or a material such as nickel silicide (NiSi), titanium silicide (TiSi)₂) Cobalt silicide (CoSi)_x) Platinum silicide (PtSi)₂) Other suitable metal silicides, or combinations thereof. In some embodiments, the fuse element 106 may be deposited using PVD, CVD, ALD, electroplating, ELD, or other suitable deposition process, or combinations thereof. Thereafter, a CMP process may be applied to the top surface 134 of the fuse element 106 to planarize the top surface 134.

Various embodiments described herein have advantages in implementation of electronic fuses. The increased thickness of the fuse element 106, such as the thickness T3 or in some other embodiments the thickness T1, provides a greater current density at the same program voltage (program voltage) than a conventional thinner fuse element. Therefore, the semiconductor structures 100 and 200 designed with larger current density using the same voltage without increasing power consumption can make the fuse element 106 easier to blow or burn out in current layout. In some embodiments, the fuse element 106 in the semiconductor structure 200 may burn out at a lower program voltage than the fuse element 106 in the semiconductor structure 100. Likewise, the fuse element 106 in the semiconductor structure 100 may burn out at a lower program voltage than a conventional thinner fuse element.

In one exemplary aspect, the present disclosure provides a semiconductor structure comprising an Mx-1 layer (first thin layer) comprising a first dielectric layer and a plurality of first metal features, wherein the first metal features comprise a first set of first metal features in a first region and comprise a second set of first metal features in a second region, wherein the first set of first metal features has a first pattern density and the second set of first metal features has a second pattern density, the second pattern density being greater than the first pattern density. The semiconductor structure further includes a Vx layer (second thin layer) disposed on the Mx-1 layer, the Vx layer including a plurality of first vias contacting the first set of first metal features. The semiconductor structure further includes an Mx layer (third thin layer) disposed on the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region that is less than a second thickness of the fuse element in the second region.

In one or more embodiments, the Mx-1 layer further includes a third set of first metal features in the third region, wherein the first set of first metal features, the second set of first metal features, and the third set of first metal features are aligned along the first direction, and the first region and the third region are interleaved by the second region along the first direction. In one or more embodiments, the Vx layer further includes a plurality of second vias that contact the third set of first metal features. In one or more embodiments, the fuse element extends longitudinally in a first direction, and wherein the fuse element contacts each of the first via and the second via. In one or more embodiments, the fuse element has a first width in the first region and a third region along a second direction perpendicular to the first direction, and the first width is greater than a second width in the second region. In one or more embodiments, each first metal feature of the first set of first metal features has a first width in the first direction, and each first metal feature of the second set of first metal features has a second width in the first direction that is greater than the first width. In one or more embodiments, the first set of first metal features has a first loading ratio and the second set of first metal features has a second loading ratio that is greater than the first loading ratio.

In another exemplary aspect, the present disclosure provides a method of forming a semiconductor structure. The forming method comprises providing a semiconductor substrate; forming a first thin layer on the semiconductor substrate, comprising: forming a first dielectric layer; depositing a plurality of first metal features having a first pattern density in a first region; depositing a plurality of dummy pattern metal features having a second pattern density in the second area, wherein the second pattern density is greater than the first pattern density; and performing a chemical mechanical polishing process on the first thin layer to dig into a top surface of the previous thin layer in the second region such that a first height of the first thin layer in the first region is greater than a second height of the first thin layer in the second region; and forming a fuse element on the first thin layer, the fuse element including a first thickness in the first region, the first thickness being less than a second thickness in the second region.

In one or more embodiments, the method further includes forming a second layer over the first layer, the second layer including a second dielectric layer conforming to a top surface into which the first layer is dug. In one or more embodiments, the forming method further includes forming the fuse element on the second thin layer, the fuse element conforming to a top surface of the second thin layer. In one or more embodiments, the method further includes forming a plurality of first vias contacting the first metal features in the first region, wherein each of the first vias is in electrical contact with a corresponding one of the first metal features. In one or more embodiments, the forming method further includes: providing a design layout including a first metal feature in a first region and the fuse element on the first metal feature; and modifying the design layout by adding dummy pattern metal features in the second region. In one or more embodiments, the method further includes forming the first thin layer according to the modified design layout. In one or more embodiments, the performing of the chemical mechanical polishing further comprises causing a first dishing effect in the first region, the first dishing effect being smaller than a second dishing effect in the second region. In one or more embodiments, the performing of the chemical mechanical polishing further comprises applying a slurry having a first removal rate in the first region that is less than a second removal rate in the second region. In one or more embodiments, the method further includes patterning and etching the first dielectric layer to form a plurality of first trenches having a first width in the first region and a plurality of second trenches having a second width in the second region, wherein the second width is greater than the first width.

Yet another exemplary aspect of the present disclosure provides a semiconductor structure, including a semiconductor substrate; a fuse region formed on the semiconductor substrate, the fuse region including a plurality of dummy pattern metal features having a first pattern density; a contact region formed on the semiconductor substrate adjacent to the fuse region, the contact region including a plurality of metal features having a second pattern density, wherein the second pattern density is less than the first pattern density; and a fuse element formed in the fuse region and the contact region, wherein a first thickness of the fuse element in the fuse region is greater than a second thickness of the fuse element in the contact region.

In one or more embodiments, the semiconductor structure further includes a plurality of vias disposed between the metal features and the fuse element, each of the vias being in electrical contact with one of the metal features. In one or more embodiments, the fuse region has a first duty ratio and the contact region has a second duty ratio that is less than the first duty ratio. In one or more embodiments, a bottom surface of the fuse element in the fuse region is convex.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.