阅读说明：本技术 封装结构及其制作方法 (Packaging structure and manufacturing method thereof ) 是由 陈明发 吴念芳 叶松峯 刘醇鸿 史朝文 于 2020-09-24 设计创作，主要内容包括：一种包括堆叠衬底、第一半导体管芯、第二半导体管芯及绝缘包封体的封装结构。所述第一半导体管芯设置在所述堆叠衬底之上。所述第二半导体管芯堆叠在所述第一半导体管芯之上。所述绝缘包封体包括包封所述第一半导体管芯的第一包封体部分及包封所述第二半导体管芯的第二包封体部分。(A package structure includes a stacked substrate, a first semiconductor die, a second semiconductor die, and an insulating encapsulant. The first semiconductor die is disposed over the stacked substrate. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulant includes a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die.)

1. A package structure, comprising:

stacking the substrates;

a first semiconductor die disposed over the stacked substrate;

a second semiconductor die stacked over the first semiconductor die; and

an insulating encapsulant comprising a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die.

Technical Field

The application relates to a packaging structure and a manufacturing method thereof.

Background

The semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density is derived from a concomitant reduction in minimum feature size (minimum feature size), which enables more components to be integrated into a given area. With the recent increase in demand for miniaturization, higher speed, greater bandwidth, lower power consumption, and less delay, the need for smaller and more inventive semiconductor die packaging techniques has also increased. Currently, System-on-Integrated-Chip (SoIC) devices are becoming increasingly popular for their versatility and compactness. However, there are many challenges associated with the packaging process of SoIC components.

Disclosure of Invention

According to some embodiments of the present disclosure, a structure is provided that includes a stacked substrate, a first semiconductor die, a second semiconductor die, and an insulating encapsulant. The first semiconductor die is disposed over the stacked substrate. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulant includes a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die.

In accordance with some other embodiments of the present disclosure, a structure is provided that includes a support substrate, a first semiconductor die, a second semiconductor die, a metal layer, and an insulating encapsulant. The first semiconductor die is disposed over a first surface of the support substrate. The second semiconductor die is disposed over the first semiconductor die. The metal layer is disposed over a second surface of the support substrate, and the first surface is opposite the second surface. The insulating encapsulant includes a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die.

According to some other embodiments of the present disclosure, there is provided a method comprising the following steps. Bonding a first semiconductor die to a carrier, wherein the first semiconductor die are spaced apart from each other and a front surface of the first semiconductor die faces the carrier. A first encapsulant portion is formed over the carrier to encapsulate the first semiconductor die in a lateral direction. Removing the carrier from the front surface of the first semiconductor die and the first encapsulant portion. A bonding layer is formed on the front surface of the first semiconductor die and the first encapsulant portion. Bonding a second semiconductor die to the bonding layer, wherein a front surface of the second semiconductor die faces the bonding layer. A second encapsulant portion is formed over the bonding layer to encapsulate the second semiconductor die in a lateral direction. After forming the first encapsulant portion over the carrier to laterally encapsulate the first semiconductor die, a support substrate is bonded to a back surface of the first semiconductor die and the first encapsulant portion.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-10 are cross-sectional views that schematically illustrate a process flow for fabricating an SoIC assembly, in accordance with some embodiments of the present disclosure.

Fig. 11 is a cross-sectional view schematically illustrating a package structure according to some alternative embodiments of the present disclosure.

Fig. 12 and 13 are cross-sectional views schematically illustrating a process flow for fabricating an SoIC assembly according to other embodiments of the present disclosure.

Fig. 14 and 15 are cross-sectional views that schematically illustrate process flows for fabricating SoIC assemblies, in accordance with further embodiments of the present disclosure.

Fig. 16-21 are cross-sectional views that schematically illustrate a process flow for fabricating an SoIC assembly, in accordance with some alternative embodiments of the present disclosure.

Figure 22 is a cross-sectional view that schematically illustrates another SoIC assembly, in accordance with some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may, for example, include test pads (test pads) formed in a redistribution layer or on a substrate to enable testing of a 3D package or 3DIC, use of a probe and/or a probe card (probe card), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. In addition, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce cost.

Fig. 1-10 are cross-sectional views that schematically illustrate a process flow for fabricating an SoIC assembly, in accordance with some embodiments of the present disclosure.

Referring to fig. 1, a semiconductor carrier C1 is provided, and semiconductor carrier C1 includes a bonding layer B formed on a surface thereof. The semiconductor carrier C1 may be a semiconductor wafer, and the bonding layer B may be a bonding layer ready for fusion bonding (fusion bond). In some embodiments, bonding layer B is a deposited layer formed over the top surface of semiconductor carrier C1. In some alternative embodiments, bonding layer B is part of semiconductor carrier C1 for fusion bonding. For example, the material of the semiconductor carrier C1 includes silicon (Si) or other suitable semiconductor material, and the material of the bonding layer B includes silicon (Si), silicon dioxide (SiO)₂) Or other suitable bonding material. In some other embodiments, the bonding layer B is a native oxide layer that is naturally grown on the surface of the semiconductor carrier C1.

A semiconductor die 100 (e.g., a logic die) is provided and placed on the top surface of the bonding layer B. Each of the semiconductor dies 100 may include an active surface 100a (i.e., a front surface) and a back surface 100b opposite the active surface 100a, respectively. Each of the semiconductor dies 100 may include a bonding portion 102, respectively. The semiconductor die 100 is placed on the top surface of the bonding layer B such that the active surface 100a of the semiconductor die 100 faces the bonding layer B and the bonding portion 102 of the semiconductor die 100 is in contact with the top surface of the bonding layer B. The semiconductor dies 100 may be placed on the bonding layer B in a side-by-side manner such that the semiconductor dies 100 are spaced apart from each other. In some embodiments, the material of the bonding portion 102 includes silicon (Si), silicon dioxide (SiO)₂) Or other suitable bonding material.

After the semiconductor die 100 is picked up and placed on the bonding layer B, a chip-to-wafer fusion bonding process may be performed such that a fusion bonding interface is formed between the bonding layer B and the bonding portion 102 of the semiconductor die 100. For example, for bondingThe fusion bonding process of the bonding layer B to the bonding portion 102 of the semiconductor die 100 is performed at a temperature in a range from about 250 degrees celsius to about 400 degrees celsius. The bonding layer B may be bonded directly to the bonding portion 102 of the semiconductor die 100. In other words, no intermediate layer is formed between the bonding layer B and the bonding portion 102 of the semiconductor die 100. The above-described fusion bonding interface formed between bonding layer B and bonding portion 102 of semiconductor die 100 may be or include a Si-Si fusion bonding interface, Si-SiO₂Melt bonding interface, SiO₂-SiO₂A melt bond interface or other suitable melt bond interface.

Referring to fig. 1 and 2, after the semiconductor die 100 is bonded to the bonding layer B, an insulating material is formed to cover the bonding layer B and the semiconductor die 100. In some embodiments, the insulating material is formed by an over-molding process such that the back surface 100b and side surfaces of the semiconductor die 100 (shown in fig. 1) are covered by the insulating material. After performing the overmolding process, a grinding process may be performed to reduce the thickness of the insulating material and the thickness of the semiconductor die 100 (shown in fig. 1) such that the semiconductor die 100' and the first encapsulant portion 110 having the reduced thickness are formed over the bonding layer B. In some embodiments, the grinding process used to reduce the thickness of the insulating material and the thickness of semiconductor die 100 (shown in fig. 1) includes a mechanical grinding process, a Chemical Mechanical Polishing (CMP) process, or a combination thereof.

As shown in fig. 2, in some embodiments, the thickness of the semiconductor die 100 'is equal to the thickness of the first encapsulant portion 110, and the semiconductor die 100' is encapsulated by the first encapsulant portion 110 in a lateral direction. In other words, the first encapsulant portion 110 contacts only the side surfaces of the semiconductor die 100 ', and the rear surface 100b ' of the semiconductor die 100 ' is exposed by the first encapsulant portion 110. In some alternative embodiments not shown in fig. 2, the thickness of the semiconductor die is slightly less than or slightly greater than the thickness of the first encapsulant portion due to the polishing selectivity of the grinding process. In other words, the top surface of the first encapsulant portion may be slightly above or below the back surface of the semiconductor die.

Referring to fig. 3, in some embodiments, an alignment mark 120 is formed over the back surface 100b 'of the semiconductor die 100'. In some alternative embodiments, alignment marks are formed over the top surface of the first enclosure portion. The number, shape and position of the alignment marks 120 are not limited in the present invention. The alignment marks 120 may be formed by deposition, photolithography, and etching processes. In some embodiments, a metallic material is deposited over the back surface 100b 'of the semiconductor die 100' and the top surface of the first encapsulant portion 110, and then the deposited metallic material is patterned by, for example, a photolithography process followed by an etching process.

After forming the alignment mark 120, a bonding layer 130 may be formed over the rear surface 100b 'of the semiconductor die 100' and the top surface of the first encapsulant portion 110 such that the alignment mark 120 is covered by the bonding layer 130. The bonding layer 130 may be formed by a Chemical Vapor Deposition (CVD) process or other suitable deposition process. The bonding layer 130 may be a bonding layer to be fusion bonded, and the material of the bonding layer 130 may include silicon (Si), silicon dioxide (SiO), and the like₂) Or other suitable bonding material. In some embodiments, bonding layer 130 has a flat top surface.

Referring to fig. 4, after the alignment mark 120 and the bonding layer 130 are formed, a support substrate 140 for warpage control is provided and placed over the bonding layer 130. The support substrate 140 is aligned with the resulting structure shown in fig. 3 using the alignment marks 120. The thickness of the support substrate 140 may range from about 750 microns to about 800 microns. For example, as shown in fig. 4, the support substrate 140 is a semiconductor wafer (e.g., a silicon wafer), and the thickness of the support substrate 140 is about 775 microns. In some embodiments, a wafer-to-wafer fusion bonding process is performed such that a fusion bonding interface is formed between the support substrate 140 and the bonding layer 130. For example, the fusion bonding process for bonding the support substrate 140 and the bonding layer 130 is performed at a temperature ranging from about 250 degrees celsius to about 400 degrees celsius. The support substrate 140 may be directly bonded to the bondLayer 130. In other words, no intermediate layer is formed between the support substrate 140 and the bonding layer 130. In some alternative embodiments not shown in fig. 4, the support substrate is formed with a dielectric bonding layer (e.g., SiO) formed thereon₂Layer) of a semiconductor wafer (e.g., a silicon wafer). In addition, the fusion bonding interface formed between the support substrate 140 and the bonding layer 130 may be a Si-Si fusion bonding interface, Si-SiO₂Melt bonding interface, SiO₂-SiO₂A melt bond interface or other suitable melt bond interface.

Referring to fig. 4 and 5, after bonding the support substrate 140 and the bonding layer 130, a peeling or removal process may be performed such that the bonding layer B and the semiconductor carrier C1 are peeled off from the semiconductor die 100' and the first encapsulant portion 110. The lift-off process may be a laser lift-off process or other suitable removal process. After the bonding layer B and the semiconductor carrier C1 are removed, the active surface 100a of the semiconductor die 100' and the surface of the first encapsulant portion 110 are exposed.

After the bonding layer B and the semiconductor carrier C1 are removed, the structure peeled off from the bonding layer B and the semiconductor carrier C1 is turned upside down so that the active surface 100a of the semiconductor die 100' and the exposed surface of the first encapsulant portion 110 may face upward. A bonding structure 150 is then formed over the active surface 100a of the semiconductor die 100' and the exposed surface of the first encapsulant portion 110. The bonding structure 150 may include a dielectric layer 150a and conductors 150b, each conductor 150b penetrating the dielectric layer 150 a. The material of the dielectric layer 150a may be silicon oxide (SiO)_xWherein x is>0) Silicon nitride (SiN)_xWherein x is>0) Silicon oxynitride (SiO)_xN_yWherein x is>0 and y>0) Or other suitable dielectric material, and conductor 150b may be a via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding layer 150 may be formed by: depositing a dielectric material by a Chemical Vapor Deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable deposition process); patterning the dielectric material to form a dielectric layer 150a including openings or through-holes; and filling the openings or through holes defined in the dielectric layer 150a with a conductive materialAnd then removed to form a conductor 150b embedded in the dielectric layer 150 a.

Referring to fig. 6, a semiconductor die 160 (e.g., a memory die) is provided and placed on some portion of the bonding structure 150. In some embodiments, each of the semiconductor dies 160 is placed over a respective one of the semiconductor dies 100. Each of semiconductor die 160 may include a semiconductor substrate 162, an interconnect structure 164 disposed on semiconductor substrate 162, a bonding structure 166 disposed on interconnect structure 164 and electrically connected to interconnect structure 164, and a semiconductor via 168 formed in semiconductor substrate 162. Semiconductor die 160 is placed on bonding structure 150 such that bonding structure 166 of semiconductor die 160 is in contact with some portion of bonding structure 150. Semiconductor die 160 may be placed on bonding structure 150 in a side-by-side manner such that semiconductor die 160 are spaced apart from each other. Bonding structure 166 may include a dielectric layer 166a and conductors 166b, each conductor 166b penetrating through dielectric layer 166 a. The material of the dielectric layer 166a may be silicon oxide (SiO)_xWherein x is>0) Silicon nitride (SiN)_xWherein x is>0) Silicon oxynitride (SiO)_xN_yWherein x is>0 and y>0) Or other suitable dielectric material, and conductor 166b may be a via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof.

Conductor 166b of bonding structure 166 is aligned with conductor 150b of bonding structure 150 and sub-micron alignment accuracy between semiconductor die 160 and bonding structure 150 may be achieved. Once bonding structures 166 of semiconductor die 160 are precisely aligned with bonding structures 150, wafer-to-wafer Hybrid bonding (Hybrid bonding) is performed such that semiconductor die 160 is Hybrid bonded to bonding structures 150.

In some embodiments, to facilitate wafer-to-wafer hybrid bonding between bonding structure 150 and bonding structures 166 of semiconductor die 160, surface preparation (surface preparation) of bonding structures 166 and the bonding surfaces of bonding structures 150 is performed. Surface preparation may include, for example, surface cleaning and activation. Surface cleaning may be performed on the bonding surfaces of bonding structures 166 and 150 to remove particles on the bonding surfaces of conductor 150b, dielectric layer 150a, conductor 166b, and dielectric layer 166 a. The bonding structures 166 and the bonding surfaces of the bonding structures 150 are cleaned by, for example, wet cleaning. Not only the particles but also the native oxide formed on the bonding surfaces of the conductor 150b and the conductor 166b can be removed. Native oxide formed on the bonding surfaces of conductors 150b and 166b may be removed by the chemicals used in the wet clean.

After cleaning the bonding surfaces of bonding structure 166 and bonding structure 150, activation of the top surfaces of dielectric layer 150a and dielectric layer 166a may be performed to form a high bonding strength. In some embodiments, plasma activation is performed to treat the bonding surfaces of the dielectric layer 150a and the dielectric layer 166 a.

Dielectric layer 150a of bonding structure 150 and dielectric layer 166a of semiconductor die 160 are pre-bonded while the activated bonding surface of dielectric layer 150a is in contact with the activated bonding surface of dielectric layer 166 a. Semiconductor die 160 is pre-bonded to bonding structure 150 by pre-bonding dielectric layer 150a to dielectric layer 166 a. After pre-bonding dielectric layer 150a and dielectric layer 166a, conductor 150b is contacted with conductor 166 b.

After pre-bonding dielectric layer 150a and dielectric layer 166a, hybrid bonding of semiconductor die 160 and bonding structure 150 is performed. Hybrid bonding of semiconductor die 160 and bonding structure 150 may include processing for dielectric bonding and thermal annealing for conductor bonding. A process for dielectric bonding is performed to strengthen the bond between dielectric layer 150a and dielectric layer 166 a. The processing for dielectric bonding may be performed at a temperature, for example, in a range from about 100 degrees celsius to about 150 degrees celsius. After the process for dielectric bonding is performed, thermal annealing for conductor bonding is performed to promote bonding between the conductors 150b and 166 b. The thermal anneal for the conductor bond may be performed at a temperature, for example, in a range from about 300 degrees celsius to about 400 degrees celsius. The process temperature for the thermal annealing of the conductor bond is higher than the process temperature for the treatment of the dielectric bond. Since the thermal annealing for conductor bonding is performed at a relatively high temperature, metal diffusion and crystal growth may occur at the bonding interface between the conductor 150b and the conductor 166 b. After performing the thermal anneal for conductor bonding, dielectric layer 150a is bonded to dielectric layer 166a and conductor 150b is bonded to conductor 166 b. The conductor bond between conductor 150b and conductor 166b may be a via-to-via bond, a pad-to-pad bond, or a via-to-pad bond.

Referring to fig. 6 and 7, after semiconductor die 160 is bonded to bonding structure 150, an insulating material is formed to cover bonding structure 150 and semiconductor die 160. In some embodiments, the insulating material is formed by an overmolding process such that the back and side surfaces of the semiconductor die 160 (shown in fig. 6) are covered by the insulating material. After performing the overmolding process, a grinding process may be performed to reduce the thickness of the insulating material and the thickness of the semiconductor die 160 (shown in fig. 6) such that a semiconductor die 160' and a second encapsulant portion 170 having a reduced thickness are formed over the bonding structure 150. After the grinding process is performed, the semiconductor substrate 162 'having a reduced thickness is formed, and the semiconductor via 168 is exposed from the rear surface of the semiconductor substrate 162'. In some embodiments, the grinding process used to reduce the thickness of the insulating material and the thickness of semiconductor die 160 (shown in fig. 6) includes a mechanical grinding process, a Chemical Mechanical Polishing (CMP) process, or a combination thereof.

As shown in fig. 7, in some embodiments, the thickness of the semiconductor die 160 'is equal to the thickness of the second encapsulant portion 170, and the semiconductor die 160' is encapsulated by the second encapsulant portion 170 in the lateral direction. In other words, the second encapsulant portion 170 contacts only the side surfaces of the semiconductor die 160 ', and the back surface of the semiconductor die 160' may be exposed through the second encapsulant portion 170. In some alternative embodiments not shown in fig. 7, the thickness of the semiconductor die is slightly less than or slightly greater than the thickness of the second encapsulant portion due to the polishing selectivity of the grinding process. In other words, the top surface of the second encapsulant portion may be slightly above or below the back surface of the semiconductor die.

A Through Insulator Via (TIV) 172 is formed in the second encapsulant portion 170. The insulator perforations 172 are electrically connected to the portions of the conductors 150b not covered by the semiconductor die 160'. Second encapsulant portion 170 may be patterned by a laser drilling process, a photolithography process, followed by an etching process, or other suitable patterning process to form perforations in second encapsulant portion 170, and a conductive material may be filled in the perforations to form insulator perforations 172. In some embodiments, after the perforations are formed in second encapsulant portion 170, insulator perforations 172 are formed by depositing a conductive material followed by a chemical mechanical polishing process. For example, a metallic material (e.g., copper) is deposited over the semiconductor die 160 'and the second encapsulant portion 170 to fill the perforations defined in the second encapsulant portion 170, and then the metallic material is polished by a chemical-mechanical polishing process until the semiconductor die 160' and the second encapsulant portion 170 are exposed.

Referring to fig. 8, a redistribution layer 174 is formed on the back surfaces of the semiconductor die 160' and the second encapsulant portion 170. The redistribution routing layer 174 may be electrically connected to the semiconductor die 100' through the insulator vias 172. Redistribution layer 174 may be electrically connected to semiconductor vias 168 in semiconductor die 160'. A passivation layer 176 may be formed on the back surfaces of the semiconductor die 160' and the second encapsulant portion 170 to cover the redistribution routing layer 174. After the redistribution layer 174 and the passivation layer 176 are formed, structure D is fabricated.

Referring to fig. 9, structure D is flipped upside down and transfer bonded to semiconductor carrier C2 such that passivation layer 176 is in contact with semiconductor carrier C2. A bonding layer 180 is formed on a surface of the support substrate 140 of the structure D carried by the semiconductor carrier C2. Bonding layer 180 may be a deposited bonding layer ready for fusion bonding. For example, the material of the bonding layer 180 includes silicon dioxide (SiO)₂) Or other suitable bonding material.

After the bonding layer 180 is formed, a support substrate 182 for warp control is provided and placed on the bonding layer 180. The thickness of the support substrate 182 may range from about 750 microns to about 800 microns. For example, as shown in fig. 9, the support substrate 182 is a semiconductor wafer (e.g., a silicon wafer), and the thickness of the support substrate 182 is about 775 microns. In some embodiments, wafer-to-wafer fusion is performedThe bonding process results in a fusion bonded interface being formed between the support substrate 182 and the bonding layer 180. For example, the fusion bonding process for bonding the support substrate 182 and the bonding layer 180 is performed at a temperature in a range from about 250 degrees celsius to about 300 degrees celsius. The support substrate 182 may be directly bonded to the bonding layer 180. In other words, no intermediate layer is formed between the bonding layer 180 and the support substrate 182. In some alternative embodiments not shown in fig. 9, the support substrate is formed with a dielectric bonding layer (e.g., SiO) formed thereon₂Layer) of a semiconductor wafer (e.g., a silicon wafer). In addition, the fusion bonding interface formed between the support substrate 182 and the bonding layer 180 may be Si — SiO₂Melt bonding interface, SiO₂-SiO₂A melt bond interface or other suitable melt bond interface.

After performing the fusion bonding process of the support substrate 182 and the bonding layer 180, a backside metal layer 184 may be formed over the surface of the support substrate 182. In other words, the backside metal layer 184 is formed over the surfaces of the stacked substrates 140 and 182. For example, the thickness of the backside metal layer 184 is in a range from about 10 microns to about 1000 microns to provide suitable warpage control capability. A backside metal layer 184 is disposed over a surface of the stacked substrates 140 and 182 and a semiconductor die 100' is disposed over another surface of the stacked substrates 140 and 182. In other words, backside metal layer 184 and semiconductor die 100' are disposed on opposite sides of stacked substrates 140 and 182. In some embodiments, the backside metal layer 184 may comprise a multi-layered structure metal structure. For example, the backside metal layer 184 may include an aluminum (Al) layer formed on the surface of the support substrate 182, a titanium (Ti) layer formed on the Al layer, a NiV layer formed on the Ti layer, an Au layer formed on the NiV layer, a copper (Cu) layer formed on the Au layer, and an Ni layer formed on the Cu layer. The thickness of the Al layer may be about 200 microns, the thickness of the Ti layer may be about 100 microns, the thickness of the NiV layer may be about 350 microns, the thickness of the Au layer may be about 100 microns, and the thickness of the Cu layer may range from about 10 microns to about 1000 microns; and the thickness of the Ni layer may range from about 1 micron to about 30 microns.

Referring to fig. 9 and 10, after formation of backside metal layer 184, semiconductor carrier C2 is stripped from structure D such that passivation layer 176 is exposed. The passivation layer 176 is patterned by, for example, a photolithography process followed by an etching process such that the redistribution layer 174 is exposed. Conductive terminals 186 (e.g., conductive bumps) are formed to electrically connect the redistribution layer 174 covered by the passivation layer 176. After forming the conductive terminals 186, a singulation process is performed along the scribe line SL1 to obtain a plurality of singulated SoIC assemblies D1.

Singulated SoIC assembly D1 comprises stacked substrates 140 and 182, semiconductor die 100 ', semiconductor die 160', and an insulating encapsulant comprising first encapsulant portion 110 encapsulating semiconductor die 100 'and second encapsulant portion 170 encapsulating semiconductor die 160'. Semiconductor die 100' is disposed over stacked substrates 140 and 182. Semiconductor die 160 'is stacked over semiconductor die 100'. The support substrate 140 may be bonded to the support substrate 182 by a bonding layer 180, and the SoIC assembly D1 may further include a backside metal layer 284 disposed on the bottom surface of the support substrate 182. In some embodiments, the overall thickness of stacked substrates 140 and 182 is in a range from about 1500 microns to about 1600 microns to provide suitable warpage control capability. As shown in fig. 10, a first encapsulant portion 110 is disposed over the stack substrates 140 and 182, and a second encapsulant portion 170 is disposed over the first encapsulant portion 110 and the semiconductor die 100'. Further, the first encapsulant portion 110 is spaced apart from the second encapsulant portion 170 by a bonding layer 150 located between the semiconductor die 100 'and the semiconductor die 160'.

Support substrate 140 and support substrate 182 having sufficient overall thickness can be used to balance or control warpage of SoIC assembly D1. In addition, the backside metal layer 184 can be used to balance or control the warpage of the SoIC assembly D1.

Fig. 11 is a cross-sectional view schematically illustrating a package structure according to some alternative embodiments of the present disclosure.

Referring to fig. 10 and 11, the package structure 200 includes an interposer 202, an SoIC assembly D1 disposed on the interposer 202 and electrically connected to the interposer 202, a memory stack 204 disposed on the interposer 202 and electrically connected to the interposer 202, an underfill material 206, an insulating encapsulant 208, a circuit substrate 210 having conductive terminals 212, conductive terminals 220, and another underfill material 230. The interposer 202 may be a silicon interposer. The memory stack 204 may be a High Bandwidth Memory (HBM) stack that includes stacked high bandwidth memory dies. The SoIC assembly D1 and the memory stack 204 can be electrically connected to the interposer 202 through micro-bumps encapsulated by the underfill material 206. Insulating encapsulant 208 can encapsulate SoIC component D1, memory stack 204, and underfill material 206. The interposer 202 may be electrically connected to the circuit substrate 210 by conductive terminals 220, such as controlled collapse chip connection (C4) bumps, encapsulated by an underfill material 230. The conductive terminals 212 may be Ball Grid Array (BGA) conductive balls.

In package structure 200, backside metal layer 184 of SoIC component D1, support substrate 140, and support substrate 182 can not only control warpage of SoIC component D1, but can also minimize the thickness difference between SoIC component D1 and memory stack 204. Since the backside metal layer 184, the support substrate 140, and the support substrate 182 can control warpage of the SoIC assembly D1, the yield of the bond between the SoIC assembly D1 and the interposer 202 can be increased.

Fig. 12 and 13 are cross-sectional views schematically illustrating a process flow for fabricating an SoIC assembly according to other embodiments of the present disclosure.

Referring to fig. 8 and 12, after the process shown in fig. 8 is performed, conductive terminals 186 (e.g., conductive bumps) are formed on the structure D such that the conductive terminals 186 are electrically connected to the redistribution layer 174 covered by the passivation layer 176.

Referring to fig. 13, after forming the conductive terminals 186, a backside metal layer 184 is formed over the surface of the support substrate 140. For example, the thickness of the backside metal layer 184 ranges from about 10 microns to about 1000 microns. The backside metal layer 184 and the conductive terminals 186 are disposed on opposite sides of structure D. After the backside metal layer 184 is formed, a singulation process is performed along the scribe line SL2 to obtain a plurality of singulated SoIC assemblies D2.

In fig. 13, SoIC assembly D2 includes a single support substrate 140 and a backside metal layer 184 formed on support substrate 140. Since the supporting substrate 140 and the backside metal layer 184 can control the warpage of the SoIC device D2, the fabrication yield of the SoIC device D2 can be increased.

Fig. 14 and 15 are cross-sectional views that schematically illustrate process flows for fabricating SoIC assemblies, in accordance with further embodiments of the present disclosure.

Referring to fig. 8 and 14, after the process shown in fig. 8 is performed, conductive terminals 186 (e.g., conductive bumps) are formed on the structure D such that the conductive terminals 186 are electrically connected to the redistribution layer 174 covered by the passivation layer 176.

Referring to fig. 15, the structure D is turned upside down, and a bonding layer 180 is formed on a surface of the support substrate 140 of the structure D. Bonding layer 180 may be a deposited bonding layer ready for fusion bonding. For example, the material of the bonding layer 180 includes silicon dioxide (SiO)₂) Or other suitable bonding material. After the bonding layer 180 is formed, a support substrate 182 for warp control is provided and placed over the bonding layer 180. The thickness of the support substrate 182 may range from about 750 microns to about 800 microns. For example, as shown in fig. 15, the support substrate 182 is a semiconductor wafer (e.g., a silicon wafer), and the thickness of the support substrate 182 is about 775 microns. In some embodiments, a wafer-to-wafer fusion bonding process is performed such that a fusion bonded interface is formed between the support substrate 182 and the bonding layer 180. For example, the fusion bonding process for bonding the support substrate 182 and the bonding layer 180 is performed at a temperature in a range from about 250 degrees celsius to about 400 degrees celsius. The support substrate 182 may be directly bonded to the bonding layer 180. In other words, no intermediate layer is formed between the bonding layer 180 and the support substrate 182. In some alternative embodiments not shown in fig. 15, the support substrate is a semiconductor wafer (e.g., a silicon wafer) having a dielectric bonding layer (e.g., a SiO2 layer) formed thereon. Further, the fusion bonding interface formed between the support substrate 182 and the bonding layer 180 may be a Si — SiO2 fusion bonding interface, SiO₂-SiO₂A melt bond interface or other suitable melt bond interface.

After the bonding of the support substrate 182 and the support substrate 140 is performed, a singulation process is performed along the scribe lines SL3 to obtain a plurality of singulated SoIC assemblies D3.

In fig. 15, SoIC assembly D3 includes a plurality of stacked substrates 140 and 182, and the backside metal layers are omitted. The overall thickness of stacked substrates 140 and 182 ranges from about 1500 microns to about 1600 microns. Since the thicknesses of the stacked substrates 140 and 182 are sufficient to control the warpage of the SoIC assembly D3, the fabrication yield of the SoIC assembly D3 can be increased.

Fig. 16-21 are cross-sectional views that schematically illustrate a process flow for fabricating an SoIC assembly, in accordance with some alternative embodiments of the present disclosure.

Referring to fig. 3 and 16 to 20, after the process shown in fig. 3 is performed, the processes shown in fig. 16 to 20 are performed. The process shown in fig. 16 to 20 is similar to that shown in fig. 4 to 8, except that the single support substrate 140' used in the present embodiment is thicker. For example, the thickness of the single support substrate 140' ranges from about 1500 microns to about 1600 microns. As shown in fig. 20, after the redistribution layer 174 and the passivation layer 176 are formed, a structure D' is fabricated.

Referring to fig. 21, conductive terminals 186 (e.g., conductive bumps) are formed on the structure D' such that the conductive terminals 186 are electrically connected to the redistribution layer 174 covered by the passivation layer 176. After forming the conductive terminals 186, a singulation process is performed along the scribe line SL4 to obtain a plurality of singulated SoIC assemblies D4.

Figure 22 is a cross-sectional view that schematically illustrates another SoIC assembly, in accordance with some embodiments of the present disclosure.

Referring to fig. 21 and 22, the structure shown in fig. 22 is similar to that shown in fig. 21 except for a backside metal layer 184 located on the bottom surface of a single support substrate 140'. After the backside metal layer 184 is formed on the bottom surface of the single support substrate 140', a singulation process is performed along the scribe lines SL5 to obtain a plurality of singulated SoIC assemblies D5.

Although the package structure 200 including the SoIC package D1 is shown in fig. 11, other types of SoIC packages (e.g., SoIC package D2, D3, D4, or D5) can also be packaged in the package structure 200 as shown in fig. 11.

According to some embodiments of the present disclosure, a structure is provided that includes a stacked substrate, a first semiconductor die, a second semiconductor die, and an insulating encapsulant. The first semiconductor die is disposed over the stacked substrate. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulant includes a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die. In some embodiments, the overall thickness of the stacked substrate is in a range from about 1500 microns to about 1600 microns. In some embodiments, the first encapsulant portion is disposed over the stacked substrate and the second encapsulant portion is disposed over the first encapsulant portion and the first semiconductor die. In some embodiments, the first encapsulant portion is spaced apart from the second encapsulant portion by a bonding layer between the first semiconductor die and the second semiconductor die. In some embodiments, the structure further includes a backside metal layer disposed over the stacked substrate, wherein the backside metal layer is disposed over a first surface of the stacked substrate, the first semiconductor die is disposed over a second surface of the stacked substrate, and the first surface is opposite the second surface. In some embodiments, the thickness of the backside metal layer is in a range from about 10 microns to about 1000 microns.

In accordance with some other embodiments of the present disclosure, a structure is provided that includes a support substrate, a first semiconductor die, a second semiconductor die, a metal layer, and an insulating encapsulant. The first semiconductor die is disposed over a first surface of the support substrate. The second semiconductor die is disposed over the first semiconductor die. The metal layer is disposed over a second surface of the support substrate, and the first surface is opposite the second surface. The insulating encapsulant includes a first encapsulant portion encapsulating the first semiconductor die and a second encapsulant portion encapsulating the second semiconductor die. In some embodiments, the support substrate has a thickness in a range from about 1500 microns to about 1600 microns. In some embodiments, the first encapsulant portion is disposed on the first surface of the support substrate, and the second encapsulant portion is disposed over the first encapsulant portion and the first semiconductor die to encapsulate the second semiconductor die in a lateral direction. In some embodiments, the first encapsulant portion is spaced apart from the second encapsulant portion by a bonding layer between the first semiconductor die and the second semiconductor die. In some embodiments, the metal layer has a thickness in a range from about 10 microns to about 1000 microns. In some embodiments, the support substrate comprises a single support substrate having a thickness in a range from about 1500 microns to about 1600 microns.

According to some other embodiments of the present disclosure, there is provided a method comprising the following steps. Bonding a first semiconductor die to a carrier, wherein the first semiconductor die are spaced apart from each other and a front surface of the first semiconductor die faces the carrier. A first encapsulant portion is formed over the carrier to encapsulate the first semiconductor die in a lateral direction. Removing the carrier from the front surface of the first semiconductor die and the first encapsulant portion. A bonding layer is formed on the front surface of the first semiconductor die and the first encapsulant portion. Bonding a second semiconductor die to the bonding layer, wherein a front surface of the second semiconductor die faces the bonding layer. A second encapsulant portion is formed over the bonding layer to encapsulate the second semiconductor die in a lateral direction. After forming the first encapsulant portion over the carrier to laterally encapsulate the first semiconductor die, a support substrate is bonded to a back surface of the first semiconductor die and the first encapsulant portion. In some embodiments, the support substrate comprises a single support substrate. In some embodiments, the support substrate is bonded to the back surface of the first semiconductor die and the first encapsulant portion prior to removing the carrier from the front surface of the first semiconductor die and the first encapsulant portion. In some embodiments, the method further comprises: forming a redistribution layer on the back surface of the second semiconductor die and the second encapsulant portion; and forming conductive terminals on the redistribution layer. In some embodiments, the support substrate comprises a first support substrate and a second support substrate bonded to the first support substrate. In some embodiments, the first support substrate is bonded to the back surface of the first semiconductor die and the first encapsulant portion prior to removing the carrier from the front surface of the first semiconductor die and the first encapsulant portion. In some embodiments, the second support substrate is bonded to the first support substrate after the redistribution routing layer is formed over the second semiconductor die and the second encapsulant portion; and the second support substrate is bonded to the back surface of the first semiconductor die and the first encapsulant portion prior to forming the conductive terminals on the redistribution routing layer. In some embodiments, the second support substrate is bonded to the first support substrate after the conductive terminals are formed on the redistribution routing layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[ description of symbols ]

100. 100': semiconductor die

100 a: active surface of semiconductor die

100b, 100 b': rear surface of semiconductor die

102: binding moieties

110: first enclosure portion

120: alignment mark

130: bonding layer

140: supporting substrate

140': supporting substrate

150: combination structure

150 a: dielectric layer

150 b: conductor

160. 160': semiconductor die

162. 162': semiconductor substrate

164: interconnection structure

166: combination structure

166 a: dielectric layer

166 b: conductor

168: semiconductor via

170: second enclosure portion

172: insulator piercing

174: rewiring circuit layer

176: passivation layer

180: bonding layer

182: supporting substrate

184: rear side metal layer

186: conductive terminal

200: packaging structure

202: interposer

204: memory stack

206: underfill material

208: insulating packaging body

210: circuit substrate

212: conductive terminal

220: conductive terminal

230: underfill material

B: bonding layer

C1, C2: semiconductor carrier

D. D': structure of the product

D1, D2, D3, D4, D5: SoIC assembly

SL1, SL2, SL3, SL4, SL 5: cutting path