阅读说明：本技术 半导体装置及半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 三浦正幸 于 2020-01-16 设计创作，主要内容包括：本实施方式涉及一种半导体装置及半导体装置的制造方法。根据一实施方式,于半导体装置中,基板具有主面。控制芯片具有第1正面及第1背面。控制芯片在第1正面与主面对面的状态下介隔多个凸块电极安装在主面。第1间隔片具有第2正面及第2背面。第1间隔片的第2背面安装在主面。第1间隔片的第2正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。第2间隔片具有第3正面及第3背面。第2间隔片的第3背面安装在主面。第2间隔片的第3正面距主面的高度为第1背面距主面的高度的上限与下限之间的范围内。(The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device. According to one embodiment, in a semiconductor device, a substrate has a main surface. The control chip has a1 st front surface and a1 st back surface. The control chip is mounted on the main surface via a plurality of bump electrodes in a state where the 1 st front surface faces the main surface. The No. 1 spacing piece has a No. 2 front surface and a No. 2 back surface. The No. 2 back surface of the No. 1 spacing piece is mounted on the main surface. The height of the 2 nd front surface of the 1 st spacer from the main surface is within a range between the upper limit and the lower limit of the height of the 1 st back surface from the main surface. The No. 2 spacing piece has No. 3 front and No. 3 back. The No. 3 back surface of the No. 2 spacing piece is mounted on the main surface. The height of the 3 rd front surface of the 2 nd spacer from the main surface is within the range between the upper limit and the lower limit of the height of the 1 st back surface from the main surface.)

1. A semiconductor device includes:

a substrate having a1 st terminal on a main surface thereof;

a1 st semiconductor chip having a1 st front surface on which a bump electrode connected to the 1 st terminal is provided, the 1 st front surface having a1 st rear surface opposite to the 1 st front surface, the 1 st front surface facing the main surface;

a1 st spacer having a2 nd front surface and a2 nd back surface opposite to the main surface, the 2 nd front surface having a height from the main surface within a range between an upper limit and a lower limit of the height from the 1 st back surface to the main surface; and

and a2 nd spacer having a 3 rd front surface and a 3 rd back surface opposite to the main surface, wherein the height of the 3 rd front surface from the main surface is within a range between an upper limit and a lower limit of the height of the 1 st back surface from the main surface.

2. The semiconductor device according to claim 1, wherein an area of the 1 st spacer and an area of the 2 nd spacer are substantially equal to each other in a plan view,

the outer edge of the 1 st semiconductor chip has a1 st side and a2 nd side opposite to the 1 st side,

the 1 st spacer is arranged side by side with the 1 st side in a plan view,

the 2 nd spacer is arranged side by side with the 2 nd side in a plan view.

3. The semiconductor device according to claim 1, wherein an area of the 1 st spacer and an area of the 2 nd spacer are substantially equal to each other in a plan view,

the outer edge of the 1 st semiconductor chip has a1 st edge and a2 nd edge intersecting the 1 st edge,

the 1 st spacer is arranged side by side with the 1 st side in a plan view,

the 2 nd spacer is arranged side by side with the 2 nd side in a plan view.

4. The semiconductor device according to any one of claims 1 to 3, wherein a2 nd terminal is further provided on the main surface, and further comprising:

a1 st film provided between the main surface and the 1 st spacer;

a2 nd film provided between the main surface and the 2 nd spacer;

a 3 rd film covering at least the 1 st back surface and the 2 nd front surface;

a2 nd semiconductor chip having a 4 th front surface provided with a1 st pad electrode and a 4 th back surface facing the 3 rd adhesive film; and

a1 st bonding wire connecting the 2 nd terminal and the 1 st pad electrode; and is

The thickness of the 3 rd film is approximately equal to the thickness of the 1 st film, or is greater than the thickness of the 1 st film,

the thickness of the 3 rd film is substantially equal to the thickness of the 2 nd film, or greater than the thickness of the 2 nd film.

5. The semiconductor device according to claim 4, further comprising:

a 4 th film covering the 4 th front surface;

a 3 rd semiconductor chip having a 5 th front surface provided with a2 nd pad electrode and a 5 th back surface facing the 4 th film; and

a2 nd bonding wire connecting the 2 nd terminal with the 2 nd pad electrode; and is

The thickness of the 3 rd film is substantially equal to the thickness of the 4 th film, or greater than the thickness of the 4 th film.

6. A semiconductor device includes:

a substrate having a1 st terminal on a main surface thereof;

a1 st semiconductor chip having a1 st front surface on which a bump electrode connected to the 1 st terminal is provided, the 1 st front surface having a1 st rear surface opposite to the 1 st front surface, the 1 st front surface facing the main surface;

a1 st spacer having a2 nd front surface and a2 nd back surface opposite to the main surface, the 2 nd front surface having a height from the main surface lower than a lower limit of the height from the 1 st back surface to the main surface; and

and a2 nd spacer having a 3 rd front surface and a 3 rd back surface opposite to the main surface, wherein the height of the 3 rd front surface from the main surface is lower than the lower limit of the height of the 1 st back surface from the main surface.

7. The semiconductor device according to claim 6, wherein a2 nd terminal is provided on the main surface, and further comprising:

a film covering at least the 1 st back surface and the 2 nd front surface or the 3 rd front surface;

a2 nd semiconductor chip having a 4 th front surface provided with a pad electrode and a 4 th back surface facing the film; and

and a bonding wire connecting the 2 nd terminal and the pad electrode.

8. A method for manufacturing a semiconductor device includes:

arranging a1 st spacing piece on the main surface of a substrate, and arranging a2 nd spacing piece on the main surface of the substrate; and

after the 1 st and 2 nd spacers are provided,

the 1 st semiconductor chip is provided on the main surface via a plurality of bump electrodes in a state where a front surface of the 1 st semiconductor chip is opposed to the main surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the providing of the 1 st semiconductor chip on the main surface comprises:

disposing the 1 st semiconductor chip on a main surface of the substrate with the front surface of the 1 st semiconductor chip facing the main surface through the plurality of bump electrodes; and

the back surface of the 1 st semiconductor chip is pressed toward the substrate side by a head of a bonding tool.

Technical Field

The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background

In a semiconductor device, a semiconductor chip and a spacer are mounted on a main surface of a substrate, and other plural semiconductor chips are mounted on the spacer, thereby constituting a mounting form of a spacer structure. In this case, it is preferable that the spacer structure is appropriately configured in the mounting form.

Disclosure of Invention

An object of one embodiment is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can appropriately configure a mounting form of a spacer structure.

According to one embodiment, a semiconductor device includes a substrate, a control chip, a1 st spacer, and a2 nd spacer. The substrate has a main surface. The control chip has a1 st front surface and a1 st back surface. The control chip is mounted on the main surface via a plurality of bump electrodes in a state where the 1 st front surface faces the main surface. The No. 1 spacing piece has a No. 2 front surface and a No. 2 back surface. The No. 2 back surface of the No. 1 spacing piece is mounted on the main surface. The height of the 2 nd front surface of the 1 st spacer from the main surface is within a range between the upper limit and the lower limit of the height of the 1 st back surface from the main surface. The No. 2 spacing piece has No. 3 front and No. 3 back. The No. 3 back surface of the No. 2 spacing piece is mounted on the main surface. The height of the 3 rd front surface of the 2 nd spacer from the main surface is within the range between the upper limit and the lower limit of the height of the 1 st back surface from the main surface.

Drawings

Fig. 1 is a sectional view showing a structure of a semiconductor device according to embodiment 1.

Fig. 2 is an enlarged cross-sectional view showing the height of the spacer and the control chip in embodiment 1.

Fig. 3 is an enlarged cross-sectional view showing the height of the spacer and the control chip in embodiment 1.

Fig. 4 is a plan view showing a layout structure of a spacer and a control chip in variation 1 of embodiment 1.

Fig. 5 is a cross-sectional view showing a laminated structure of a spacer, a control chip, and a memory chip in variation 1 of embodiment 1.

Fig. 6 is a plan view showing a layout structure of a spacer and a control chip in variation 2 of embodiment 1.

Fig. 7 is a plan view showing a layout structure of a spacer and a control chip in variation 3 of embodiment 1.

Fig. 8 is a cross-sectional view showing a laminated structure of a spacer, a control chip, and a memory chip in variation 3 of embodiment 1.

Fig. 9 is a cross-sectional view showing a laminated structure of a spacer, a control chip, and a memory chip in variation 4 of embodiment 1.

Fig. 10(a) to (d) are sectional views showing steps of a method for manufacturing a semiconductor device according to embodiment 2.

Fig. 11 is an enlarged cross-sectional view showing the heights of the spacers and the control chip in a modification of embodiment 2.

Fig. 12 is an enlarged cross-sectional view showing the heights of the spacer and the control chip in a modification of embodiment 2.

Detailed Description

Hereinafter, the semiconductor device according to the embodiment will be described in detail with reference to the drawings. The present invention is not limited to these embodiments.

(embodiment 1) the semiconductor device according to embodiment 1 may be configured using a multi-chip module In which a control chip and a plurality of memory chips are mounted In a mixed manner In order to satisfy the requirements of SIP (System In Package). In the multi-chip module structure, the control chip is configured to reduce the chip area in response to the demand for higher speed and lower power consumption, whereas the memory chip is configured to increase the chip area in response to the demand for higher capacity. In the semiconductor device, in accordance with a demand for miniaturization of the package, a spacer structure is adopted in which a difference in area between the control chip and the memory chip is filled with the spacer, and a plurality of chips are stacked one on top of another and arranged in layers.

For example, a control chip is mounted face-up on the surface (main surface) of the substrate having the largest area by wire bonding, a plurality of spacers are mounted on the periphery of the control chip, and a plurality of memory chips are stacked on the control chip and the spacers via an adhesive film and mounted face-up on the substrate by wire bonding. This spacer configuration is referred to as a face-up + face-up spacer configuration.

In the face-up + face-up spacer configuration, a gap space for the bonding wire of the control chip needs to be secured between the control chip and the lowermost memory chip. Therefore, the mounting height from the substrate on which the predetermined number of memory chips are mounted to the uppermost memory chip is likely to be increased.

Alternatively, the control chip is face-down mounted on the main surface of the substrate by flip-chip bonding, and the plurality of spacers are mounted on the periphery thereof, and the plurality of memory chips are stacked on the control chip and the spacers via the adhesive film and face-up mounted on the substrate by wire bonding. This spacer configuration is referred to as a face down + face up spacer configuration.

In the face-down + face-up spacer configuration, no clearance space for the bond wires of the control chip is required between the control chip and the lowermost memory chip. Therefore, the spacer structure of face-down mounting + face-up mounting can reduce the mounting height from the substrate on which a predetermined number of memory chips are mounted to the uppermost memory chip, as compared with the spacer structure of face-up mounting + face-up mounting.

In a face-down mounting + face-up mounting spacer structure semiconductor device, if the control chip is thinned in response to a demand for further miniaturization of the mounting, the control chip may be bent under the influence of thermal deformation or the like at the time of mounting. In this case, if the height difference between the back surface of the control chip on the substrate and the front surface of the spacer is large, the adhesive film to be laminated thereon becomes large in thickness to absorb the height difference, and the mounting height from the substrate to the uppermost memory chip may become high.

In this case, in the semiconductor device having the spacer structure of face-down mounting + face-up mounting, the height of each spacer from the main surface of the substrate is set to fall within the range between the upper limit and the lower limit of the height of the control chip, thereby reducing the thickness of the adhesive film and the mounting height.

Specifically, the semiconductor device 1 may be configured as shown in fig. 1. Fig. 1 is a diagram showing a structure of a semiconductor device 1.

The semiconductor device 1 includes a substrate 10, a control chip 20, a plurality of memory chips 40-1 to 40-8, a sealing resin 50, an external electrode 60, a plurality of spacers 70-1 to 70-2, and a plurality of adhesive films 30-1 to 30-10. Hereinafter, a direction perpendicular to one of the surfaces (the front surface 10a, the 1 st main surface) of the substrate 10 having the largest area is referred to as a Z direction, and 2 directions orthogonal to each other in a plane perpendicular to the Z direction are referred to as an X direction and a Y direction.

In a semiconductor device 1, a control chip 20 and a plurality of memory chips 40-1 to 40-8 are sequentially stacked on a substrate 10, and a plurality of spacers 70-1 to 70-2 are arranged on a side of the control chip 20 between the lowermost memory chip 40-1 of the plurality of memory chips 40-1 to 40-8 and the substrate 10. The control chip 20 is flip-chip mounted on the substrate 10 in a face-down state, and the plurality of memory chips 40-1 to 40-8 are wire-bonded on the substrate 10 in a face-up state. Thereby, a face-down mounting + face-up mounting spacer structure is constituted.

The substrate 10 has a front surface (main surface) 10a on the + Z side and a back surface 10b on the-Z side. A control chip 20, a plurality of spacers 70-1 to 70-2, a plurality of memory chips 40-1 to 40-8, and a plurality of adhesive films 30-1 to 30-10 are mounted on a front surface 10a of a substrate 10, respectively, and an external electrode 60 is mounted on a rear surface 10b of the substrate 10. The control chip 20, the plurality of spacers 70-1 to 70-2, the plurality of memory chips 40-1 to 40-8, and the plurality of adhesive films 30-1 to 30-10 mounted on the front surface 10a side of the substrate 10 are sealed with a sealing resin 50. The sealing resin 50 is formed of a material mainly composed of an insulator, and for example, may be formed of a material mainly composed of a1 st resin having insulating properties and thermoplasticity. The external electrode 60 mounted on the rear surface 10b side of the substrate 10 may be formed of a material mainly composed of a conductive material, and its surface is exposed so as to be electrically connected from the outside.

The substrate 10 includes a solder resist layer 11, a prepreg layer 12, a core layer 13, a conductive layer 14, and a via electrode 15. The solder resist layer 11 may be formed of a material containing an insulator (e.g., an insulating organic substance) as a main component. The prepreg layer 12 may be formed of a material containing an insulator (e.g., an insulating resin) as a main component. The core layer 13 may be formed of a material containing an insulator (e.g., an insulating resin) as a main component. The conductive layer 14 may be formed of a material containing a conductive substance (e.g., copper) as a main component. The via electrode 15 may be formed of a material having a conductive substance (e.g., copper) as a main component.

The control chip 20 has a front surface 20a on the-Z side and a back surface 20b on the + Z side. The control chip 20 can be flip-chip mounted on the substrate 10. The front surface 20a of the control chip 20 is opposite to the front surface 10a of the substrate 10. The control chip 20 is mounted face down (flip chip) on the front surface 10a of the substrate 10 via a plurality of bump electrodes 21. That is, the control chip 20 is mounted on the front surface 10a of the substrate 10 via the plurality of bump electrodes 21 in a state where the front surface 20a faces the front surface 10a of the substrate 10. Gaps between the plurality of bump electrodes 21 separated in the space between the control chip 20 and the substrate 10 are filled with an adhesive resin (underfill) 22.

The control chip 20 is mainly formed of a material having a semiconductor (e.g., silicon) as a main component. The bump electrode 21 is formed of a material containing a metal (e.g., copper) as a main component. The adhesive resin 22 is formed of a material mainly composed of an insulator, and may be formed of a material mainly composed of, for example, a2 nd resin having insulating and adhesive properties (for example, a material mainly composed of an epoxy resin).

For example, as shown in fig. 2 and 3, the back surface 20b of the control chip 20 is curved so as to protrude toward the + Z side due to the influence of thermal deformation or the like at the time of mounting. Fig. 2 and 3 are enlarged sectional views showing the height of the spacer 70 and the control chip 20. The height of the back surface 20b of the control chip 20 from the front surface 10a of the substrate 10 has an upper limit height H20b _ max and a lower limit height H20b _ min. The rear surface 20b has an upper limit height H20b _ max at a position near the center in the Y direction, and has a lower limit height H20b _ min at the + Y-side end and the-Y-side end.

In fig. 2 and 3, the case where the substrate 10 is flat is exemplified, but when the substrate 10 itself is bent due to the influence of thermal deformation or the like at the time of mounting, the reference of the height from the front surface 10a of the substrate 10 may be the Z position of the portion of the front surface 10a where the control chip 20 is mounted.

The adhesive film 30-1 shown in FIG. 1 covers the front surface 10a of the substrate 10 and is used for laminating the spacer sheet 70-1. The adhesive film 30-1 is disposed around the control chip 20, for example, on the-Y side of the control chip 20. The adhesive film 30-1 serves as a medium for adhering the spacer 70-1 to the front surface 10a of the substrate 10. The adhesive Film 30-1 is also referred to as DAF (Die Attach Film) or DBF (Die Bonding Film).

The spacer 70-1 has a front surface 70a and a back surface 70 b. The back surface 70b of the spacer 70-1 is attached to the front surface 10a of the substrate 10 via the adhesive film 30-1, and the memory chip 40-1 is laminated on the front surface 70a via the adhesive film 30-3. The spacer 70-1 may be formed of a material having a strength sufficient to support the memory chip 40-1 on the + Z side of the substrate 10 via the adhesive film 30-3. The spacer 70-1 may be formed of a material having a semiconductor (e.g., silicon) as a main component, or may be formed of a material having a resin (e.g., polyimide resin) as a main component.

For example, as shown in fig. 2, the height H70a1 of the front surface 70a of the spacer 70-1 from the front surface 10a of the substrate 10 is within a range between an upper limit height H20b _ max and a lower limit height H20b _ min. Thus, the height of the spacer 70-1 can be considered to substantially coincide with the height of the control chip 20.

The adhesive film 30-2 shown in FIG. 1 covers the front surface 10a of the substrate 10 and is used for laminating the spacer sheet 70-2. The adhesive film 30-2 is disposed around the control chip 20, for example, on the + Y side of the control chip 20. The adhesive film 30-2 serves as a medium for adhering the spacer sheet 70-2 to the front surface 10a of the substrate 10. The adhesive film 30-2 is also called DAF (die Attach film) or DBF (die Bonding film).

The spacer 70-2 has a front surface 70a and a back surface 70 b. The back surface 70b of the spacer 70-2 is attached to the front surface 10a of the substrate 10 via the adhesive film 30-2, and the memory chip 40-1 is laminated on the front surface 70a via the adhesive film 30-2. The spacer 70-2 may be formed of a material having strength sufficient to support the memory chip 40-1 on the + Z side of the substrate 10 via the adhesive film 30-3. The spacer 70-2 may be formed of a material mainly composed of a semiconductor (e.g., silicon) or a material mainly composed of a resin (e.g., polyimide resin).

For example, as shown in fig. 3, the height H70a2 of the front surface 70a of the spacer 70-2 from the front surface 10a of the substrate 10 is within a range between an upper limit height H20b _ max and a lower limit height H20b _ min. Thus, the height of the spacer 70-2 can be considered to substantially coincide with the height of the control chip 20. The height of the spacer 70-2 may also be equal to the height of the spacer 70-1.

The adhesive film 30-3 shown in FIG. 1 covers the back surface 20b of the control chip 20, covers the front surface 70a of the spacer 70-1, covers the front surface 70a of the spacer 70-2, and is used for laminating the memory chip 40-1. The adhesive film 30-3 is disposed between the control chip 20 and the plurality of spacers 70-1 and 70-2 and the memory chip 40-1. The adhesive film 30-3 adheres the memory chip 40-1 to the control chip 20 and the plurality of spacers 70-1, 70-2, also referred to as DAF (die Attach film) or DBF (die Bonding film).

For example, as shown in fig. 2 and 3, the height of the spacer 70-1 can be regarded as approximately matching the height of the control chip 20, and the height of the spacer 70-2 can be regarded as approximately matching the height of the control chip 20, so that the thickness of the adhesive film 30-3 can be easily made thin. For example, the thickness of the adhesive film 30-3 may be a size obtained by adding a specific thickness margin to the difference between the upper limit height H20b _ max and the lower limit height H20b _ min (Δ H20b is H20b _ max-H20 b _ min) of the control chip 20.

A plurality of memory chips 40-1 to 40-8 are stacked on the + Z side of the control chip 20 and the plurality of spacers 70-1, 70-2. The memory chips 40-1 to 40-8 are disposed across the control chip 20 and at least 1 spacer 70. In FIG. 1, memory chips 40-1 to 40-8 are disposed across the control chip 20 and 2 spacers 70. Adhesive films 30-4 to 30-10 are interposed between the plurality of memory chips 40-1 to 40-8, and the memory chips are bonded to each other through the adhesive films 30-4 to 30-10.

Each of the memory chips 40-1 to 40-8 has a front surface and a back surface. In each of the memory chips 40-1 to 40-8, the back surface is bonded to the adhesive film 30, and the front surface is provided with an electrode pad. Each of the memory chips 40-1 to 40-8 is mainly formed of a material containing a semiconductor (e.g., silicon) as a main component.

A plurality of memory chips 40-1 to 40-8 are respectively mounted on the substrate 10 by wire bonding. In this case, the conductive layer 14 in the substrate 10 has a plurality of electrode patterns on the front surface (+ Z-side main surface) 10a, and the electrode pads of the memory chips 40-1 to 40-8 are electrically connected to the electrode patterns on the front surface of the substrate 10 via bonding wires 41. Thus, the plurality of memory chips 40-1 to 40-8 can be mounted on the substrate 10 in a spacer structure by wire bonding.

In the semiconductor device 1, the thicknesses of the adhesive films 30-1 to 30-10 are compared, and as shown in FIG. 1, the thickness of the adhesive film 30-3 is the same as or slightly larger than the thicknesses of the adhesive film 30-1 and the adhesive film 30-2. The thickness of the adhesive film 30-3 is the same as or slightly thicker than the thickness of the adhesive film 30-4-30-10. That is, if the thickness of the adhesive film 30-3 can be made as thin as the thickness of each of the adhesive films 30-4 to 30-10 between the plurality of memory chips 40-1 to 40-8, the mounting height of the semiconductor device 1 can be easily reduced.

The adhesive films 30-1 to 30-10 are made of a material mainly composed of an insulator, and may be made of a material mainly composed of, for example, a 3 rd resin having insulating and adhesive properties (for example, a material containing an acrylic polymer and an epoxy resin).

As described above, in the semiconductor device 1 having the spacer structure of face-down mounting + face-up mounting according to embodiment 1, the height of each of the spacers 70-1 and 70-2 from the front surface 10a of the substrate 10 is set to fall within the range between the upper limit and the lower limit of the height of the control chip 20. This makes it possible to easily reduce the thickness of the adhesive film 30-3, and thus to easily reduce the mounting height of the semiconductor device 1.

Further, the control chip 20 may be curved so as to protrude to the-Z side. Even in this case, the same effects as those of the embodiment can be achieved by configuring the height of each of the spacers 70-1 and 70-2 from the front surface 10a of the substrate 10 to be within the range between the upper limit and the lower limit of the height of the control chip 20.

Alternatively, in the semiconductor device 1i, the plurality of spacers 70i-1, 70i-2 may be arranged as shown in FIG. 4. Fig. 4 is a plan view showing a layout structure of spacers 70i-1 and 70i-2 and a control chip 20i in variation 1 of embodiment 1.

The control chip 20i is disposed in a region including the center of the front surface 10a of the substrate 10 in the XY plan view. The spacers 70i-1, 70i-2 are equal in area to each other. The spacer 70i-1 is disposed on the-X side of the control chip 20 i. The spacer 70i-2 is disposed on the + X side of the control chip 20 i.

In this case, as shown in FIG. 5, a plurality of memory chips 40i-1 and 40i-2 may be laminated on the + Z side of the spacer 70i-1 and the control chip 20i via adhesive films 30i-3 and 30 i-4. The memory chips 40i-3 and 40i-4 may be laminated on the + Z side of the spacer 70i-2 and the control chip 20i via adhesive films 30i-5 and 30 i-6. Fig. 5 is a cross-sectional view showing a laminated structure of spacers 70i-1 and 70i-2, a control chip 20i, and memory chips 40i-1 to 40i-4 in variation 1 of embodiment 1, and shows a cross-section corresponding to a case of cutting along line a-a of fig. 4. In fig. 5, the bonding wires are not shown for simplification.

The spacer 70i-1 may be formed of a material having strength sufficient to support the memory chip 40i-1 via the adhesive film 30 i-3. The spacer 70i-1 may be formed of a material having a semiconductor (e.g., silicon) as a main component, or may be formed of a material having a resin (e.g., polyimide resin) as a main component. The spacer 70i-2 may be formed of a material having strength sufficient to support the memory chip 40i-3 via the adhesive film 30 i-5. The spacer 70i-2 may be formed of a material having a semiconductor (e.g., silicon) as a main component, or may be formed of a material having a resin (e.g., polyimide resin) as a main component.

Each of the memory chips 40i-1 to 40i-4 is electrically connected to a plurality of electrode patterns 101-1 to 101-2k (k is an arbitrary integer of 2 or more) on the front surface 10a of the substrate 10 shown in FIG. 4 via bonding wires. The spacer 70i-1 is disposed between the plurality of electrode patterns 101-1 to 101-k and the control chip 20i in an XY plan view. The spacer 70i-2 is disposed between the plurality of electrode patterns 101- (k +1) to 101-2k and the control chip 20 i.

The control chip 20i has, for example, a rectangular outer shape and has 4 sides 20i1 to 20i 4. The sides 20i1 extend in the Y direction, are spaced apart and face each other in the X direction with respect to the sides 20i2, and intersect the sides 20i3 and 20i4 at both ends in the ± Y direction. The sides 20i2 extend in the Y direction, are spaced apart and face each other in the X direction with respect to the sides 20i1, and intersect the sides 20i3 and 20i4 at both ends in the ± Y direction. The sides 20i3 extend in the X direction, are spaced apart and face each other in the Y direction with respect to the sides 20i4, and intersect the sides 20i2 and 20i1 at both ends in the ± X direction. The sides 20i4 extend in the X direction, are spaced apart and face each other in the Y direction with respect to the sides 20i3, and intersect the sides 20i2 and 20i1 at both ends in the ± X direction.

The spacer 70i-1 is arranged in parallel with the side 20i 1. The spacer 70i-1 has a rectangular shape with the direction along the Y direction being the long side direction, and extends along the side 20i 1. The spacer 70i-2 is arranged in parallel with the edge 20i 2. The spacer 70i-2 has a rectangular shape with the direction along the Y direction being the long side direction, and extends along the side 20i 2. The spacers 70i-1 and 70i-2 may have the same outer dimensions. The areas of the spacers 70i-1 and 70i-2 can be made equal to each other.

In this way, in the semiconductor device 1i, since the areas of the spacers 70i-1 and 70i-2 can be made equal to each other, the efficiency of using the material (e.g., a semiconductor such as silicon) of the spacers 70i-1 and 70i-2 can be improved.

In addition, by making the outside dimensions of the spacer 70i-1 and the spacer 70i-2 equal to each other, variation in the thickness of the spacer 70i-1 and the spacer 70i-2 can be reduced, and in this point, the thickness of the adhesive films 30i-3 and 30i-5 can be reduced, so that the mounting height of the semiconductor device 1i can be easily reduced.

Alternatively, in the semiconductor device 1j, the plurality of spacers 70j-1 to 70j-4 may be arranged as shown in FIG. 6. FIG. 6 is a plan view showing a layout structure of spacers 70j-1 to 70j-4 and a control chip 20i in variation 2 of embodiment 1.

The plurality of spacers 70j-1 to 70j-4 have equal areas. The spacers 70j-1 to 70j-4 can have the same outer dimensions. The spacers 70j-1 and 70j-3 are disposed on the-X side of the control chip 20 i. The spacers 70j-2 and 70j-4 are disposed on the + X side of the control chip 20 i.

The spacers 70j-1 and 70j-3 are obtained by removing the portion near the center of the spacer 70i-1 (see fig. 4) in the Y direction and dividing the same by 2. Since the space of the gap exists between the spacers 70j-1 and 70j-3 in the Y direction, the space between the spacers 70j-1 and 70j-3 and the control chip 20i can be easily filled with the sealing resin 50 through the gap when the semiconductor device 1j is manufactured.

The spacers 70j-2 and 70j-4 are obtained by 2-dividing the spacer 70i-2 (see fig. 4) by removing a portion near the center in the Y direction. Since there is a gap space between the spacers 70j-2 and 70j-4 in the Y direction, the space between the spacers 70j-1 and 70j-3 and the control chip 20i can be easily filled with the sealing resin 50 through the gap when the semiconductor device 1j is manufactured.

In this case, the lamination structure of the spacers 70j-1 to 70j-4, the control chip 20i and the memory chips 40i-1 to 40i-4 may be the same as that shown in FIG. 5.

In this way, in the semiconductor device 1j, the areas of the spacers 70j-1 to 70j-4 can be made uniform, and therefore, the use efficiency of the material of the spacers 70j-1 to 70j-4 can be improved.

In addition, the outer dimensions of the spacers 70j-1 to 70j-4 are made uniform, so that variations in the thickness of the spacers 70j-1 to 70j-4 can be reduced, and in this viewpoint, the thickness of the adhesive films 30i-3 and 30i-5 can be reduced, so that the mounting height of the semiconductor device 1j can be easily reduced.

Alternatively, in the semiconductor device 1k, a plurality of spacers 70k-1 to 70k-5 may be arranged as shown in FIG. 7. FIG. 7 is a plan view showing the layout structure of the spacers 70k-1 to 70k-5 and the control chip 20i in the 3 rd variation of embodiment 1.

The control chip 20i is disposed in a region including the center of the front surface 10a of the substrate 10 in the XY plan view. The spacers 70k-1 to 70k-5 have equal areas. The spacer 70k-1 is disposed on the-X side of the control chip 20 i. The spacer 70k-2 is disposed on the + X side of the control chip 20 i. The spacer 70k-3 is disposed on the + X side of the control chip 20i and on the + Y side of the spacer 70 k-2. The spacer 70k-4 is disposed on the-Y side of the control chip 20 i. The spacer 70k-5 is disposed on the + Y side of the control chip 20 i.

In this case, as shown in FIG. 8, a plurality of memory chips 40k-1 to 40k-4 may be laminated on the + Z side of the spacers 70k-1 to 70k-5 and the control chip 20i via adhesive films 30k-6 to 30 k-9. The spacers 70k-1 to 70k-5 are disposed on the substrate via the adhesive films 30k-1 to 30k-5, as in the embodiment. FIG. 8 is a cross-sectional view showing a laminated structure of spacers 70k-1 to 70k-5, a control chip 20i and memory chips 40k-1 to 40k-4 in variation 3 of embodiment 1, and a cross-section corresponding to a case of cutting along line B-B of FIG. 7. In fig. 8, the bonding wires are not shown for simplification.

Each of the spacers 70k-1 to 70k-5 may be formed of a material having a strength sufficient to support the memory chip 40k-1 via the adhesive film 30 k-6. Each of the spacers 70k-1 to 70k-5 may be formed of a material mainly composed of a semiconductor (e.g., silicon) or a material mainly composed of a resin (e.g., polyimide resin).

Each of the memory chips 40k-1 to 40k-4 is electrically connected to a plurality of electrode patterns 101-1 to 101-2k (k is an arbitrary integer of 2 or more) on the front surface 10a of the substrate 10 shown in FIG. 7 via bonding wires. The spacer 70k-1 is disposed between the plurality of electrode patterns 101-1 to 101-k and the control chip 20i in an XY plan view. The spacers 70k-2 and 70k-3 are respectively disposed between the plurality of electrode patterns 101- (k +1) to 101-2k and the control chip 20 i. The spacer 70k-4 is disposed between the plurality of electrode patterns 101-1 to 101-k and the plurality of electrode patterns 101- (k +1) to 101-2k on the-Y side of the control chip 20 i. The spacer 70k-5 is disposed between the plurality of electrode patterns 101-1 to 101-k and the plurality of electrode patterns 101- (k +1) to 101-2k on the + Y side of the control chip 20 i.

The spacer 70k-1 is arranged in parallel with the side 20i1 of the control chip 20 i. The spacer 70k-1 has a rectangular shape with the direction along the Y direction being the long side direction, and extends along the side 20i 1. The spacers 70k-2 and 70k-3 are arranged side by side with the side 20i2, respectively. The spacers 70k-2 and 70k-3 have a rectangular shape whose longer side is the direction along the Y direction, and extend along the side 20i 2. The spacer 70k-4 is arranged in parallel with the side 20i 4. The spacer 70k-4 has a rectangular shape whose longer side is the direction along the X direction, and extends along the side 20i 4. The spacer 70k-5 is arranged in a side-by-side relationship with the edge 20i 3. The spacer 70k-5 has a rectangular shape whose longer side is the direction along the X direction, and extends along the side 20i 3.

The spacers 70k-1 to 70k-5 can have equal outer dimensions. The areas of the spacers 70k-1 to 70k-5 can be made equal to each other.

In this way, in the semiconductor device 1k, the areas of the spacers 70k-1 to 70k-5 can be made uniform, and therefore, the efficiency of using the material (e.g., a semiconductor such as silicon) of the spacers 70k-1 to 70k-5 can be improved.

In addition, the outer dimensions of the spacers 70k-1 to 70k-5 are made uniform, so that the variation in the thickness of the spacers 70k-1 to 70k-5 can be reduced, and in this viewpoint, the thickness of the adhesive film 30k-6 can be reduced, so that the mounting height of the semiconductor device 1k can be easily reduced.

Alternatively, in the semiconductor device 1n, as shown in fig. 9, the spacer 90n may be disposed on the back surface 20bn of the control chip 20 n. Fig. 9 is a cross-sectional view showing a laminated structure of spacers 70i-1, 70i-2, and 90n, a control chip 20n, and memory chips 40i-1 to 40i-4 in variation 4 of embodiment 1, and shows a cross-section corresponding to a case of cutting along line a-a of fig. 4. In fig. 9, the bonding wires are not shown for simplification. The spacer 90n is made of a material capable of reducing the difference in thermal expansion coefficient between the back surface 20bn of the control chip 20n and the sealing resin 50 (for example, a material having an intermediate thermal expansion coefficient between the semiconductor and the 1 st resin, or a material capable of reducing stress generated by the difference in thermal expansion coefficient), and may be made of a material mainly composed of, for example, a polyimide resin. The spacer 90n and the back surface 20bn of the control chip 20n are bonded to each other by an adhesive film not shown. A plurality of memory chips 40i-1, 40i-2 are laminated on the + Z side of the spacer 70i-1 and the spacer 90n via adhesive films 30i-3, 30 i-4.

In the manufacturing process of the semiconductor device 1n, the spacer 90n is attached to the wafer including the control chip 20n before singulation, then the spacer 90n and the control chip 20n are singulated as one body, and then the spacer 90n and the control chip 20n are mounted on the substrate 10 as one body. Therefore, the lower limit height H20b _ min and the upper limit height H20b _ max shown in fig. 2 and 3 may be heights of the + Z side surface of the member in which the spacer 90n and the control chip 20n are integrated (i.e., the + Z side surface of the spacer 90 n).

In the configuration of fig. 5, the adhesion between the rear surface 20bi of the control chip 20i and the sealing resin 50 is small, and the sealing resin 50 may be peeled off from the rear surface 20bi after sealing.

In contrast, in the configuration of fig. 9, the adhesion between the back surface 20bn of the control chip 20n and the sealing resin 50 can be improved via the spacer 90n, and the sealing resin 50 can be prevented from peeling off from the back surface 20bi side (surface on the + Z side of the spacer 90 n) after sealing.

(embodiment 2) the semiconductor device according to embodiment 2 will be described. Hereinafter, the following description will be focused on differences from embodiment 1.

In embodiment 1, the method for manufacturing the semiconductor device 1 is not particularly limited.

For example, in manufacturing the semiconductor device 1, the control chip 20 is mounted (mount) on the substrate 10 via the plurality of bump electrodes, and the underfill paste is filled into the gaps between the plurality of bump electrodes, and then the spacer 70 is mounted (mount).

When the control chip 20 is mounted, after the adhesive resin 22 is filled, a molten sheet (Bleed) of the adhesive resin 22 may flow out around the control chip 20. Thereafter, if the spacer sheet 70 is attached to the melt sheet (Bleed), the adhesion of the spacer sheet 70 to the substrate 10 may deteriorate and the spacer sheet may be peeled off. When the spacer 70 is peeled off, stress or the like is applied to other chips, and thus, any one of the electrical connection paths of the bonding wire between the electrode pad of the memory chip and the electrode pattern on the substrate may be cut off by disconnection, peeling, or the like, thereby causing an electrical connection failure.

In addition, the unevenness in the height direction may increase depending on the thickness of the melt sheet (Bleed). That is, the height difference between the upper surface of the control chip 20 on the substrate 10 and the upper surface of the spacer 70 is increased, and the adhesive film 30 to be laminated thereon is increased to absorb the height difference, so that there is a possibility that the mounting height from the substrate 10 to the uppermost memory chip 40 is increased.

In embodiment 2, as shown in fig. 10, in the method of manufacturing the semiconductor device 1, the spacer sheet 70 is mounted on the substrate 10, and then the control chip 20 is mounted, so that the molten sheet (blade) of the adhesive resin 22 is prevented from being interposed between the spacer sheet 70 and the substrate 10. Fig. 10 is a step sectional view showing a method of manufacturing the semiconductor device 1 according to embodiment 2.

In the step of fig. 10(a), adhesive films 30-1 and 30-2 are disposed on the front surface 10a of the substrate 10 in regions where the spacers 70-1 and 70-2 are to be mounted. Then, spacers 70-1 and 70-2 are disposed on the + Z sides of the adhesive films 30-1 and 30-2. Thus, the spacers 70-1 and 70-2 are adhesively mounted (mount) on the front surface 10a of the substrate 10 via the adhesive films 30-1 and 30-2.

In the step of fig. 10(b), the control chip 20 is disposed in the region between the spacers 70-1 and 70-2 on the front surface 10a of the substrate 10 with the bump electrodes 21 interposed therebetween. At this time, the control chip 20 is disposed on the front surface 10a of the substrate 10 in a state where the front surface 20a of the control chip 20 faces the front surface 10a of the substrate 10. Then, the adhesive resin 22 is filled in the gaps of the plurality of bump electrodes 21 between the front surface 10a of the substrate 10 and the front surface 20a of the control chip 20. Thereafter, the plurality of bump electrodes 21 are heated to the 1 st temperature via the substrate 10 and melted to some extent.

At this time, although there is a possibility that the melted sheet (Bleed)22a of the adhesive resin 22 flows out, since the spacer sheet 70 is already attached to the front surface 10a of the substrate 10 via the adhesive film 30, the melted sheet (Bleed) of the adhesive resin 22 is not interposed between the spacer sheet 70 and the substrate 10.

In the step of fig. 10(c), the bonding head 210 presses the back surface 20b of the control chip 20, and the plurality of bump electrodes 21 are pressed against the electrodes on the front surface 10a of the substrate 10. At the same time, the plurality of bump electrodes 21 are heated to the 2 nd temperature higher than the 1 st temperature via the substrate 10 to be bonded to the electrodes on the front surface 10 a.

At this time, the 2 nd temperature may be set to a temperature higher than the glass transition point of the adhesive resin 22. If the bonding resin 22 is heated to a temperature lower than the glass transition point, there is a possibility that the bonding resin 22 thermally shrinks to bend the substrate 10. On the other hand, if the adhesive resin 22 is heated to a temperature higher than the glass transition point, the adhesive resin 22 becomes amorphous and stress due to thermal shrinkage can be released, so that the substrate 10 can be restored to be flat.

In the step of FIG. 10(d), an adhesive film 30-3 is disposed on the + Z side of the control chip 20 and the spacers 70-1 and 70-2. Then, the memory chip 40-1 is disposed on the + Z side of the adhesive film 30-3. Thus, the memory chip 40-1 is adhesively mounted (mount) on the + Z side of the control chip 20 and the spacers 70-1 and 70-2 via the adhesive film 30-3.

Thereafter, the memory chips 40-2 to 40-8 are mounted (mount) on the + Z side by bonding via the adhesive films 30-4 to 30-10. Thereby, the semiconductor device 1 shown in fig. 1 can be obtained.

As described above, in embodiment 2, the spacer 70 is mounted on the front surface 10a of the substrate 10, and thereafter, the control chip 20 is mounted on the front surface 10a of the substrate 10. This can prevent a molten sheet (blade) of the adhesive resin 22 from being interposed between the spacer sheet 70 and the substrate 10, thereby preventing poor electrical connection and facilitating reduction in the mounting height of the semiconductor device 1.

In the steps of fig. 10(a) and 10(b), the height of each spacer 70 from the main surface 10a of the substrate 10 is set to fall within a range between the upper limit and the lower limit of the height of the control chip 20. Therefore, in the step of fig. 10(c), there is a possibility that the bonding head 210 cannot press the portion of the back surface 20b of the control chip 20 lower than the front surface 70a of the spacer 70, and there is a possibility that the bonding of the bump electrode 21 and the electrode on the front surface 10a of the substrate 10 is insufficient.

In view of this, in the semiconductor device, the height of each spacer from the main surface of the substrate may be set to be lower than the lower limit of the height of the control chip.

For example, the spacers 70p-1 and 70p-2 may be configured as shown in FIGS. 11 and 12. Fig. 11 is an enlarged cross-sectional view showing the heights of the spacer 70p-1 and the control chip 20 in a modification of embodiment 2. Fig. 12 is an enlarged cross-sectional view showing the heights of the spacer 70p-2 and the control chip 20 in a modification of embodiment 2. The height H70ap1 of the front surface 70ap of the spacer 70p-1 from the front surface 10a of the substrate 10 is lower than the lower limit height H20b _ min of the back surface 20b of the control chip 20. The height H70ap2 of the front surface 70ap of the spacer 70p-2 from the front surface 10a of the substrate 10 is lower than the lower limit height H20b _ min of the back surface 20b of the control chip 20. Thus, in the step of fig. 10(c), the bonding head 210 can easily press the back surface 20b of the control chip 20.

In this case, the difference between the lower height H20b _ min and the height H70ap2 may be smaller than the difference between the upper height H20b _ max and the lower height H20b _ min. That is, the following numerical expression 1 is also true. H20b _ min-H70 ap2 < H20b _ max-H20 b _ min … and the formula 1

Thus, in the step of fig. 10(c), the bonding head 210 can easily press the back surface 20b of the control chip 20, and can suppress a difference in height between the back surface of the control chip 20 and the front surface of the spacer.

Several embodiments of the present invention have been described, but these embodiments are only provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.