阅读说明：本技术 封装结构和其制造方法 (Package structure and method for manufacturing the same ) 是由 李佑茗 李江浩 郭宏瑞 何明哲 于 2019-12-23 设计创作，主要内容包括：本揭露实施例是有关于一种封装结构及其制造方法。本揭露实施例提供一种封装结构,包含半导体管芯和重布线电路结构。重布线电路结构设置在半导体管芯上且电连接到半导体管芯,且包含金属化层和设置在金属化层上的介电层。金属化层具有多个导电图案,其中所述多个导电图案中的每一个包含多个晶粒,晶粒各自呈柱形且包含具有在(220)晶格平面上定向的铜原子的多个第一带状结构。(The disclosed embodiments relate to a package structure and a method for manufacturing the same. Embodiments of the present disclosure provide a package structure including a semiconductor die and a redistribution circuit structure. The rewiring circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has a plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises a plurality of grains that are each columnar and comprise a plurality of first strip-like structures having copper atoms oriented on a (220) lattice plane.)

1. A package structure, comprising:

a semiconductor die; and

a rerouting circuit structure disposed on and electrically connected to the semiconductor die and comprising:

a metallization layer having a plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises a plurality of grains, each of the plurality of grains being columnar in shape and comprising a plurality of first strip-like structures having a plurality of copper atoms oriented on a (220) lattice plane; and

a dielectric layer disposed on the metallization layer.

Technical Field

The disclosed embodiments relate to a package structure and a method for manufacturing the same.

Background

Semiconductor devices and integrated circuits are typically fabricated on a single semiconductor wafer. The dies of a wafer may be processed and packaged with other semiconductor devices or dies at the wafer level (wafer level), and various techniques have been developed for wafer level packaging (e.g., forming rewiring circuit structures/layers). Furthermore, such a package may be further integrated into a semiconductor substrate or carrier after dicing (dicing). Therefore, reliability of electrical performance within internal components (e.g., redistribution circuit structures) within each package becomes important.

Disclosure of Invention

Embodiments of the present disclosure provide a package structure including a semiconductor die and a redistribution circuit structure. The rewiring circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has a plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises a plurality of grains that are each columnar and comprise a plurality of first strip-like structures having copper atoms oriented on a (220) lattice plane.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-6 and 8-15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Fig. 7A is an enlarged schematic cross-sectional view of a portion of the conductive pattern depicted in fig. 6.

Fig. 7B is an enlarged schematic top view of a portion of the conductive pattern depicted in fig. 6.

Fig. 16 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 17 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 18 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 21 is a schematic diagram illustrating an electroplating apparatus for performing an electrochemical plating process, according to some exemplary embodiments of the present disclosure.

[ description of reference numerals ]

10: a plating bath box;

11: an anode;

12: a cathode;

13: a plating solution;

14: a power source;

112: a carrier;

114: a peeling layer;

116: a buffer layer;

130. 130-1, 130-2, 130-3, 820a, 820 b: a semiconductor die;

130 a: an active surface;

130 b: a pad;

130 c: a passivation layer;

130 d: a via hole;

130e, 130 e: a protective layer;

130 f: a backside surface;

130 s: a semiconductor substrate;

130 sw: a side wall;

130t, 140t, S130d, S130e, S151-1, S151-2, S154-1, S154-2b, S154-3, S154-4: a top surface;

140. 140', 860: an insulating seal body;

150. 230, 240: rewiring the circuit structure;

151. 151-1, 151-2, 151-3, 151-4, 232, 242: a dielectric layer;

152. 152-1, 152-2, 152-3, 152-4, 153-1, 153-2, 153-3, 153-4, Sla, SLb: a seed layer;

154. 154-1, 154-2a, 154-2b, 154-3, 154-4, 234, 244, 530: a metallization layer;

160: a seed layer pattern;

170. 180, 190: a conductive element;

200: a circuit element;

210: a core portion;

220: a through hole;

245b, 252a, 252 b: a solder mask layer;

254a, 254 b: a bonding pad;

300: copper crystal grains;

310: a first ribbon-like structure;

320: a second belt structure;

400. 600: a conductive terminal;

500. 810: a substrate;

510. 520, the method comprises the following steps: a contact pad;

800: a package body;

830a, 830 b: a bonding wire;

840. 850: a conductive pad;

u1, u 2: an under ball metal pattern;

CP1, CP2a, CP2b, CP3, CP 4: a conductive pattern;

DA1, DA2, DA3, DA4, DA 5: connecting the films;

DI: a layer of dielectric material;

GB: grain boundaries;

HD: a holding device;

o1, O2, OP: an opening;

p1, P2, P3: a packaging structure;

PR: a resist layer;

RDL 1: a first build-up layer;

RDL 2: a second build-up layer;

RDL 3: a third build-up layer;

RDL 4: a fourth build-up layer;

s1, S2: a surface;

ta, Tb: thickness;

and (3) TIV: perforating between layers;

UF1, UF 2: an underfill;

w300: a width;

x, Y: direction;

z: the stacking direction.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are contemplated. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms such as "below …," "below …," "lower," "above …," "above …," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Furthermore, for ease of description, terms such as "first," "second," "third," "fourth," and the like may be used herein to describe similar or different elements or features as shown in the figures, and may be used interchangeably depending on the order of presence or context of description.

Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow for testing of 3D packages or 3 DICs, use of probes and/or probe cards (probe cards), and the like. Verification testing can be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies (innown good die) to improve yield (yield) and reduce cost.

Fig. 1-6 and 8-15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig. 7A is an enlarged schematic cross-sectional view of a portion of the conductive pattern depicted in fig. 6. Fig. 7B is an enlarged schematic top view of a portion of the conductive pattern depicted in fig. 6. In some embodiments, the method of manufacturing is part of a packaging process. In fig. 1 to 6 and 8 to 15, more than one (semiconductor) chip or die is depicted to represent a plurality of (semiconductor) chips or dies of a wafer, and one (semiconductor) package structure is depicted to represent a plurality of (semiconductor) package structures obtained following a (semiconductor) manufacturing method, but the present disclosure is not limited thereto. In other embodiments, one or more than one (semiconductor) chip or die is depicted to represent a plurality of (semiconductor) chips or dies of a wafer, and one or more than one (semiconductor) package structure is depicted to represent a plurality of (semiconductor) package structures obtained following a (semiconductor) fabrication method, although the disclosure is not so limited.

Referring to fig. 1, in some embodiments, a carrier 112 having a release layer 114 and a buffer layer 116 coated thereon is provided. In one embodiment, carrier 112 may be a glass carrier or any suitable carrier for carrying semiconductor wafers or reconstituted wafers for use in a manufacturing process for semiconductor packaging. In some embodiments, the exfoliation layer 114 is disposed on the carrier 112, and the material of the exfoliation layer 114 can be any material suitable for bonding and exfoliating the carrier 112 with respect to an overlying layer (e.g., the buffer layer 116 depicted in fig. 1) or bonding and exfoliating any wafer (e.g., the carrier 112 depicted in fig. 1) disposed thereon. In some embodiments, the release layer 114 may include a release layer (e.g., a light-to-heat conversion ("LTHC") layer) or an adhesive layer (e.g., a uv-curable adhesive or a thermally curable adhesive layer).

As depicted in fig. 1, in some embodiments, the buffer layer 116 is disposed on the exfoliation layer 114, and the exfoliation layer 114 is located between the carrier 112 and the buffer layer 116. In some embodiments, the buffer layer 116 may be a layer of dielectric material. In some embodiments, the buffer layer 116 may be a polymer layer made of Polyimide (PI), Polybenzoxazole (PBO), benzocyclobutene (BCB), or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer 116 may be an Ajinomoto build up film (ABF), a solder resist film (SR), or the like. The top surface of the buffer layer 116 may be horizontal and may have a high degree of coplanarity. However, the present disclosure is not limited thereto; in other embodiments, the buffer layer 116 may be omitted.

For example, the release layer 114 and the buffer layer 116 may be formed by suitable fabrication techniques, such as spin coating, lamination, deposition, or the like. The present disclosure is not particularly limited thereto.

In some embodiments, at least one semiconductor die is disposed on carrier 112. As shown in fig. 1, in some embodiments, the at least one semiconductor die includes a plurality of semiconductor dies, such as semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3. Semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are referred to as semiconductor die 130 in this disclosure. As depicted in fig. 1, only three semiconductor dies 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) are presented for illustrative purposes, however, it should be noted that the number of semiconductor dies 130 can be one or more than one, and the disclosure is not limited thereto.

In some embodiments, semiconductor die 130 is picked and placed over carrier 112 and semiconductor die 130 is disposed on buffer layer 116. For example, as depicted in fig. 1, semiconductor die 130-2, semiconductor die 130-3 are arranged beside each other along direction X, and direction X is perpendicular to carrier 112, exfoliation layer 114, buffer layer 116, and stacking direction Z of semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3. In other embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are arranged beside each other along direction Y, and direction Y is different from and perpendicular to direction X and stacking direction Z.

In some embodiments, the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 each include a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite the active surface 130a, a plurality of pads 130b distributed over the active surface 130a, a passivation layer 130c covering the active surface 130a and a portion of the pads 130b, a plurality of vias 130d connected to the pads 130b exposed by the passivation layer 130c, and a protective layer 130e disposed over the vias 130 d. The pad 130b, the passivation layer 130c, the via 130d, and the passivation layer 130e are formed on the semiconductor substrate 130 s. The pad 130b is partially exposed by the passivation layer 130c, the via holes 130d are respectively disposed on the pad 130b and electrically connected to the pad 130b, and the passivation layer 130c and the via holes 130d exposed by the via holes 130d are covered by the protection layer 130 e.

However, the present disclosure may not be limited thereto. For example, the via 130d and the protection layer 130e may be omitted. In alternative embodiments, the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 may each include a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite the active surface 130a, a plurality of pads 130b distributed over the active surface 130a, and a passivation layer 130c covering the active surface 130a and a portion of the pads 130 b.

The material of the semiconductor substrate 130s may include a silicon substrate including active components (e.g., transistors and/or memories, such as N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, or the like) and/or passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. In some embodiments, such active and passive components may be formed in front-end-of-line (FEOL). In alternative embodiments, the semiconductor substrate 130s may be a bulk silicon substrate, such as a bulk substrate of monocrystalline silicon, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. The present disclosure is not limited thereto.

In addition, the semiconductor substrate 130s may further include an interconnect structure (not shown) disposed on the active surface 130 a. In some embodiments, the interconnect structure may include one or more inter-dielectric layers (inter-dielectric layers) and one or more patterned conductive layers stacked alternately to provide a wiring function to active and passive components embedded in the semiconductor substrate 130s, wherein the pad 130b may be referred to as an outermost layer of the patterned conductive layers. In one embodiment, the interconnect structure may be formed in a back-end-of-line (BEOL) process. For example, the interlayer dielectric layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed by other suitable dielectric materials, and the interlayer dielectric layer may be formed by deposition or the like. For example, the patterned conductive layer may be a patterned copper layer or other suitable patterned metal layer, and the patterned conductive layer may be formed by electroplating or deposition. However, the present disclosure is not limited thereto.

For example, the pad 130b is an aluminum pad or other suitable metal pad. For example, the via 130d is a copper pillar, a copper alloy pillar, or other suitable metal pillar containing copper metal. In some embodiments, the passivation layer 130c and the protection layer 130e may be PBO layers, PI layers, or other suitable polymers. In some alternative embodiments, the passivation layer 130c and the protection layer 130e may be made of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. For example, the material of the passivation layer 130c may be the same as or different from the material of the protection layer 130 e.

It should be noted that at least one of the semiconductor dies described herein, such as semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3), may be referred to as a semiconductor chip or Integrated Circuit (IC). In alternative embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 described herein may be semiconductor devices. In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may comprise one or more digital, analog, or mixed-signal chips, such as an application-specific integrated circuit ("ASIC") chip, a sensor chip, a wireless and Radio Frequency (RF) chip, a memory chip, a logic chip, or a voltage regulator chip.

In some embodiments, at least one semiconductor die described herein may further include additional semiconductor dies of the same type or different types in addition to semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3). In alternative embodiments, the additional semiconductor die may include a digital chip, an analog chip, or a mixed signal chip, such as an ASIC chip, a sensor chip, a wireless and RF chip, a memory chip, a logic chip, or a voltage regulator chip. The present disclosure is not limited thereto.

In this disclosure, it should be understood that the illustration of the semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) and other components throughout the figures is schematic and not to scale. In one embodiment, at least two of semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) may be identical. In alternative embodiments, at least two of the semiconductor dies 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) may be different from each other.

Continuing with fig. 1, in some embodiments, semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) is disposed on buffer layer 116 with a connection film DA1, a connection film DA2, a connection film DA3, respectively. In other words, the backside surface 130f of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 is adhered to the buffer layer 116 through the connection film DA1, the connection film DA2, and the connection film DA3, respectively. That is, the connection film DA1 is interposed between the backside surface 130f of the semiconductor die 130-1 and the buffer layer 116, the connection film DA2 is interposed between the backside surface 130f of the semiconductor die 130-2 and the buffer layer 116, and the connection film DA3 is interposed between the backside surface 130f of the semiconductor die 130-3 and the buffer layer 116. Due to the connection films DA1, DA2, DA3, the semiconductor die 130-1, 130-2, 130-3 are stably adhered to the buffer layer 116. In some embodiments, the connection film DA1, the connection film DA2, the connection film DA3 may be, but is not limited to, a die attach film (die attach film) or a layer made of an adhesive, an epoxy-based resin, an acrylic polymer, other suitable insulating material, or the like, and the connection film may or may not have a filler (e.g., silica, alumina, or the like) filled therein. In an alternative embodiment, the connection films DA1, DA2, DA3 may be omitted, and the present disclosure is not limited thereto.

In other embodiments, where buffer layer 116 is omitted as mentioned above, each of semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) is then disposed on release layer 114 through connecting film DA1, connecting film DA2, connecting film DA3, respectively. In still other embodiments that omit the connecting film DA1, the connecting film DA2, the connecting film DA3 as mentioned above, each of the semiconductor dies 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, semiconductor die 130-3) is then disposed on the peeling layer 114 through the buffer layer 116, respectively.

Referring to fig. 2, in some embodiments, a semiconductor die 130 is encapsulated in an insulating encapsulant 140. In some embodiments, an insulating seal 140 is formed on the buffer layer 116 and over the carrier 112. As illustrated in fig. 2, for example, the insulating seal 140 fills at least the gaps between the semiconductor dies 130 (e.g., the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3) and the gaps between the connection films DA1, DA2, DA 3. In some embodiments, an insulating seal 140 covers the semiconductor die 130. In other words, for example, the semiconductor die 130 is not exposed in a accessible manner by the insulating seal 140 and is embedded in the insulating seal 140.

In some embodiments, the insulating seal 140 is a molding compound formed by a molding process. In some embodiments, the insulating seal 140 may comprise, for example, a polymer (e.g., epoxy, phenolic, silicon-containing, or other suitable resin), a dielectric material, or other suitable material. In alternative embodiments, the insulating seal 140 may comprise an acceptable insulating sealing material. In some embodiments, the insulating seal 140 may further comprise an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that may be added thereto to optimize the Coefficient of Thermal Expansion (CTE) of the insulating seal 140. The present disclosure is not limited thereto.

Referring to fig. 3, in some embodiments, the insulating seal 140 is planarized to form an insulating seal 140' that exposes the semiconductor die 130. In some embodiments, as depicted in fig. 3, after planarization, the top surface 130t of the semiconductor die 130 (including the top surface S130d of the vias 130d and the top surface S130e of the protective layer 130e of each of the semiconductor die 130-1, the semiconductor die 130-2, the semiconductor die 130-3) is exposed by the top surface 140t of the insulating seal 140'. That is, for example, the top surface 130t of the semiconductor die 130 becomes substantially flush with the top surface 140t of the insulating seal 140'. In other words, the top surface 130t of the semiconductor die 130 and the top surface 140t of the insulating seal 140' are substantially coplanar with one another. In some embodiments, as depicted in fig. 3, the semiconductor die 130 is exposed in a accessible manner by the insulating seal 140'. That is, for example, the via 130d of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 is exposed in a manner that is accessible by the insulating seal 140'. In some embodiments, for example, the sidewalls 130sw of the semiconductor die 130 are also covered by the insulating seal 140'.

For example, the insulating seal 140 may be planarized by mechanical grinding or Chemical Mechanical Polishing (CMP). After the planarization step, a cleaning step may optionally be performed, for example, to clean and remove residues resulting from the planarization step. However, the present disclosure is not so limited and the planarization step may be performed by any other suitable method.

In some embodiments, during planarization of the insulating seal 140, the vias 130d and the protective layer 130e of the semiconductor die 130-1, the semiconductor die 130-2, and/or the semiconductor die 130-3 may also be planarized. In some embodiments, a planarization step may be performed, for example, on the overmolded insulating seal 140 to make the top surface 140t of the insulating seal 140' flush with the top surface 130t of the semiconductor die 130 (including the top surface S130d of the vias 130d and the top surface S130e of the protective layer 130e of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3).

In some embodiments, the rerouting circuit structure 150 is formed on the semiconductor die 130 and the insulating encapsulant 140'. In some embodiments, as illustrated in fig. 4-12, the redistribution circuit structure 150 includes at least one dielectric layer 151 (e.g., dielectric layer 151-1, dielectric layer 151-2, dielectric layer 151-3, and dielectric layer 151-4), at least one seed layer 152 (e.g., seed layer 152-1, seed layer 152-2, seed layer 152-3, and seed layer 152-4), at least one seed layer 153 (e.g., seed layer 153-1, seed layer 153-2, seed layer 153-3, and seed layer 153-4), and at least one metallization layer 154 (e.g., metallization layer 154-1, metallization layer 154-2a, metallization layer 154-2b, metallization layer 154-3, and metallization layer 154-4). However, in the present disclosure, the number of layers of the dielectric layer 151, the seed layer 152, the seed layer 153, and the metallization layer 154 is not limited to the numbers depicted in fig. 4 to 12, wherein the number of layers of the dielectric layer 151, the seed layer 152, the seed layer 153, and the metallization layer 154 may be one or more than one.

Referring to fig. 4, in some embodiments, a seed layer SLa is formed on the semiconductor die 130 and the insulating seal 140'. For example, the seed layer SLa is formed on the semiconductor die 130 and the insulating seal 140' in the form of a blanket layer made of a metal or metal alloy material, to which the present disclosure is not limited. In the present disclosure, the seed layer SLa is referred to as a metal seed layer. In some embodiments, the material of the seed layer SLa may comprise titanium. The seed layer SLa may be formed using, for example, sputtering, Physical Vapor Deposition (PVD), or the like. In some embodiments, the thickness Ta of the seed layer SLa is greater than 0 angstroms and less than or substantially equal to 2 kiloangstroms. In some embodiments, the seed layer SLa is conformally formed as a thin layer of titanium over the semiconductor die 130 and the insulating seal 140'. As depicted in fig. 4, in some embodiments, the seed layer SLa is in physical contact with the via 130d of the semiconductor die 130 and the top surface 140t of the insulating seal 140'.

Continuing with fig. 4, in some embodiments, a seed layer SLb is formed on the seed layer SLa. For example, the seed layer SLb is formed on the seed layer SLa in the form of a blanket layer made of a metal or metal alloy material, to which the present disclosure is not limited. In the present disclosure, the seed layer SLb is referred to as a metal seed layer. In some embodiments, the material of the seed layer SLb may include copper. The seed layer SLb may be formed using, for example, sputtering, PVD, or the like. In some embodiments, the thickness Tb of the seed layer SLb is greater than 0 angstroms and less than or substantially equal to 10 kiloangstroms. In some embodiments, the seed layer SLb is conformally formed as a thin layer of copper on the seed layer SLa. As depicted in fig. 4, in some embodiments, the seed layer SLb is in physical contact with the seed layer SLa. That is, for example, the seed layer SLa is interposed between the insulating seal 140' and the seed layer SLb and between the semiconductor die 130 and the seed layer SLb.

In some embodiments, the sum of the thickness Ta of the seed layer SLa and the thickness Tb of the seed layer SLb is approximately in the range of 0.1 kiloangstrom to 12 kiloangstrom. In one embodiment, the thickness Tb of the seed layer SLb is greater than the thickness Ta of the seed layer SLa. In another embodiment, the thickness Tb of the seed layer SLb is substantially equal to the thickness Ta of the seed layer SLa. In other words, the thickness Ta of the seed layer SLa is smaller than the thickness Tb of the seed layer SLb.

As shown in fig. 4, in some embodiments, a resist layer PR is formed on the seed layer SLb, wherein the resist layer PR, for example, comprises at least one opening OP. In some embodiments, as illustrated in fig. 4, a plurality of openings OP are formed in the resist layer PR. As illustrated in fig. 4, portions of the seed layer SLb are respectively exposed by the openings OP formed in the resist layer PR. The number of openings OP may, for example, correspond to the number of conductive structures (e.g., conductive pillars, vias, conductive traces or conductive segments) to be formed later. As depicted in fig. 4, for example, the positional location of at least a portion of the opening OP corresponds to (e.g., overlaps) the positional location of the via 130d of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3. In one embodiment, the resist layer PR may be formed by a coating and photolithography process or the like; however, the present disclosure is not limited thereto. In some embodiments, the material of the resist layer PR comprises, for example, a positive resist material or a negative resist material suitable for a patterning process, such as a photolithography process using a mask or a maskless photolithography process (e.g., electron beam (e-beam) writing or ion beam writing). In the present disclosure, the resist layer PR is referred to as a photoresist layer.

Referring to fig. 5, in some embodiments, a metallization layer 154-1 is formed over the seed layer SLb and in the opening OP of the resist layer PR. In some embodiments, the material of the metallization layer 154-1 may comprise a metallic material, such as copper or a copper alloy or the like. Throughout the description, the term "copper" is intended to include copper as a substantially pure element, copper containing unavoidable impurities, and copper alloys containing trace elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium, among others. The number of patterns of the metallization layer 154-1 may be selected based on requirements and adjusted by varying the number of openings OP. In some embodiments, the metallization layer 154-1 is formed by a plating process.

For example, the metallization layer 154-1 is formed by forming a metal material filling the opening OP in the resist layer PR by Electroplating (ECP), wherein metal ions in a plating solution are deposited on a target object as a result of an electric current passing through the target object (e.g., the seed layer SLb exposed by the opening OP) and into the plating solution (also referred to as a plating bath) such that the metal ions in the plating solution migrate to the surface of the target object. In some embodiments, the formation of the metallization layer 154-1 may include the following steps: providing an anode (indicated at 11 in FIG. 21) placed in a plating bath tank (indicated at 10 in FIG. 21) filled with a plating solution (indicated at 13 in FIG. 21); the structure depicted in fig. 4 (acting as a cathode and labeled 12 in fig. 21) is placed into a plating solution 13; and applying a voltage from a power source (labeled 14 in fig. 21) to the structure depicted in fig. 4 (e.g., cathode 12) and anode 11, respectively, to electrodeposit at the exposed seed layer SLb of the structure depicted in fig. 4 for an electroplating process.

The anode is, for example, of the same material as the metallization layer 154-1, such as copper. In an electroplating process, the structure and anode depicted in fig. 4 are immersed in a plating solution containing ions that permit the flow of electricity. In some embodiments, the voltage applied to the anode is a positive voltage, while the voltage applied to the structure depicted in fig. 4 (acting as a cathode) is a lower voltage relative to the voltage applied to the anode. After a positive voltage is applied to the anode, the copper in the anode oxidizes by losing two electrons, which allows the copper to dissolve in the plating solution in the form of metal ions (cationic Cu2 +). After a lower voltage is applied to the structure depicted in fig. 4 (acting as a cathode), the dissolved metal ions in the plating solution (cationic Cu2+) are reduced to metallic copper located on the structure depicted in fig. 4 (e.g., exposed seed layer SLb) by gaining two electrons. As a result, copper is transferred from the anode to the structure depicted in fig. 4, i.e., the formation of the metallization layer 154-1 on the exposed seed layer SLb, as depicted in fig. 5. The rate of anodic dissolution is substantially equal to the plating rate of the structure depicted in fig. 4 (e.g., the exposed seed layer SLb). In some embodiments, the structure depicted in fig. 4 (acting as a cathode) and the anode may be rotated at a plating rotation speed (plating rotation speed) after (or before, while) being immersed in the plating solution to prevent entrainment of bubbles on the plating surface of the exposed seed layer SLb of the structure depicted in fig. 4, thereby ensuring uniformity of plating and averaging out possible disturbances, and increasing the electrolyte (electrolyte) transferred to the structure depicted in fig. 4.

For example, the plating solution for plating copper includes chlorous acid (HCl), copper sulfate (CuSO4), sulfuric acid (H2SO4), and a first additive. The sulfuric acid dissociates copper ions from the copper sulfate, allowing the copper sulfate to migrate to the exposed seed layer SLb and form a copper plate, while the chloride ions prevent the formation of copper oxide by the reaction between the copper ions in the plating solution and oxygen (O2) in the environment. In some embodiments, the amount of chloride ion in the plating solution is in the range of about 5 volume concentration (ppm) to 100 ppm. In some embodiments, the concentration of copper sulfate in the plating solution is in a range from about 5 grams per liter (g/L) to about 300 g/L. In some embodiments, the concentration of sulfuric acid in the plating solution is in the range of about 10 grams/liter to about 200 grams/liter.

In some embodiments, the first additive comprises a compound represented by the formula,

wherein R1 and R2 are independently selected from the group consisting of substituted or unsubstituted aromatic groups and substituted or unsubstituted heteroaromatic groups, and n is an integer from 5 to 250. In some embodiments, the first additive has a weight average molecular weight (Mw) in the range of about 200 to 10,000. For example, the concentration of the first additive in the plating solution is in a range of about 0.2 milliliters per liter (gL/L) to about 20 ml/L.

In the present disclosure, the first additive may be referred to as an inhibitor (suppressor), wherein the first additive prevents growth of copper oriented (original) at (111) copper lattice planes (e.g., second strip structures 320 in fig. 7A) but promotes growth of copper oriented (220) at copper lattice planes (e.g., first strip structures 310 in fig. 7A) in forming the metallization layer 154-1 by a plating process (e.g., ECP). In some embodiments, each pattern of the metallization layer 154-1 has a plurality of copper grains (copper grains) 300 by a plating process, and the copper grains 300 each have a columnar shape (e.g., a columnar structure) extending along the stacking direction Z, as depicted in the enlarged cross-sectional view of fig. 7A. For example, each copper die 300 is formed in a pillar structure by stacking the first strip structure 310 and the second strip structure 320 in the stacking direction Z. In some embodiments, for the metallization layer 154-1, a ratio of the number of first strip structures 310 to the number of second strip structures 320 is about less than or substantially equal to 0.4 and about less than 1.0. In other words, in each copper die 300, the number of first strip-shaped structures 310 is greater than the number of second strip-shaped structures 320. Due to the first additive, the growth orientation of copper grains 300 in the metallization layer 154-1 may be fine-tuned by the first additive, wherein copper ions are provided on the exposed seed layer SLb by (220) crystallization.

For example, the first and second ribbon structures 310 and 320 individually have a first dimension measured along the direction X and a second dimension measured along the stacking direction Z, wherein the first dimension is greater than the second dimension, as depicted in fig. 7A. In the present disclosure, the first dimension may be referred to as a width and the second dimension may be referred to as a height, taking into account the geometry of the copper grains 300. That is, for each copper die 300, the width W300 of the copper die 300 corresponds to the width of a respective one of the first strip-shaped structures 310 or the width of a respective one of the second strip-shaped structures 320 of the copper die 300, wherein the width of the respective one of the first strip-shaped structures 310 or the width of the respective one of the second strip-shaped structures 320 is the largest width compared to the other first strip-shaped structures 310 and second strip-shaped structures 320 in the copper die 300. In some embodiments, copper grains 300 have a width W300 approximately in the range of 0.1 microns to 1.5 microns.

As shown in fig. 7A and 7B, in some embodiments, each of the copper grains 300 is physically connected at its grain boundary GB with its immediately adjacent neighboring copper grains 300, and thus the copper grains 300 in each pattern of the metallization layer 154-1 are electrically coupled to each other. The microstructure of the metallization layer 154-1 is improved due to the growth orientation of the copper grains 300 in the metallization layer 154-1, thereby reducing voids therein. Since the copper grains 300 each have a columnar shape and more than 50% of the strip-like structures (e.g., the total number of the first strip-like structures 310 and the second strip-like structures 320) included in each copper grain 300 have copper atoms oriented on the (220) copper lattice plane, the metallization layer 154-1 has higher thermal stability and improved mechanical properties (e.g., better toughness, tensile strength, and elongation), which improves its electromagnetic behavior; thereby enhancing the reliability of the package structure P1. Furthermore, the growth orientation of the copper grains 300 in the metallization layer 154-1 may be further adjusted by controlling the ratio of the thickness Tb to the thickness Ta to be greater than or substantially equal to 1, making the copper ions more prone to be disposed on the exposed seed layer SLb by (220) crystallization than by (111) crystallization.

In some embodiments, suitable plating conditions for performing the above electroplating process include a plating rotation speed of about 30 revolutions per minute (rpm) to about 500 rpm, a plating current density of about 0.5 amperes per square decimeter (ASD) to about 30 amperes per square decimeter, a plating bath pH of about 0.5 to about 3.5, a workable bath temperature of about 20 ℃ to about 50 ℃, and a workable bath pressure of about 1 atm. Further, the workable working gas of the above electroplating process may include air or nitrogen (N2), and the present disclosure is not limited thereto.

In some embodiments, the plating solution may further include additional second additives, such as brighteners (also referred to as accelerators), levelers, and suppressors. For example, the brightener may comprise bis (3-sulfopropyl) disulfide (bis (3-sulfopropyl) disulfide), 3-mercapto-propanesulfonic acid (3-capto-propylsulfonic acid), 3-mercapto-propanesulfonic acid- (3-sulfopropyl) ester (3-capto-propylsulfonic acid- (3-sulfopropyl) ester), or the like. In some embodiments, the concentration of the brightener may be in the range of about 0 ml/l to about 50 ml/l. For example, the leveling agent may comprise alkylated polyalkyleneimine (alkylated polyalkyleneimine), 2-mercaptothiazoline (2-mercaptothiazoline), or the like. In some embodiments, the concentration of the leveler may be in the range of approximately 0 ml/l to 50 ml/l. For example, the inhibitor may comprise polyalkylene glycol, polyoxyalkylene glycol, copolymer of polyoxyalkylene, or the like. In some embodiments, the concentration of inhibitor may be in the range of about 0 ml/l to about 50 ml/l. The present disclosure is not limited thereto.

Referring to fig. 5 and 6, in some embodiments, after the formation of metallization layer 154-1, resist layer PR is removed from the structure depicted in fig. 5. In some embodiments, the resist layer PR is removed to expose the seed layer SLb not covered by the metallization layer 154-1. In one embodiment, the resist layer PR is removed by an acceptable ashing process and/or photoresist stripping process (e.g., using oxygen plasma or the like), and the disclosure is not limited thereto.

In some embodiments, seed layer SLb and seed layer SLa are sequentially patterned to form seed layer 153-1 and seed layer 152-1, respectively. Seed layer 152-1 and seed layer 153-1 are also referred to as metal seed layers. In some embodiments, portions of seed layer SLb not covered by metallization layer 154-1 (depicted in fig. 5) are removed to form seed layer 153-1, and portions of seed layer SLa corresponding to the removed portions of seed layer SLb are likewise removed to form seed layer 152-1. In other words, seed layer 152-1 shares the same geometry in a top view (e.g., in an X-Y plane) as seed layer 153-1.

In some embodiments, the patterning process may be performed by etching, wherein the seed layers SLa, SLb are etched by using the metallization layer 154-1 as an etch mask to form the seed layers 152-1, 153-1. That is, for example, metallization layer 154-1, seed layer 152-1, and seed layer 153-1 share the same geometry in a top view (e.g., in an X-Y plane). For example, the etch process may include a dry etch process or a wet etch process. As depicted in fig. 6, for example, seed layers 152-1, 153-1 each include one or more conductive segments that are physically and electrically isolated from each other. In some embodiments, the conductive segments of seed layer 152-1 are physically and electrically connected to a respective one of the conductive segments of seed layer 153-1, and the conductive segments of seed layer 153-1 are each physically and electrically connected to a respective one of the patterns of metallization layer 154-1, as depicted in FIG. 6. In the present disclosure, one pattern of metallization layer 154-1, a respective one of the conductive segments of seed layer 153-1, and a respective one of the conductive segments of seed layer 152-1 are collectively referred to as conductive pattern CP 1. In some embodiments, in each of the conductive patterns CP1, the sidewalls of metallization layer 154-1 are aligned with the sidewalls of the respective seed layer 152-1 and the sidewalls of the respective seed layer 153-1. As depicted in fig. 6, seed layer 152-1 is sandwiched between semiconductor die 130 and seed layer 153-1, and seed layer 153-1 is sandwiched between seed layer 152-1 and metallization layer 154-1. For example, metallization layer 154-1 is electrically connected to semiconductor die 130 through seed layer 152-1 and seed layer 153-1. For example, seed layer 153-1 is electrically connected to semiconductor die 130 through seed layer 152-1, and metallization layer 154-1 is electrically connected to seed layer 152-1 through seed layer 153-1.

Referring to fig. 8, in some embodiments, a layer of dielectric material DI is formed over the metallization layer 154-1, the semiconductor die 130, and the insulating seal 140'. The dielectric layer DI is formed by, but is not limited to, forming a blanket layer of dielectric material over the structure depicted in fig. 6 to completely cover the metallization layer 154-1 and the semiconductor die 130 and insulating seal 140' exposed by the metallization layer 154-1 and the seed layer 152-1, the seed layer 153-1. In some embodiments, the material of the dielectric material layer DI may be polyimide, PBO, BCB, nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, or the like. In some embodiments, the dielectric material layer DI may be formed by a suitable manufacturing technique, such as spin-on coating, Chemical Vapor Deposition (CVD) (e.g., Plasma Enhanced Chemical Vapor Deposition (PECVD)), or the like. As illustrated in fig. 8, the conductive pattern CP1 (including the seed layer 152-1, the seed layer 153-1, and the metallization layer 154-1) is embedded in the dielectric material layer DI and is not exposed to the dielectric material layer DI in a accessible manner.

Referring to fig. 9, in some embodiments, a planarization step is performed on the dielectric material layer DI to form a dielectric layer 151-1. For example, the dielectric material layer DI may be planarized by mechanical grinding or CMP. In some embodiments, the top surface S151-1 of the dielectric layer 151-1 is substantially flush with the top surface S154-1 of the metallization layer 154-1. That is, the top surface S151-1 of the dielectric layer 151-1 and the top surface S154-1 of the metallization layer 154-1 are substantially coplanar with each other. As depicted in fig. 9, a top surface of the conductive pattern CP1 (e.g., the top surface S154-1 of the metallization layer 154-1) is exposed in a touchable manner by the dielectric layer 151-1 and is substantially coplanar with the dielectric layer 151-1.

The metallization layer 154-1 may also be partially planarized during the planarization of the dielectric material layer DI. As illustrated in fig. 9, for example, the sidewalls of the metallization layer 154-1 and the seed layer 152-1, the seed layer 153-1 are wrapped by the dielectric layer 151-1 (wrap around), and the top surface S154-1 of the metallization layer 154-1 is exposed by the dielectric layer 151-1. After the planarization step, a cleaning step may optionally be performed, for example, to clean and remove residues resulting from the planarization step. However, the present disclosure is not so limited and the planarization step may be performed by any other suitable method. In the present disclosure, the film layers formed in fig. 4-9, such as dielectric layer 151-1 and conductive pattern CP1 (including seed layer 152-1, seed layer 153-1, and metallization layer 154-1), may be referred to as a first build-up layer RDL1 of redistribution circuit structure 150.

Referring to fig. 10, in some embodiments, a dielectric layer 151-2, a seed layer 152-2, a seed layer 153-2, a metallization layer 154-2a, and a metallization layer 154-2b are sequentially formed on the first build-up RDL1 of the redistribution circuit structure 150. The formation and material of dielectric layer 151-2 is the same as or similar to the formation and material of dielectric layer 151-1, the formation and material of seed layer 152-2 is the same as or similar to the formation and material of seed layer 152-1, the formation and material of seed layer 153-2 is the same as or similar to the formation and material of seed layer 153-1, and the formation and material of metallization layer 154-2a and metallization layer 154-2b is the same as or similar to the formation and material of metallization layer 154-1; and therefore are not repeated herein for simplicity. It should be noted that in the present disclosure, the plating process of metallization layer 154-2b shares the same seed layer (e.g., seed layer 152-2, seed layer 153-2) as the plating process of metallization layer 154-2a, where resist layers having different sized openings are used in the formation of metallization layer 154-2a and metallization layer 154-2 b. The above materials and formation of the resist layer having openings of different sizes are the same as or similar to those of the resist layer PR, and thus are not repeated herein.

In some embodiments, one pattern of metallization layer 154-2a, a respective one conductive segment of seed layer 152-2, and a respective one conductive segment of seed layer 153-2 are collectively referred to as conductive pattern CP2a, and one pattern of metallization layer 154-2a, a respective one pattern of metallization layer 154-2b, a respective one conductive segment of seed layer 152-2, and a respective one conductive segment of seed layer 153-2 are collectively referred to as conductive pattern CP2 b. In some embodiments, for each of conductive pattern CP2a and conductive pattern CP2b, the sidewalls of metallization layer 154-2a are aligned with the sidewalls of respective seed layer 152-2 and the sidewalls of respective seed layer 153-2. In other words, for each of conductive pattern CP2a and conductive pattern CP2b, metallization layer 154-2a, seed layer 153-2, and seed layer 152-2 share the same geometry in the X-Y plane. As depicted in fig. 10, in some embodiments, for each of the conductive patterns CP2b, the protruding area of metallization layer 154-2b is smaller than the protruding area of metallization layer 154-2a, wherein metallization layer 154-2b completely overlaps metallization layer 154-2a in the stacking direction Z in the X-Y plane.

As depicted in fig. 10, in some embodiments, the seed layer 152-2 is located directly on the top surface S154-1 of the metallization layer 154-1 and is sandwiched between the seed layer 153-2 and the metallization layer 154-1, the seed layer 153-2 is located directly on the seed layer 152-2 and is sandwiched between the seed layer 152-2 and the metallization layer 154-2a, and the metallization layer 154-2a is located directly on the seed layer 153-2 and is sandwiched between the seed layer 153-2 and the metallization layer 154-2b or is sandwiched between the seed layer 153-2 and the dielectric layer 151-2. In some embodiments, metallization layer 154-2b (if present) is located directly on metallization layer 154-2 a. For example, seed layer 153-2 is electrically connected to metallization layer 154-1 through seed layer 152-2, and metallization layer 154-2a is electrically connected to seed layer 152-2 through seed layer 153-2. For example, metallization layer 154-2b is electrically connected to metallization layer 154-2a by a physical connection.

As illustrated in fig. 10, for example, the metallization layer 154-2a is embedded in the dielectric layer 151-2, while the metallization layer 154-2b is exposed by the dielectric layer 151-2. In some embodiments, the top surface S154-2b of the metallization layer 154-2b is exposed by the dielectric layer 151-2. For example, the top surface S154-2b of the metallization layer 154-2b is substantially flush with the top surface S151-2 of the dielectric layer 151-2. In some embodiments, as depicted in FIG. 10, the top surface S154-2b of the metallization layer 154-2b and the top surface S151-2 of the dielectric layer 151-2 are substantially coplanar with each other. That is, the top surface of the conductive pattern CP2a (e.g., the top surface of the metallization layer 154-2 a) is not exposed to be accessible by the dielectric layer 151-2, while the top surface of the conductive pattern CP2b (e.g., the top surface S154-2b of the metallization layer 154-2b) is exposed to be accessible by the dielectric layer 151-2 and is substantially coplanar with the dielectric layer 151-2. In the present disclosure, the film layer (e.g., dielectric layer 151-2, conductive pattern CP2a (each including metallization layer 154-2a, seed layer 153-2, and seed layer 152-2) and conductive pattern CP2b (each including metallization layer 154-2b, metallization layer 154-2a, seed layer 153-2, and seed layer 152-2)) may be referred to as a second build-up RDL2 of the redistribution circuit structure 150.

Referring to FIG. 11, in some embodiments, a dielectric layer 151-3, a seed layer 152-3, a seed layer 153-3, and a metallization layer 154-3 are sequentially formed on the second build-up RDL2 of the redistribution circuit structure 150. The formation and material of dielectric layer 151-3 is the same as or similar to the formation and material of dielectric layer 151-1, the formation and material of seed layer 152-3 is the same as or similar to the formation and material of seed layer 152-1, the formation and material of seed layer 153-3 is the same as or similar to the formation and material of seed layer 153-1, and the formation and material of metallization layer 154-3 is the same as or similar to the formation and material of metallization layer 154-1; and therefore are not repeated herein.

In some embodiments, one pattern of metallization layer 154-3, a respective one of the conductive segments of seed layer 152-3, and a respective one of the conductive segments of seed layer 153-3 are collectively referred to as conductive pattern CP 3. In some embodiments, as depicted in fig. 11, for each of conductive patterns CP3, the sidewalls of metallization layer 154-3 are aligned with the sidewalls of respective seed layer 152-3 and the sidewalls of respective seed layer 153-3. In other words, for each of the conductive patterns CP3, metallization layer 154-3, seed layer 153-3, and seed layer 152-3 share the same geometry in the X-Y plane.

As shown in fig. 11, in some embodiments, seed layer 152-3 is located directly on metallization layer 154-2b and is sandwiched between seed layer 153-3 and metallization layer 154-2b, seed layer 153-3 is located directly on seed layer 152-3 and is sandwiched between seed layer 152-3 and metallization layer 154-3, and metallization layer 154-3 is located directly on seed layer 153-3 and is sandwiched between seed layer 153-3 and dielectric layer 151-3. In some embodiments, seed layer 153-3 is electrically connected to metallization layer 154-2b through seed layer 152-3, and metallization layer 154-3 is electrically connected to seed layer 152-3 through seed layer 153-3, as depicted in fig. 11.

In some embodiments, the dielectric layer 151-3 includes a plurality of openings O1 that expose at least a portion of the metallization layer 154-3. That is, for example, a top surface S154-3 of a portion of the metallization layer 154-3 is at least partially exposed by the opening O1 formed in the dielectric layer 151-3. The number of openings O1 is not limited to the number depicted in fig. 11 and may be selected and specified based on requirements; the present disclosure is not limited thereto. As depicted in fig. 11, in some embodiments, a top surface of the conductive pattern CP3 (e.g., a top surface S154-3 of a portion of the metallization layer 154-3) is exposed in a manner that is accessible by the dielectric layer 151-3. In the present disclosure, the film layer (e.g., dielectric layer 151-3 and conductive pattern CP3 (each including metallization layer 154-3, seed layer 153-3, and seed layer 152-3)) may be referred to as a third build-up RDL3 of redistribution circuit structure 150.

Referring to fig. 12, in some embodiments, a dielectric layer 151-4, a seed layer 152-4, a seed layer 153-4, and a metallization layer 154-4 are sequentially formed on the third build-up RDL3 of the redistribution circuit structure 150. The formation and material of dielectric layer 151-4 is the same as or similar to the formation and material of dielectric layer 151-1, the formation and material of seed layer 152-4 is the same as or similar to the formation and material of seed layer 152-1, the formation and material of seed layer 153-4 is the same as or similar to the formation and material of seed layer 153-1, and the formation and material of metallization layer 154-4 is the same as or similar to the formation and material of metallization layer 154-1; and therefore are not repeated herein.

In some embodiments, one pattern of metallization layer 154-4, a respective one of the conductive segments of seed layer 152-4, and a respective one of the conductive segments of seed layer 153-4 are collectively referred to as conductive pattern CP 4. In some embodiments, as depicted in fig. 12, for each of conductive patterns CP4, the sidewalls of metallization layer 154-4 are aligned with the sidewalls of respective seed layer 152-4 and the sidewalls of respective seed layer 153-4. In other words, for each of the conductive patterns CP4, metallization layer 154-4, seed layer 153-4, and seed layer 152-4 share the same geometry in the X-Y plane.

As shown in fig. 12, in some embodiments, seed layer 152-4 is located directly on metallization layer 154-3 and is sandwiched between seed layer 153-4 and metallization layer 154-3, seed layer 153-4 is located directly on seed layer 152-4 and is sandwiched between seed layer 152-4 and metallization layer 154-4, and metallization layer 154-4 is located directly on seed layer 153-4 and is sandwiched between seed layer 153-4 and dielectric layer 151-4. In some embodiments, seed layer 153-4 is electrically connected to metallization layer 154-3 through seed layer 152-4, and metallization layer 154-4 is electrically connected to seed layer 152-4 through seed layer 153-4, as depicted in fig. 12.

In some embodiments, the dielectric layer 151-4 includes a plurality of openings O2 that expose portions of the metallization layer 154-4 for electrical connections to later-formed connections or semiconductor devices. That is, for example, at least a portion of the top surface S154-4 of the metallization layer 154-4 is exposed by the opening O2 formed in the dielectric layer 151-4. The number of openings O2 is not limited to the number depicted in fig. 12 and may be selected and specified based on requirements; the present disclosure is not limited thereto. As depicted in fig. 12, in some embodiments, a top surface of the conductive pattern CP4 (e.g., a top surface S154-4 of at least a portion of the metallization layer 154-4) is exposed in a manner that is accessible by the dielectric layer 151-4. In the present disclosure, the film layer (e.g., dielectric layer 151-4 and conductive pattern CP4 (each including metallization layer 154-4, seed layer 153-4, and seed layer 152-4)) may be referred to as a fourth build-up RDL4 of redistribution circuit structure 150. At this time, the manufacturing of the rewiring circuit structure 150 of the package structure P1 is completed. In some embodiments, the conductive patterns CP1, CP2, CP3, CP4 may independently act as vias (referred to as via patterns) or conductive traces (referred to as wiring patterns) for providing a routing function for the package structure P1.

Continuing, in fig. 12, for example, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are in electrical communication with each other through redistribution circuit structure 150. For purposes of illustration, four build-up layers are included in the re-routing circuit structure 150 of FIG. 12 (e.g., one layer each for each of the first, second, third, and fourth build-up layers RDL1, RDL2, RDL3, and RDL 4); however, the present disclosure is not limited thereto. The number of first build-up layers RDL1, second build-up layers RDL2, third build-up layers RDL3, and fourth build-up layers RDL4 included in the rewiring circuit structure 150 is not limited in this disclosure. For example, the number of first build-up RDL1 and second build-up RDL2 included in the rewiring circuit structure 150 may be one or more than one, while the number of third build-up RDL3 and fourth build-up RDL4 included in the rewiring circuit structure 150 may be zero, one, or more than one.

Referring to fig. 13, in some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are formed over the redistribution circuit structure 150. In some embodiments, seed layer patterns 160 are each located between a respective one of conductive elements 170 and dielectric layer 151-4/conductive pattern CP4 of rerouted circuit structure 150. Due to the seed layer pattern 160, the adhesive strength between the conductive element 170 and the re-wiring circuit structure 150 is enhanced. In some embodiments, the seed layer pattern 160 is located directly on the portion of the metallization layer 154-4 exposed by the opening O2 formed in the dielectric layer 151-4. As illustrated in fig. 13, in some embodiments, the seed layer pattern 160 is electrically connected to the redistribution circuit structure 150, and the conductive element 170 is electrically connected to the redistribution circuit structure 150 through the seed layer pattern 160.

In some embodiments, the conductive element 170 is electrically connected to the semiconductor die 130 through the rerouting circuit structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-1 by respective ones of the rerouting circuit structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-2 by respective ones of the rerouting circuit structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-3 by corresponding ones of the rerouting circuit structure 150 and the seed layer pattern 160.

In some embodiments, the seed layer pattern 160 is formed by (but not limited to) the following steps: forming a blanket layer (not shown) of seed layer material on the dielectric layer 151-4; forming conductive elements 170 on the blanket layer of seed layer material; the blanket layer of seed layer material is patterned by using the conductive elements 170 as a mask. For example, a blanket layer of seed layer material is conformally formed over dielectric layer 151-4 and extends into opening O2 formed in dielectric layer 151-4 to physically and electrically contact metallization layer 154-4 exposed by opening O2, wherein the sidewalls of opening O2 are completely covered by the blanket layer of seed layer material. In some embodiments, the blanket layer of seed layer material is referred to as a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the blanket layer of seed layer material may comprise titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the blanket layer of seed layer material may comprise a titanium layer and a copper layer over the titanium layer. The blanket layer of seed layer material may be formed using, for example, sputtering, PVD, or the like.

In some embodiments, the formation of the conductive element 170 may be formed by: forming a patterned photoresist layer (not shown) having a plurality of openings exposing portions of the blanket layer of seed layer material by photolithography; and immersing the entire structure including the patterned photoresist layer formed thereon into a plating solution to plate the conductive element 170 on the blanket layer of seed layer material, the conductive element 170 corresponding in position to the portion of the blanket layer of seed layer material exposed by the opening formed in the patterned photoresist layer. In one embodiment, the patterned photoresist layer may be formed by a coating and photolithography process or the like. In some embodiments, the formation and material of the patterned photoresist layer may be the same as or similar to the formation and material of the resist layer PR described in fig. 4, for example. As a result of patterning the photoresist layer, the size and number of conductive elements 170 can be modified by adjusting the size and number of openings in the patterned photoresist layer. As depicted in fig. 13, the conductive element 170 includes, for example, a copper pillar, a copper via, or the like; the present disclosure is not limited thereto.

After the conductive elements 170 are formed, the patterned photoresist layer is removed to expose the blanket layer of seed layer material that is not covered by the conductive elements 170. In one embodiment, the patterned photoresist layer is removed by an acceptable ashing process and/or photoresist stripping process (e.g., using an oxygen plasma or the like), and the disclosure is not limited thereto.

In some embodiments, the blanket layer of seed layer material is patterned to form seed layer pattern 160 by using conductive element 170 as an etch mask. For example, the etching process may be a dry etching process, a wet etching process, or a combination thereof; the present disclosure is not limited thereto. In other words, the blanket layer of seed layer material not covered by the conductive elements 170 is removed to form the seed layer pattern 160. In some embodiments, as depicted in fig. 13, sidewalls of the seed layer pattern 160 are aligned with sidewalls of a respective one of the conductive elements 170.

Referring to fig. 14, in some embodiments, the entire structure depicted in fig. 13 is flipped (upside down) along with the carrier 112, with the conductive elements 170 placed to the holding devices HD, and then the carrier 112 is peeled off the buffer layer 116. In some embodiments, the holding device HD may be a tape (tape), a carrier film (carrier film), or a suction pad (suction pad). The present disclosure is not limited thereto.

In some embodiments, the buffer layer 116 is easily separated from the carrier 112 due to the exfoliation layer 114. In some embodiments, the carrier 112 is detached from the buffer layer 116 by a peeling process, and the carrier 112 and the peeling layer 114 are removed. In some embodiments, the buffer layer 116 is exposed, as illustrated in fig. 14. In one embodiment, the lift-off process is a laser lift-off process. During the peeling step, the holding device HD is used to fix the package structure P1 before peeling the carrier 112 and the peeling layer 114.

Referring to fig. 15, in some embodiments, the conductive element 170 is released from the holding device HD to form a package structure P1. In some embodiments, prior to releasing conductive element 170 from holding device HD, a singulation process is performed to cut the plurality of package structures P1 interconnected therebetween into individual and separate plurality of package structures P1. In one embodiment, the dicing (singulation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. The present disclosure is not limited thereto. At this point, the manufacture of the package structure P1 is completed.

However, the present disclosure is not limited thereto. In alternative embodiments, the conductive elements 170 may be replaced by conductive elements 180 including solder balls or Ball Grid Array (BGA) balls, see package structure P2 depicted in FIG. 16. In the case of the embodiment in which the conductive elements 180 are solder balls or BGA balls as illustrated in fig. 16, the seed layer pattern 160 is replaced by an under-ball metal (UBM) pattern u1 to prevent the solder material from diffusing from the conductive elements 180 to the rewiring circuit structure 150, thereby ensuring the performance of the package structure P2. In some embodiments, for example, the material of the UBM pattern u1 may include copper, nickel, titanium, tungsten, or alloys thereof, or the like, and may be formed in a multi-layer manner (e.g., with different materials in any two adjacent layers in the UBM pattern u 1) by an electroplating process. The number of UBM patterns u1 is not limited in this disclosure.

In other alternative embodiments, a plurality of inter-layer via TIVs may be further included, see package structure P3 depicted in fig. 17. In some embodiments, the inter-layer puncture TIV may be an integrated fan-out (INFO) puncture. With the embodiment including an inter-layer via TIV as depicted in fig. 17, where the inter-layer via TIV is arranged alongside the semiconductor die 130 along direction X (and direction Y) and embedded in the insulating seal 140'. For simplicity, only two inter-layer perforated TIVs are presented in fig. 17 for illustrative purposes, however, it should be noted that the number of inter-layer perforated TIVs may be less than two or greater than two; the present disclosure is not limited thereto. The number of inter-layer perforated TIVs to be formed may be selected based on requirements. For example, as shown in fig. 17, the conductive element 170 may be replaced by a conductive element 180 including a solder ball or a BGA ball, and the seed layer pattern 160 is replaced by a UBM pattern u 1; however, the present disclosure is not limited thereto.

In some embodiments, both ends of each of the interlayer via TIVs are exposed through the insulating seal 140'. For example, an inter-layer perforated TIV is sandwiched between buffer layer 116 and rerouting circuit structure 150, wherein a first end of each of the inter-layer perforated TIVs is physically connected to rerouting circuit structure 150, and the inter-layer perforated TIVs are electrically connected to semiconductor die 130 through rerouting circuit structure 150. For example, the inter-layer via TIV is formed on the buffer layer 116 by photolithography, plating, a photoresist stripping process, or any other suitable method. In one embodiment, the inter-layer perforated TIV may be formed by (but is not limited to) the following steps: forming a mask pattern (not shown) covering the buffer layer 116, the mask pattern having a plurality of openings exposing portions of the buffer layer 116; forming a metal material filling the plurality of openings to form an inter-layer via TIV by electroplating (e.g., a plating process described in fig. 5) or deposition; and then removing the mask pattern. For example, the material of the inter-layer perforated TIV may include a metal material such as copper or a copper alloy, or the like. However, the present disclosure is not limited thereto.

Continuing with fig. 17, in some embodiments, a plurality of openings (not labeled) are formed in the buffer layer 116 to expose a second end of each of the inter-layer perforated TIVs. The number of openings is not limited in this disclosure and may be specified based on requirements and design layout. In some embodiments, a plurality of conductive elements 190 are respectively formed on the second end of each of the interlayer through holes TIV exposed by the opening, and a plurality of UBM patterns u2 are respectively formed to be located between one of the interlayer through holes TIV and a corresponding one of the conductive elements 190. However, the present disclosure is not so limited, and in alternative embodiments, the UBM pattern u2 may be omitted based on design layout and requirements. The formation and material of the conductive element 190 are the same as or similar to those of the conductive element 180, and the formation and material of the UBM pattern u2 are the same as or similar to those of the UBM pattern u1, and thus are not repeated herein. As depicted in fig. 17, conductive element 190 is electrically connected to semiconductor die 130 through UBM pattern u2, inter-layer via TIV, and rerouting circuit structure 150. For example, after the conductive element 190 is disposed on the inter-layer through-hole TIV, a package structure P3 having a dual-side terminal (dual-side terminal) is realized.

In a further alternative embodiment, additional semiconductor elements (not shown) may be disposed on rerouting circuit structure 150 through seed layer pattern 160 and/or UBM pattern u1 in addition to conductive element 170 in fig. 15 and/or conductive element 180 in fig. 16-17 to be electrically connected to at least one of semiconductor die 130. In some embodiments, the additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in this disclosure and may be specified based on requirements and design layout.

In some embodiments, package structures P1 through P3 may further mount a (semiconductor) circuit substrate (e.g., an organic substrate such as a Printed Circuit Board (PCB) having circuit structures embedded therein), an interposer (interposer), an additional package, a chip/die, or other electronic device, to form a stacked package structure, through conductive elements 170, 180, 190, and/or other additional connections, without limitation to this disclosure. For illustration, the following examples are provided, but the disclosure is not limited thereto.

Fig. 18 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will use the same reference numerals, and certain details or descriptions (e.g., materials, formation processes, positioning configurations, etc.) of the same elements will not be repeated herein. Referring to fig. 18, in some embodiments, a substrate 500 is provided, wherein the package structure P2 depicted in fig. 16 is bonded on the substrate 500 to form a package structure having a stacked structure.

In some embodiments, the substrate 500 includes a plurality of contact pads 510, a plurality of contact pads 520, a plurality of metallization layers 530, and a plurality of vias (not shown). In some embodiments, contact pads 510 and contact pads 520 are distributed on two opposing sides of substrate 500 and exposed for electrical connection with later-formed elements/features, respectively. In some embodiments, metallization layer 530 and vias are embedded in substrate 500 and collectively provide routing functionality for substrate 500, wherein metallization layer 530 and vias are electrically connected to contact pads 510 and contact pads 520. That is, at least some of the contact pads 510 are electrically connected to some of the contact pads 520 through the metallization layer 530 and vias. In some embodiments, the contact pads 510 and the contact pads 520 may comprise metal pads or metal alloy pads. In some embodiments, the material of metallization layer 530 and the vias may be substantially the same as or similar to the material of metallization layer 154, and thus are not repeated herein for simplicity.

In some embodiments, as depicted in fig. 18, package structure P2 depicted in fig. 16 is mounted onto substrate 500 by physically connecting conductive elements 180 and contact pads 510 to form a package structure having a stacked structure, where package structure P2 is physically and electrically connected to substrate 500. The details of package structure P2 are described in fig. 16, and therefore are not repeated herein. In some embodiments, the substrate 500 is referred to as a circuit substrate, such as an organic flexible substrate or a printed circuit board. In such embodiments, conductive elements 180 are, for example, chip connectors or BGA balls. In some embodiments, an underfill (not shown) may be applied to fill the gap between the package structure P2 and the substrate 500, which enhances the bonding strength between the package structure P2 and the substrate 500; thereby improving the reliability of the package structure depicted in fig. 18.

In some embodiments, a plurality of conductive terminals 600 are respectively formed on the substrate 500. As depicted in fig. 18, for example, conductive terminal 600 is connected to contact pad 520 of substrate 500. In other words, the conductive terminal 600 is electrically connected to the substrate 500 through the contact pad 520. Some of the conductive terminals 600 are electrically connected to the package structure P2 (e.g., the semiconductor die 130 contained therein) through contact pads 510 and contact pads 520. In some embodiments, conductive terminals 600 are solder balls or BGA balls, for example. In some embodiments, the package structure P2 is bonded to the substrate 500 by flip chip bonding (flip chip bonding) via contact pads 510 that physically connect the conductive terminals 180 and the substrate 500. However, the present disclosure is not limited thereto; in alternative embodiments, the conductive terminals 600 may be omitted.

Fig. 19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will use the same reference numerals, and certain details or descriptions (e.g., materials, formation processes, positioning configurations, etc.) of the same elements will not be repeated herein. Referring to fig. 19, in some embodiments, a circuit element 200 is provided in which a package structure P2 depicted in fig. 16 is bonded on the circuit element 200 mounted to a substrate 500 to form a package structure having a stacked structure. Details of package structure P2 are described in fig. 16, and details of substrate 500 are described in fig. 18, and therefore are not repeated herein. In some embodiments, the circuit element 200 includes a core portion 210, a plurality of vias 220, a redistribution circuit structure 230, a redistribution circuit structure 240, a plurality of bond pads 254a, a plurality of bond pads 254b, a solder mask layer 252a, and a solder mask layer 252 b.

In some embodiments, the core portion 210 may include a bulk silicon substrate, such as a bulk substrate of monocrystalline silicon, a doped silicon substrate, an undoped silicon substrate, or an SOI substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. In some embodiments, the vias 220 are through-silicon vias that penetrate the core portion 210. In the present disclosure, the circuit element 200 is referred to as an interposer (see fig. 19).

In some embodiments, the rerouting circuit structures 230 and 240 are disposed on two opposite sides of the core portion 210, respectively, as depicted in fig. 19. In some embodiments, the rerouting circuit structures 230 and/or 240 are electrically connected to the vias 220 that penetrate the core portion 210. As depicted in fig. 19, in some embodiments, the core portion 210 with the embedded vias 220 is located between the rerouted circuit structure 230 and the rerouted circuit structure 240. The rewiring circuit structure 230 and the rewiring circuit structure 240 are electrically connected to each other through the via hole 220.

In some embodiments, rerouting circuit structure 230 includes alternately sequentially forming one or more dielectric layers 232 and one or more metallization layers 234, with one metallization layer 234 sandwiched between two dielectric layers 232. As depicted in fig. 19, portions of the top surface of the topmost layer of the metallization layer 234 are exposed by openings formed in the topmost layer of the dielectric layer 232, respectively, to connect with other conductive features, and portions of the bottom surface of the bottommost layer of the metallization layer 234 are exposed by openings formed in the bottommost layer of the dielectric layer 232, respectively, to connect with the vias 220. The number of metallization layers and dielectric layers included in the rewiring circuit structure 230 is not limited thereto, and may be designated and selected based on the needs.

In some embodiments, rerouting circuit structure 240 includes alternately sequentially forming one or more dielectric layers 242 and one or more metallization layers 244, with one metallization layer 244 sandwiched between two dielectric layers 242. As depicted in fig. 19, portions of the top surface of the topmost layer of the metallization layer 244 are exposed by openings formed in the topmost layer of the dielectric layer 242, respectively, to connect with the vias 220, and portions of the bottom surface of the bottommost layer of the metallization layer 244 are exposed by openings formed in the bottommost layer of the dielectric layer 242, respectively, to connect with other conductive features. The number of metallization layers and dielectric layers included in the rewiring circuit structure 240 is not limited thereto, and may be designated and selected based on requirements.

In some embodiments, the material of the dielectric layers 232 and 242 may be PI, PBO, BCB, nitride such as silicon nitride, oxide such as silicon oxide, PSG, BSG, BPSG, combinations thereof, or the like, which may be patterned using photolithography and/or etching processes. In some embodiments, the dielectric layer 232 and the dielectric layer 242 are formed by a suitable fabrication technique, such as spin-on coating, CVD, PECVD, or the like. The present disclosure is not limited thereto. In one embodiment, the dielectric layer 232 and the dielectric layer 242 may be the same material. In alternative embodiments, the material of the dielectric layer 232 and the dielectric layer 242 may be different.

In some embodiments, the material of metallization layers 234 and 244 may be made of a conductive material formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using photolithography and etching processes. In some embodiments, the metallization layers 234 and 244 may be patterned copper layers or other suitable patterned metal layers. In one embodiment, the metallization layer 234 and the metallization layer 244 may be the same material. In alternative embodiments, the metallization layer 234 and the metallization layer 244 may be different materials.

In some embodiments, bond pads 254a are disposed on the surface of the rewiring circuit structure 230 and physically connected to portions of the top surface of the topmost layer of the metallization layer 234 that are exposed by openings formed in the topmost layer of the dielectric layer 232, wherein the bond pads 254a are physically separated from each other by a solder mask layer 252a, the solder mask layer 252a being formed on the surface of the rewiring circuit structure 230 having the bond pads 254a disposed thereon. The bonding pads 254a are electrically connected to the vias 220 embedded in the core portion 210 by the re-routing circuit structure 230.

In some embodiments, bond pads 254b are disposed on the surface of the rewiring circuit structure 240 and physically connected to portions of the bottom surface of the bottommost layer of the metallization layer 244 that are exposed by openings formed in the bottommost layer of the dielectric layer 242, wherein the bond pads 254b are physically separated from each other by a solder mask layer 252b, the solder mask layer 252b being formed on the surface of the rewiring circuit structure 240 having the bond pads 254b disposed thereon. The bonding pads 254b are electrically connected to the vias 220 embedded in the core portion 210 by the re-routing circuit structure 240.

As depicted in fig. 19, for example, bond pad 254a is electrically connected to redistribution circuit structure 230 and bond pad 254b is electrically connected to redistribution circuit structure 240. In some embodiments, bonding pads 254a and 254b may comprise Under Bump Metallurgy (UBM) patterns, although the disclosure is not so limited. As illustrated in fig. 19, for example, the bonding pads 254a and 254b are electrically connected to each other through the via holes 220, the redistribution circuit structures 230, and the redistribution circuit structures 240.

In alternative embodiments, the rerouting circuit structures 230 and 240 (one or both) may be omitted from the circuit element 200, and the disclosure is not limited thereto. That is, for example, the circuit element 200 may include a core portion 210, a plurality of vias 220, a plurality of bonding pads 254a, a plurality of bonding pads 254b, a solder mask layer 252a, and a solder mask layer 252b, wherein the bonding pads 254a and the bonding pads 254b are electrically connected to each other through the vias 220.

In some embodiments, a plurality of conductive terminals 400 are respectively formed on the bonding pads 254 b. As depicted in fig. 19, for example, the conductive terminal 400 is physically connected to the bonding pad 254 b. In other words, the conductive terminal 400 is electrically connected to the circuit element 200 through the bonding pad 254 b. Some of the conductive terminals 400 are electrically connected to some of the bonding pads 254a through the bonding pads 254 b. In some embodiments, the conductive terminals 400 are, for example, chip connectors or BGA balls.

Continuing with fig. 19, in some embodiments, the package structure P2 is physically connected to the circuit element 200 by connecting the conductive element 180 with the bond pad 254a of the circuit element 200, and the circuit element 200 is physically connected to the substrate 500 by connecting the conductive terminal 400 with the contact pad 510 of the substrate 500. In other words, the package structure P2 is electrically connected to the circuit element 200 through the conductive element 180 and the bonding pad 254a, and the circuit element 200 is electrically connected to the substrate 500 through the conductive terminal 400 and the contact pad 510, so that the package structure P2 is electrically connected to the substrate 500 through the conductive element 180, the bonding pad 254a, the conductive terminal 400 and the contact pad 510. In such embodiments, conductive elements 180 are, for example, micro-bumps, conductive terminals 400 are chip connectors and conductive terminals 600 are solder balls or BGA balls. In some embodiments, the package structure depicted in FIG. 19 may be formed by a chip on wafer (CoWOS) packaging process on a substrate.

In some embodiments, underfill UF1 is preferably formed on circuit element 200. As depicted in fig. 19, underfill UF1 fills at least the gap between package structure P2 and circuit element 200 and wraps around the sidewalls of conductive element 180, for example. In some alternative embodiments, the sidewalls of package structure P2 may be further covered by underfill UF1, to which the present disclosure is not limited. For example, underfill UF1 may be any acceptable material such as a polymer, epoxy, molded underfill, or the like. In one embodiment, the underfill UF1 may be formed by underfill dispensing (underfil dispensing) or any other suitable method. Due to the underfill UF1, the bonding strength between the package structure P2 and the circuit element 200 is enhanced, thereby improving the reliability of the package structure depicted in fig. 19.

Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will use the same reference numerals, and certain details or descriptions (e.g., materials, formation processes, positioning configurations, etc.) of the same elements will not be repeated herein. Referring to fig. 20, in some embodiments, a package body 800 is provided and the package body 800 is bonded to the package structure P2 depicted in fig. 16 to form a package structure having a stacked structure. The details of package structure P2 are described in fig. 16, and therefore are not repeated herein. In some embodiments, package 800 has a substrate 810, a semiconductor die 820a and a semiconductor die 820b, a plurality of bond wires 830a and a plurality of bond wires 830b, a plurality of conductive pads 840, a plurality of conductive pads 850, an insulating seal 860, and a plurality of solder balls (not shown).

As illustrated in fig. 20, for example, a semiconductor die 820a and a semiconductor die 820b are provided, the semiconductor die 820a having a connection film DA4 disposed thereon and the semiconductor die 820b having a connection film DA5 disposed thereon, and the semiconductor dies 820a, 820b are disposed on a substrate 810. In some embodiments, a connecting film DA4 is located between the semiconductor die 820a and the substrate 810, and a connecting film DA5 is located between the semiconductor die 820a and the semiconductor die 820 b. In some embodiments, the semiconductor dies 820a, 820b are stably adhered to the substrate 810 due to the connection films DA4 and DA5 disposed between the semiconductor die 820a and the substrate 810 and between the semiconductor die 820a and the semiconductor die 820b, respectively. In some embodiments, the connecting films DA4, DA5 may be, for example, die attach films, layers made of adhesives or epoxies, or the like.

For example, semiconductor die 820a and semiconductor die 820b are mounted on one surface of substrate 810 (e.g., surface S1). In some embodiments, the semiconductor die 820a and the semiconductor die 820b may be logic chips (e.g., a central processing unit, a microcontroller, etc.), memory chips (e.g., Dynamic Random Access Memory (DRAM) chips, Static Random Access Memory (SRAM) chips, etc.), power management chips (e.g., Power Management Integrated Circuit (PMIC) chips), Radio Frequency (RF) chips, sensor chips, signal processing chips (e.g., Digital Signal Processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), the like, or combinations thereof). For example, semiconductor die 820a and semiconductor die 820b are DRAM chips, as depicted in fig. 20. In one embodiment, semiconductor die 820a and semiconductor die 820b may be identical. However, the present disclosure is not limited thereto; in alternative embodiments, semiconductor die 820a and semiconductor die 820b may be different from each other.

In some embodiments, bond wires 830a and 830b are used to provide electrical connections between the semiconductor die 820a, 820b and some of the conductive pads 840 (e.g., bond pads) located on the surface S1 of the substrate 810, respectively. Semiconductor die 820a and semiconductor die 820b are electrically connected to substrate 810 due to bond wires 830a and 830 b.

In some embodiments, an insulating seal 860 is formed on surface S1 of substrate 810 to seal semiconductor die 820a, semiconductor die 820b, bond wires 830a, bond wires 830b, and conductive pads 840 to protect these components. In some embodiments, the material of the insulation seal 860 is the same as the insulation seal 140/insulation seal 140', and thus is not repeated herein. In one embodiment, the material of the insulation seal 860 is different than the insulation seal 140/insulation seal 140', to which the present disclosure is not limited.

In some embodiments, an interconnect (not shown) or a through-insulator via (not shown) embedded in the substrate 810 may be used to provide an electrical connection between the conductive pad 840 and a conductive pad 850 (e.g., a bond pad) positioned on another surface of the substrate 810 (e.g., surface S2 opposite surface S1). In some embodiments, some of the conductive pads 850 are electrically connected to the semiconductor die 820a and the semiconductor die 820b through the insulator vias or interconnects (not shown), in addition to through some of the conductive pads 840 and the bond wires 830a, 830 b.

In some embodiments, the conductive pad 850 of the package body 800 is physically connected to the conductive element 180 of the package structure P2, and the package body 800 is electrically connected to the package structure P2. In some embodiments, the rerouting circuit structure 150 is electrically connected to the substrate 810 of the package 800 through the conductive element 180 and the conductive pad 850. In some embodiments, semiconductor die 820a, 820b are electrically communicated to semiconductor die 130 of package structure P2.

Further, as depicted in fig. 20, underfill UF2 fills the gap between conductive element 180 and substrate 810, for example. In one embodiment, the formation and material of the underfill UF2 may be the same as or similar to the formation of the material of the underfill UF1 described in fig. 19, and the disclosure is not limited thereto. Due to underfill UF2, the bonding strength between package structure P2 and package body 800 is enhanced, thereby improving the reliability of the package structure depicted in fig. 20.

In addition, the package structure P2 may be replaced by the package structure P1 depicted in fig. 15 or the package structure P3 depicted in fig. 17, to which the present disclosure is not limited.

According to some embodiments, a package structure includes a semiconductor die and a rerouting circuit structure. The rewiring circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has a plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises a plurality of grains that are each columnar and comprise a plurality of first strip-like structures having a plurality of copper atoms oriented on a (220) lattice plane.

In some embodiments, in the package structure, wherein each of the plurality of dies further comprises a plurality of second strip-like structures having a plurality of copper atoms oriented in a (111) lattice plane. In some embodiments, in the package structure, wherein in each of the plurality of dies, the plurality of first strip structures are stacked on the plurality of second strip structures along a stacking direction of the semiconductor die and the rewiring circuit structure, and wherein the plurality of dies adjacent to each other are in physical contact with each other. In some embodiments, in the package structure, each of the plurality of first strip structures has a first width and a first height smaller than the first width, and each of the plurality of second strip structures has a second width and a second height smaller than the second width, wherein the first width and the second width are measured in a direction perpendicular to the stacking direction, and the first height and the second height are measured in the stacking direction. In some embodiments, in the package structure, a ratio of the number of the plurality of first strip structures to the number of the plurality of second strip structures is about less than or substantially equal to 0.4 and about less than 1.0. In some embodiments, in the package structure, wherein the rerouting circuit structure further comprises: a first metal seed layer; and a second metal seed layer stacked on the first metal seed layer in a stacking direction of the semiconductor die and the rewiring circuit structure, wherein the first metal seed layer is between the semiconductor die and the second metal seed layer, and the second metal seed layer is between the first metal seed layer and the metallization layer. In some embodiments, in the package structure, wherein along the stacking direction, a first thickness of the first metal seed layer is less than or substantially equal to a second thickness of the second metal seed layer. In some embodiments, in the package structure, a grain size of the plurality of grains is approximately in a range of 0.1 microns to 1.5 microns in a direction perpendicular to a stacking direction of the semiconductor die and the redistribution circuit structure. In some embodiments, the package structure further comprises: an insulating seal encapsulating the semiconductor die and located over the rewired circuit structure; and a plurality of first conductive terminals located on the rewiring circuit structure and connected to the rewiring circuit structure, wherein the rewiring circuit structure is located between the insulating encapsulant and the plurality of first conductive terminals. In some embodiments, the package structure further comprises: a plurality of vias penetrating the insulating seal and disposed alongside the semiconductor die, the plurality of vias electrically connected to the semiconductor die through the rerouting circuit structure; and a plurality of second conductive terminals located on and connected to the plurality of through holes, wherein the insulating seal is located between the rewiring circuit structure and the plurality of second conductive terminals.

According to some embodiments, a circuit structure includes a copper conductive layer and a dielectric layer. The copper conductive layer includes a plurality of via patterns and a plurality of wiring patterns, wherein each of the plurality of via patterns and the plurality of wiring patterns includes a plurality of copper crystal grains, the plurality of copper crystal grains each include a plurality of first strip-shaped structures having a plurality of copper atoms oriented on a (220) lattice plane and a plurality of second strip-shaped structures having a plurality of copper atoms oriented on a (111) lattice plane, wherein a ratio of the number of the plurality of first strip-shaped structures to the number of the plurality of second strip-shaped structures is about less than or substantially equal to 0.4 and about less than 1.0. The dielectric layer is disposed on the copper conductive layer and at least partially overlaps the plurality of via patterns and the plurality of wiring patterns.

In some embodiments, in the circuit structure, wherein in each of the plurality of copper crystal grains, the plurality of first strip-shaped structures and the plurality of second strip-shaped structures are randomly stacked on each other in a columnar form along a stacking direction of the copper conductive layer and the dielectric layer, and wherein the plurality of copper crystal grains adjacent to each other are in physical contact with each other. In some embodiments, in the circuit structure, wherein each of the plurality of first strip-shaped structures has a first width and a first height smaller than the first width, and each of the plurality of second strip-shaped structures has a second width and a second height smaller than the second width, wherein the first width and the second width are measured in a direction perpendicular to the stacking direction, and the first height and the second height are measured in the stacking direction. In some embodiments, in the circuit structure, a ratio of the number of the plurality of first strip-shaped structures to the number of the plurality of second strip-shaped structures is about less than or substantially equal to 0.4 and about less than 1.0. In some embodiments, the circuit structure further comprises: a seed layer electrically coupled to the copper conductive layer, the seed layer comprising: a first metal seed layer; and a second metal seed layer interposed between the first metal seed layer and the copper conductive layer, wherein the copper conductive layer is between the second metal seed layer and the dielectric layer, wherein a first thickness of the first metal seed layer is less than or substantially equal to a second thickness of the second metal seed layer along a stacking direction of the first metal seed layer, the second metal seed layer, and the copper conductive layer, and wherein the thickness of the seed layer is approximately in a range of 0.1 kiloangstroms to 12 kiloangstroms as measured along the stacking direction.

According to some embodiments, a method of manufacturing a package structure comprises: providing at least one semiconductor die; encapsulating the at least one semiconductor die in an insulating encapsulant; forming a rerouting circuit structure on the at least one semiconductor die, wherein the rerouting circuit structure is electrically connected to the at least one semiconductor die, and forming the rerouting circuit structure comprises: forming a metallization layer having a plurality of conductive patterns comprised of columnar structures including a plurality of copper grains, each of the plurality of copper grains including a plurality of first strip-like structures having a plurality of copper atoms oriented on a (220) lattice plane; and depositing a dielectric layer at least partially covering the metallization layer; and arranging a plurality of first conductive terminals on the redistribution circuit structure.

In some embodiments, in the method of fabricating an encapsulation structure, wherein in the step of forming the metallization layer, the plurality of copper grains are each formed to further include a plurality of second strip-like structures having a plurality of copper atoms oriented on a (111) lattice plane, wherein a ratio of a number of the plurality of first strip-like structures to a number of the plurality of second strip-like structures is about less than or substantially equal to 0.4 and about less than 1.0. In some embodiments, in the method of fabricating a package structure, wherein prior to forming the metallization layer, the method further comprises: forming a first metal seed layer on the insulating seal; and forming a second metal seed layer on the first metal seed layer, wherein the second metal seed layer is between the first metal seed layer and the metallization layer, and a first thickness of the first metal seed layer is less than or substantially equal to a second thickness of the second metal seed layer. In some embodiments, in the method of fabricating an encapsulation structure, wherein forming the metallization layer comprises performing an electroplating process with a plating solution comprising: an electrolyte; and an additive comprising a compound represented by the following formula:wherein: r1 and R2 are independently selected from the group consisting ofA substituted or unsubstituted aromatic group and a substituted or unsubstituted heteroaromatic group, and n is an integer from 5 to 250. In some embodiments, in the method of manufacturing a package structure, before encapsulating the at least one semiconductor die, further comprising: forming a plurality of perforations disposed alongside the at least one semiconductor die, wherein the plurality of perforations are electrically connected to the at least one semiconductor die by the rerouting circuit structure, wherein encapsulating the at least one semiconductor die further comprises encapsulating the plurality of perforations in the insulating encapsulant.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.