阅读说明：本技术 功率半导体封装和用于制造功率半导体封装的方法 (Power semiconductor package and method for manufacturing power semiconductor package ) 是由 J·乌利希 于 2021-03-12 设计创作，主要内容包括：一种功率半导体封装,包括：衬底；布置在衬底上的功率半导体芯片；以及包封功率半导体芯片的包封剂,其中,包封剂包括稳压添加剂,稳压添加剂被配置为最小化或消化包封剂内的局部放电。(A power semiconductor package, comprising: a substrate; a power semiconductor chip disposed on the substrate; and an encapsulant encapsulating the power semiconductor chip, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or digest partial discharge within the encapsulant.)

1. A power semiconductor package, comprising:

a substrate, a first electrode and a second electrode,

a power semiconductor chip arranged on the substrate, and

an encapsulant encapsulating the power semiconductor chip,

wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

2. The power semiconductor package of claim 1, wherein the encapsulant comprises a polymer.

3. The power semiconductor package of claim 2, wherein the polymer is one or more of silicone, polyimide, epoxy, acrylate, and polyurethane.

4. The power semiconductor package according to one of the preceding claims, wherein the voltage stabilizing additive comprises thioxanthone,Benzil, benzophenone, acetophenone, nitrated aromatic structures, halogenated aromatics, fullerene, SiO₂One or more of particles, polycyclic aromatic, phenylenediamine, methylated phenothiazine, and malononitrile.

5. The power semiconductor package according to one of claims 2 to 4, wherein the voltage stabilizing additive is covalently incorporated into the polymer matrix of the polymer.

6. The power semiconductor package according to one of the preceding claims, further comprising:

a plastic frame forming a cavity, wherein the encapsulant is disposed in the cavity, and wherein the plastic frame comprises the voltage stabilizing additive configured to minimize or eliminate partial discharge within the plastic frame.

7. The power semiconductor package of claim 6, wherein the plastic frame comprises a voltage stabilizing additive different from the encapsulant.

8. Power semiconductor package according to one of the preceding claims, wherein the content of the voltage stabilizing additive in the encapsulant is in the range of 0.1 wt% to 10 wt%.

9. Power semiconductor package according to one of the preceding claims, wherein encapsulation comprises a passivating organic coating arranged at an edge of the power semiconductor chip and/or at an edge of the substrate and/or at a trench,

wherein the passivating organic coating includes the voltage stabilizing additive.

10. The power semiconductor package of claim 9, wherein the passivating organic coating has a different material composition than the remainder of the encapsulation.

11. A method for manufacturing a power semiconductor package, the method comprising:

a substrate is provided and is provided,

arranging a power semiconductor chip on said substrate, and

encapsulating the power semiconductor chip with an encapsulant,

wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

12. The method of claim 11, wherein the encapsulant comprises a polymer, and wherein the voltage stabilizing additive is covalently incorporated into a polymer matrix of the polymer.

13. The method of claim 11 or claim 12, wherein the voltage stabilizing additive comprises a thioxanthone, a benzil, a benzophenone, an acetophenone, a nitrated aromatic structure, a halogenated aromatic, a fullerene, SiO₂One or more of particles, polycyclic aromatic, phenylenediamine, methylated phenothiazine, and malononitrile.

14. The method of one of claims 11 to 13, further comprising:

adding the voltage stabilizing additive to the encapsulant prior to encapsulating the power semiconductor chip,

wherein the stabilising additive is added to the encapsulant in powder form, or wherein the stabilising additive is added to the encapsulant dissolved in a solvent.

15. Use in a power semiconductor package of a voltage stabilizing additive configured to minimize or eliminate partial discharge within an encapsulant of the power semiconductor package.

Technical Field

The present disclosure relates generally to power semiconductor packages and methods for manufacturing power semiconductor packages.

Background

Power semiconductor packages (e.g., including AC/DC or DC/DC converter circuits) may operate at high voltages and/or high currents. Due to, among other things, the small size of power semiconductor packages and the close proximity of their electrical components, stringent insulation requirements must be met. Typical insulator components that may be used in power semiconductor packages are encapsulants, plastic frames, insulating glues, and the like. Such components may generally include a polymer matrix. However, defects (e.g., gas-filled voids) in such insulators may be the starting point of an electrical fault, such as a partial discharge, which in turn may cause sufficient damage to the insulator such that an electrical short may occur. It may be impractical or even impossible to further reduce the number or size of defects (such as gas-filled voids) in the insulator. Accordingly, it may be advantageous to use an improved power semiconductor package and an improved method for manufacturing a power semiconductor package comprising an improved electrical insulator.

The problem on which the invention is based is solved by the features of the independent claims. Further advantageous examples are described in the dependent claims.

Disclosure of Invention

Various aspects relate to a power semiconductor package, comprising: a substrate; a power semiconductor chip disposed on the substrate; and an encapsulant encapsulating the power semiconductor chip, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

Various aspects relate to a method for manufacturing a power semiconductor package, the method comprising: providing a substrate; disposing a power semiconductor chip on a substrate; and encapsulating the power semiconductor chip with an encapsulant, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

Various aspects relate to the use of a voltage stabilizing additive in a power semiconductor package, the voltage stabilizing additive configured to minimize or eliminate partial discharge within an encapsulant of the power semiconductor package.

Drawings

The drawings illustrate examples and together with the description serve to explain the principles of the disclosure. Other examples and many of the intended advantages of the present disclosure will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

Fig. 1 shows a schematic cross-sectional view of a power semiconductor package, wherein the insulator of the power semiconductor package comprises a voltage stabilizing additive.

Fig. 2 shows a schematic view of an electron avalanche in an electrical insulator caused by a partial discharge.

Fig. 3A to 3C show examples of different substances that may be used as voltage stabilizing additives in power semiconductor packages.

Fig. 4 schematically shows how a voltage stabilizing additive may prevent partial discharges from damaging the insulation.

Fig. 5 shows a schematic cross-sectional view of a detail of a power semiconductor package.

Fig. 6 shows a schematic cross-sectional view of another power semiconductor package including various electrically insulating components.

Fig. 7 shows a flow chart of a method for manufacturing a power semiconductor package.

Detailed Description

In the following detailed description, directional terminology, such as "top," "bottom," "left," "right," "up," "down," etc., is used with reference to the orientation of the figure(s) being described. Because components of the present disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only.

In addition, while an example particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically indicated otherwise or unless technically limited. The terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other, whether or not they are in direct physical or electrical contact, or they are not in direct contact with each other; intermediate elements or layers may be provided between elements that are "joined," attached, "or" connected. However, it is also possible that elements that are "engaged," "attached," or "connected" are in direct contact with one another. Moreover, the term "exemplary" is used only as an example, and not a list of preferred or optimal.

Examples of power semiconductor packages may use various types of semiconductor chips or circuits incorporated in semiconductor chips, including AC/DC or DC/DC converter circuits, power MOSFET transistors, power schottky diodes, JFETs (junction gate field effect transistors), power bipolar transistors, logic integrated circuits, analog integrated circuits, power integrated circuits, chips with integrated passive devices, and so forth. Further, examples of insulating materials may be used, for example, to provide an insulating layer in various types of housings and for insulation of electrical circuits and electrical components, and/or to provide an insulating layer in various types of semiconductor chips or circuits incorporated in semiconductor chips (including the above-described semiconductor chips and circuits).

The power semiconductor packages described below may include one or more semiconductor chips. As an example, one or more power semiconductor chips may be included. Further, one or more logic integrated circuits may be included in the power semiconductor package. The logic integrated circuit may be configured as an integrated circuit that controls other semiconductor chips, such as an integrated circuit of a power semiconductor chip. The logic integrated circuit may be implemented in a logic chip.

Fig. 1 shows a power semiconductor package 100 including a substrate 110, a power semiconductor chip 120, and an encapsulant 130. The power semiconductor chip 120 is disposed on the substrate 110, and the encapsulant 130 encapsulates the power semiconductor chip 120. Further, the encapsulant 130 includes a voltage stabilization additive 140, the voltage stabilization additive 140 configured to minimize or eliminate partial discharge within the encapsulant 130.

The power semiconductor package 100 may be configured to be operable at high voltages (e.g., voltages of 6.5kV or higher) and/or high currents. The power semiconductor package 100 may, for example, include a converter circuit, a half-bridge circuit, an inverter circuit, or any other suitable circuit. The power semiconductor package 100 may, for example, be configured for use in automotive applications.

The power semiconductor package 100 may be configured to be attached to a base plate, for example, such that the substrate 110 is disposed on the base plate. The power semiconductor package 100 may be configured to attach to a heat sink. Further, the power semiconductor package 100 may be configured to be connected to a circuit board. For example, the circuit board may be arranged at an upper main side of the power semiconductor package 100 opposite to a lower main side, wherein the lower main side comprises the substrate 110.

In the example shown in fig. 1, the power semiconductor package 100 includes only one substrate 110. However, it is also possible that the power semiconductor package 100 includes two or more substrates 110. Furthermore, the power semiconductor package 100 may comprise more than one power semiconductor chip 120, e.g. several power semiconductor chips 120 on a single substrate 110 or several substrates 110, wherein each of the substrates 110 carries at least one power semiconductor chip 120.

The substrate 110 may be a die carrier and it may include, for example, Direct Copper Bonding (DCB), Direct Aluminum Bonding (DAB), Active Metal Brazing (AMB), or a lead frame.

The substrate 110 may comprise an upper main face and an opposite lower main face, wherein the power semiconductor chip 120 is arranged on the upper main face. The upper major face may be partially or completely covered by the encapsulant 130. The lower major face may be partially or completely free of the encapsulant 130.

The power semiconductor chip 120 may be electrically coupled to the substrate 110. For example, a first power electrode arranged on a lower main face of the power semiconductor chip 120 may be coupled to the substrate 110 via a solder joint, wherein the lower main face faces the substrate 110. A second power electrode and/or control electrode arranged on an upper main face opposite the lower main face may be coupled to the substrate 110, e.g. via one or more bond wires.

Encapsulant 130 may include a polymer, and it may be electrically insulating. According to an example, the encapsulant 130 is a molded body or gel disposed on the power semiconductor chip 120 and/or the substrate 110. The encapsulant 130 may be configured to completely encapsulate the power semiconductor chip 120. The encapsulant 130 may act as a protective cover that protects the power semiconductor chip 120 from the environment.

According to an example, the polymer of the encapsulant 130 is one or more of polyethylene, silicone, polyimide, epoxy, acrylate, and polyurethane.

According to an example, the encapsulant 130 may include one or more additional additives in addition to the voltage stabilization additive 140. For example, the encapsulant 130 may include a filler material configured to improve the heat dissipation capability of the encapsulant 130.

The voltage stabilization additive 140 may be uniformly distributed within the encapsulant 130. However, the voltage stabilization additive 140 may also be unevenly distributed within the encapsulant 130. For example, encapsulant 130 may include different portions, e.g., several layers, where one portion includes voltage stabilization additive 140 and another portion does not include voltage stabilization additive 140.

According to the example of encapsulant 130, voltage stabilization additive 140 may simply be mixed into the polymer. According to another example, the voltage stabilizing additive 140 may be covalently incorporated into the polymer matrix of the polymer. The latter case may, for example, provide the advantage of preventing or at least reducing diffusion or redistribution of voltage stabilization additive 140 (particularly when encapsulant 130 is still fluid during fabrication of power semiconductor package 100).

The encapsulant 130 may include any suitable amount of the voltage stabilization additive 140. For example, about 0.1 wt% to 10 wt%, or about 0.5 wt% to 5 wt%, or about 0.75 wt% to 2 wt% of the content of encapsulant 130 may be comprised of voltage stabilization additive 140.

In addition to encapsulant 130, power semiconductor package 100 may include additional components including voltage stabilization additive 140. For example, the power semiconductor package 100 may comprise a (hard) plastic frame and/or glue comprising a voltage stabilizing additive 140. Different components of the power semiconductor package 100 may include different amounts of voltage stabilizing additive 140 and/or different types of voltage stabilizing additives (examples of different voltage stabilizing additives are described further below).

Next, a brief description of "partial discharge" is given. The partial discharge may be a localized dielectric breakdown of an electrical insulator (e.g., a polymer) under high voltage stress. In other words, a partial discharge does not completely connect two spaced apart conductors (e.g., two conductive traces of a DCB).

Fig. 2 schematically illustrates a partial discharge occurring within an insulator 200 (the insulator 200 may, for example, correspond to the encapsulant 130) disposed in a space between two conductors 210. An initial ionization event 220 occurs within the insulator 200 due to, for example, background radiation. The potential difference between the two conductors 210 results in an electric field that is at a positive voltage V₊Accelerating the free electrons toward the conductor 210. After the free electrons are sufficiently acceleratedI.e. at a sufficiently high energy, the free electrons may cause a further ionization event 230 (avalanche effect).

Such partial discharge typically occurs in voids (gas-filled voids) within the insulator 200 because the dielectric constant within the voids is less than the dielectric constant in the surrounding dielectric material. Thus, the electric field strength in the voids is higher than the electric field strength in the surrounding dielectric material.

To prevent partial discharge, it may therefore be desirable to minimize the amount and size of voids in the insulator 200. Beyond a certain point, however, this may no longer be practical or economical. Therefore, it may be beneficial to add the voltage stabilizing additive 140 to the insulator 200 and thereby prevent or at least reduce partial discharge.

Examples of substances that can be used as the voltage stabilization additive 140 are listed below. Alternative materials are also contemplated.

According to an example, the pressure stabilizing additive 140 includes one or more of the following listed substances:

thioxanthone

Benzil radical

Benzophenone

Acetophenone

Nitrated aromatic structures

Halogenated aromatic

Fullerene

·SiO₂Granules

Polycyclic aromatic hydrocarbons

Phenylenediamine (E)

Methylated phenothiazines

Malononitrile

Fig. 3A-3C illustrate three different examples of substances that may be used in the voltage stabilization additive 140.

FIG. 3A shows acetophenone (formula: C)₆H₅C(O)CH₃) Fig. 3B shows benzophenone (chemical formula: (C)₆H₅)₂CO), and fig. 3C shows benzil (chemical formula: (C)₆H₅CO)₂). Acetophenone may have a boiling point of 202 deg.C, benzophenoneMay have a boiling point of 305 ℃ and the benzil may have a boiling point of 346 ℃.

Acetophenone is an example of an aromatic carbonyl compound. It can migrate more easily from the polymer matrix, e.g., encapsulant 130, than, e.g., benzophenone or benzil. Therefore, it may be advantageous to use the voltage stabilization additive 140 including an aromatic carbonyl or benzil type compound having a larger alkoxy chain.

According to an example, the compound included in the voltage stabilizing additive 140 includes a modifier, such as a selected functional group, that increases the compatibility of the compound with the polymer matrix, e.g., encapsulant 130. In particular, the voltage stabilization additive 140 may be configured to be covalently incorporated into a polymer matrix, such as the encapsulant 130. For example, the voltage stabilization additive 140 may include a substance such as benzophenone disposed at the end of a silicone oligomer chain.

Referring to fig. 4, a possible partial discharge prevention effect of the voltage-stabilizing additive 140 is described.

For example, free electrons 400 within insulator 200 (e.g., caused by background radiation as further described above) may have a relatively high energy E₁Which may be sufficient to cause damage to the insulator 200. However, the insulator 200 includes a voltage stabilizing additive 140, which without loss of generality may include benzophenone. Upon collision with a molecule of the voltage stabilizing additive 140, the free electrons 400 may cause ionization of the molecule. Thus, a stable free radical cation 410 is created and released with a relatively low energy E₂Two electrons 420. Since the voltage stabilizing additive 140 is ionized at a relatively lower energy level than the insulator 200, the electrons 420 are prevented from having an energy level sufficient to cause damage to the insulator 200.

Fig. 5 shows a detailed view of a section of a power semiconductor package, which may be similar or identical to power semiconductor package 100. According to an example, fig. 5 may show section a in fig. 1.

The detailed view of fig. 5 shows an example of the substrate 110 including an upper conductive layer 510, an insulating layer 520, and a lower conductive layer 530. The upper conductive layer 510 comprises two conductive tracks 511 separated by a trench 540. The grooves may be filled with an encapsulant 130 that includes a voltage stabilization additive 140.

At sharp edges of the conductor, such as at the edge 512 of the conducting track 511, the electric field strength may be particularly high, thereby promoting partial discharge in the adjoining insulator, such as the encapsulant 130. Furthermore, individual conductors like the conducting tracks 511 may be arranged close together in a power semiconductor package, and partial discharges may easily be the cause of electrical short-circuits between such conductors. Therefore, it may be particularly important to protect the insulation near the edge 512 with the stabilizing additive 140.

Fig. 6 illustrates a power semiconductor package 600, which may be similar or identical to power semiconductor package 100, except for the differences described below.

The power semiconductor package 600 includes a plurality of power semiconductor chips 120 disposed on a substrate 110 and encapsulated by an encapsulant 130. The power semiconductor package 600 may further comprise a (hard) plastic frame 610 forming a cavity, wherein the encapsulant 130, the power semiconductor chip 120 and the substrate 110 are arranged in the cavity. The power semiconductor package 600 may include one or more power terminals 620 and/or one or more control terminals 630, which may be exposed at the upper main side of the power semiconductor package 600. The power terminal 620 may be coupled to the power semiconductor chip 120, and the control terminal 630 may be configured to transmit a control signal to the power semiconductor chip 120.

According to an example, the power semiconductor package 600 may further include a control circuit 640, for example, disposed on a printed circuit board. The control circuitry 640 may be disposed, for example, in a cavity formed by the plastic frame 610. The control circuit 640 may, for example, be configured to control the power semiconductor chip 120, and it may be coupled to the control terminal 630.

According to an example, the power semiconductor package 600 may further include a base plate 650, wherein the substrate 110 is disposed on the base plate 650. The substrate 650 may be arranged, for example, at a lower main side of the power semiconductor package 600.

As described with reference to power semiconductor package 100, encapsulant 130 of power semiconductor package 600 may include voltage stabilization additive 140. Additionally or alternatively, other components may include voltage stabilization additive 140 (where voltage stabilization additives 140 of different components of power semiconductor package 600 may include the same substance or different substances, e.g., benzophenone in one component and benzil in another component).

According to an example, the power semiconductor package 600 may include a silicone potting gel and/or a molding compound and/or a high hardness potting material and/or a passivating organic coating and/or a thermoplastic housing material and/or a frame glue material, wherein one or more of these components may include the voltage stabilizing additive 140.

The molding compound may be based, for example, on an epoxy, or an acrylate, or a silicone, or a polyurethane. The high stiffness potting material may be based on, for example, epoxy, or acrylate, or silicone, or polyurethane, and it may include a filler material. The passivating organic coating may for example be arranged on the chip edge and/or in the substrate trench, and it may be based on polyimide, or polyamide-imide, or acrylate. The thermoplastic shell material may for example be based on PBT, or PPA, or PA, or PPS, or PPSO. The frame gluing material may for example be configured to glue the plastic frame 610 to other components of the power semiconductor package 600, and it may for example be based on silicone, or epoxy, or acrylate, or methacrylate, or polyurethane.

Fig. 7 shows a flow chart of a method 700 for manufacturing a power semiconductor package. The method 700 may be used, for example, to manufacture the power semiconductor packages 100 and 600.

The method 700 comprises: an act of providing a substrate at 701; an act of disposing a power semiconductor chip on a substrate at 702; and an act of encapsulating the power semiconductor chip with an encapsulant at 703, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

According to an example of the method 700, the encapsulant includes a polymer, wherein the voltage stabilizing additive is covalently incorporated into a polymer matrix of the polymer. According to another example of method 700, a voltage stabilizing additive is added to an encapsulant prior to encapsulating the power semiconductor chip with the encapsulant. Further, the pressure stabilizing additive may be added to the encapsulant in powder form, or the pressure stabilizing additive may be added to the encapsulant dissolved in the solvent.

Another aspect of the present disclosure relates to the use of a voltage stabilizing additive in a power semiconductor package, wherein the voltage stabilizing additive is configured to minimize or eliminate partial discharge within an encapsulant of the power semiconductor package or within any other suitable electrically insulating component.

Examples of the invention

Hereinafter, the power semiconductor package and the method for manufacturing the power semiconductor package are further explained using specific examples.

Example 1 is a power semiconductor package, comprising: the semiconductor package includes a substrate, a power semiconductor chip disposed on the substrate, and an encapsulant encapsulating the power semiconductor chip, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

Example 2 is a power semiconductor package according to example 1, wherein the encapsulant comprises a polymer.

Example 3 is a power semiconductor package according to example 2, wherein the polymer is one or more of silicone, polyimide, epoxy, acrylate, and polyurethane.

Example 4 is a power semiconductor package according to one of the preceding examples, wherein the voltage stabilizing additive comprises thioxanthone, benzil, benzophenone, acetophenone, nitrated aromatic structures, halogenated aromatics, fullerenes, SiO₂One or more of particles, polycyclic aromatic, phenylenediamine, methylated phenothiazine, and malononitrile.

Example 5 is a power semiconductor package according to one of examples 2 to 4, wherein the voltage stabilizing additive is covalently incorporated into the polymer matrix of the polymer.

Example 6 is a power semiconductor package according to one of the preceding examples, further comprising: a plastic frame forming a cavity, wherein an encapsulant is disposed in the cavity, and wherein the plastic frame comprises a voltage stabilizing additive configured to minimize or eliminate partial discharge within the plastic frame.

Example 7 is a power semiconductor package according to example 6, wherein the plastic frame includes a voltage stabilizing additive different from the encapsulant.

Example 8 is a power semiconductor package according to one of the preceding examples, wherein a content of the voltage stabilizing additive in the encapsulant is in a range of 0.1 wt% to 10 wt%.

Example 9 is a power semiconductor package according to one of the preceding examples, the encapsulation comprising a passivating organic coating disposed at an edge of the power semiconductor chip and/or at an edge of the substrate and/or at the trench, wherein the passivating organic coating comprises a voltage stabilizing additive.

Example 10 is a power semiconductor package according to example 9, wherein the passivating organic coating has a different material composition than a remainder of the encapsulation.

Example 11 is a method for manufacturing a power semiconductor package, the method comprising: the method includes providing a substrate, disposing a power semiconductor chip on the substrate, and encapsulating the power semiconductor chip with an encapsulant, wherein the encapsulant includes a voltage stabilizing additive configured to minimize or eliminate partial discharge within the encapsulant.

Example 12 is the method of example 11, wherein the encapsulant comprises a polymer, and wherein the voltage stabilizing additive is covalently incorporated into a polymer matrix of the polymer.

Example 13 is the method of example 11 or example 12, wherein the voltage stabilizing additive comprises thioxanthone, benzil, benzophenone, acetophenone, nitrated aromatic structure, halogenated aromatic, fullerene, SiO₂One or more of particles, polycyclic aromatic, phenylenediamine, methylated phenothiazine, and malononitrile.

Example 14 is the method of one of examples 11 to 13, further comprising: before encapsulating the power semiconductor chip, a voltage-stabilizing additive is added to the encapsulant, wherein the voltage-stabilizing additive is added to the encapsulant in powder form, or wherein the voltage-stabilizing additive is added to the encapsulant dissolved in a solvent.

Example 15 is the use of a voltage stabilizing additive in a power semiconductor package, the voltage stabilizing additive configured to minimize or eliminate partial discharge within an encapsulant of the power semiconductor package.

Example 16 is an apparatus comprising means for performing a method according to one of examples 11 to 14.

Although the disclosure has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure.