Semiconductor device and imaging device
阅读说明:本技术 半导体装置和成像装置 (Semiconductor device and imaging device ) 是由 琴尾健吾 小池薫 于 2016-04-26 设计创作,主要内容包括:本发明提高了半导体芯片之间的接合强度。在半导体装置中,第一半导体芯片设置有第一接合面,第一接合面包括:第一绝缘层;与通过第一绝缘层而被绝缘的第一内层电路电连接的多个第一焊盘;和布置在多个第一焊盘的外部的线状的第一金属层。第二半导体芯片包括接合至第一接合面的第二接合面,第二接合面包括:第二绝缘层;布置在与第一焊盘面对的位置处且与通过第二绝缘层而被绝缘的第二内层电路电连接的多个第二焊盘;和布置在与第一金属层面对的位置处的线状的第二金属层。第一金属层和第二金属层的宽度是基于从第一半导体芯片的端部至第一焊盘的区域中的第一绝缘层与第二绝缘层之间的接合强度和第一金属层与第二金属层之间的接合强度的宽度。(The invention improves the bonding strength between the semiconductor chips. In a semiconductor device, a first semiconductor chip is provided with a first bonding surface including: a first insulating layer; a plurality of first pads electrically connected to the first inner layer circuit insulated by the first insulating layer; and a first metal layer in a line shape disposed outside the plurality of first pads. The second semiconductor chip includes a second bonding surface bonded to the first bonding surface, the second bonding surface including: a second insulating layer; a plurality of second pads arranged at positions facing the first pads and electrically connected to a second inner layer circuit insulated by a second insulating layer; and a second metal layer arranged in a line shape at a position facing the first metal layer. The widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region from an end portion of the first semiconductor chip to the first pad.)
1. A semiconductor device, comprising:
a first semiconductor chip including a first bonding surface including
A first insulating layer, a second insulating layer,
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and
a first metal layer in a line shape, the first metal layer being arranged outside the plurality of first pads; and
a second semiconductor chip including a second bonding surface bonded to the first bonding surface, the second bonding surface including
A second insulating layer is formed on the first insulating layer,
a plurality of second pads which are arranged at positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and
a second metal layer in a line shape, the second metal layer being arranged at a position facing the first metal layer,
wherein widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region from an end of the first semiconductor chip to the first pad.
2. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,
wherein widths of the first metal layer and the second metal layer are widths based on an average of a bonding strength between the first insulating layer and the second insulating layer in the region and a bonding strength between the first metal layer and the second metal layer.
3. The semiconductor device as set forth in claim 2,
wherein the widths of the first and second metal layers are substantially equal to a width Q satisfying the following relation,
(x×P+y×Q)/R>z
wherein the content of the first and second substances,
z: a bonding strength per unit area between the first semiconductor chip and the second semiconductor chip,
x: a bonding strength per unit area between the first insulating layer and the second insulating layer,
y: a bonding strength per unit area between the first metal layer and the second metal layer,
p: a length of a joint portion of the first insulating layer and the second insulating layer on a path substantially perpendicularly intersecting with an end portion of the first semiconductor chip, and
r: a length between the first pad on the path and an end of the first semiconductor chip.
4. The semiconductor device according to claim 3, wherein the first and second semiconductor layers are stacked,
wherein the path is a path that: which substantially perpendicularly intersects an end portion of the first semiconductor chip and extends from the end portion of the first semiconductor chip and first reaches the first pad.
5. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are stacked,
wherein the path is a path having the longest distance among such paths: substantially perpendicularly intersects an end portion of the first semiconductor chip, and extends from the end portion of the first semiconductor chip and first reaches the first pad.
6. The semiconductor device according to any one of claims 1 to 5,
wherein the first bonding surface further includes a first dummy pad not electrically connected to the first inner layer circuit,
the second bonding surface further includes a second dummy pad arranged at a position facing the first dummy pad and not electrically connected to the second inner layer circuit, and
widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip and reaching first the first pad or the first dummy pad.
7. The semiconductor device according to any one of claims 1 to 5,
wherein the first metal layer and the second metal layer are divided into a predetermined number of parts.
8. The semiconductor device according to any one of claims 1 to 5,
wherein the first semiconductor chip and the second semiconductor chip are configured in a rectangular shape, and
widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in the region for each side of each of the first semiconductor chip and the second semiconductor chip.
9. An imaging device includes a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a first bonding surface and a first diffusion layer,
the first engagement surface comprises
A first insulating layer, a second insulating layer,
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and
a first metal layer in a line shape, the first metal layer being arranged outside the plurality of first pads,
the first diffusion layer includes a semiconductor region that is electrically connected to the first inner layer circuit and converts applied light into an electric signal; and is
The second semiconductor chip bonded to the first bonding surface, the second semiconductor chip including a second bonding surface and a second diffusion layer,
the second engagement surface comprises
A second insulating layer is formed on the first insulating layer,
a plurality of second pads which are arranged at positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and
a second metal layer in a line shape, the second metal layer being arranged at a position facing the first metal layer,
the second diffusion layer includes a semiconductor region electrically connected to the second inner layer circuit and processing the electric signal,
wherein widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip to the first pad.
Technical Field
The invention relates to a semiconductor device and an imaging device. More particularly, the present invention relates to a semiconductor device and an imaging device formed by bonding two semiconductor chips.
Background
Heretofore, a semiconductor device has been used which: a plurality of semiconductor chips are stacked to form a three-dimensional configuration, and thus miniaturization is achieved. For example, in the imaging device, the light receiving element chip and the peripheral circuit chip are separately manufactured based on respective manufacturing processes. The light receiving element chip is a semiconductor chip having such a configuration: wherein pixels each including a light receiving element are arranged in a two-dimensional array configuration. The peripheral circuit chip is formed of a peripheral circuit that drives the light receiving element chip. Thereafter, the following production method was used: these chips are bonded together and stacked, thereby constructing an imaging device. In the case of using this manufacturing method, it is desirable to enhance the bonding strength at the bonding surface to improve the reliability of the imaging device.
On the bonding surface of the chip, a pad electrically connected to a circuit in the semiconductor chip is arranged; and the transmission of electrical signals between chips can be achieved through these bonded pads. The pad is made of metal such as copper (Cu), and thus relatively high bonding strength can be obtained. On the other hand, an insulating layer for insulating the pad and the like is arranged in a region other than the pad of the bonding surface. The bonding strength between the insulating layers is lower than that between the bonding pads; therefore, a system for activating the bonding surface by plasma treatment to improve the bonding strength has been proposed (for example, see patent document 1).
Reference list
Patent document
Patent document 1: japanese patent laid-open No. 5-082404
Disclosure of Invention
Technical problem to be solved by the invention
The conventional technique described above has an effect of improving the bonding strength between insulating films on the bonding surfaces by activation, but on the other hand, has a problem that: the pad is damaged and deteriorated, and copper (Cu) constituting the pad is scattered around and an apparatus for bonding the semiconductor chip is contaminated.
The present invention has been made in view of the above circumstances, and an object of the present invention is to improve bonding strength between semiconductor chips without performing an activation treatment of a bonding surface.
Solution to the technical problem
The present invention is conceived to solve the above-described problems, and a first aspect of the present invention is a semiconductor device including: a first semiconductor chip including a first bonding surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged outside the plurality of first pads; and a second semiconductor chip including a second bonding surface bonded to the first bonding surface, the second bonding surface including a second insulating layer, a plurality of second pads arranged at positions facing the first pads and electrically connected to a second inner layer circuit insulated by the second insulating layer, and a second metal layer in a linear shape arranged at positions facing the first metal layer. Widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region from an end portion of the first semiconductor chip to the first pad. This produces the following effect: the first metal layer and the second metal layer are arranged with a width based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region from an end portion of the first semiconductor chip to the first pad.
Further, according to the first aspect, the widths of the first metal layer and the second metal layer may be a width based on an average of a bonding strength between the first insulating layer and the second insulating layer in the region and a bonding strength between the first metal layer and the second metal layer. This produces the following effect: the first metal layer and the second metal layer having a width based on an average of a bonding strength between the first insulating layer and the second insulating layer in the region and a bonding strength between the first metal layer and the second metal layer are arranged.
Further, according to the first aspect, the widths of the first metal layer and the second metal layer may be substantially equal to a width Q satisfying the following relation, (x × P + y × Q)/R > z, where z: bonding strength per unit area between the first semiconductor chip and the second semiconductor chip, x: bonding strength per unit area between the first insulating layer and the second insulating layer, y: a bonding strength per unit area between the first metal layer and the second metal layer, P: a length of a joint of the first insulating layer and the second insulating layer on a path substantially perpendicularly intersecting with an end portion of the first semiconductor chip, and R: a length between the first pad on the path and an end of the first semiconductor chip. This produces the following effect: the first metal layer and the second metal layer are arranged with a width based on a length of a joint of the first insulating layer and the second insulating layer on a path substantially perpendicularly intersecting with an end portion of the first semiconductor chip and a width based on other factors.
Further, according to the first aspect, the path may be a path that: substantially perpendicularly intersects an end portion of the first semiconductor chip, and extends from the end portion of the first semiconductor chip and first reaches the first pad. This produces the following effect: the first metal layer and the second metal layer are arranged with a width based on the length of the joint of the first insulating layer and the second insulating layer on the shortest path between the end portion of the first semiconductor chip and the first pad and based on other factors.
Further, according to the first aspect, the path may be a path having the longest distance among such paths: substantially perpendicularly intersects an end portion of the first semiconductor chip, and extends from the end portion of the first semiconductor chip and first reaches the first pad. This produces the following effect: the first and second metal layers are arranged to have widths based on the lengths of the junctions of the first and second insulating layers on the path having the minimum bonding strength and based on other factors.
Further, according to the first aspect, the first bonding surface may further include a first dummy pad that is not electrically connected to the first inner layer circuit. The second bonding surface may further include a second dummy pad arranged at a position facing the first dummy pad and not electrically connected to the second inner layer circuit. Widths of the first metal layer and the second metal layer may be widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip and reaching first the first pad or the first dummy pad. This produces the following effect: the first metal layer and the second metal layer are arranged with a width based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end portion of the first semiconductor chip and reaching first the first pad or the first dummy pad.
Further, according to the first aspect, the first metal layer and the second metal layer may be divided into a prescribed number of parts. This produces the following effect: and partitioning the first metal layer and the second metal layer.
Further, according to the first aspect, the first semiconductor chip and the second semiconductor chip may be configured in a rectangular shape. The widths of the first and second metal layers may be widths based on a bonding strength between the first and second insulating layers and a bonding strength between the first and second metal layers in the region for each side of each of the first and second semiconductor chips. This produces the following effect: the first metal layer and the second metal layer are arranged with widths based on a bonding strength between the first insulating layer and the second insulating layer in the region and a bonding strength of the first metal layer and the second metal layer for each side of each of the semiconductor chips.
Further, a second aspect of the present invention is an image forming apparatus comprising: a first semiconductor chip including a first bonding surface and a first diffusion layer, the first bonding surface including a first insulating layer, a plurality of first pads electrically connected to a first inner layer circuit insulated by the first insulating layer, and a linear first metal layer arranged outside the plurality of first pads, the first diffusion layer including a semiconductor region electrically connected to the first inner layer circuit and converting applied light into an electrical signal; and a second semiconductor chip bonded to the first bonding surface, the second semiconductor chip including a second bonding surface and a second diffusion layer, the second bonding surface including a second insulating layer, a plurality of second pads arranged at positions facing the first pads and electrically connected to a second inner layer circuit insulated by the second insulating layer, and a second metal layer in a linear shape arranged at positions facing the first metal layer, the second diffusion layer including a semiconductor region electrically connected to the second inner layer circuit and processing the electric signal. Widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip to the first pad. This produces the following effect: the first metal layer and the second metal layer are arranged with a width based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in such a region as to extend from an end portion of the first semiconductor chip to the first pad.
The invention has the advantages of
According to the present invention, a favorable effect of improving the bonding strength between semiconductor chips can be exhibited without performing an activation treatment of the bonding surface. Note that the effects described herein are not necessarily restrictive, and any effects to be described in the present invention may be exhibited.
Drawings
Fig. 1 shows a configuration example of a semiconductor device 10 in a first embodiment of the present invention.
Fig. 2 shows a configuration example of a semiconductor chip in a first embodiment of the present invention.
Fig. 3 shows the width of the guard ring in the first embodiment of the present invention.
Fig. 4 shows an offset or the like during alignment in the first embodiment of the present invention.
Fig. 5 shows the width of the guard ring in a modification of the first embodiment of the present invention.
Fig. 6 shows a guard ring in a second embodiment of the invention.
Fig. 7 shows a configuration example of the semiconductor device 10 in the third embodiment of the present invention.
Fig. 8 shows a dummy pad in a third embodiment of the present invention.
FIG. 9 shows a design procedure for a guard ring in an embodiment of the invention.
Fig. 10 shows a maximum insulator joint length calculation procedure (step S910) in the embodiment of the present invention.
Detailed Description
Hereinafter, an embodiment for carrying out the present invention (hereinafter, referred to as an embodiment) is explained. The description is given in the following order.
1. First embodiment (example of case of using guard ring)
2. Second embodiment (example of case of dividing guard ring)
3. Third embodiment (example of case of using dummy pad)
<1. first embodiment >
[ Structure of semiconductor device ]
Fig. 1 shows a configuration example of a semiconductor device 10 in a first embodiment of the present invention. The figure is a cross-sectional view of the configuration of an imaging apparatus for a camera or the like. The configuration of the semiconductor device 10 in the embodiment of the present invention will now be described using this imaging device as an example. The semiconductor device 10 includes a
The
The microlens 101 forms an optical image on the above-described pixel. The color filter 102 is an optical filter for causing light of a desired wavelength to be incident on the pixel.
The
The wiring layer 131 transmits electrical signals. The wiring layer 131 is wired for each of a plurality of pixels arranged in an XY matrix configuration formed in the
The first insulating
The
The
The
The
The wiring layer 231 transmits an electrical signal. Similarly to the wiring layer 131, the wiring layer 231 may be stacked as a plurality of layers. The figure shows an example of the wiring layer 231 stacked in four layers. The via hole 232 electrically connects the wiring layers 231 arranged in different layers. For example, copper (Cu) may be used for the wiring layer 231 and the via hole 232. Further, the wiring layer 231 and the via hole 232 constitute a second interlayer circuit.
The second
The
The
[ Structure of semiconductor chip ]
Fig. 2 shows a configuration example of a semiconductor chip in a first embodiment of the present invention. The figure shows the configuration of the
The first insulating
The
The second
The
The
The bond strength between metal features, such as
[ Width of guard Ring ]
Fig. 3 shows the width of the guard ring in the first embodiment of the present invention. The figure shows a method of calculating the widths of the first and second guard rings 121 and 221. A in the drawing shows a front view of an end portion of the
As described above, the bonding strength between the insulating layers is lower than that between metal members such as the
If the
If the desired bond strength is represented by z, then the relationship between z and P, Q is shown below.
(x × P + y × Q)/R > z …
Here, x represents the bonding strength per unit area between the first insulating
As illustrated in fig. 2, the bonding surface of the
Further, as shown in a of the present drawing, the length of the joint portion of the first insulating
Further, Q is preferably calculated from the longest path among the paths on which the above-described
[ case of taking into account a shift during alignment, etc. ]
Fig. 4 shows a shift during alignment and the like in the first embodiment of the present invention. A of the figure shows an example of a case where the alignment shift e1 occurs during the bonding of the
In addition, b of the figure shows an example of a case where a dicing shift e2 occurs when the semiconductor device 10 is diced from a wafer. Here,
[ method for manufacturing semiconductor device ]
The semiconductor device 10 can be manufactured by the following procedure. The
Therefore, in the first embodiment of the present invention, the bonding surface of the semiconductor chip is provided with the
[ first modification ]
In the above-described embodiment, the
Fig. 5 shows the width of the guard ring in a modification of the first embodiment of the present invention. The figure shows an example of a case where the widths of the
<2 > second embodiment
In the above-described embodiments, one guard ring is used per semiconductor chip. In contrast, in the second embodiment of the present invention, the guard ring is divided, and a plurality of guard rings are used. Therefore, generation of defects during CMP polishing is prevented.
[ Structure of guard Ring ]
Fig. 6 shows a guard ring in a second embodiment of the invention. As described above, in the manufacturing process of the semiconductor device 10, the polishing of the bonding surface of the semiconductor chip by the CMP method is performed. In this case, if the widths Q of the first and second guard rings 121 and 221 are excessively large, there is a case where a so-called dishing defect (disking) in which the guard ring portion is excessively cut off occurs. To prevent this, as shown in the present drawing, the
Therefore, in the second embodiment of the present invention, by dividing the guard ring, it is possible to prevent the occurrence of the dishing defect during CMP polishing while maintaining a desired bonding strength.
<3. third embodiment >
In the above-described embodiment, Q is calculated from the strength of the joint portion of the insulating layer in the region extending from the end portion of the
[ Structure of semiconductor device ]
Fig. 7 shows a configuration example of the semiconductor device 10 in the third embodiment of the present invention. The semiconductor device 10 of this figure differs from the semiconductor device 10 described in fig. 1 in that: the
[ Structure of dummy pad ]
Fig. 8 shows a dummy pad in a third embodiment of the present invention. In the first embodiment of the present invention, Q is calculated from the bonding strength between the insulator members in the region from the end portion of the
Further, the dummy pads 225 are arranged in positions on the
[ design procedure for guard Ring ]
FIG. 9 shows a design procedure for a guard ring in an embodiment of the invention. The figure shows a design procedure for a guard ring comprising the following steps: the steps include the addition of dummy pads and the segmentation of guard rings. First, the maximum insulator joint length is calculated (step S910). Here, the maximum insulator joint length is the maximum value of P. Next, the width of the guard ring is calculated from the maximum insulator bonding length (step S901). This can be calculated by
On the other hand, in the case where the design rule is not met (step S902: NO), it is judged whether or not the guard ring and the pad interfere with each other (step S904). That is, whether the distance between the guard ring and the pad is appropriate is evaluated. Therefore, in the case where the guard ring and the pad interfere with each other (YES in step S904), a dummy pad is added (step S906), and the process from step S910 is executed again. On the other hand, in the case where the guard ring and the pad do not interfere with each other (step S904: NO), the guard ring is divided (step S905), and the procedure from step S910 is executed again.
Fig. 10 shows a maximum insulator joint length calculation procedure (step S910) in the embodiment of the present invention. First, the maximum insulator joining length (Pmax) is initialized to a value of 0 (step S911). Next, the side of the semiconductor chip is selected (step S912), and the pad is selected (step S913). It is judged whether or not there is another pad between the selected pad and the selected edge (step S914). In the case where there is another pad (step S914: YES), the procedure returns to step S913 again, and another pad is selected. On the other hand, in the case where there is no other pad (step S914: NO), P described in FIG. 3 is calculated (step S915). The calculated P is compared to Pmax. In the case where P is larger than Pmax (YES in step S916), Pmax is changed to P (step S917), and the process goes to the process of step S918. On the other hand, in the case where P is Pmax or smaller (step S916: NO), the process of step S917 is skipped, and the process goes to the process of step S918.
In step S918, it is judged whether or not there is a next pad (step S918). That is, it is judged whether or not the calculation of P has been performed for all the pads. In the case where the next pad exists (step S918: yes), the procedure from step S913 on is executed again. On the other hand, in the case where there is no next pad (step S918: NO), it is judged whether or not there is a next edge (step S919). That is, it is evaluated whether the calculation of Pmax has been performed for all edges. Therefore, in the case where the next edge exists, the procedure from step S912 is executed again. On the other hand, in the case where the next edge does not exist, the maximum insulator joint length calculation routine is completed.
Therefore, in the third embodiment of the present invention, by adding dummy pads, it is possible to avoid violating the design rule while maintaining the desired bonding strength.
As described above, in the embodiment of the present invention, the guard ring having the following width is arranged on the joint face and used: the width is calculated from the strength of the bonding portion of the insulating layer and the strength of the bonding portion of the guard ring in the region from the end of the semiconductor chip to the pad. Therefore, the bonding strength of the semiconductor device can be set to a desired bonding strength without performing an activation process of the bonding surface.
The above-described embodiments are examples for embodying the present invention, and matters in the embodiments have correspondence with matters specifically disclosed in the claims. Also, matters in the embodiments and specific disclosure matters in the claims denoted by the same names have corresponding relationships with each other. However, the present invention is not limited to the embodiments, and various modifications of the embodiments may be embodied within the scope of the present invention without departing from the spirit of the invention.
The processing sequence described in the above-described embodiment may be processed as a method having a series of sequences, or may be processed as a computer program for causing a computer to execute a series of sequences and a recording medium storing the computer program. As the recording medium, a hard Disk, a CD (Compact Disc), an MD (MiniDisc), a DVD (digital versatile Disc), a memory card, and a blu-ray Disc (registered trademark) can be used.
Further, the effects described in the present invention are not restrictive but merely exemplary, and other effects may exist.
Further, the present invention may be configured as follows.
(1) A semiconductor device, comprising:
a first semiconductor chip including a first bonding surface including
A first insulating layer, a second insulating layer,
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and
a first metal layer in a line shape, the first metal layer being arranged outside the plurality of first pads; and
a second semiconductor chip including a second bonding surface bonded to the first bonding surface, the second bonding surface including
A second insulating layer is formed on the first insulating layer,
a plurality of second pads which are arranged at positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and
a second metal layer in a line shape, the second metal layer being arranged at a position facing the first metal layer,
wherein widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region from an end of the first semiconductor chip to the first pad.
(2) The semiconductor device according to (1),
wherein widths of the first metal layer and the second metal layer are widths based on an average of a bonding strength between the first insulating layer and the second insulating layer in the region and a bonding strength between the first metal layer and the second metal layer.
(3) The semiconductor device according to (2),
wherein the widths of the first and second metal layers are substantially equal to a width Q satisfying the following relation,
(x×P+y×Q)/R>z
wherein the content of the first and second substances,
z: a bonding strength per unit area between the first semiconductor chip and the second semiconductor chip,
x: a bonding strength per unit area between the first insulating layer and the second insulating layer,
y: a bonding strength per unit area between the first metal layer and the second metal layer,
p: a length of a joint portion of the first insulating layer and the second insulating layer on a path substantially perpendicularly intersecting with an end portion of the first semiconductor chip, and
r: a length between the first pad on the path and an end of the first semiconductor chip.
(4) The semiconductor device according to the above (3),
wherein the path is a path that: which substantially perpendicularly intersects an end portion of the first semiconductor chip and extends from the end portion of the first semiconductor chip and first reaches the first pad.
(5) The semiconductor device according to the above (4),
wherein the path is a path having the longest distance among such paths: substantially perpendicularly intersects an end portion of the first semiconductor chip, and extends from the end portion of the first semiconductor chip and first reaches the first pad.
(6) The semiconductor device according to any one of (1) to (5),
wherein the first bonding surface further includes a first dummy pad not electrically connected to the first inner layer circuit,
the second bonding surface further includes a second dummy pad arranged at a position facing the first dummy pad and not electrically connected to the second inner layer circuit, and
widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip and reaching first the first pad or the first dummy pad.
(7) The semiconductor device according to any one of (1) to (6),
wherein the first metal layer and the second metal layer are divided into a predetermined number of parts.
(8) The semiconductor device according to any one of (1) to (7),
wherein the first semiconductor chip and the second semiconductor chip are configured in a rectangular shape, and
widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in the region for each side of each of the first semiconductor chip and the second semiconductor chip.
(9) An imaging device includes a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a first bonding surface and a first diffusion layer,
the first engagement surface comprises
A first insulating layer, a second insulating layer,
a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and
a first metal layer in a line shape, the first metal layer being arranged outside the plurality of first pads,
the first diffusion layer includes a semiconductor region that is electrically connected to the first inner layer circuit and converts applied light into an electric signal; and is
The second semiconductor chip bonded to the first bonding surface, the second semiconductor chip including a second bonding surface and a second diffusion layer,
the second engagement surface comprises
A second insulating layer is formed on the first insulating layer,
a plurality of second pads which are arranged at positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and
a second metal layer in a line shape, the second metal layer being arranged at a position facing the first metal layer,
the second diffusion layer includes a semiconductor region electrically connected to the second inner layer circuit and processing the electric signal,
wherein widths of the first metal layer and the second metal layer are widths based on a bonding strength between the first insulating layer and the second insulating layer and a bonding strength between the first metal layer and the second metal layer in a region extending from an end of the first semiconductor chip to the first pad.
List of reference numerals
10 semiconductor device
100 first semiconductor chip
101 micro lens
102 color filter
110 first diffusion layer
120 first joint surface
121 first guard ring
124 first bonding pad
125 first dummy pad
129 first insulating layer
131, 231 wiring layer
132, 232 via hole
200 second semiconductor chip
210 second diffusion layer
220 second joint face
221 second guard ring
224 second bonding pad
225 second dummy pad
229 second insulating layer
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