阅读说明：本技术 半导体装置及包括半导体装置的存储器装置和系统 (Semiconductor device, and memory device and system including the same ) 是由 金南局 李南宰 于 2019-12-27 设计创作，主要内容包括：半导体装置及包括半导体装置的存储器装置和系统。根据本公开的实施方式的半导体装置可以包括：层叠结构,其包括交替层叠的多个第一导电图案和多个电介质层,层叠结构具有使得第一导电图案中的任何一个比紧接着位于其上方的第一导电图案进一步突出的阶梯结构；多个第二导电图案,其分别形成在第一导电图案的突出部上方；多个接触插塞,其分别与多个第二导电图案交叠,并且穿过交叠的第二导电图案和层叠结构；以及密封层图案,其插置于第一导电图案和接触插塞之间并且将第一导电图案与接触插塞分离开。(Semiconductor devices and memory devices and systems including the same. The semiconductor device according to an embodiment of the present disclosure may include: a stacked structure including a plurality of first conductive patterns and a plurality of dielectric layers which are alternately stacked, the stacked structure having a stepped structure such that any one of the first conductive patterns protrudes further than the first conductive pattern located immediately above it; a plurality of second conductive patterns respectively formed over the protrusions of the first conductive patterns; a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the overlapped second conductive patterns and the laminated structure; and a sealing layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.)

1. A semiconductor device, comprising:

a stacked structure including a plurality of first conductive patterns and a plurality of dielectric layers that are alternately stacked, the stacked structure having a stepped structure such that any one of the plurality of first conductive patterns protrudes further than a first conductive pattern located immediately above the any one of the first conductive patterns;

a plurality of second conductive patterns formed over the protrusions of the plurality of first conductive patterns, respectively;

a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the stacked structure and the overlapping second conductive patterns; and

a seal layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

2. The semiconductor device according to claim 1, wherein the contact plug is electrically connected to the first conductive pattern contacting the overlapping second conductive pattern through the overlapping second conductive pattern.

3. The semiconductor device according to claim 1, wherein a distance from a side surface of the contact plug to a side surface of the seal layer pattern is smaller than a distance from a side surface of the contact plug to a side surface of the second conductive pattern.

4. The semiconductor device according to claim 1, wherein the sealing layer pattern is present between the first conductive pattern and the contact plug.

5. The semiconductor device according to claim 1, wherein the sealing layer pattern is formed to have substantially the same thickness at the same height as the first conductive pattern.

6. The semiconductor device according to claim 1, wherein the sealing layer pattern surrounds sidewalls of each of the plurality of contact plugs except between the second conductive pattern and the contact plug.

7. The semiconductor device according to claim 1, further comprising a peripheral circuit element which is provided below the stacked structure and is electrically connected to the first conductive pattern through each of the plurality of contact plugs, wherein a bottom surface of each of the plurality of contact plugs is in direct contact with the peripheral circuit element.

8. The semiconductor device of claim 1, wherein each of the plurality of second conductive patterns is spaced apart from a dielectric layer having a bottom surface at substantially the same level as a level at which a second conductive pattern of the plurality of second conductive patterns is located.

9. The semiconductor device according to claim 1, wherein each of the plurality of second conductive patterns has a thickness smaller than a thickness of the dielectric layer having the bottom surface located at substantially the same level as a level at which the second conductive pattern of the plurality of second conductive patterns is located.

10. The semiconductor device according to claim 1, further comprising support pillars which overlap the plurality of second conductive patterns, respectively, pass through the stacked structure and the overlapped second conductive patterns, and are formed to be spaced apart from the contact plugs.

11. The semiconductor device of claim 10, wherein the support posts comprise a dielectric material.

12. The semiconductor device according to claim 10, wherein the support pillar has a bottom level substantially the same as a bottom level of the contact plug.

13. A memory device, the memory device comprising:

a stacked structure formed in a cell array region and a contact region and including a plurality of first conductive patterns and a plurality of dielectric layers that are alternately stacked, wherein the stacked structure has a stepped structure such that any one of the plurality of first conductive patterns protrudes further in the contact region than a first conductive pattern located immediately above the any one of the first conductive patterns;

a channel pillar passing through the stacked structure of the cell array region;

a memory layer interposed between the channel pillar and the first conductive pattern;

a plurality of second conductive patterns formed over protrusions of the plurality of first conductive patterns in the contact region, respectively;

a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the stacked structure and the overlapping second conductive patterns; and

a seal layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

14. The memory device according to claim 13, wherein the contact plug is electrically connected to the first conductive pattern contacting the overlapping second conductive pattern through the overlapping second conductive pattern.

15. The memory device according to claim 13, wherein a distance from a side surface of the contact plug to a side surface of the seal layer pattern is smaller than a distance from a side surface of the contact plug to a side surface of the second conductive pattern.

16. The memory device according to claim 13, wherein the sealing layer pattern is present between the first conductive pattern and the contact plug.

17. The memory device according to claim 13, wherein the seal layer pattern surrounds sidewalls of each of the plurality of contact plugs except between the second conductive pattern and the contact plug.

18. The memory device according to claim 13, further comprising a peripheral circuit element disposed under the stacked structure and electrically connected to the first conductive pattern through each of the plurality of contact plugs, wherein a bottom surface of each of the plurality of contact plugs is in direct contact with the peripheral circuit element.

19. The memory device according to claim 13, further comprising support pillars respectively overlapping the plurality of second conductive patterns, passing through the stacked structure and the overlapping second conductive patterns, and formed to be spaced apart from the contact plugs.

20. A system, the system comprising:

a memory device for storing data;

a host accessing data stored in the memory device; and

a controller for controlling the memory device between the host and the memory device in response to a request of the host,

wherein the memory device comprises:

a stacked structure formed in a cell array region and a contact region and including a plurality of first conductive patterns and a plurality of dielectric layers that are alternately stacked, wherein the stacked structure has a stepped structure such that any one of the plurality of first conductive patterns protrudes further in the contact region than a first conductive pattern located immediately above the any one of the first conductive patterns;

a channel pillar passing through the stacked structure of the cell array region;

a memory layer interposed between the channel pillar and the first conductive pattern;

a plurality of second conductive patterns formed over protrusions of the plurality of first conductive patterns in the contact region, respectively;

a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the stacked structure and the overlapping second conductive patterns; and

a seal layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

Technical Field

This patent document relates to a memory device, and more particularly, to a memory device and a method for manufacturing the memory device.

Background

Nonvolatile memory devices, for example, NAND-type flash memory devices, have been developed that can store data and retain the stored data even when power is interrupted.

In recent years, as the degree of integration of a two-dimensional memory device having memory cells formed as a single layer on a semiconductor substrate has increased to the limit, various three-dimensional memory devices having memory cells stacked in multiple layers on a semiconductor substrate have been proposed.

Disclosure of Invention

In one embodiment, a semiconductor device may include: a stacked structure including a plurality of first conductive patterns and a plurality of dielectric layers which are alternately stacked, the stacked structure having a stepped structure such that any one of the first conductive patterns protrudes further than the first conductive pattern located immediately above it; a plurality of second conductive patterns respectively formed over the protrusions of the first conductive patterns; a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the overlapped second conductive patterns and the laminated structure; and a sealing layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

In another embodiment, a method for manufacturing a semiconductor device may include: forming a stacked structure including a plurality of sacrificial layers and a plurality of dielectric layers which are alternately stacked, the stacked structure having a stepped structure such that any one of the sacrificial layers protrudes further than a sacrificial layer located immediately above it; forming a plurality of sacrifice pads over the protruding portions of the plurality of sacrifice layers, respectively; forming a plurality of contact holes respectively overlapping the plurality of sacrifice pads and passing through the overlapped sacrifice pads and the laminated structure; forming a groove by recessing a portion of the sacrificial layer exposed through the contact hole; forming a sealing layer filling the groove; forming a contact plug filling the contact hole; forming a slit through the laminated structure; removing the sacrificial layer and the sacrificial pad exposed through the slit; and filling the space from which the sacrifice layer and the sacrifice pad have been removed with a conductive material.

In another embodiment, a method for manufacturing a semiconductor device may include: forming a stacked structure including a plurality of sacrificial layers and a plurality of dielectric layers which are alternately stacked, the stacked structure having a stepped structure such that any one of the sacrificial layers protrudes further than a sacrificial layer located immediately above it; forming a plurality of sacrifice pads over the protruding portions of the plurality of sacrifice layers, respectively; forming a plurality of contact holes respectively overlapping the plurality of sacrifice pads and passing through the overlapped sacrifice pads and the laminated structure; forming a sealing layer on the side wall of the contact hole; forming a contact plug filling the contact hole having the sealing layer formed thereon; forming a slit through the laminated structure; removing the sacrifice pad exposed through the slit, and removing the sealing layer exposed by the removal of the sacrifice pad; removing the sacrificial layer exposed through the slit; and filling the space from which the sacrifice layer and the sacrifice pad have been removed with a conductive material.

In yet another embodiment, a memory device may include: a stacked structure formed in the cell array region and the contact region and including a plurality of first conductive patterns and a plurality of dielectric layers alternately stacked, wherein the stacked structure has a stepped structure such that any one of the first conductive patterns protrudes further in the contact region than the first conductive pattern located immediately thereabove; a channel pillar passing through the stacked structure of the cell array region; a memory layer interposed between the channel pillar and the first conductive pattern; a plurality of second conductive patterns respectively formed over the protrusions of the plurality of first conductive patterns in the contact region; a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the overlapped second conductive patterns and the laminated structure; and a sealing layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

In yet another embodiment, a system may include: a memory device for storing data; a host accessing data stored in the memory device; and a controller for controlling the memory device between the host and the memory device in response to a request of the host, wherein the memory device includes: a stacked structure formed in the cell array region and the contact region and including a plurality of first conductive patterns and a plurality of dielectric layers alternately stacked, wherein the stacked structure has a stepped structure such that any one of the first conductive patterns protrudes further in the contact region than the first conductive pattern located immediately thereabove; a channel pillar passing through the stacked structure of the cell array region; a memory layer interposed between the channel pillar and the first conductive pattern; a plurality of second conductive patterns respectively formed over the protrusions of the plurality of first conductive patterns in the contact region; a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the overlapped second conductive patterns and the laminated structure; and a sealing layer pattern interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug.

Drawings

Fig. 1A is a circuit diagram illustrating a cell array of a memory device according to an embodiment of the present disclosure; FIG. 1B is a perspective view of a cell array corresponding to that shown in FIG. 1A; and fig. 1C is an enlarged view of a portion a shown in fig. 1B.

Fig. 2A and 2B are a cross-sectional view and a top view, respectively, illustrating a memory device according to an embodiment of the present disclosure.

Fig. 3A and 3B to fig. 11A and 11B are diagrams illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure.

Fig. 12A and 12B are cross-sectional views illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure.

Fig. 13A and 13B to 17A and 17B are diagrams illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure.

Fig. 18A and 18B to fig. 24A and 24B are diagrams illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure.

Fig. 25 shows an example of an apparatus or a system capable of implementing the memory circuit or the semiconductor device of the above embodiments.

Detailed Description

Various embodiments will be described below with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the disclosure. The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated to clearly illustrate features of embodiments.

Various embodiments relate to a semiconductor device that may enable an improved process and may have a reduced area, a method for manufacturing the semiconductor device, and a memory device and system including the semiconductor device.

Fig. 1A is a circuit diagram illustrating a cell array of a memory device according to an embodiment of the present disclosure; FIG. 1B is a perspective view of a cell array corresponding to that shown in FIG. 1A; and fig. 1C is an enlarged view of a portion a shown in fig. 1B.

Referring to fig. 1A, a cell array of a memory device according to an embodiment may include a plurality of strings, a plurality of bit lines BL, a plurality of word lines WL, a plurality of drain select lines DSL, a plurality of source select lines SSL, and a common source line CSL. Here, the number of strings, the number of bit lines BL, the number of word lines WL, the number of drain select lines DSL, and the number of source select lines SSL are not limited to those shown in the drawing, and various modifications may be made as needed.

The string may be connected between the bit line BL and the common source line CSL. Fig. 1A shows a case where three strings are connected to each of the bit lines BL, but the number of strings connected to each bit line BL may be changed in various ways. Each string may include a source selection transistor SST, a plurality of memory cells MC, and a drain selection transistor DST connected in series. Fig. 1A shows a case where eight memory cells MC are connected in series between one source selection transistor SST and one drain selection transistor DST, but the number of source selection transistors SST, the number of drain selection transistors DST, and the number of memory cells MC connected therebetween may be variously changed. In an embodiment, the memory cells MC and the strings may be NAND flash memory cells and NAND strings, respectively.

Two junctions of the source selection transistor SST may be connected to the common source line CSL and one junction of the adjacent memory cells MC, respectively, and the gate may be connected to the corresponding source selection line SSL. Two junctions of the memory cell MC may be connected to the adjacent memory cell MC and one junction of the adjacent source select transistor SST or the adjacent drain select transistor DST, respectively, and the gate may be connected to the corresponding word line WL. Two junctions of the drain select transistor DST may be connected to a corresponding bit line BL and one junction of the adjacent memory cell MC, respectively, and the gate may be connected to a corresponding drain select line DSL.

In the above-described memory device, operations such as writing and reading for the selected memory cell MC can be performed by controlling biases applied to the word line WL connected to the selected memory cell MC, the source select line SSL and the source select line DSL respectively connected to the source select transistor SST and the drain select transistor DST of the string including the selected memory cell MC, and the bit line BL connected to the string including the selected memory cell MC. Each memory cell MC may store one bit or more. For example, each memory cell MC may function as a Single Level Cell (SLC), a multi-level cell (MLC), or a tri-level cell.

Referring to fig. 1B, the cell array shown in fig. 1A may have a three-dimensional structure in which memory cells MC are arranged and/or stacked in a direction perpendicular to a substrate SUB.

The substrate SUB may include a semiconductor substrate, and may further include various elements (not shown) formed in and/or on the semiconductor substrate. In one example, the substrate SUB may include a semiconductor substrate such as silicon containing an impurity of a predetermined conductivity type (e.g., p-type), and an impurity region formed in the semiconductor substrate and being of a conductivity type (e.g., n-type) different from that of the semiconductor substrate. The impurity region may serve as a common source line CSL. In another example, the substrate SUB may include a semiconductor substrate and a patterned semiconductor layer formed on the semiconductor substrate. In the patterned semiconductor layer, an impurity region serving as the common source line CSL may also be formed.

On the Substrate (SUB), a plurality of stacked structures each extending along the X direction may be provided, and wherein a plurality of gate electrode layers GE and a plurality of inter-gate dielectric layers IGD are alternately stacked along the Z direction. The plurality of stacked structures may be arranged to be spaced apart from each other along the Y direction. The plurality of gate electrode layers GE may function as a source select line SSL, a word line WL, or a drain select line DSL. For example, in the embodiment, the lowermost gate electrode layer GE may serve as the source selection line SSL, the uppermost gate electrode layer GE may serve as the drain selection line DSL, and the remaining gate electrode layers GE may serve as the word lines WL.

In addition, on the substrate SUB, a channel pillar CP may be provided, which is connected to the substrate and passes through a stacked structure in which the gate electrode layers GE and the inter-gate dielectric layers IGD are alternately stacked. Each channel pillar CP may be connected to a necessary portion of the substrate SUB, for example, a portion of the above-described semiconductor substrate or semiconductor layer. Each channel pillar CP may have a cylindrical shape extending along the Z direction and may include a semiconductor material such as silicon.

The memory layer ML may be disposed between each channel pillar CP and each stacked structure in which the gate electrode layers GE and the inter-gate dielectric layers IGD are alternately stacked. The memory layer ML may include three layers consisting of a tunnel dielectric layer Tox, a charge storage layer CTN, and a charge blocking layer Box sequentially arranged from the channel pillar CP (see fig. 1C). In the embodiment, the memory layer ML has a cylindrical shape extending in the Z direction while surrounding the side surface of the channel pillar CP, but is not limited to that shown in the drawings, and the shape of the memory layer ML may be variously modified as long as the memory layer ML is located between the gate electrode layer GE serving as the word line WL and the channel pillar CP.

Instead of the memory layer ML, a gate dielectric layer (not shown) different from the memory layer ML may be formed between the gate electrode layer GE serving as the drain select line DSL and the channel pillar CP and/or between the gate electrode layer GE serving as the source select line SSL and the channel pillar CP.

One word line WL surrounding one channel pillar CP and the memory layer ML disposed therebetween may form one memory cell MC; a source selection line SSL surrounding a channel pillar CP and a memory layer ML (or gate dielectric layer (not shown)) disposed therebetween may form a source selection transistor SST; and one drain select line DSL surrounding one channel pillar CP and the memory layer ML (or gate dielectric layer (not shown)) disposed therebetween may form one drain select transistor DST. In addition, the source selection transistor SST, the memory cells MC, and the drain selection transistor DST stacked along one channel pillar CP may form one string.

On top of each channel pillar CP, a drain contact DC may be disposed. The drain contact DC may include a semiconductor material such as silicon doped with impurities of a predetermined conductivity type (e.g., n-type).

On the drain contact DC, bit lines BL may be provided, the bit lines BL being arranged to be spaced apart from each other along the X direction while extending in the Y direction.

As a result, the cell array of fig. 1A can be implemented in three dimensions on the substrate SUB, as shown in fig. 1B.

As shown in fig. 1B, the stacked structure in which the gate electrode layers GE and the inter-gate dielectric layers IGD are alternately stacked may also extend in the X direction and may terminate in a region where the memory cell MC is not disposed. An end portion of the stacked structure in which the gate electrode layers GE and the intergate dielectric layers IGD are alternately stacked may be patterned to have a substantially stepped shape to form a contact plug connected to each gate electrode layer GE. This will be described with reference to fig. 2A and 2B.

Fig. 2A and 2B are a cross-sectional view and a top view, respectively, illustrating a memory device according to an embodiment of the present disclosure. For example, FIG. 2A is a cross-sectional view taken along line X-X' of FIG. 2B.

Referring to fig. 2A and 2B, a memory device of an embodiment may include a cell array region a1 and a contact region a 2.

The cell array region a1 is a region in which a plurality of memory cells are disposed, and may have a structure similar to that of the cell array shown in fig. 1B. The cell array region a1 corresponds to a cross section obtained by cutting the cell array of fig. 1B in the X direction. However, for convenience of explanation, it is shown that only a part of the cell array shown in fig. 1B, that is, three gate electrode layers GE and two channel pillars CP arranged in each of the X and Y directions are included. As described above, the cell array region a1 may include: a stacked structure ST in which a plurality of gate electrode layers GE and a plurality of inter-gate dielectric layers IGD are alternately stacked on a substrate SUB; a channel pillar CP formed to pass through the laminated structure ST; and a memory layer ML interposed between the stack structure ST and the channel pillar CP. The stacked structures ST may be arranged in the Y direction and may be separated from each other by a slit S. In the embodiment, the memory layer ML has a shape surrounding the sidewall of the channel pillar CP, but is not limited thereto, and may have various shapes as long as the memory layer ML is interposed between the channel pillar CP and the gate electrode layer GE. For example, the shape of the memory layer ML may be changed such that the memory layer ML may be formed along the top surface of each gate electrode layer GE, the side facing the channel pillar CP, and the bottom surface thereof. In addition, the channel pillar CP may also have various shapes such as a hollow cylindrical shape as long as it extends in the Z direction.

The lamination structure ST may extend in the X direction and may also be located on the substrate SUB in the contact region a2 adjacent to the cell array region a 1. Since the stacked structure ST may terminate at the contact area a2, the stacked structure ST of the contact area a2 will be referred to as "an end portion of the stacked structure ST" hereinafter. The end of the laminated structure ST may be patterned to have a substantially stepped shape by an etching process called thinning. Therefore, any gate electrode layer GE positioned at a predetermined height from the substrate SUB may have a portion protruding further toward the contact region a2 in the X direction than the gate electrode layer GE positioned immediately above it. Hereinafter, among the gate electrode layers GE, a portion of any of the gate electrode layers GE that protrudes further toward the contact region a2 than the gate electrode layer GE located immediately above it will be referred to as a protruding portion of the gate electrode layer GE. The slits S in the cell array region a1 may extend to the contact region a2 and separate the ends of the stacked structure ST arranged in the X direction in the contact region a2 from each other.

On the substrate SUB and the stack structure ST of each of the cell array region a1 and the contact region a2, an interlayer dielectric layer ILD may be formed to cover them.

Although not shown in the drawings, in the cell array region a1, drain contact plugs penetrating the interlayer dielectric ILD and respectively connected to the channel pillars CP, bit lines extending in one direction on the interlayer dielectric ILD while connecting the drain contact plugs to each other, and the like may also be formed.

In the contact region a2, contact plugs C may be formed, penetrating the interlayer dielectric layer ILD and connected to the gate electrode layer GE, respectively. In order to appropriately drive the word line WL, the source selection line SSL, and the drain selection line DSL, each of the gate electrode layers GE serving as the word line WL, the source selection line SSL, and the drain selection line DSL needs to be connected to a part of a peripheral circuit (not shown), such as a switching transistor. For this reason, it may be necessary to form contact plugs C respectively connected to the gate electrode layers GE in one stacked structure ST. The contact plug C may overlap and be connected to the protruding portion of each of the uppermost gate electrode layer GE and the remaining gate electrode layer GE.

The process of forming the contact plug C may be performed by selectively etching the interlayer dielectric layer ILD to form contact holes H each exposing the protrusion of each gate electrode layer GE, and then filling the contact holes H with a conductive material. Etching of the interlayer dielectric layer ILD to form the contact holes H may be performed such that etching is stopped on each gate electrode layer GE while the etching is performed until the lowermost gate electrode layer GE is exposed. However, the gate electrode layer GE at a relatively high level is exposed by the contact hole H earlier than the gate electrode layer GE at a relatively low level. Therefore, in the process of etching the interlayer dielectric layer ILD until the lowermost gate electrode layer GE is exposed, a perforation failure may occur in which the etch stop function is not implemented and perforation occurs. As an example, as indicated by reference P, such a situation may occur: the contact hole H exposing the uppermost gate electrode layer GE passes through the uppermost gate electrode layer GE and exposes the gate electrode layer GE located therebelow. In this case, there may occur a problem that the contact plug C to be connected to the uppermost gate electrode layer GE also undesirably contacts the gate electrode layer GE located below the uppermost gate electrode layer GE. Such a perforation failure is exacerbated as the integration degree of the memory device increases, i.e., as the number of stacked gate electrode layers GE increases.

In the following embodiments, a memory device and a method for manufacturing the same, which can prevent the above-described problems and have various improved effects, will be described.

Fig. 3A and 3B to fig. 11A and 11B are diagrams illustrating a memory device and a method for manufacturing the same according to an embodiment of the present disclosure. For example, in the figures, each figure with a after the number is a sectional view, and each figure with B after the number is a top view taken along the line H1-H1' of a. For ease of description, these figures are shown centered on contact area a 2.

First, the manufacturing method will be described.

Referring to fig. 3A and 3B, a substrate 100 may be provided. The substrate 100 may include a semiconductor substrate, and may further include various elements formed in and/or on the semiconductor substrate. Specifically, in an embodiment, the substrate 100 may include the peripheral circuit element 105 formed in the contact area a 2. The peripheral circuit elements 105 are elements that can be connected to the gate electrode layers of the memory cells, respectively. They are shown in the form of a box for convenience, but may include one junction of a switching transistor, a metal pad, a metal wiring, and the like.

Then, on the substrate 100 including the peripheral circuit element 105, a stacked structure ST in which a plurality of inter-gate dielectric layers 112 and a plurality of sacrificial layers 114 are alternately stacked may be formed. The inter-gate dielectric layer 112 functions to insulate vertically adjacent gate electrode layers of the memory cell from each other, and may include various dielectric materials, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination of two or more thereof. The sacrificial layer 114 is a layer to be replaced with a conductive material used as a gate electrode layer of the memory cell, may include various materials having an etching rate different from that of the intergate dielectric layer 112, and may include a semiconductor material or a conductive material in addition to a dielectric material. The reason why the etching rate of the sacrificial layer 114 is different from that of the intergate dielectric layer 112 is to prevent the intergate dielectric layer 112 from being lost in a subsequent process of removing the sacrificial layer 114. In one example, the intergate dielectric layer 112 may include silicon oxide, and the sacrificial layer 114 may include silicon nitride. Although the embodiment shows three inter-gate dielectric layers 112 and three sacrificial layers 114 alternately stacked in the vertical direction, the number of inter-gate dielectric layers 112 and the number of sacrificial layers 114 may be changed in various ways.

Here, the laminated structure ST in the contact area a2 may be patterned to have a substantially stepped shape. Accordingly, any sacrificial layer 114 may have a portion that protrudes further toward the contact region a2 than the sacrificial layer 114 immediately above it. Accordingly, the surface of the protruding portion of each of the uppermost sacrificial layer 114 and the remaining sacrificial layers 114 may be in an exposed state immediately after being patterned to have a stepped shape.

Although not shown in the drawings, the channel pillars CP and the memory layer ML described above with reference to fig. 2A and 2B may be formed in the stacked structure ST including the plurality of inter-gate dielectric layers 112 and the plurality of sacrificial layers 114 formed in the cell array region before patterning the stacked structure ST of the contact region a 2. However, if necessary, in this step, only the channel pillars CP may be formed, and the memory layer ML may not be formed, or only a portion of the memory layer ML may be formed. In this case, all or a part of the memory layer ML that has not been formed yet may be formed later (for example, between the process of removing the sacrifice layer 114 and the process of filling the gate electrode layer). This will be described in the corresponding section.

Referring to fig. 4A and 4B, a sacrifice pad 120 may be formed on an exposed surface of each sacrifice layer 114. The sacrifice pad 120 is a layer to be replaced with a conductive material connected to the gate electrode layer of the memory cell, and may be removed before or after a subsequent process of removing the sacrifice layer 114. The sacrificial pad 120 may be formed of various materials having an etch rate different from that of the sacrificial layer 114 and the inter-gate dielectric layer 112. The reason is to prevent the inter-gate dielectric layer 112 from being lost in a subsequent process of removing the sacrifice pad 120, and to prevent the sacrifice pad 120 from being lost in a subsequent process of recessing the sacrifice layer 114. In an example, if inter-gate dielectric layer 112 comprises silicon oxide and sacrificial layer 114 comprises silicon nitride, sacrificial pad 120 may comprise polysilicon. However, these materials may be selected in various combinations as long as the intergate dielectric layer 112, the sacrificial layer 114, and the sacrificial pad 120 have different etching rates while the intergate dielectric layer 112 includes a dielectric material.

The sacrificial pad 120 on any sacrificial layer 114 should not be in contact with the sacrificial layer 114 immediately above it. To this end, the thickness of the sacrifice pad 120 and/or its distance from the intergate dielectric layer 112 may be appropriately controlled. For example, the sacrifice pad 120 may be spaced apart from the inter-gate dielectric layer 112, the bottom surface of which is located at the same height as the sacrifice pad 120, by a predetermined distance. Alternatively, the thickness of the sacrifice pad 120 may be smaller than the thickness of the inter-gate electrode dielectric layer 112 whose bottom surface is located at the same height as the sacrifice pad 120. Alternatively, the sacrifice pad 120 may be spaced apart from the intergate dielectric layer 112, the bottom surface of which is located at the same height as the sacrifice pad 120, by a predetermined distance, and at the same time, may have a smaller thickness than the intergate dielectric layer 112.

Here, the process of forming the sacrifice pad 120 may be performed in various ways. In one example, although not shown in the figures, the victim pad 120 may be formed by: depositing a sacrificial layer for forming the sacrificial pad 120 along the surface of the stepped structure shown in fig. 3A and 3B; forming a passivation layer along a surface of the deposited sacrificial layer by depositing a material having poor step coverage characteristics to form a passivation layer having a greater thickness on a top surface of the step structure and a smaller thickness on sidewalls of the step structure; isotropically etching the passivation layer to expose the sacrificial layer on the sidewalls of the stepped structure such that the passivation layer remains only on the top surface of the stepped structure; removing the exposed sacrificial layer on the sidewalls of the stepped structure by isotropic etching such that the sacrificial layer remains only on the top surface of the stepped structure; and removing the passivation layer. Here, the thickness of the sacrifice pad 120 or the distance between the sacrifice pad 120 and the intergate dielectric layer 112 can be controlled by controlling the degree of isotropic etching during the removal of the sacrifice layer.

Next, an interlayer dielectric ILD covering the stacked structure ST on which the sacrifice pad 120 is formed may be formed over the substrate 100. In an example, the interlayer dielectric layer ILD may include silicon oxide.

Referring to fig. 5A and 5B, contact holes 130 may be formed, the contact holes 130 providing a space in which contact plugs are to be formed, the contact plugs being connected to gate electrode layers of the memory cells, respectively.

When viewed from the top, each contact hole 130 may be formed at a position overlapping each sacrifice pad 120 and/or the protruding portion of each sacrifice layer 114, similar to that described above with reference to fig. 2A and 2B. Further, each contact hole 130 may be formed at a position overlapping with the corresponding peripheral circuit element 105 when viewed from the top. The peripheral circuit element 105 may be one junction of the switching transistor, or a pad or a wiring connected to one junction of the switching transistor.

When viewed in cross section, each contact hole 130 may be formed to have a depth passing through all of the interlayer dielectric ILD, the sacrifice pad 120, and the stack structure ST, unlike as described above with reference to fig. 2A and 2B. Further, in the embodiment, each contact hole 130 may be formed to have a depth to expose the peripheral circuit element 105 formed in the substrate 100. The formation of such contact holes 130 may be performed by selectively etching the interlayer dielectric ILD, the sacrifice pad 120, the stacked structure ST, and the substrate 100 until the peripheral circuit element 105 is exposed. That is, in an embodiment, the etching does not stop on the sacrificial pad 120 and/or the sacrificial layer 114, but may intentionally cause perforation.

Referring to fig. 6A and 6B, the sacrificial layer 114 exposed through the contact hole 130 may be partially recessed. The recessing of the sacrificial layer 114 may be performed by isotropic etching.

The space formed by recessing the sacrificial layer 114 is hereinafter referred to as a groove G. The groove G may have a shape surrounding a side surface of the contact hole 130 at a position corresponding to each sacrificial layer 114 (see a dotted line in fig. 6B). In addition, a distance from a side surface of the contact hole 130 to a side surface of the groove G may be smaller than a distance from a side surface of the contact hole 130 to a side surface of the sacrifice pad 120. Accordingly, although the groove G is formed, the sacrifice layer 114 and the sacrifice pad 120 can be connected to each other.

As described above, the etch rate of the sacrifice layer 114 is different from the etch rate of the intergate dielectric layer 112 and the sacrifice pad 120, and thus the intergate dielectric layer 112 and the sacrifice pad 120 can be prevented from being lost during the recessing of the sacrifice layer 114.

Referring to fig. 7A and 7B, the sealing layer 140 may be formed along the entire surface of the structure resulting from the process shown in fig. 6A and 6B. The sealing layer 140 may be formed to have a thickness that substantially fills the groove G.

Here, the sealing layer 140 serves to prevent physical and electrical connection between the gate electrode layer and the contact plug in a subsequent process of replacing the sacrificial layer 114 with the gate electrode layer and filling the contact hole 130 with the contact plug, and may be made of various dielectric materials. In addition, since the sealing layer 140 should not be lost in the subsequent processes of removing the sacrificial layer 114 and removing the sacrificial pad 120, it may be formed of a material having an etching rate different from those of the sacrificial layer 114 and the sacrificial pad 120. In an example, the sealing layer 140 may include silicon oxide.

Referring to fig. 8A and 8B, an etch-back process may be performed on the sealing layer 140 to form a sealing layer pattern 140' remaining only in the groove G.

An etch-back process may be performed so that the sealing layer 140 on the sidewalls of the contact holes 130 and the sealing layer 140 on the top surface of the peripheral circuit element 105 may be sufficiently removed. Accordingly, the side surfaces of the sacrifice pad 120 and the top surface of the peripheral circuit element 105 can be exposed.

The sealing layer pattern 140' may have a shape surrounding a side surface of the contact hole 130 at a position corresponding to each sacrificial layer 114. That is, the sealing layer pattern 140' may have the same thickness as each sacrificial layer 114 at the same height. In addition, the width of the seal layer pattern 140 '(i.e., the distance from the side surface of the contact hole 130 to the outer side surface of the seal layer pattern 140') may be smaller than the X-direction width of the sacrifice pad 120 (i.e., the width from the side surface of the contact hole 130 to the side surface of the sacrifice pad 120 in the X-direction).

Referring to fig. 9A and 9B, a contact plug 150 filling each contact hole 130 may be formed.

The contact plug 150 may have a thickness to substantially fill the contact hole 130. The contact plug 150 may be formed by depositing a conductive material such as a metal, a metal nitride, or a combination thereof, and then performing a planarization process (e.g., a CMP (chemical mechanical polishing) process) until a top surface of the inter-layer dielectric layer ILD is exposed.

Each contact plug 150 may pass through the interlayer dielectric ILD, the sacrifice pad 120, the stack structure ST, and a portion of the substrate 100, and may be directly connected to the corresponding peripheral circuit element 105.

Referring to fig. 10A and 10B, the stacked structure ST may be selectively etched to form a slit S in the stacked structure ST.

The slit S may extend in the X direction, and the laminated structure ST may be divided into a plurality of structures in the Y direction by the slit S. The slit S may be formed to have a depth at least through the lowermost sacrificial layer 114 in the stacked structure ST. Further, the slits S may be formed simultaneously with the cell array region slits (not shown), or may be formed separately.

Next, the sacrificial layer 114 exposed through the slit S may be removed. The removal of the sacrificial layer 114 may be performed by an isotropic etching method such as wet etching. During the removal of the sacrificial layer 114, the inter-gate dielectric layer 112, the sacrificial pad 120 and the sealing layer pattern 140' having an etch rate different from that of the sacrificial layer 114 may be prevented from being lost. Even if the sacrificial layer 114 is removed, a portion of the sidewall of the contact plug 150 corresponding to each sacrificial layer 114 may not be exposed because it is surrounded by the sealing layer pattern 140'. The space formed by removing the sacrificial layer 114 will be referred to as a first space SP1 hereinafter.

Then, the sacrifice pad 120 exposed through the slit S may be removed. The removal of the sacrifice pad 120 may also be performed by an isotropic etching method such as wet etching. The intergate dielectric layer 112 and the sealing layer pattern 140' having an etching rate different from that of the sacrifice pad 120 may be prevented from being lost during the removal of the sacrifice pad 120. By removing the sacrifice pads 120, a portion of the sidewalls of the contact plug 130 corresponding to each sacrifice pad 120 may be exposed. The space formed by removing the sacrifice pad 120 will be referred to as a second space SP2 hereinafter.

In an embodiment, the sacrificial layer 114 is removed first, and then the sacrificial pad 120 is removed, but the order of removal may be reversed.

Although not shown in the drawings, if all or a portion of the memory layer ML is not formed in the cell array region, the process of forming the slits S and the process of removing the sacrificial layer 114 may be separately performed in the cell array region and the contact region a 2. In other words, the process of forming the slits S in the cell array region and removing the sacrificial layer 114 may be performed first, and then the process of forming the slits S in the contact region a2 and removing the sacrificial layer 114 may be performed, or vice versa. After the process of forming the slits and removing the sacrificial layer 114 in the cell array region and before the subsequent process shown in fig. 11A and 11B, a part or all of the memory layer ML that has not been formed may be formed along the inner wall of the space from which the sacrificial layer 114 has been removed.

Referring to fig. 11A and 11B, the first space SP1 and the second space SP2 may be filled with a conductive material to form the conductive pattern 160.

The formation of the conductive pattern 160 may be performed by: a conductive material such as a metal, a metal nitride, or a combination thereof is deposited on the structure resulting from the processes shown in fig. 10A and 10B to a thickness that substantially fills the first and second spaces SP1 and SP2, and then an etch-back process is performed such that the conductive material remains only in the first and second spaces SP1 and SP 2.

The conductive pattern 160 may be divided into a first conductive pattern 160A filling the first space SP1 and a second conductive pattern 160B filling the second space SP 2. The first conductive pattern 160A may function as a gate electrode layer of the memory cell. The second conductive pattern 160B may serve as a connection portion connecting any gate electrode layer of the memory cell to the corresponding contact plug 130. That is, the uppermost second conductive pattern 160B may connect the uppermost first conductive pattern 160A to the leftmost contact plug 150; the second uppermost second conductive pattern 160B may connect the second uppermost first conductive pattern 160A to the second contact plug 150 from the left side; and the lowermost second conductive pattern 160B may connect the lowermost first conductive pattern 160A to the rightmost contact plug 150.

In this case, although the contact plug 150 is formed to completely pass through the first laminate structure ST, it may be separated from the first conductive pattern 160A by the seal layer pattern 140'. However, it may be connected to the first conductive pattern 160A of the layer to be connected through the second conductive pattern 160B formed thereon.

As a result, a memory device including the contact region a2 structure shown in fig. 11A and 11B can be manufactured.

Referring again to fig. 11A and 11B, the memory device of an embodiment may include: a substrate 100 including a peripheral circuit element 105; a stacked structure formed on the substrate 100 and in which the inter-gate dielectric layer 112 and the first conductive patterns 160A are alternately stacked, wherein the stacked structure has a stepped shape such that any first conductive pattern 160A has a portion protruding further than the first conductive pattern 160A located immediately above it; a second conductive pattern 160B formed on the protruding portion of each first conductive pattern 160A; contact plugs 150 penetrating the laminated structure and the substrate 100 in which each of the second conductive patterns 160B, the intergate dielectric layer 112, and the first conductive patterns 160A are alternately laminated, and connected to the corresponding peripheral circuit element 105; and a sealing layer pattern 140' interposed between each of the first conductive patterns 160A and the contact plug 150 and physically and electrically separating them. Here, a distance from the sidewall of the contact plug 150 to the side surface of the sealing layer pattern 140' may be less than a distance from the side surface of the contact plug 150 to the side surface of the second conductive pattern 160B, and thus, a portion of the top surface of the first conductive pattern 160A may be in direct contact with a portion of the bottom surface of the second conductive pattern 160B.

Here, the contact plug 150 to be connected to the first conductive pattern 160A of any one layer may be connected to the corresponding first conductive pattern 160A through the second conductive pattern 160B disposed on and in direct contact with the corresponding first conductive pattern 160A, not in direct contact with the corresponding first conductive pattern 160A, and the contact plug 150 may be separated from the first conductive patterns 160A of the remaining layers through the sealing layer pattern 140'.

Further, the bottom surface of the contact plug 150 may be directly connected to the peripheral circuit element 105 to be connected. In an example, the left contact plug 150 connected to the uppermost first conductive pattern 160A may be separated from the uppermost first conductive pattern 160A by the seal layer pattern 140', and a portion of a side surface thereof may be connected to the second conductive pattern 160B located on and in contact with the uppermost first conductive pattern 160A, and a bottom surface of the left contact plug 150 may be connected to the left peripheral circuit element 105. As a result, a current path may be generated, which passes through the uppermost first conductive pattern 160A, the second conductive pattern 160B thereon, the left contact plug 150, and the left peripheral circuit element 105.

According to the above embodiment, the following advantages can be obtained.

First, it is not necessary to stop etching on each sacrificial layer 114 and/or each sacrificial pad 120 during the formation of the contact holes 130, and thus a via failure can be fundamentally prevented. In addition, since it is not necessary to precisely control the etching so that the etching stops on each sacrificial layer 114 and/or each sacrificial pad 120, process difficulty may be reduced.

Further, in the embodiment, the peripheral circuit region in which the peripheral circuit element 105 is formed may be disposed below the stacked structure of the contact region a2, and thus the area of the memory device may be reduced.

Further, since the bottom surface of the contact plug 150 connected to each of the first conductive patterns 160A serving as the gate electrode layer is directly connected to the peripheral circuit element 105, there is an advantage that an additional connection member does not have to be formed. If the bottom surface of the contact plug 150 is not directly connected to the peripheral circuit element 105, for example, if the bottom surface of the contact plug C contacts each gate electrode layer GE as in the embodiment shown in fig. 2A and 2B, it may be necessary to form various connection members such as a contact plug, a pad, and a wiring that connect the top surface of the contact plug C to the peripheral circuit element in order to connect the contact plug C to the peripheral circuit element. However, in the embodiment, the contact plug 150 may perform both a function of connecting to the gate electrode layer and a function of connecting to the peripheral circuit element, and thus the formation of such an additional connection member may be omitted.

However, in the embodiment, the peripheral circuit element may not be arranged below the contact plug, and thus the contact plug may perform only a function of being connected to the gate electrode layer without being directly connected to the peripheral circuit element. This will be described below by way of example with reference to fig. 12A and 12B.

Fig. 12A and 12B are cross-sectional views illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure. Fig. 12A is a sectional view illustrating a case where the depth of the contact hole in the process shown in fig. 5 is changed, and fig. 12B is a sectional view illustrating a memory device manufactured according to a subsequent process after the process shown in fig. 12A, and also particularly illustrates a peripheral circuit region a 3.

Referring to fig. 12A, a substrate 100' may be provided. The substrate 100' may include various elements, but may not include a peripheral circuit element to be connected to at least one contact plug.

Then, on the substrate 100', a stack structure ST in which a plurality of inter-gate dielectric layers 112 and a plurality of sacrificial layers 114 are alternately stacked and patterned to have a stepped shape, a sacrificial pad 120 on a protruding portion of each of the sacrificial layers 114, and an interlayer dielectric layer ILD covering the stack structure ST and the sacrificial pad 120 may be formed.

Then, the contact hole 130 'may be formed, and the contact hole 130' passes through the interlayer dielectric layer ILD, the sacrifice pad 120, and the stack structure ST. Since no peripheral circuit element is present in the substrate 100', the depth of the contact hole 130' can be variously adjusted on the premise that the contact hole passes through the stack structure ST. In an example, as shown, the contact hole 130' may have a depth passing through the stack structure ST and exposing the substrate 100', and the depth of the contact hole 130' may be uniform. That is, the bottom levels of the plurality of contact holes 130' may be substantially the same as each other. However, in other embodiments, the bottom levels of the plurality of contact holes 130' may also be different from each other on the premise that they pass through the stack structure ST.

Next, substantially the same subsequent processes as those of the above-described embodiment (i.e., the processes shown in fig. 6A and 6B to 11A to 11B) may be performed, thereby forming the memory device shown in fig. 12B.

Referring to fig. 12B, in the contact region a2, a contact plug 150 'may be formed, and the bottom level of the contact plug 150' is different from that of the contact plug 150 shown in fig. 11A. Since there is no peripheral circuit element under the contact plug 150', the contact plug 150' may not be directly connected to the peripheral circuit element. For this reason, a process of connecting the contact plug 150 'to the peripheral circuit element 105' of the peripheral circuit region a3 may be required.

In an example, the peripheral circuit region A3 may be disposed adjacent to one side of the contact region a2 or spaced apart from the contact region a2, and the peripheral circuit element 105 'may be formed on the substrate 100' in the peripheral circuit region A3. As described above, the peripheral circuit element 105' may be one junction of the switching transistor, or a pad or a wiring connected thereto.

The contact plug 150' may be connected to a conductive pattern (e.g., the wiring 180) connected to a top surface of the contact plug. The wiring 180 may extend to the peripheral circuit region A3, and may be connected to the peripheral contact plug 170, and the peripheral contact plug 170 passes through the interlayer dielectric ILD of the peripheral circuit region A3 and is connected to the peripheral circuit element 105'.

As a result, a current path may be generated through the contact plug 150', the wiring 180, the peripheral contact plug 170, and the peripheral circuit element 105'.

In these embodiments, it is possible to obtain the effect of preventing the via failure and reducing the difficulty of the etching process.

Fig. 13A and 13B to 17A and 17B are diagrams illustrating a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure. In fig. 13A and 13B to fig. 17A and 17B, each figure with a after the number is a sectional view, and each figure with B after the number is a top view taken along a line H1-H1' in each figure with a after the number. The following description will focus on differences from the above-described embodiments in fig. 3A and 3B to fig. 11A and 11B.

Referring to fig. 13A and 13B, substantially the same process as described above with reference to fig. 3A and 3B through 5A and 5B is performed, and then a sealing layer 240 may be formed on the sidewalls of each contact hole 130.

The sealing layer 240 may be formed of various dielectric materials. Specifically, it may include a material (e.g., silicon oxide) having an etch rate different from that of the sacrificial layer 114 and the sacrificial pad 120.

The formation of the sealing layer 240 may be performed by: a dielectric material is deposited along the structure resulting from the process shown in fig. 5A and 5B to a small thickness that does not completely fill the contact hole 130, and then an etch-back process is performed to remove the dielectric material from the top of the interlayer dielectric ILD and the bottom of the contact hole 130. Therefore, the peripheral circuit element 105 may be exposed through the bottom of the contact hole 130.

Referring to fig. 14A and 14B, a contact plug 250 filling each of the contact holes 130 on which the sealing layer 240 is formed may be formed.

The contact plug 250 may be formed by depositing a conductive material such as a metal, a metal nitride, or a combination thereof to a thickness sufficient to fill the contact hole 130 on which the sealing layer 240 is formed, and then performing a planarization process until a top surface of the interlayer dielectric ILD is exposed.

Through this process, the entire sidewall of the contact plug 250 may be surrounded by the sealing layer 240, so that the contact plug 250 may be separated from the sacrificial layer 114 and the sacrificial pad 120.

Referring to fig. 15A and 15B, the stacked structure ST may be selectively etched to form a slit S extending in the X direction while having a depth passing through at least the lowermost sacrificial layer 114.

Next, the sacrifice pad 120 exposed through the slit S may be removed, and then a portion of the sealing layer 240 exposed by removing the sacrifice pad 120 may also be removed. The space formed by removing the sacrifice pad 120 and the sealing layer 240 will be referred to as a third space SP3 hereinafter. By forming the third space SP3, a portion of the sidewall of the contact plug 250 facing the sacrifice pad 120 may be exposed.

Referring to fig. 16A and 16B, the sacrificial layer 114 exposed through the slit S may be removed. The space formed by removing the sacrificial layer 114 will be referred to as a fourth space SP4 hereinafter.

In an embodiment, the process of removing the sacrifice pad 120 and a part of the sealing layer 240 is performed first, and the process of removing the sacrifice layer 114 is performed subsequently. However, the order of these removal processes may also be reversed.

Referring to fig. 17A and 17B, the third space SP3 and the fourth space SP4 may be filled with a conductive material to form a conductive pattern 260.

The conductive patterns 260 may include a first conductive pattern 260A filling the fourth space SP4 and a second conductive pattern 260B filling the third space SP 3. The first conductive pattern 260A may function as a gate electrode layer of the memory cell. The second conductive pattern 260B may serve as a connection portion connecting any gate electrode layer of the memory cell to the corresponding contact plug 250.

As a result, a memory device including the structure of the contact region a2 shown in fig. 17A and 17B can be manufactured.

Referring again to fig. 17A and 17B, the memory device of these embodiments may include: a substrate 100 including a peripheral circuit element 105; a stacked structure formed on the substrate 100 and in which the inter-gate dielectric layer 112 and the first conductive patterns 260A are alternately stacked, wherein the stacked structure has a stepped shape such that any first conductive pattern 260A has a portion protruding further than the first conductive pattern 260A located immediately above it; a second conductive pattern 260B formed on the protruding portion of each first conductive pattern 260A; a contact plug 250 passing through the laminated structure and the substrate 100 in which each of the second conductive patterns 260B, the first conductive patterns 260A, and the inter-gate dielectric layer 112 are alternately laminated, and connected to the corresponding peripheral circuit element 105; and a sealing layer 240 interposed between each of the first conductive patterns 260A and the contact plug 250 and physically and electrically separating them.

Here, the main difference from the memory device of fig. 11A and 11B is the shape of the sealing layer 240. For example, in the memory device of fig. 11A and 11B, the sealing layer pattern 140' is interposed only between the first conductive pattern 160A and the contact plug 150. That is, the sealing layer pattern 140' may have the same thickness as the first conductive pattern 160A while being located at the same height as the first conductive pattern 160A. However, in an embodiment, the sealing layer 240 may completely surround the sidewalls of the contact plug 150 except between the second conductive pattern 260B and the contact plug 250.

The contact plug 250 to be connected to the first contact pattern 260A of any one layer may be connected to the corresponding first conductive pattern 260A through the second conductive pattern 260B disposed on and directly contacting the corresponding first conductive pattern 260A, instead of being directly connected to the corresponding first conductive pattern 260A, and the contact plug 250 may be separated from the first conductive patterns 260A of the remaining layers through the sealing layer 240'. As a result, effects similar to those obtained in the embodiments of fig. 3A and 3B to fig. 11A and 11B can be obtained.

Further, in the above-described embodiment, after the process of removing the sacrificial layer 114 and before the process of filling the space from which the sacrificial layer has been removed with the conductive material, the channel pillars of the cell array region and the contact plugs of the contact regions may function to support the stacked structure having the space from which the sacrificial layer 114 has been removed.

Examples of a memory device and a method for manufacturing the memory device, which can further enhance the support function, will be described.

Fig. 18A and 18B to fig. 24A and 24B illustrate a memory device and a method for manufacturing the memory device according to an embodiment of the present disclosure. In fig. 18A and 18B to fig. 24A and 24B, each figure with a after the number is a sectional view, and each figure with B after the number is a top view taken along a line H1-H1' in each figure with a after the number. 3 further 3, 3 each 3 cross 3- 3 sectional 3 view 3 illustrates 3a 3 cross 3- 3 section 3 taken 3 along 3 line 3A 3- 3A 3 ' 3 of 3 the 3 top 3 view 3 and 3a 3 cross 3- 3 section 3 taken 3 along 3 line 3B 3- 3B 3' 3 thereof 3. 3 The following description will not include the repetitive description that has been discussed with respect to the embodiments described above with reference to fig. 3A and 3B through fig. 11A and 11B.

Referring to fig. 18A and 18B, substantially the same process as that illustrated in fig. 3A and 3B through 4A through 4B is performed, and then the contact hole 130 may be formed, and at the same time, a hole for forming the support post (i.e., the support hole 135) may be formed.

When viewed from the top, the support hole 135 may be formed in a region overlapping each of the sacrifice pads 120 and/or the protruding portion of each of the sacrifice layers 114 and in which the contact hole 130 is not formed. In the embodiment, four support holes 135 are arranged to be spaced apart from the contact hole 130 by a predetermined distance in a diagonal direction of the contact hole 130, and a planar size of the support holes 135 is substantially the same as that of the contact hole 130, but the embodiment is not limited thereto. The number, arrangement, and planar size of the support holes 135 may be variously changed.

The support hole 135 may be formed to have the same depth as the contact hole 130 when viewed in cross section. However, the depth of the support hole 135 may be variously changed as long as the support hole 135 passes through the laminated structure ST.

Referring to fig. 19A and 19B, the sacrificial layer 114 exposed through the contact hole 130 and the support hole 135 may be partially recessed to form a groove G surrounding sidewalls of the contact hole 130 and the support hole 135 while having a width smaller than that of the sacrificial pad 120.

The sealing layer 140 may be formed to have a thickness that substantially fills the grooves G along the entire surface of the resulting structure in which the grooves G are formed.

Referring to fig. 20A and 20B, the sealing layer 140 may be etched back to form a sealing layer pattern 140' remaining only in the groove G.

Then, the contact hole 130 and the support hole 135 may be filled with a conductive material to form the contact plug 150. However, in the support hole 135, a support column should be formed, and the support column should play a single role of supporting the stacked structure without performing an electrical function such as a current moving path. Accordingly, the subsequent processes shown in fig. 21A and 21B to fig. 22A and 22B may also be performed.

Referring to fig. 21A and 21B, the contact plug 150 in each support hole 135 may be selectively removed. This may be performed in a state where a mask pattern (not shown) that may cover the contact hole 130 and expose the support hole 135 is formed.

Accordingly, an empty space may be formed again in each of the support holes 135.

Referring to fig. 22A and 22B, each support hole 135 may be filled with a dielectric material to form a support post 155. In an embodiment, the support columns 155 may have a bottom level substantially the same as or the same as the bottom level of the contact plugs 150, as shown in fig. 22A. For example, the bottom level of the contact plug 150 may contact the peripheral circuit element 105, and the bottom level of the support post 155 may be positioned substantially the same or the same as the bottom level of the contact plug 150. In some embodiments, the support hole 135 may have a depth substantially the same as that of the contact hole 130.

The support pillars 155 may be formed by depositing a dielectric material to a thickness to substantially fill the support holes 135 and then performing a planarization process until a top surface of the inter-layer dielectric layer ILD is exposed.

Since the support posts 155 should not be lost during a subsequent process of removing the sacrificial layer 114 and the sacrificial pad 120, the support posts 155 may include a dielectric material (e.g., silicon oxide) having an etch rate different from that of the sacrificial layer 114 and the sacrificial pad 120.

Referring to fig. 23A and 23B, the stacked structure ST may be selectively etched to form a slit S, and then the sacrificial layer 114 and the sacrificial pad 120 exposed through the slit S may be removed. A space formed by removing the sacrifice layer 114 may be referred to as a first space SP1, and a space formed by removing the sacrifice pad 120 may be referred to as a second space SP 2.

Even if the first space SP1 and the second space SP2 exist in the stacked structure due to the removal of the sacrifice layer 114 and the sacrifice pad 120, not only the contact plug 150 but also the support post 155 contact the intergate dielectric layer 112 and play a role of supporting them, and thus the tilting phenomenon in which the stacked structure collapses can be further prevented.

Referring to fig. 24A and 24B, the first space SP1 and the second space SP2 may be filled with a conductive material, thereby forming a conductive pattern 160 including a first conductive pattern 160A serving as a gate electrode layer of a memory cell and a second conductive pattern 160B serving as a connection portion connecting the gate electrode layer to the contact plug 150.

As a result, a memory device including the structure of the contact region a2 shown in fig. 24A and 24B can be manufactured.

Referring again to fig. 24A and 24B, the memory device of this embodiment may further include a support pillar 155 that performs a supporting function around the contact plug 150 together with the contact plug 150. Therefore, in addition to the same effects as those obtained in the embodiments of fig. 3A and 3B to fig. 11A and 11B, an effect of further preventing the inclination of the laminated structure can be obtained.

The embodiment shown in fig. 18A and 18B to 24A and 24B describes the case where the supporting columns 155 are further formed based on the embodiment of fig. 3A and 3B to 11A and 11B, but these embodiments can also be sufficiently applied to the case where the supporting columns 155 are further formed based on the embodiment of fig. 12A and 12B to 17A and 17B.

Although the above embodiments have been described with respect to a contact region having a stepped structure in a three-dimensional memory device, embodiments of the present disclosure are not limited thereto. The above embodiment is applicable if any semiconductor device has a stepped structure and a contact plug to be connected to each step needs to be formed.

As described above, the semiconductor device, the method for manufacturing the semiconductor device, and the memory device including the semiconductor device according to the embodiments of the present disclosure make it possible to improve processes and to reduce an area.

The memory circuit or the semiconductor device of the above embodiments can be used in various devices or systems. Fig. 25 shows an example of an apparatus or a system capable of implementing the memory circuit or the semiconductor device of the above embodiments.

Fig. 25 is an example of a configuration diagram of a data processing system for implementing a memory device according to an embodiment of the present disclosure.

Referring to fig. 25, a data processing system 1000 may include a host 1200 and a memory system 1100.

The host 1200 may include wired or wireless electronic devices. For example, the host 1200 may include a portable electronic device such as a mobile phone, an MP3 player, a laptop computer, or the like, or an electronic device such as a desktop computer, a game console, a television, a projector, or the like.

In addition, the host 1200 may include at least one Operating System (OS). An operating system may generally manage and control the functions and operations of host 1200 and provide interoperability between host 1200 and a user using data processing system 1000 or memory system 1100. Here, the operating system may support functions and operations corresponding to the use purpose of the user, and may be classified into a general operating system and a mobile operating system according to the mobility of the host 1200. General-purpose operating systems can be classified into personal operating systems and enterprise operating systems according to the use environment of a user. The personal operating system may be a system characterized by supporting a service providing function of a general user, and may include, for example, Windows, Chrome, and the like. The enterprise operating system may be a system characterized as secure and supporting high performance, and may include, for example, Windows server, Linux, Unix, and the like. The Mobile operating system may be a system characterized by supporting a user's mobility service provision function and a power saving function, and may include, for example, Android, iOS, Windows Mobile, and the like. The host 1200 may include a plurality of operating systems, and may execute the operating systems to perform an operation corresponding to a request of a user with the memory system 1100.

The memory system 1100 may operate in response to a request from the host 1200, and in particular, may store data accessed by the host 1200. In other words, the memory system 1100 may be used as a primary memory or a secondary memory of the host 1200. Here, the memory system 1100 may be implemented as any of various types of storage devices according to a host interface protocol connected to the host 1200. For example, the memory system 1100 may be implemented as any one of a Solid State Drive (SSD), a multimedia card (MMC), such as MMC, an embedded MMC (eMMC), a reduced-size MMC (RS-MMC), or a micro MMC, a Secure Digital (SD) card, such as SD, mini SD, or micro SD, a universal memory bus (USB) storage device, a universal flash memory (UFS) device, a Compact Flash (CF) card, a smart media card, a memory stick, and the like.

The memory system 1100 may include a memory device 1400 as a part storing data accessed by the host 1200 and a controller 1300 controlling data storage in the memory device 1400.

Here, the controller 1300 and the memory device 1400 may be integrated in one semiconductor device. For example, the controller 1300 and the memory device 1400 may be integrated in one semiconductor device to constitute the SSD. When the memory system 1100 is used as an SSD, the operation speed of the host 1200 connected to the memory system 1100 can be further improved. Alternatively, for example, the controller 1300 and the memory device 1400 may be integrated into one semiconductor device to constitute a memory card, such as a Personal Computer (PC) card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (such as an MMC, RS-MMC, or micro MMC), an SD card (such as an SD, a mini SD, a micro SD, or a Secure Digital High Capacity (SDHC)), a Universal Flash (UFS), or the like. Alternatively, for example, the memory system 1100 may constitute a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a desktop computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage constituting a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, A Radio Frequency Identification Device (RFID) or one of the various components that make up the computing system.

The memory device 1400 in the memory system 1100 can hold stored data even when power is not supplied, and can store data supplied from the host 1200 via a write operation and supply the stored data to the host 1200 via a read operation, for example. Here, the memory device 1400 may include a plurality of memories 1420, 1440, and 1460. Each of the plurality of memories 1420, 1440, and 1460 may include the three-dimensional nonvolatile memory device of the above-described embodiment. For example, each of the plurality of memories 1420, 1440, and 1460 may include: a stacked structure including a plurality of first conductive patterns and a plurality of dielectric layers that are alternately stacked, the stacked structure having a stepped structure such that any one of the plurality of first conductive patterns protrudes further than a first conductive pattern located immediately above it; a plurality of second conductive patterns respectively formed over the protrusions of the first conductive patterns; a plurality of contact plugs respectively overlapping the plurality of second conductive patterns and passing through the overlapping second conductive patterns and the laminated structure; and a sealing layer interposed between the first conductive pattern and the contact plug and separating the first conductive pattern from the contact plug. Thus, the manufacturing process of the memory device 1400 may be improved and the area of the memory device 1400 may be reduced. As a result, the manufacturing process of the memory system 1100 may be improved and the area of the memory system 1100 may be reduced.

The controller 1300 in the memory system 1100 can control the memory device 1400 in response to a request from the host 1200. For example, the controller 1300 may provide data read from the memory device 1400 to the host 1200 and store the data provided from the host 1200 in the memory device 1400. To this end, the controller 1300 may control operations such as reading, writing, programming, erasing, and the like.

With the above operations, the controller 1300 may include an interface unit for communicating with the host 1200, an interface unit for communicating with the memory device 1400, an operation memory for storing data for the operation of the controller 1300 and/or the memory system 1100, a processor for controlling the overall operation of the controller 1300 and/or the memory system 1100, and for this purpose, includes firmware such as a Flash Translation Layer (FTL) and is implemented as a microprocessor or a Central Processing Unit (CPU), or the like.

However, a system in which the memory circuit or the semiconductor device of the above embodiment can be used is not limited to the system of fig. 25. The memory circuit or the semiconductor device of the above embodiments can be provided in various systems requiring a nonvolatile memory.

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely exemplary. Accordingly, the disclosure described herein should not be limited based on the described embodiments.

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2019-0052203, filed on 3/5/2019, the entire contents of which are incorporated herein by reference.