阅读说明：本技术 芯片封装结构及电子设备 (Chip packaging structure and electronic equipment ) 是由 武正辉 顾沧海 于 2020-06-19 设计创作，主要内容包括：本申请公开了芯片封装结构及电子设备,涉及人工智能芯片技术领域。具体方案为：通过在封装基板上设置半导体基板,并在半导体基板上设置第一组管脚和第二组管脚,且第一组管脚与第二组管脚之间通过连接层上的多个连接通道相连,设置在半导体基板上的第一芯片所具有的第三组管脚与第一组管脚相连,设置在半导体基板上的第二芯片所具有的第四组管脚与第二组管脚相连,由于第一组管脚和第二组管脚是相连的,从而,使得第一芯片的第三组管脚和第二芯片的第四组管脚是相连的,由此,实现了第一芯片与第二芯片的互联,解决了现有封装技术中在封装基板上封装芯片,难以实现芯片之间的互联的技术问题。(The application discloses chip packaging structure and electronic equipment relates to artificial intelligence chip technical field. The specific scheme is as follows: the semiconductor substrate is arranged on the packaging substrate, the first group of pins and the second group of pins are arranged on the semiconductor substrate, the first group of pins and the second group of pins are connected through the plurality of connecting channels on the connecting layer, the third group of pins of the first chip arranged on the semiconductor substrate are connected with the first group of pins, the fourth group of pins of the second chip arranged on the semiconductor substrate are connected with the second group of pins, and the first group of pins and the second group of pins are connected, so that the third group of pins of the first chip and the fourth group of pins of the second chip are connected, and therefore the interconnection of the first chip and the second chip is achieved, and the technical problem that the chips are packaged on the packaging substrate in the prior art and the interconnection between the chips is difficult to achieve is solved.)

1. A chip package structure, comprising:

a package substrate;

a semiconductor substrate disposed over the package substrate, wherein the semiconductor substrate comprises:

a first set of pins and a second set of pins disposed over the semiconductor substrate;

the connecting layer is connected between the first group of pins and the second group of pins, the connecting layer is provided with a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels;

the semiconductor chip comprises a first chip and a second chip which are arranged on the semiconductor substrate, wherein the first chip is provided with a third group of pins, the second chip is provided with a fourth group of pins, the third group of pins are respectively connected with the first group of pins, and the fourth group of pins are respectively connected with the second group of pins.

2. The chip package structure of claim 1, wherein the third set of pins are connected to the first set of pins through a plurality of first metal balls, respectively, and the fourth set of pins are connected to the second set of pins through a plurality of second metal balls, respectively.

3. The chip package structure of claim 2, wherein the plurality of first metal balls and the plurality of second metal balls are tin.

4. The chip package structure of claim 1, wherein the semiconductor substrate is silicon.

5. The chip package structure of claim 1, further comprising:

a heat dissipation layer covering the first chip and the second chip.

6. The chip package structure according to claim 5, wherein the heat dissipation layer is a heat dissipation adhesive.

7. The chip packaging structure according to claim 1, wherein the semiconductor substrate is formed by a chip process, and the plurality of connection channels are formed by a wiring process.

8. The chip package structure of claim 1, further comprising:

a package case covering the package substrate; and

and the filling medium is filled in the packaging shell.

9. The chip package structure of claim 1, wherein the package substrate is a ceramic substrate.

10. An electronic device, comprising:

the chip packaging structure according to any one of claims 1 to 9.

Technical Field

Embodiments of the present application relate generally to the field of electronic devices and, more particularly, to the field of artificial intelligence chip technology.

Background

An Artificial Intelligence (AI) chip, also known as an AI accelerator or computing card, is a module dedicated to handling a large number of computing tasks in Artificial Intelligence applications.

With the development of electronic technology, the electronic devices are updated more and more quickly, and the market end has higher and higher requirements for chips used in the electronic devices. At present, for the packaging of chips, the required chips are generally directly mounted on a packaging substrate, so as to realize the modularization of multiple chips. However, when chips are packaged on a package substrate, it is difficult to interconnect the chips.

Disclosure of Invention

The application provides a chip packaging structure and electronic equipment.

According to a first aspect, there is provided a chip packaging structure, comprising:

a package substrate;

a semiconductor substrate disposed over the package substrate, wherein the semiconductor substrate comprises:

a first set of pins and a second set of pins disposed over the semiconductor substrate;

the connecting layer is connected between the first group of pins and the second group of pins, the connecting layer is provided with a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels;

the semiconductor chip comprises a first chip and a second chip which are arranged on the semiconductor substrate, wherein the first chip is provided with a third group of pins, the second chip is provided with a fourth group of pins, the third group of pins are respectively connected with the first group of pins, and the fourth group of pins are respectively connected with the second group of pins.

According to a second aspect, there is provided an electronic device comprising: the chip package structure according to the embodiment of the first aspect.

The application provides a chip packaging structure and electronic equipment has following beneficial effect:

the semiconductor substrate is arranged on the packaging substrate, the first group of pins and the second group of pins are arranged on the semiconductor substrate, the first group of pins and the second group of pins are connected through the plurality of connecting channels on the connecting layer, the third group of pins of the first chip arranged on the semiconductor substrate are connected with the first group of pins, the fourth group of pins of the second chip arranged on the semiconductor substrate are connected with the second group of pins, and the first group of pins and the second group of pins are connected, so that the third group of pins of the first chip and the fourth group of pins of the second chip are connected, and therefore the interconnection of the first chip and the second chip is achieved, and the technical problem that the chips are packaged on the packaging substrate in the prior art and the interconnection between the chips is difficult to achieve is solved.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not intended to limit the present application. Wherein:

fig. 1 is a schematic structural diagram of a chip package structure according to a first embodiment of the present application;

fig. 2 is a schematic structural diagram of a chip package structure according to a second embodiment of the present application;

fig. 3 is an exemplary diagram of a chip package structure according to an embodiment of the present application.

Detailed Description

The following description of the exemplary embodiments of the present application, taken in conjunction with the accompanying drawings, includes various details of the embodiments of the application for the understanding of the same, which are to be considered exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The chip package structure and the electronic apparatus of the present application are described below with reference to the drawings.

In the chip packaging technology, a 2D packaging process assembles active electronic components and passive devices having different functions, and other devices such as Micro Electro Mechanical Systems (MEMS), optical devices, and the like together to realize a single standard package having a certain function, so as to form a System or subsystem. The 2D packaging process has the characteristics of low packaging precision requirement and small packaging technology challenge, and the size of the package obtained by the 2D packaging process is large.

Moore's law puts requirements on the improvement of chip performance, and indicates that every 18-24 months, the size of the chip is reduced by half, and the performance is improved by one time. With the continuous development of electronic technology and internet technology, the market end needs chip products with high performance, low power consumption, small size and low time delay to meet the requirements of big data, artificial intelligence and the like. However, in the 2D packaging process, since a package substrate is adopted, and a required chip (i.e., an electronic component) is directly placed on the package substrate, it is difficult to achieve interconnection between chips, and for the design of transistors requiring tens of thousands or more, the size of the chip obtained by the 2D packaging process is larger and larger, the signal transmission delay is higher and higher, and the design requirements of high density and low power consumption of the chip cannot be met. Therefore, the existing 2D packaging process cannot meet the high performance and small size requirements of moore's law.

In view of the above problems, the present application discloses a chip package structure, in which a semiconductor substrate is disposed on the package substrate, a first group of pins and a second group of pins are disposed on the semiconductor substrate, and the first group of pins and the second group of pins are connected through a plurality of connection channels on a connection layer, a third group of pins of a first chip disposed on the semiconductor substrate are connected to the first group of pins, and a fourth group of pins of a second chip disposed on the semiconductor substrate are connected to the second group of pins. In addition, the first chip and the second chip are arranged on the same semiconductor substrate and are interconnected, so that the distance between the two chips is shortened, the transmission time of signals is shortened, the signal transmission time delay is smaller, the signal transmission speed is faster due to the fact that the time delay is small, the throughput ratio of the whole link is larger, and the signal bandwidth is higher. In addition, when the chip packaging structure comprises a plurality of semiconductor substrates, the semiconductor substrates can be overlapped and connected, so that the high-density packaging requirement of the chip can be met in a limited space, the packaging area is saved, and the packaging size is reduced. Therefore, the chip packaging structure provided by the application can meet the requirements of Moore's law on high performance and small size.

Fig. 1 is a schematic structural diagram of a chip package structure according to a first embodiment of the present application. As shown in fig. 1, the chip package structure 10 includes: the package substrate 110, the semiconductor substrate 120 disposed over the package substrate 110, and the first chip 130 and the second chip 140 disposed over the semiconductor substrate 120.

As shown in fig. 1, two sets of pins, namely a first set of pins and a second set of pins, are disposed on the semiconductor substrate 120. The semiconductor substrate 120 further includes a connection layer connected between the first group of pins and the second group of pins, and the connection layer has a plurality of connection channels, and the first group of pins and the second group of pins are connected through the plurality of connection channels.

In the present embodiment, the first chip 130 disposed on the semiconductor substrate 120 has a third group of pins (not shown in fig. 1), and the second chip 140 disposed on the semiconductor substrate 120 has a fourth group of pins (not shown in fig. 1), wherein the third group of pins is respectively connected to the first group of pins, and the fourth group of pins is respectively connected to the second group of pins. Since the first group of pins and the second group of pins on the semiconductor substrate 120 are connected to each other, the third group of pins are respectively connected to the first group of pins, and the fourth group of pins are respectively connected to the second group of pins, so that the third group of pins and the fourth group of pins are also connected to each other, thereby realizing interconnection between the first chip and the second chip.

Because the first chip 130 and the second chip 140 are interconnected and disposed on the same semiconductor substrate 120, the communication distance between the first chip 130 and the second chip 140 is shortened, a signal output by one chip can be quickly transmitted to another chip, and the transmission time of the signal is reduced, so that the time delay of signal transmission is small, and the small time delay reflects that the signal transmission speed is high, which is equivalent to that the throughput ratio of the whole link is large, so that the signal bandwidth is higher. Therefore, compared with a package obtained by a traditional 2D packaging process, the chip packaging structure of the embodiment of the application not only realizes interconnection between chips, but also reduces time delay, saves energy consumption, and has a higher bandwidth.

It should be noted that fig. 1 illustrates the present application by merely providing the first chip and the second chip on the semiconductor substrate as an example, and does not limit the present application. In practical application, a plurality of chips can be arranged on the semiconductor substrate according to requirements, so that interconnection of multiple chips is realized.

In addition, the present application is illustrated in fig. 1 only by way of example, and not by way of limitation, as the chip package structure includes one semiconductor substrate. In practical application, a plurality of semiconductor substrates can be arranged according to requirements, each semiconductor substrate can be provided with a plurality of chips, and the plurality of semiconductor substrates can be connected through a rewiring layer technology of a chip process to realize interconnection among the plurality of semiconductor substrates. The rewiring layer technology is to deposit a metal layer and a dielectric layer on the surface of a wafer and form a corresponding metal wiring pattern to re-arrange the input and output ports of the chip and arrange the input and output ports in a new area with looser pitch occupation. By adopting the rewiring layer technology to connect the plurality of semiconductor substrates, the plurality of semiconductor substrates can be overlapped like accumulated wood, the high-density packaging requirement of the chip can be met in a limited space, the packaging area is saved, the packaging size is reduced, and the small-size and high-density design of the chip packaging structure is realized.

In the embodiment of the present application, the package substrate 110 may be, but is not limited to, a Ball Grid Array (BGA) substrate, a multi-chip Module (MCM) substrate, and the like.

In one possible implementation manner of the embodiment of the present application, the package substrate 110 may be a ceramic substrate.

The ceramic substrate is a special process plate with copper foil directly bonded on the surface of an aluminum oxide or aluminum nitride ceramic substrate at high temperature, and has excellent electrical insulation performance, high heat conduction characteristic, high adhesion strength and large current carrying capacity. Therefore, in the embodiment of the application, the ceramic substrate is used as the package substrate to bear the semiconductor substrate, so that the semiconductor substrate can be firmly attached to the ceramic substrate, the heat conducting capacity and the electric insulating capacity of the chip package structure can be improved, and the usability of the chip package structure can be improved.

In the embodiment of the present application, for the connection between the package substrate 110 and the semiconductor substrate 120, the connection may be performed by using a conventional connection method between a chip and a package substrate, and the current mature package process is used for packaging, so that the package difficulty can be reduced, and the package success rate can be improved.

In a possible implementation manner of the embodiment of the present application, the third group of pins are connected to the first group of pins through a plurality of first metal balls, and the fourth group of pins are connected to the second group of pins through a plurality of second metal balls.

For example, for each pin in the third group of pins, the pin is connected to a corresponding one of the first group of pins through a first metal ball; for each pin in the fourth set of pins, the pin is connected to a corresponding one of the second set of pins through a second metal ball.

Through adopting first metal ball to connect third group pin and first group pin, adopt second metal ball to connect fourth group pin and second group pin, not only realized the interconnection between the pin to realize the interconnection of chip, still improved the flexibility that the pin is connected.

In the embodiment of the present application, the first metal ball and the second metal ball may be made of the same material or different materials. For example, the first metal ball may be silver and the second metal ball may be tin, or both the first metal ball and the second metal ball may be silver or tin.

In one possible implementation manner of the embodiment of the present application, the plurality of first metal balls and the plurality of second metal balls may be tin. For example, solder balls with small volume may be used as the first metal ball and the second metal ball to connect the first group of pins and the third group of pins, and the second group of pins and the fourth group of pins, respectively. Because the solder balls with small volume are adopted, gaps between the first chip 130 and the second chip 140 and the semiconductor substrate 120 are smaller, and the connection density between the chips and the semiconductor substrate is increased. In addition, since the melting point of tin metal is low, tin is used to connect the chip and the semiconductor substrate, which is beneficial to protecting the semiconductor substrate 120 from being damaged during soldering.

In one possible implementation manner of the embodiment of the present application, the semiconductor substrate 120 may be formed by a chip process, and the plurality of connection channels of the connection layer may be formed by a wiring process.

The chip process includes several links including chip design, wafer fabrication, package fabrication and test. Chip design, namely generating a chip pattern according to actual design requirements; the chip manufacturing comprises wafer manufacturing, wafer coating, wafer photoetching development and etching, impurity doping and wafer testing; fixing the manufactured wafer in a packaging manufacturing part, binding pins, and manufacturing different packaging forms according to requirements; and finally, testing the packaged chip, and removing defective products to finish the chip manufacturing.

In the application, the semiconductor substrate is formed by adopting a chip process, the manufacturing process of the semiconductor substrate is simplified, and the condition is provided for realizing interconnection between chips through the semiconductor substrate by adopting a wiring process to form a plurality of connecting channels.

In one possible implementation manner of the embodiment of the present application, the material used for the semiconductor substrate 120 may be silicon, that is, the silicon substrate is used as a carrier for carrying the first chip 130 and the second chip 140. In this embodiment, the silicon substrate may be manufactured by a standard digital chip manufacturing process, and different from the manufacturing of other chips, the silicon substrate may be manufactured by only using a limited number of metal layers of the standard digital chip manufacturing process, that is, a small number of metal layers, such as gold plating, are plated on the outer layer of the silicon wafer, so that a silicon substrate with a long service life may be obtained. Because the manufacturing of the silicon substrate adopts a chip production process, the winding resources of the silicon substrate are very rich, a plurality of interfaces can be reserved, and the expansion of a plurality of chips is facilitated, so that the expansion of a plurality of chips on the silicon substrate and the interconnection of the chips can be realized, the chip density can be improved, and the cost can be saved.

The packaged chip may generate heat during use, and if the heat dissipation capability is not good, the chip may be damaged, and therefore, in a possible implementation manner of the embodiment of the present application, the chip package structure 10 may further include a heat dissipation layer (not shown in fig. 1) covering the first chip 130 and the second chip 140. Therefore, the heat dissipation layer covering the first chip 130 and the second chip 140 is disposed in the chip package structure, so that heat dissipation of the chips is facilitated, and the service life of the chips is prolonged.

Further, in a possible implementation manner of the embodiment of the present application, the heat dissipation layer may be a heat dissipation adhesive. The heat dissipation glue has the advantage of high heat conductivity, so that the heat dissipation glue is adopted as the heat dissipation layer to cover the first chip and the second chip, the heat dissipation efficiency of the chip packaging structure can be improved, and the usability of the chip is improved.

Fig. 2 is a schematic structural diagram of a chip package structure according to a second embodiment of the present application. As shown in fig. 2, based on the embodiment shown in fig. 1, the chip package structure 10 further includes:

a package case 150 covering the package substrate 110, and a filling medium filled in the package case 150.

In fig. 2, the gray shaded area represents a filling medium, and the filling medium is used to fill the area between the package housing 150 and the package substrate 110, so as to improve the pressure resistance of the chip package structure and prevent the semiconductor substrate 120 on the package substrate 110 from being damaged due to an excessive pressure.

In this embodiment, the package housing 150 may be made of metal iron, and the manufactured package housing 150 may be thinner to improve the heat conduction efficiency.

In the embodiment of the application, the packaging substrate is covered by the packaging shell, and the filling medium is filled in the packaging shell, so that the pressure resistance of the chip packaging structure in the installation and use processes can be improved.

Fig. 3 is an exemplary diagram of a chip package structure according to an embodiment of the present application. In this example, the first chip is an Application Specific Integrated Circuit (ASIC), and the second chip is a High Bandwidth Memory (HBM). In fig. 3, a region enclosed by a dotted line is a silicon substrate, a white strip on the silicon substrate is a pin in the embodiment of the present application, the ASIC and the HBM are mounted on the silicon substrate through the pin, and the ASIC and the HBM are interconnected through the silicon substrate. When in connection, the ASIC, the HBM and the silicon substrate are connected by adopting the miniature solder balls, so that the connection density between the chip and the silicon substrate is increased, and the occupation of space is reduced. In fig. 3, the white stripe on the package substrate is a via hole, and the silicon substrate and the package substrate may be connected by using tin through the via hole to package the silicon substrate on the package substrate, and the tin ball under the package substrate may also be used to connect with other substrates. As shown in fig. 3, the silicon substrate is covered with a high thermal conductive heat dissipation adhesive to improve the heat dissipation efficiency, and the package substrate is covered with a package cover (i.e., a package housing in the embodiment of the present application), and the package cover can be an ultra-thin iron cover to improve the heat dissipation efficiency, and can also improve the pressure resistance of the chip during installation and use.

It should be noted that, in the actually fabricated chip package structure, the pins on the silicon substrate, the vias between the silicon substrate and the package substrate, and the solder balls under the package substrate cannot be seen, and the illustration in fig. 3 is only for convenience of understanding the composition of the chip package structure, and should not be taken as a limitation to the present application.

According to an embodiment of the present application, the present application also provides an electronic device. The electronic device comprises the chip packaging structure in the embodiment.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, sequentially, or in different orders, and the present invention is not limited thereto as long as the desired results of the technical solutions disclosed in the present application can be achieved.

The above-described embodiments should not be construed as limiting the scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.