阅读说明：本技术 集成电路芯片 (Integrated circuit chip ) 是由 湛伟 马淑彬 夏明刚 丛伟林 于 2020-04-20 设计创作，主要内容包括：集成电路芯片,涉及集成电路技术。本发明包括基板、封装外壳和设置于基板与封装外壳之间的芯片电路,其特征在于,所述封装外壳包括内外两层,内层和外层设置有金属区域,分布于内外两层的金属区域构成电容的两个极板,形成外壳电容,两个极板之间填充有导热绝缘材料；外壳电容至少有一个连接端穿过基片上的通孔连接到基片底面。本发明利用封装外壳形成电容器的电容值远远大于芯片本身集成的电容值,并且无需考虑电容器的高度,封装金属外壳电容器可以离芯片(die)本身足够近,因此芯片的高度(厚度)可以非常小。(An integrated circuit chip relates to the integrated circuit technology. The invention comprises a substrate, a packaging shell and a chip circuit arranged between the substrate and the packaging shell, and is characterized in that the packaging shell comprises an inner layer and an outer layer, the inner layer and the outer layer are provided with metal areas, the metal areas distributed on the inner layer and the outer layer form two polar plates of a capacitor to form a shell capacitor, and a heat-conducting insulating material is filled between the two polar plates; the housing capacitor has at least one connection terminal connected to the bottom surface of the substrate through a via in the substrate. The capacitance value of the capacitor formed by the packaging shell is far greater than the capacitance value integrated by the chip, the height of the capacitor does not need to be considered, the packaging metal shell capacitor can be close enough to the chip (die), and therefore the height (thickness) of the chip can be very small.)

1. The integrated circuit chip comprises a substrate, a packaging shell and a chip circuit arranged between the substrate and the packaging shell, and is characterized in that the packaging shell comprises an inner layer and an outer layer, the inner layer and the outer layer are provided with metal areas, the metal areas distributed on the inner layer and the outer layer form two polar plates of a capacitor to form a shell capacitor, and a heat-conducting insulating material is filled between the two polar plates; the housing capacitor has at least one connection terminal connected to the bottom surface of the substrate through a via in the substrate.

2. The integrated circuit chip of claim 1, wherein the case capacitor is electrically connected to the chip circuitry by a conductor, and the capacitor plate at the outermost layer is electrically connected to the GND terminal of the chip.

3. The integrated circuit chip of claim 1, wherein the outer layers are entirely metal.

4. The integrated circuit chip of claim 2, wherein the inner layers are entirely metal, and the inner and outer layers form a capacitor.

5. The integrated circuit chip of claim 2, wherein the inner layer has at least two metal regions, the inner and outer layers forming at least two case capacitors.

6. The integrated circuit chip of claim 1, wherein the inner layer is entirely metal, the outer layer has at least two metal regions, and the inner and outer layers form at least two shell capacitors.

Technical Field

The present invention relates to integrated circuit technology.

Background

The chip (die) internally integrated with the large capacitor occupies a large chip area, technically affects the manufacturing yield of the chip, and has a high cost due to the increase of the chip area. Therefore, the typical chip-internal integrated capacitance ranges from a few hundred femtofarads (fF, 10-15F) to a few tens of picofarads (pF, 10-12F).

Thus, larger capacitors typically require external connection through the chip, or integration of additional capacitors within the package, or connection of the capacitors to a Printed Circuit Board (PCB) through package pins.

The extra capacitor is integrated in the package, so that the height of the capacitor is greatly limited, and the height of the capacitor is generally required to be within 0.5 mm. Therefore, there are many restrictions on the selection of the capacitor.

Connecting capacitors on a Printed Circuit Board (PCB) through package pins may occupy PCB board area. Further, due to soldering or the like, the external large-capacitance capacitor generally cannot be sufficiently close to the chip pin.

The cross-sectional view of a conventional package is shown in fig. 1, wherein the reference L ID is a package metal shell layer, and it can be seen that the package metal shell has only one layer, which plays the role of protecting the chip and dissipating heat, and cannot play the role of a capacitor.

Disclosure of Invention

The invention aims to solve the technical problem of providing an integrated circuit chip which simultaneously meets the requirements of miniaturization and large capacitance.

The invention solves the technical problem by adopting the technical scheme that the integrated circuit chip comprises a substrate, a packaging shell and a chip circuit arranged between the substrate and the packaging shell, and is characterized in that the packaging shell comprises an inner layer and an outer layer, the inner layer and the outer layer are provided with metal regions, the metal regions distributed on the inner layer and the outer layer form two polar plates of a capacitor to form a shell capacitor, and a heat-conducting insulating material is filled between the two polar plates; the housing capacitor has at least one connection terminal connected to the bottom surface of the substrate through a via in the substrate.

The shell capacitor is in circuit connection with the chip circuit through a conductor, and the capacitor plate positioned on the outermost layer is in circuit connection with the GND end of the chip.

Further, the whole outer layer is made of metal. The inner layer is entirely made of metal, and the inner layer and the outer layer form a capacitor. Or the inner layer is provided with at least two metal areas, and the inner layer and the outer layer form at least two shell capacitors.

Or the inner layer is wholly made of metal, the outer layer is provided with at least two metal areas, and the inner layer and the outer layer form at least two shell capacitors.

The invention has the beneficial effect that the invention utilizes the multilayer packaging metal shell as the capacitor, and completely overcomes the defects of the prior art. The capacitance value of the capacitor formed by the packaging shell is far greater than the capacitance value integrated by the chip, the height of the capacitor does not need to be considered, the packaging metal shell capacitor can be close enough to the chip (die), and therefore the height (thickness) of the chip can be very small. The invention realizes the large capacitor with capacitance value far exceeding that of the prior art in limited space and has the characteristic of miniaturization.

The packaging metal shell is used as a capacitor, and is very suitable for being applied to the field of power decoupling (decoupling) of an integrated circuit, and the fields of power circuits and chips, filter circuits and chips and the like in the integrated circuit which need to be externally connected with large capacitors, such as a linear modulation output power (L DO) circuit, a low-pass filter circuit, a high-pass filter circuit, a band-pass filter circuit and the like.

The packaging metal shell of the invention is used as a capacitor and can be applied to the field of other integrated circuits needing large external capacitors.

In the circuit, the integrated circuit chip of the invention is taken as a specific chip, and the shell capacitor on the specific chip can be taken as a circuit device of a circuit part except the specific chip.

Drawings

Fig. 1 is a schematic view of a prior art structure.

Fig. 2 is a schematic structural diagram of a first embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a second embodiment of the present invention.

Detailed Description

See fig. 2. In the figure, 1-outer layer, 2-inner layer, 3-heat conducting insulating material, 4-substrate, 5-chip circuit, 6-signal connection point and 7-through hole.

First embodiment

The packaging shell comprises an inner layer and an outer layer, wherein the two layers are made of metal materials and respectively comprise an outer layer 1 and an inner layer 2. The insulating heat conduction material is filled between the outer layer 1 and the inner layer 2, so that the effect of insulation between the cathode and the anode of the capacitor is achieved, and the effect of heat generation of the chip is achieved.

The signal connection points of the outer layer 1 and the inner layer 2 are connected with circuit signals of a chip (die) or a printed circuit board through signal routing and via holes in the packaging substrate.

The signal connection points have a width wider than that of the metal layer on the section, and are favorable for bonding connection with signal routing and via holes in the packaging substrate. And the thickness of the packaging metal layer can be more flexible, and the packaging metal layer can be made thinner.

In the circuit, the device formed by the outer layer 1, the inner layer 2 and the insulating heat conduction material is equivalent to a capacitor.

When the chip is tested and used, the package metal layer 1 may be accidentally contacted with other signals. In order to avoid interference with the signals inside the chip, the outer layer 1 should be connected to a Ground (GND) signal, i.e. as the negative pole of the capacitor.

Second embodiment

See fig. 3. The shaded area of fig. 3 represents a metal area.

The present embodiment provides a plurality of capacitors, and the package housing includes an inner package layer and an outer package layer, which are referred to as an inner layer and an outer layer. The first encapsulation layer includes a metal region and an insulator region, and the insulator region surrounds the metal region or is embedded in the insulator region. In this way, the first encapsulation layer can be provided with a plurality of metal regions, or capacitor plates. At this moment, the second packaging layer can be wholly made of metal, a metal pole plate arrangement mode of the first packaging layer can also be adopted, pole plates on the two packaging layers correspond in position, a plurality of capacitors can be achieved, and all or part of connecting wires are led to the bottom surface of the substrate through wires.