阅读说明：本技术 预通材料在各向异性导体中的使用 (Use of pre-vias in anisotropic conductors ) 是由 M·E·塔特尔 J·F·克丁 O·R·费伊 中野永一 罗时剑 于 2020-02-07 设计创作，主要内容包括：本申请涉及预通材料在各向异性导体中的使用。一种半导体装置组合件具有第一衬底、第二衬底和各向异性导电膜。所述第一衬底包含第一多个连接器。所述第二衬底包含第二多个连接器。所述各向异性导电膜定位在所述第一多个连接器与所述第二多个连接器之间。所述各向异性导电膜具有电绝缘材料以及通过所述电绝缘材料横向分隔开的多个互连件。所述多个互连件形成从所述第一多个连接器延伸到所述第二多个连接器的导电通道。一种方法包含将所述多个互连件连接到所述第一多个连接器和所述第二多个连接器,使得所述导电通道可操作以将电从所述第一衬底传导到所述第二衬底。所述方法可包含通过所述多个互连件传送电流。(The present application relates to the use of a pre-via material in an anisotropic conductor. A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulating material and a plurality of interconnects laterally separated by the electrically insulating material. The plurality of interconnects form conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors such that the conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method can include communicating a current through the plurality of interconnects.)

1. A semiconductor device assembly, comprising:

a first substrate having a first plurality of connectors;

a second substrate having a second plurality of connectors; and

an anisotropic conductive film positioned between the first plurality of connectors and the second plurality of connectors, the anisotropic conductive film having an electrically insulating material and a plurality of interconnects laterally separated by the electrically insulating material, the plurality of interconnects forming conductive channels extending from the first plurality of connectors to the second plurality of connectors.

2. The semiconductor device assembly of claim 1, wherein the anisotropic conductive film is a microporous film and the plurality of interconnects are pores of the microporous film.

3. The semiconductor device assembly of claim 2, wherein the electrically insulating material is acrylic-based or epoxy-based.

4. The semiconductor device assembly of claim 1, wherein the plurality of interconnects form a plurality of conductive channels extending from one of the first plurality of connectors to one of the second plurality of connectors.

5. The semiconductor device assembly of claim 1, wherein the plurality of interconnects each have a width, the first plurality of connectors have a spacing, the spacing of the first plurality of connectors is a distance between adjacent connectors of the first plurality of connectors, and a width of at least a subset of the plurality of interconnects is less than the spacing of the first plurality of connectors.

6. The semiconductor device assembly of claim 5, wherein the subset of the plurality of interconnects are first interconnects, and the plurality of interconnects includes at least one second interconnect having a width greater than a width of the first interconnects, the at least one second interconnect positioned laterally between first interconnects.

7. The semiconductor device assembly of claim 5, wherein the spacing of the first plurality of connectors is uniform and the width of the plurality of interconnects is uniform.

8. The semiconductor device assembly of claim 5, wherein the widths of the plurality of interconnects include a first width and a second width, the second width being orthogonal to the first width, and wherein the spacing of the first plurality of connectors includes a first spacing and a second spacing, the second spacing being orthogonal to the first spacing, the first widths of the plurality of interconnects being less than the first spacing of the first plurality of connectors, and the second widths of the plurality of interconnects being less than the second spacing of the first plurality of connectors.

9. The semiconductor device assembly of claim 8, wherein the first width of the plurality of interconnects is less than the second spacing of the first plurality of connectors and the second width of the plurality of interconnects is less than the first spacing of the first plurality of connectors.

10. The semiconductor device assembly of claim 5, wherein the first plurality of connectors each have a width, the plurality of interconnects have a spacing, the spacing of the plurality of interconnects is a distance between adjacent ones of the plurality of interconnects, and the spacing of the plurality of interconnects is less than the width of the first plurality of connectors.

11. The semiconductor device assembly of claim 10, wherein the width of the first plurality of connectors is uniform and the spacing of the plurality of interconnects is uniform.

12. The semiconductor device assembly of claim 10, wherein the spacing of the plurality of interconnects includes a first spacing and a second spacing, the second spacing being orthogonal to the first spacing, and wherein the width of the first plurality of connectors includes a first width and a second width, the second width being orthogonal to the first width, the first spacing of the plurality of interconnects being less than the first width of the first plurality of connectors, and the second spacing of the plurality of interconnects being less than the second width of the first plurality of connectors.

13. The semiconductor device assembly of claim 12, wherein the first spacing of the plurality of interconnects is less than the second width of the first plurality of connectors and the second spacing of the plurality of interconnects is less than the first width of the first plurality of connectors.

14. The semiconductor device assembly of claim 1, wherein the anisotropic conductive film does not include an adhesive.

15. An anisotropic conductive film, comprising:

an upper portion;

a lower portion;

a plurality of interconnects extending from the upper portion to the lower portion, each interconnect forming a conductive channel prior to application to a substrate; and

an electrically insulating material through which the plurality of interconnects are laterally separated.

16. The acf of claim 15 wherein the plurality of interconnects each have a width and a spacing, the spacing of the plurality of interconnects being a distance between adjacent interconnects, the width being uniform, and the spacing being uniform.

17. The acf of claim 16 wherein the widths of the plurality of interconnects include a first width and a second width, the second width being orthogonal to the first width, and wherein the spacings of the plurality of interconnects include a first spacing and a second spacing, the second spacing being orthogonal to the first spacing, the first width being uniform, the second width being uniform, the first spacing being uniform, and the second spacing being uniform.

18. The acf of claim 17 wherein the first spacing is equal to the second spacing.

19. The acf of claim 15 wherein the electrically insulating material is a microporous membrane and the plurality of interconnects are pores of the microporous membrane.

20. A method of fabricating a semiconductor device assembly, comprising:

providing a first substrate having a first plurality of connectors;

providing a second substrate having a second plurality of connectors;

providing an anisotropic conductive film having a plurality of interconnects laterally separated by an electrically insulating material and forming a plurality of conductive channels;

connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, wherein the conductive vias are operable to conduct electricity from the first substrate to the second substrate; and

passing current between the first substrate and the second substrate through the plurality of interconnects.

Technical Field

Embodiments described herein relate to anisotropic conductors that can increase reliability and conductivity between substrates and methods of using such anisotropic conductors.

Background

Semiconductor processing and packaging technologies continue to evolve to meet industry demands for increased performance, reduced cost, and/or reduced size. Electronic products, such as cellular telephones, smart phones, tablet computers, personal digital assistants, laptop computers, and other electronic devices, may utilize packaged semiconductor assemblies having a high density of devices while having a relatively small footprint. To connect two substrates together, a semiconductor assembly may utilize an anisotropic conductive film (also known as ACF tape) to conduct through the thickness of the film.

Fig. 8 shows the semiconductor device assembly 100 with the ACF tape 120 positioned between the connector 102 of the first substrate 101 and the connector 112 of the second substrate 111. The ACF tape 120 may contain an adhesive 122 filled with conductive particles 121. The adhesive 122 forms a mechanical connection between the connector 102 of the first substrate 101 and the connector 112 of the second substrate 111. The first substrate 101 has a spacing 106, which is the distance between adjacent connectors 102 of the first substrate 101. The second substrate 111 has a spacing 116, which is the distance between adjacent connectors 112 of the second substrate 111. The spacing 106 between the connectors 102 of the first substrate 101 is selected based on the size and density of the conductive particles 121. For example, a larger spacing 106 may be required due to increased particle size and/or density.

Fig. 9 shows an ACF tape 120 electrically connecting the first substrate 101 to the second substrate 111. Prior to application, the conductive particles 121 are inoperable to provide electrical interconnection throughout the thickness of the ACF tape 120. During the application process, the conductive particles 121 positioned between the connectors 102 of the first substrate 101 and the connectors 112 of the second substrate 111 are compressed into compressed conductive particles 123. When the adhesive 122 is cured, the ACF tape 120 mechanically adheres the first substrate 101 to the second substrate 111, and the compressed conductive particles 123 remain in a compressed state. The one or more compressed conductive particles 123 form an electrical connection in the z-direction between the connector 102 of the first substrate 101 and the connector 112 of the second substrate 111. However, the size of the conductive particles 121, and thus the compressed conductive particles 123, may limit the spacing 106 of the connectors 102 of the first substrate 101.

As shown in fig. 9, the connector 102 on the first substrate 101 includes a first connector 103, a second connector 104, and a third connector 105, and the connector 112 on the second substrate 111 includes a first connector 113, a second connector 114, and a third connector 115. The compressed conductive particles 123 form an electrical connection in the z-direction between the first connector 103 of the first substrate 101 and the first connector 113 of the second substrate 111 and between the second connector 104 of the first substrate 101 and the second connector 114 of the second substrate 111. However, the density of the conductive particles 121 may form groups 124 that also create electrical connections in the x-direction and/or the y-direction and cause undesirable shorting between adjacent connectors. The likelihood of shorting may be reduced by increasing the spacing 106 of the connectors 102 of the first substrate 101 and the spacing 116 of the connectors 112 of the second substrate 111, which may increase the overall size of the semiconductor device assembly 100.

In addition, the distribution of the conductive particles 121 may be insufficient to create an electrical connection between certain connectors. As shown in fig. 9, in the ACF tape 120, the distribution of the conductive particles 121 in the gap 125 (best shown in fig. 8) between the third connector 105 of the first substrate 101 and the third connector 115 of the second substrate 111 may be insufficiently dispersed. Thus, the ACF tape 120 may be highly dependent on alignment and/or require a more labor intensive process to achieve adequate distribution of the conductive particles 121. Additional drawbacks and disadvantages may exist.

Disclosure of Invention

In an embodiment, a semiconductor device assembly is provided. The semiconductor device assembly includes: a first substrate having a first plurality of connectors; a second substrate having a second plurality of connectors; and an anisotropic conductive film positioned between the first and second plurality of connectors, the anisotropic conductive film having an electrically insulating material and a plurality of interconnects laterally separated by the electrically insulating material, the plurality of interconnects forming conductive channels extending from the first plurality of connectors to the second plurality of connectors.

In an embodiment, an anisotropic conductive film is provided. The anisotropic conductive film includes: an upper portion; a lower portion; a plurality of interconnects extending from the upper portion to the lower portion, each interconnect forming a conductive channel prior to application to a substrate; and an electrically insulating material through which the plurality of interconnects are laterally separated.

In an embodiment, a method of fabricating a semiconductor device assembly is provided. The method comprises the following steps: providing a first substrate having a first plurality of connectors; providing a second substrate having a second plurality of connectors; providing an anisotropic conductive film having a plurality of interconnects laterally separated by an electrically insulating material and forming a plurality of conductive channels; connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, wherein the conductive vias are operable to conduct electricity from the first substrate to the second substrate; and transferring current between the first substrate and the second substrate through the plurality of interconnects.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a semiconductor device assembly having an anisotropic conductive film connecting multiple substrates.

Fig. 2 is a schematic view of an embodiment of a substrate having a plurality of connectors.

Fig. 3 is a schematic view of the substrate of fig. 2, with an array of electrical interconnects positioned throughout the substrate.

Fig. 4 is a schematic diagram of an embodiment of a semiconductor device assembly having an anisotropic conductive film connecting multiple substrates.

Fig. 5 is a schematic diagram of an embodiment of an electrical interconnect of a connector and an anisotropic conductive film.

Fig. 6 is a schematic diagram of an embodiment of a semiconductor device assembly having an anisotropic conductive film connecting multiple substrates.

Fig. 7 is a flow chart of an embodiment of a method of fabricating a semiconductor device assembly.

Fig. 8 is a schematic diagram of a semiconductor device assembly having an ACF tape having conductive particles positioned between connectors of a first substrate and connectors of a second substrate.

Fig. 9 is a schematic diagram of a semiconductor device assembly having an ACF tape having conductive particles compressed between connectors of a first substrate and connectors of a second substrate.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the appended claims.

Detailed Description

In the present disclosure, numerous specific details are set forth to provide a thorough and informative description of embodiments of the disclosure. One skilled in the art will recognize that the present disclosure may be practiced without one or more of the specific details. Well-known structures and/or operations typically associated with semiconductor devices and semiconductor device packages may not be shown and/or may not be described in detail to avoid obscuring other aspects of the disclosure. In general, it is understood that various other devices, systems, and/or methods in addition to those specific embodiments disclosed herein are also within the scope of this disclosure.

The term "semiconductor device assembly" may refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates, which may include interposers, supports, and/or other suitable substrates. The semiconductor device assembly may be fabricated in, but not limited to, a discrete package form, a strip or matrix form, and/or a wafer sheet form. The term "semiconductor device" generally refers to a solid state device comprising a semiconductor material. The semiconductor device may include, for example, a semiconductor substrate, a wafer, a board, or a single die from a wafer or substrate. The semiconductor device may refer to a semiconductor die herein, but the semiconductor device is not limited to a semiconductor die.

As used herein, the terms "vertical," "lateral," "upper," and "lower" may refer to the relative directions or positions of features in a semiconductor device and/or semiconductor device assembly shown in the figures. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. Additionally, orthogonal x, y, and z directions may also be used for illustration purposes, where the z direction is referred to as "vertical" and the x and y directions are referred to as "lateral". However, these terms should be interpreted broadly to include semiconductor devices and/or semiconductor device assemblies having other orientations, such as upside down or tilted orientation, where top/bottom, above/below, up/down, and left/right may be interchanged depending on the orientation. Further, it should be understood that the figures herein are not necessarily drawn to scale or uniform and that certain features may be exaggerated for ease of illustration. As will be appreciated by those of ordinary skill in the art having the benefit of the present disclosure, the shape, size, configuration, and/or location of elements are shown for illustrative purposes and may vary.

Various embodiments of the present disclosure relate to semiconductor devices, semiconductor device assemblies, semiconductor packages, semiconductor device packages, and methods of making and/or operating semiconductor devices.

An embodiment of a semiconductor device assembly includes a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulating material and a plurality of interconnects laterally separated by the electrically insulating material. The plurality of interconnects form conductive channels extending from the first plurality of connectors to the second plurality of connectors.

An embodiment of an anisotropic conductive film includes an upper portion, a lower portion, a plurality of interconnects, and an electrically insulating material. The plurality of interconnects extend from the upper portion to the lower portion. Each interconnect forms a conductive via prior to application to the substrate. The plurality of interconnects are laterally separated by electrically insulating material.

An embodiment of a method of making a semiconductor device assembly includes providing a first substrate, providing a second substrate, and providing an anisotropic conductive film. The first substrate has a first plurality of connectors. The second substrate has a second plurality of connectors. The anisotropic conductive film has a plurality of interconnects. The plurality of interconnects are laterally separated by an electrically insulating material and form a plurality of conductive channels. The method includes connecting the plurality of interconnects to a first plurality of connectors and a second plurality of connectors, wherein the conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method includes transferring current between a first substrate and a second substrate through the plurality of interconnects.

Fig. 1 is a schematic diagram in the XZ plane of an embodiment of a semiconductor device assembly 200. The semiconductor device assembly 200 includes a first substrate 201 and a second substrate 211. The first substrate 201 includes a plurality of connectors 202. The second substrate 211 includes a plurality of connectors 212 in electrical communication with the plurality of connectors 202 of the first substrate 201. As will be appreciated by those skilled in the art having the benefit of this disclosure, the first substrate 201 and/or the second substrate 211 may be a semiconductor device.

The plurality of connectors 202 of the first substrate 201 have a width 205. The pitch of the plurality of connectors 202 is the distance between the centers of adjacent connectors 202. The width 205 of the plurality of connectors 202 of the first substrate 201 may be uniform. As used herein, the term "uniform" encompasses both the same characteristic as well as a repeating pattern of characteristics. The first substrate 201 has a spacing 206, which is the distance between adjacent connectors 202 of the first substrate 201. The spacing 206 between each pair of adjacent connectors 202 of the first substrate 201 may be uniform. The plurality of connectors 212 of the second substrate 211 have a width 215. The pitch of the plurality of connectors 212 is the distance between the centers of adjacent connectors 212. The width 215 of the plurality of connectors 212 of the second substrate 211 may be uniform. In some embodiments, the width 215 of the plurality of connectors 212 of the second substrate 211 is equal to the width 205 of the plurality of connectors 202 of the first substrate 201. The second substrate 211 has a spacing 216, which is the distance between adjacent connectors 212 of the second substrate 211. The spacing 216 between each pair of adjacent connectors 212 of the second substrate 211 may be uniform. In some embodiments, the spacing 206 of the plurality of connectors 202 of the first substrate 201 is equal to the spacing 216 of the plurality of connectors 212 of the second substrate 211.

Fig. 2 shows a portion of a first substrate 201 in an XY plane and a plurality of connectors 202 of the first substrate 201. The plurality of connectors 202 of the first substrate 201 have a width 207. The width 207 of the plurality of connectors 202 of the first substrate 201 may be uniform. Width 205 is referenced in the x-direction and width 207 is referenced in the y-direction. The first substrate 201 has a spacing 208, which is the distance between adjacent connectors 202 of the first substrate 201. The spacing 208 between each pair of adjacent connectors 202 of the first substrate 201 may be uniform. The spacing 206 is oriented in the x-direction and the spacing 208 is referenced in the y-direction. Interval 206 may be equal to interval 208. As will be appreciated by those skilled in the art, the connectors 212 of the second substrate 211 likewise have a width and spacing in the x-direction and the y-direction.

Referring again to fig. 1, the plurality of connectors 202 of the first substrate 201 are electrically connected to the plurality of connectors 212 of the second substrate 211 via the anisotropic conductive film 220. The anisotropic conductive film 220 includes a plurality of interconnects 221 extending in the z-direction. The plurality of interconnects 221 are vertically oriented and form a plurality of conductive channels through the thickness of the anisotropic conductive film 220. As used herein, the term "pre-pass" means that the plurality of interconnects 221 are operable to provide electrical interconnection when ends of the plurality of interconnects 221 are placed in contact with a connector that needs to be electrically connected. In contrast, the conductive particles 121 shown in fig. 8 and 9 are not pre-turned on because they are not operable to provide electrical interconnection without compressing the conductive particles 121 together after application to a substrate.

In the x-direction, the plurality of interconnects 221 have a width 225 and a spacing 226, which is the distance between adjacent interconnects 221. The spacing 226 between each pair of adjacent interconnects 221 may be uniform. Fig. 3 is a schematic view in the XZ plane of an embodiment of an array of interconnects 221 aligned with the first substrate 201. For illustration purposes, the array of interconnects 221 is not shown in fig. 3 as being aligned with the second substrate 211, but persons of ordinary skill in the art having benefit of the present disclosure will appreciate that the plurality of interconnects 221 are also aligned with the second substrate 211. The plurality of interconnects 221 have a width 225 and a spacing 226 referenced in the x-direction, and a width 227 and a spacing 228 referenced in the y-direction. The array shape of the interconnection 221 is formed by a width 225 and a space 226 in the x direction and a width 227 and a space 228 in the y direction. The array shape of the connectors 202 of the first substrate 201 is formed by widths 205 and intervals 206 in the x direction and widths 207 and intervals 208 in the y direction.

Referring again to fig. 1, a plurality of interconnects 221 provide electrical communication through the anisotropic conductive film 220. In operation, the anisotropic conductive film 220 is positioned between the first substrate 201 and the second substrate 211. At least a portion of the plurality of interconnects 221 are aligned with the connectors 202 and 212 of the first and second substrates 201 and 211. The interconnect 221 is operatively connected to one connector 202 of the first substrate 201 and one connector 212 of the second substrate 211 such that an electrical communication path is established through the interconnect 221. For example, the interconnects 221 may be electrically connected to the connectors 202 of the first substrate 201 via solder. In some embodiments, a plurality of interconnects 221 are operably connected between one connector 202 of the first substrate 201 and one connector 212 of the second substrate 211, and form a plurality of conductive channels therebetween.

The plurality of interconnects 221 are laterally spaced apart in an electrically insulating material. As used herein, the term "electrically insulating material" means a material adapted to prevent current flow between adjacent interconnects 221. The anisotropic conductive film 220 may be an electrically insulating microporous film 222, and the plurality of interconnects 221 may be vertical holes, e.g., channels, extending through the microporous film 222. A plurality of interconnects 221 extend through the thickness of the microporous membrane 222 in the z-direction to provide electrical communication between the upper portion 223 and the lower portion 224. In some embodiments, the microporous membrane 222 may be formed from polyethylene or polypropylene. In some embodiments, the microporous membrane 222 may be an acrylic-based membrane or an epoxy-based membrane. The plurality of interconnects 221 are formed of a conductive material suitable for use in integrated circuits. For example, the plurality of interconnects 221 may be formed of nickel, copper, solder, or gold. The plurality of interconnections 221 may be formed by electroless plating. For example, the microporous membrane 222 may be electrolessly plated with nickel, copper, or gold after palladium activation. The microporous membrane 222 may have a thickness in the z-direction of between two and two hundred microns.

In some embodiments, the microporous membrane 222 may include an adhesive that aids in the physical connection between the first substrate 201 and the second substrate 211 and provides a connection between the plurality of interconnects 221 and the connector 202 of the first substrate 201 and the connector 212 of the second substrate 211. In other embodiments, the microporous membrane 222 does not include an adhesive, and the connection between the plurality of interconnects 221 and the connectors 202, 212 of the first substrate 201 and the second substrate 211 may provide a physical connection therebetween. Thus, the use of adhesives can be reduced. The additional connector 202 of the first substrate 201 may be provided for the purpose of establishing additional physical connections, and may not be operable to receive or supply electrical communication.

The microporous membrane 222 may be a flexible membrane conforming to the shape of the first substrate 201 and/or the second substrate 211. In some embodiments, the microporous membrane 222 may be a non-flexible material, such as glass or ceramic. The non-flexible microporous membrane 222 may provide additional structural activity and/or reduce stress due to Coefficient of Thermal Expansion (CTE) mismatch between materials.

The widths and spacing of the connectors 202 of the first substrate 201, the connectors 212 of the second substrate 211, and the interconnects 221 may be selected based on the desired configuration of the semiconductor device assembly 200. In some embodiments, the width 205 of the connector 202 of the first substrate 201 is approximately one micron and the width 225 of the plurality of interconnects is sub-micron. In a semiconductor device assembly where overall size minimization is desired, the array of connectors 202 of the first substrate 201 can substantially correspond to the array of interconnects 221. When the anisotropic conductive film 220 is applied to the first substrate 201 and the second substrate 211, a small tolerance may be utilized. The width 225 and spacing 226 of the interconnects 221 are selected to provide electrical communication between a connector 202 on the first substrate 201 and the second substrate 211 without the interconnects 221 contacting an adjacent connector 202 on the first substrate 201 or an adjacent connector 212 on the second substrate 211.

Manufacturing advantages and efficiencies may be obtained by providing an anisotropic conductive film 220 that may be applied with greater manufacturing flexibility (e.g., greater tolerances or at different orientations) without shorting adjacent connectors 202, 212. As shown in fig. 3, the spacing 226 of the plurality of interconnects 221 is less than the width 205 of the connector 202 of the first substrate 201 such that at least one interconnect 221 will align with the connector 202 of the first substrate 201 in the x-direction. In addition, the spacing 228 of the plurality of interconnects 221 is less than the width 207 of the connector 202 of the first substrate 201 such that at least one interconnect 221 will align with the connector 202 of the first substrate 201 in the y-direction. In the x-direction, the spacing 226 and width 225 of the interconnecting members 221 and the spacing 206 and width 205 of the connectors 202 can be selected, and in the y-direction, the spacing 228 and width 227 of the interconnecting members 221 and the spacing 208 and width 207 of the connectors 202 can be selected such that the entire cross-section of at least one of the interconnecting members 221 is aligned with each connector 202. The array of interconnects 221 may be offset in the x-direction and/or the y-direction and still maintain alignment with the connector 202. If the spacing of the plurality of interconnects 221 is less than the width of the connectors 202 of the first substrate 201 in a direction, greater tolerances may be utilized along the direction when applying the anisotropic conductive film 220 (shown in fig. 1) to the first substrate 201 and the second substrate 211 without shorting adjacent connectors 202, 212.

In some embodiments, the spacings 226 and 228 of the plurality of interconnects 221 may each be less than each of the widths 205 and 207 of the connectors 202 of the first substrate 201. In some embodiments, the width 205 in the x-direction may be equal to the width 207 in the y-direction. Interval 226 may be equal to interval 228. When the spacings 226, 228 of the plurality of interconnects 221 are each less than the widths 205, 207 of the connectors 202 of the first substrate 201, the anisotropic conductive film 220 (shown in fig. 1) can be applied to align its x-direction with either the x-direction or the y-direction of the array of connectors 202 of the first substrate 201, with at least one interconnect 221 aligned with each connector 202 of the first substrate 201. In some embodiments, the anisotropic conductive film 220 may be applied at any angular offset, as will be appreciated by those skilled in the art having the benefit of this disclosure.

As shown in fig. 1, the spacing 206 of the plurality of connectors 202 of the first substrate 201 and the spacing 216 of the plurality of connectors 212 of the second substrate 211 may each be greater than the width 225 of the plurality of interconnects 221. Where the width 225 of the plurality of interconnects 221 is less than the spacings 206 and the spacings 216, the plurality of interconnects 221 of the anisotropic conductive film 220 can be used to electrically connect a connector 202 on the first substrate 201 with a corresponding connector 212 on the second substrate 211 without providing electrical communication between adjacent connectors 202 on the first substrate 201 or adjacent connectors 212 on the second substrate 211 through the interconnects 221 in the x-direction. Likewise, as shown in fig. 3, the spacing 208 of the plurality of connectors 202 of the first substrate 201 and the spacing in the y-direction of the plurality of connectors 212 of the second substrate 211 (shown in fig. 1) are each greater than the width 227 of the plurality of interconnects 221 such that the interconnects 221 do not provide electrical communication in the y-direction between adjacent connectors 202 of the first substrate 201 or adjacent connectors 212 on the second substrate 211 (shown in fig. 1). Interval 206 may be equal to interval 208. When the widths 225, 227 of the plurality of interconnects 221 are each less than the spacings 206, 208 of the connectors 202 of the first substrate 201, the anisotropic conductive film 220 (shown in fig. 1) may be applied to align its x-direction with the x-direction or y-direction of the array of connectors 202 of the first substrate 201 without forming shorts between adjacent connectors 202. Larger tolerances may be utilized when applying the anisotropic conductive film 220 (shown in fig. 1) to the first substrate 201 and the second substrate 211 without shorting adjacent connectors 202, 212.

Fig. 4 shows a schematic diagram of an embodiment of a semiconductor device assembly 300 having an anisotropic conductive film 320 that provides electrical communication between a connector 302 of a first substrate 301 and a connector 312 of a second substrate 311. A plurality of interconnects 321 are laterally spaced apart in an electrically insulating material 322 having an upper portion 323 and a lower portion 324. The upper portion 323 does not contact the connector 302 of the first substrate 301 to which it is proximate, and the lower portion 324 does not contact the connector 312 of the second substrate 311 to which it is proximate. The plurality of interconnects 321 each include an upper end 325 and a lower end 326. The upper end 325 is in contact with the connector 302 of the first substrate 301 and the lower end 326 is in contact with the connector 312 of the second substrate 311. The upper end 325 extends beyond the upper portion 323 of the electrically insulating material 322 to form an upper gap 327 between the electrically insulating material 322 and the connector 302 of the first substrate 301. Lower end 326 extends beyond lower portion 324 of electrically insulating material 322 to form a lower gap 328 between electrically insulating material 322 and connector 312 of second substrate 311. The upper gap 327 and the lower gap 328 may be the same size.

The electrically insulating material 322 does not include an adhesive for connecting the first substrate 301 and the second substrate 311, and the connection between the plurality of interconnects 321 and the connectors 302, 312 of the first substrate 301 and the second substrate 311 provides a physical connection therebetween. The additional connector 302 of the first substrate 301 may be provided for the purpose of establishing an additional physical connection, and may not be operable to receive or supply electrical communication.

Fig. 5 is a schematic diagram of an embodiment of a connector and an interconnect of an anisotropic conductive film 420 providing electrical communication between a first substrate 400 and a second substrate 410. For purposes of illustration, various embodiments have been shown laterally separated within electrically insulating material 422 to form anisotropic conductive film 420. While some embodiments may utilize different configurations of connectors, interconnects, widths, and spacings together in the same anisotropic conductive film, additional manufacturing advantages may be realized by virtue of utilizing a uniform configuration throughout the electrically insulating material. Thus, the following description should be understood to apply to embodiments utilizing a single configuration and embodiments utilizing multiple configurations.

The first configuration 441 shows two interconnects 431 that provide electrical communication between the first connector 401 of the first substrate 400 and the first connector 411 of the second substrate 410. The width of the two interconnects 431 and the spacing therebetween is approximately equal to the width of the first connector 401 of the first substrate 400 and the first connector 411 of the second substrate 410.

The second configuration 442 shows five interconnects 432 that provide electrical communication between the second connector 402 of the first substrate 400 and the second connector 412 of the second substrate 410. The width of the five interconnecting members 432 and the spacing therebetween is approximately equal to the width of the second connector 402 and the second connector 412. The smaller width of the interconnects 432 as compared to the interconnects 431 of the first configuration 441 may allow the adjacent second connector 402 and the adjacent second connector 412 to have a smaller spacing without causing shorting. Five interconnects 432 are used for illustrative purposes, but as will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, any plurality of interconnects 432, such as five or more interconnects 432, may be in contact with the second connector 402 and the second connector 412. As the width of the interconnecting members 432 decreases, the spacing between adjacent second connectors 402, 412 may also decrease.

The third configuration 443 shows three interconnects 433 that provide electrical communication between the third connector 403 of the first substrate 400 and the third connector 413 of the second substrate 410. The third connector 403 of the first substrate 400 may be formed from multiple portions that are collectively operable to receive or supply electrical communication.

The fourth configuration 444 shows a plurality of interconnects including a subset of the first interconnects 434a and a subset of the second interconnects 434b that provide electrical communication between the fourth connector 404 of the first substrate 400 and the fourth connector 414 of the second substrate 410. The adjacent fourth connectors 404 of the first substrate 400 have a spacing 406 and the adjacent fourth connectors 414 of the second substrate 410 have a spacing 416 equal to the spacing 406 of the first substrate 400. The first interconnects 434a are positioned on opposite sides of the second interconnects 434b with a space 426 therebetween. The second interconnects 434b have a width 427 that is greater than the width 425 of the first interconnects 434a and may be configured to transmit a greater magnitude of current. The width 427 of the second interconnectors 434b may also be greater than the spacing 406 of adjacent fourth connectors 404. The width 425 of the first interconnects 434a is less than the spacing 406 of the adjacent fourth connectors 404. During the application process, the fourth configuration 444 may be offset by less than the sum of the spacing 406 between adjacent fourth connectors 404 of the first substrate 400, the spacing 426 between the first interconnects 434a and the second interconnects 434b, and the width 425 of the first interconnects 434a without the second interconnects 434b shorting the adjacent fourth connectors 404 or the adjacent fourth connectors 414.

The fifth configuration 445 provides electrical communication between the fifth connector 405 of the first substrate 400 and the fifth connector 415 of the second substrate 410 through laterally spaced apart interconnects 435. The width and spacing of the fifth connector 405 of the first substrate 400 and the fifth connector 415 of the second substrate 410 substantially correspond to the width and spacing of the plurality of interconnects 435. Smaller tolerances may be utilized in applying the anisotropic conductive film and the width and spacing of the fifth connectors 405 of the first substrate 400 may be varied. However, if the width of the interconnects 435 is greater than the spacing of the adjacent fifth connectors 405 of the first substrate 400, the manufacturing tolerances used should be small enough to ensure that the misalignment during application does not cause the interconnects 435 to make contact with the two adjacent fifth connectors 405.

Fig. 6 is a schematic diagram of an embodiment of a semiconductor device assembly 500 having an anisotropic conductive film 520 providing electrical communication between a connector 502 of a first substrate 501 and a connector 512 of a second substrate 511 via a plurality of interconnects 521. The plurality of interconnects 521 are laterally spaced apart in an electrically insulating material 522. In the x-direction, the plurality of interconnects 521 have a width 525 and a spacing 526, which is the distance between adjacent interconnects 521. The plurality of connectors 502 of the first substrate 501 each have a width 505. The first substrate 501 has a spacing 506, which is the distance between adjacent connectors 502 of the first substrate 501. The spacing 506 between each pair of adjacent connectors 502 of the first substrate 501 is uniform. The plurality of connectors 512 of the second substrate 511 have a width 515. The second substrate 511 has a spacing 516, which is the distance between adjacent connectors 512 of the second substrate 511. The spacing 516 between each pair of adjacent connectors 512 of the second substrate 511 is uniform. The width 505 of the connector 502 of the first substrate 501 is equal to the width 515 of the connector 512 of the second substrate 511. The spacing 506 of the connectors 502 of the first substrate 501 is equal to the spacing 516 of the connectors 512 of the second substrate 511.

During application of the anisotropic conductive film 520 to the first substrate 501 and the second substrate 511, the first substrate 501 or the second substrate 511 may become misaligned in the x direction or the y direction (not shown). The width 505 of the connector 502, the width 525 of the interconnects 521, the spacing 506 of the connector 502 of the first substrate 501, and the spacing 526 of the plurality of interconnects 521 may be selected to reduce the likelihood of shorting between adjacent connectors 502 of the first substrate 501. For example, when the ratio of the spacing 506 is increased compared to the width 515 of the second substrate 511, there may be a greater degree of misalignment or else shorting between adjacent connectors 502 of the first substrate 501 may occur. Additionally, as the width 525 of the plurality of interconnects 521 decreases, there may be a greater degree of misalignment that may otherwise occur with shorting between adjacent connectors 502 of the first substrate 501.

Fig. 7 is a flow diagram of an embodiment of a method 600 of fabricating a semiconductor device assembly. The method 600 includes providing a first substrate in act 605, providing a second substrate in act 610, and providing an anisotropic conductive film in act 615. As discussed herein, the first and/or second substrates may be semiconductor devices. The anisotropic conductive film includes vertically oriented interconnects laterally separated by an electrically insulating material. The method 600 may include forming a plurality of interconnects in an anisotropic conductive film in act 620. The method 600 includes connecting a plurality of interconnects to a first substrate and a second substrate in act 625. One or more interconnects may be connected between corresponding connectors on the first and second substrates. In some embodiments, the anisotropic conductive film may be free of adhesive, and the method may not include adhering the anisotropic conductive film to the first substrate via the adhesive. The method 600 includes communicating current between a first substrate and a second substrate via a plurality of interconnects in act 630.

Although the present disclosure has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of the present disclosure. The disclosure may encompass other embodiments not explicitly shown or described herein. Accordingly, the scope of the disclosure is to be defined only by reference to the following claims and their equivalents.