阅读说明：本技术 具有包括硅和氮的部分的半导体器件和制造的方法 (Semiconductor device having portion including silicon and nitrogen and method of manufacture ) 是由 M.卡恩 O.胡姆贝尔 P.S.科赫 A.科普罗夫斯基 C.迈尔 G.施米德特 J.施泰 于 2019-09-06 设计创作，主要内容包括：本发明涉及具有包括硅和氮的部分的半导体器件和制造的方法。半导体器件(500)包括半导体本体(100)和包括硅和氮的第一部分(410)。第一部分(410)与半导体本体(100)直接接触。包括硅和氮的第二部分(420)与第一部分(410)直接接触。第一部分(410)在半导体本体(100)和第二部分(420)之间。在第一部分(410)中的平均硅含量比在第二部分(420)中更高。(The invention relates to a semiconductor device having a portion including silicon and nitrogen and a method of manufacture. The semiconductor device (500) comprises a semiconductor body (100) and a first portion (410) comprising silicon and nitrogen. The first portion (410) is in direct contact with the semiconductor body (100). A second portion (420) comprising silicon and nitrogen is in direct contact with the first portion (410). The first portion (410) is between the semiconductor body (100) and the second portion (420). The average silicon content is higher in the first portion (410) than in the second portion (420).)

1. A semiconductor device, comprising:

a semiconductor body (100);

a first portion (410) comprising silicon and nitrogen, the first portion (410) being in direct contact with the semiconductor body (100); and

a second portion (420) comprising silicon and nitrogen, wherein the second portion (420) is in direct contact with the first portion (410), the first portion (410) is between the semiconductor body (100) and the second portion (420), and the average silicon content is higher in the first portion (410) than in the second portion (420).

2. The semiconductor device of claim 1,

the semiconductor body (100) comprises a doped region (120) of a semiconductor diode and/or a transistor cell.

3. The semiconductor device of any one of the preceding claims,

the semiconductor body (100) comprising an active region (610) and an edge termination region (690) between the active region (610) and a side surface (103) of the semiconductor body (100),

a front side metallization (310) is in contact with the semiconductor body (100) in the active region (610), and

the first portion (410) is in direct contact with the semiconductor body (100) in the edge termination region (690).

4. The semiconductor device of claim 3,

the first portion (410) is in direct contact with a doped region (125) of an edge termination structure formed in the edge termination region (690).

5. The semiconductor device of any one of the preceding claims,

an average atomic ratio of silicon to nitrogen at a top surface (429) of the second portion (420) is at most 1.6.

6. The semiconductor device of any one of the preceding claims,

the second portion (420) comprises at least 10at% hydrogen.

7. The semiconductor device according to the preceding claim, wherein,

at a top surface (429) of the second portion (420), a ratio of silicon-hydrogen bonds to nitrogen-hydrogen bonds is at most 1.6.

8. The semiconductor device of any one of the preceding claims,

at the top surface (429), the second portion (420) is insulating.

9. The semiconductor device of any one of the preceding claims,

at an interface between the semiconductor body (100) and the first portion (410), an average atomic ratio of silicon to nitrogen in the first portion (410) is greater than 5.

10. The semiconductor device of any one of the preceding claims,

the first portion (410) comprises at least 10at% hydrogen.

11. The semiconductor device according to the preceding claim, wherein,

at the interface between the semiconductor body (100) and the first portion (410), the ratio of silicon-hydrogen bonds to nitrogen-hydrogen bonds is greater than 5.

12. The semiconductor device of any one of the preceding claims,

the first portion (410) is semi-insulating at an interface between the semiconductor body (100) and the first portion (410).

13. The semiconductor device according to any one of claims 1 to 8,

the second portion (420) comprises a first sub-portion (421) in contact with the first portion (410), and in the first sub-portion (421) the silicon content steadily decreases with increasing distance from the first portion (410).

14. The semiconductor device according to the preceding claim, wherein,

the silicon content in said first sub-portion (421) decreases from at least 5 to at most 1.8 with increasing distance to the first portion (410) by at least 100 nm.

15. The semiconductor device of any one of the preceding claims,

the second portion (420) comprises a second sub-portion (422) along the top surface (429) and wherein the silicon content is constant in the second sub-portion (422).

16. The semiconductor device of any one of the preceding claims,

the first portion (410) has a thickness in a range of 50nm to 100 nm.

17. The semiconductor device of any one of the preceding claims,

the second portion (420) has a thickness of at least 100 nm.

18. The semiconductor device of any one of the preceding claims,

the refractive index at the top surface (429) of the second portion (420) is in the range from 1.9 to 2.1 at a wavelength of 673 nm.

19. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate (700) having a main surface (701);

forming a first portion (410) directly on the main surface (701), the first portion (410) comprising silicon and nitrogen;

forming a second portion (420) directly on the first portion (410), wherein the second portion (420) comprises silicon and nitrogen, and wherein an average silicon content is higher in the first portion (410) than in the second portion (420).

20. The method according to the preceding claim, wherein,

forming the first and second portions (410, 420) includes a deposition process using a nitrogen-containing precursor (892) and a silicon-containing precursor (891), wherein a mass flow ratio between the silicon-containing precursor (891) and the nitrogen-containing precursor (892) into the deposition chamber (885) is progressively reduced during deposition of the first portion (410) and/or the second portion (420) in the deposition chamber (885).

21. The method according to the preceding claim, wherein,

the change in the mass flow ratio comprises a decrease in the mass flow ratio between the silicon-containing precursor (891) and the nitrogen-containing precursor (892) of up to 100 sccm/s.

22. The method of any of claims 20 to 21, further comprising:

removing oxide from the major surface (701) in the deposition chamber (885) and prior to forming the first portion (410).

23. The method of any one of claims 19 to 22,

the semiconductor substrate (700) comprises crystalline silicon.

Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background

In semiconductor devices such as power semiconductor diodes and power semiconductor switches, a passivation layer may protect portions of the semiconductor die and metallized portions during testing and packaging processes as well as during use. The passivation layer protects the surface and forms a barrier to impurities and contaminants that might otherwise migrate from the environment to the active area of the semiconductor device. The passivation layer may comprise a dielectric or semi-insulating material, such as DLC (Diamond like carbon), amorphous silicon carbide (a-SiC), silicon oxide, stoichiometric silicon nitride (Si)₃N₄) Or a polyimide.

Disclosure of Invention

Embodiments of the present disclosure relate to a semiconductor device including a semiconductor body. The first portion is in direct contact with the semiconductor body. The first portion includes silicon and nitrogen. The second portion is in direct contact with the first portion. The second portion includes silicon and nitrogen. The first portion is between the semiconductor body and the second portion. The average silicon content may be higher in the first portion than in the second portion.

Another embodiment of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate having a major surface. The first portion is formed directly on the major surface. The first portion includes silicon and nitrogen. The second portion is formed directly on the first portion. The second portion includes silicon and nitrogen. The average silicon content is higher in the first portion than in the second portion.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate semiconductor devices and methods of the present disclosure and, together with the description, serve to explain the principles of the embodiments. Other embodiments and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description.

Fig. 1A is a schematic vertical cross-sectional view of a portion of a semiconductor device including a semi-insulating protective layer having a silicon-rich first portion and a second portion, according to an embodiment.

FIG. 1B is a schematic diagram illustrating silicon content and nitrogen content along line B-B' of FIG. 1A, according to an embodiment.

Fig. 2A is a schematic vertical cross-sectional view of a portion of a semiconductor device in which a second portion includes a sub-portion, according to another embodiment.

Fig. 2B is a schematic diagram illustrating silicon content and nitrogen content along line B-B' of fig. 2A, according to an embodiment.

Fig. 3 is a schematic vertical cross-sectional view of a portion of a semiconductor device including a junction termination extension according to another embodiment.

Fig. 4 is a simplified flow diagram schematically illustrating a method of manufacturing a semiconductor device, in accordance with another embodiment.

Fig. 5A is a schematic block diagram of a deposition apparatus of a method for manufacturing a semiconductor device according to another embodiment.

Fig. 5B is a schematic timing chart for illustrating a process that may be performed using the deposition apparatus of fig. 5A.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the semiconductor device and method of manufacturing the semiconductor device may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described with respect to one embodiment can also be used on or in conjunction with other embodiments to yield yet a further embodiment. The present disclosure is intended to encompass such modifications and variations. The examples are described using specific language and should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements in different figures are denoted by the same reference numerals if not otherwise stated.

The terms "having," "containing," "including," "containing," and the like are open-ended and such terms are intended to specify the presence of stated features, elements, or characteristics, but not to preclude the presence or addition of other features, elements, or characteristics. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

The term "electrically connected" describes a permanent low resistance connection between electrically connected elements, such as a direct contact between the relevant elements or a low resistance connection via a metal and/or heavily doped semiconductor material. The term "electrically coupled" includes that one or more intermediate elements suitable for signal and/or power transfer may be between the electrically coupled elements, e.g. elements controllable to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state.

The figures illustrate the relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration lower than that of the "n" doped region, while the "n +" doped region has a higher doping concentration than the "n" doped region. Doped regions having the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions may have the same or different absolute doping concentrations.

The ranges given for physical dimensions include the border values. For example, the range of the parameter y for a to b is denoted as a ≦ y ≦ b. Wherein the parameter y having a value of at least c is denoted c.ltoreq.y and the parameter y having a value of at most d is denoted y.ltoreq.d.

The main component of a layer or structure from a compound or alloy is such an element that the atom forms the compound or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper aluminum alloy.

Two adjoining doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, such as an n/n + or p/p + junction along a boundary surface between the two doped regions. At a unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or inflection point where the dopant concentration profile changes from concave to convex, or vice versa.

According to an embodiment, a semiconductor device may include a semiconductor body, a first portion, and a second portion. The first portion comprises silicon and nitrogen and may be in direct contact with the semiconductor body. The second portion comprises silicon and nitrogen and may be in direct contact with the first portion, wherein the first portion is between the semiconductor body and the second portion. The average silicon content may be higher in the first portion than in the second portion.

Both the first and second portions may include silicon and nitrogen as the only major components. The first portion and/or the second portion may also include a substantial portion of hydrogen, which forms silicon-hydrogen bonds and nitrogen-hydrogen bonds. Additionally, the first portion and/or the second portion may include impurities, such as phosphorus, boron, and/or carbon. The first portion and the second portion may form at least a portion of a passivation layer.

The first part may be an electrically active semi-insulating layer, wherein the resistivity ranges from 1 x 10⁷Omega cm (1E 07 omega cm) to 1X 10¹⁵Ω cm (1E 15 Ω cm). The first portion may show a high electrical blocking capability. The resistivity may be sufficiently low to prevent accumulation of charge, for example, in a region of the semiconductor body near the passivation layer.

A high silicon content may enable a strong bond between the first portion and the semiconductor body (e.g. a silicon, germanium or silicon carbide based semiconductor body).

The second portion may effectively act as a strong and robust protective layer. The second portion may protect the first portion and the semiconductor body in a humid environment, for example, against penetration of water. The second portion is robust against galvanic corrosion even in the presence of strong electric fields.

Since the first portion and the second portion comprise the same composition, the adhesion between the second portion and the first portion may be compared to, for example, Si₃N₄Between a layer and a DLC layer, or Si₃N₄The adhesion between the layer and the a-SiC layer is better. The second portion may be formed immediately after the first portion and without interrupting the plasma applied during deposition, so that no intermediate layer, such as a native oxide layer or any kind of other interface, is formed that may impair the adhesion between the second portion and the first portion.

The passivation layer may serve as a robust electrically active shield for the edge termination structure for mirror charge accumulation and for contacting floating regions or other floating structures in the semiconductor body.

According to an embodiment, the semiconductor body may comprise a doped region of the semiconductor diode and/or a doped region of the transistor cell. For example, the doped region may form an anode or cathode region of a power semiconductor diode or a body region of a power transistor. The first portion of the passivation layer may help to maintain the electrical turn-off capability of the power semiconductor device by preventing charge accumulation.

According to an embodiment, the semiconductor body may comprise an active region and an edge termination region between the active region and a side surface of the semiconductor body. The active region may include a doped region of a semiconductor diode or a transistor cell. The front side metallization may be in contact with the semiconductor body in the active region. The first portion may be in direct contact with the semiconductor body in the edge termination region. The first portion may show a sufficient electrical blocking capability and a sufficiently high resistivity such that the first portion has no or only a negligible effect on the standard operation mode of the semiconductor device. The first portion may show sufficient conductivity to avoid accumulation of charge carriers over a long period of time, wherein the accumulated charge may contribute to a local increase of the electric field strength at the pn-junction in the edge termination region. The local bias of the electric field strength may reduce the blocking capability of the edge termination structure formed in the edge termination region.

According to an embodiment, the first portion may be in direct contact with a doped region of an edge termination structure formed in the edge termination region. The doped regions of the edge termination structure may have the same conductivity type as the doped regions in the active region. For example, the doped regions of the active region and the edge termination region may form a pn junction with the drift region. The doped region in the active region may be an emitter region. In the blocking mode of the semiconductor device, the edge termination structure regulates the electric field in the lateral direction, wherein the electric field strength can peak close to the position where the pn-junction at the front side ends. The first portion prevents an increase in electric field intensity that may be caused by charges accumulated in the passivation layer.

The edge termination region may include a Junction Termination Extension (JTE) of the emitter region, wherein a doping concentration in the emitter region may be lower than a doping concentration in a doping region of the edge termination structure, and wherein a vertical extension of the JTE may be less than a vertical extension of the emitter region.

The doped regions in the edge termination region may comprise regions of Variable Lateral Doping (VLD) in which the dopant concentration gradually decreases with increasing distance from the active region. The edge termination structure may comprise one or more guard rings of the conductivity type of the emitter region, wherein the guard rings may extend into the semiconductor body from the first surface on the front side of the semiconductor body. Along the lateral direction, the guard rings may be spaced apart from each other by a low-doped intermediate region or a counter-doped intermediate region of the same conductivity type.

The edge termination structure may include a channel stop (stopper) of opposite conductivity type to the emitter region in addition to the VLD, JTE, and/or guard rings. The channel stop may extend along a side surface of the semiconductor body, wherein the side surface is inclined with respect to the first surface.

According to an embodiment, the average atomic ratio of silicon to nitrogen at the top surface of the second portion is at most 1.6. The index of refraction at the top surface may be about 2.0. The atomic ratio of 1.6 corresponds to the atomic ratio in "conventional" silicon nitride, which is typically formed by Chemical Vapor Deposition (CVD). A silicon nitride layer having an average atomic ratio of silicon to nitrogen of about 1.6 may be mechanically strong and corrosion resistant in the presence of a strong electric field and may form an effective moisture barrier.

According to an embodiment, the second portion may comprise at least 10at% hydrogen. For example, the second portion may include at least 10at% hydrogen and at most 14 at% hydrogen. A sufficiently high hydrogen content may adjust the electrical properties of the second part, such as resistivity and blocking capability.

According to an embodiment, the ratio of the amount of silicon-hydrogen bonds Si-H to the amount of nitrogen-hydrogen N-H bonds at the top surface of the second portion is at most 1.6. The ratio of Si-H bonds to N-H bonds can be obtained from the infrared absorption band of the bonds. A silicon nitride layer having a Si-H bond to N-H bond ratio of about 1.6 may be mechanically strong and corrosion resistant in the presence of a strong electric field and may form an effective moisture barrier.

According to an embodiment, the second portion may be insulating at an uppermost surface, wherein the resistivity at the top surface is greater than 1 × 10¹²Ω cm (1E 12 Ω cm). The second portion may be more insulating than the first portion.

According to an embodiment, the average atomic ratio of silicon to nitrogen in the first portion at the interface between the semiconductor body and the first portion may be larger than 1.6, for example larger than 5 or larger than 6, wherein the refractive index may be about 2.2. For example, in the case of Si: with N >5, the first part is "silicon rich" and shows high blocking capability.

According to an embodiment, the first portion may comprise at least 10at% hydrogen. For example, the first portion may include at least 10at% hydrogen and at most 14 at% hydrogen. A sufficiently high hydrogen content may adjust the electrical properties of the first part, such as resistivity and blocking capability.

According to an embodiment, the average ratio of the amount of Si-H bonds to the amount of N-H bonds in the first portion at the interface between the semiconductor body and the first portion may be larger than 1.6, for example larger than 5 or larger than 6. The refractive index may be about 2.2. In the presence of Si-H: N-H >5, the first part is "silicon rich" and shows high blocking capability. The resistivity of the "silicon-rich" first portion is sufficiently high that the first portion has no effect on the operation of the semiconductor device. The resistance of the "silicon-rich" first portion is low enough to avoid long-term charge accumulation that may degrade the blocking capability of the edge termination structure.

According to an embodiment, the first portion may be semi-insulating at an interface between the semiconductor body and the first portion.

According to an embodiment, the second portion may comprise a first sub-portion in contact with the first portion, wherein in the first sub-portion the silicon content steadily decreases with increasing distance from the first portion. The steadily decreasing silicon content helps to tune the properties of the passivation layer in view of electrical requirements, moisture resistance and mechanical strength. The gradual transition from the "silicon-rich" silicon nitride layer to the "conventional" silicon nitride layer avoids interfaces between layers of different compositions and contributes to an improved mechanical stability of the passivation layer.

According to an embodiment, the average atomic ratio of silicon to nitrogen may be reduced from at least 5 (e.g., at least 6) to at most 1.8 (e.g., at most 1.6) across a distance of at least 100 nm. According to another embodiment, the ratio of Si-H bonds to N-H bonds may be reduced from at least 5 (e.g., at least 6) to at most 1.8 (e.g., at most 1.6) across a distance of at least 100 nm.

According to a further embodiment, the second portion may comprise a second sub-portion along the top surface, wherein in the second sub-portion the silicon content is constant and independent of the distance to the first portion. With the thickness of the second portion, the mechanical strength and the moisture resistance (humidity resistance) of the protective layer can be adjusted without further influencing the electrical properties, which is mainly defined by the first portion and at most a part of the first sub-portion of the second portion.

According to an embodiment, the thickness of the first portion may be in a range of 50nm to 100 nm. For example, the thickness of the first portion corresponds to a minimum deposition time for establishing stable plasma parameters in the deposition chamber, wherein the mass flow rate may be stabilized prior to ignition of the plasma.

According to an embodiment, the thickness of the second portion may be at least 100nm to achieve a sufficiently smooth transition between "silicon-rich" silicon nitride and "conventional" silicon nitride.

According to an embodiment, the refractive index at the top surface of the second portion may be in the range of 1.9 to 2.1 at a wavelength of 673 nm.

According to another embodiment, a method of manufacturing a semiconductor device may include providing a semiconductor substrate having a main surface. The first portion may be formed directly on the major surface. The first portion includes silicon and nitrogen. The second portion may be formed directly on the first portion. The second portion includes silicon and nitrogen. The average silicon content and/or the average content of Si-H bonds may be higher in the first portion than in the second portion.

The second portion may be formed directly after the first portion, wherein the second portion may be formed without the semiconductor body leaving the deposition apparatus, without a temporary stop of the plasma applied during deposition, and without any interface layer (e.g. native oxide layer) being formed which may weaken the adhesion between the first portion and the second portion.

According to an embodiment, forming the first and second portions may include a deposition process using a nitrogen-containing precursor and a silicon-containing precursor. The mass flow ratio between the silicon-containing precursor and the nitrogen-containing precursor entering the deposition chamber during the deposition of the first portion and/or during the deposition of the second portion in the deposition chamber may be gradually decreased.

The first portion may form an electrically active layer and the second portion may form a robust protective layer. The electrically active layer and the protective layer of the passivation layer can be formed in an economical manner by simply varying one or both flow rates during the deposition process. No interfacial layer, such as native oxide, is formed, which may have an adverse effect on device stability or may deteriorate adhesion between portions.

According to an embodiment, the change in the flow ratio may comprise a decrease in the mass flow ratio between the silicon-containing precursor and the nitrogen-containing precursor of up to 100sccm/s, wherein the electrical properties of the first portion and the second portion may be adjusted exactly without having a negative effect on the stability of the passivation layer.

According to an embodiment, the oxide may be removed from the main surface before forming the first portion. For example, the oxide may be removed using a reactive precursor (such as fluorine). After removing the oxide, the semiconductor substrate does not leave the deposition chamber until the first and second portions of the passivation layer are formed. A critical interface layer (e.g., native oxide) that may degrade adhesion of the second portion on the first portion may not be formed between the semiconductor substrate and the passivation layer such that the first portion may form a strong bond with the semiconductor substrate without an interface along which a portion of the passivation layer may delaminate or otherwise weaken.

According to an embodiment, the semiconductor substrate may comprise crystalline silicon. On crystalline silicon, the "silicon-rich" silicon nitride layer may form a strong bond that avoids delamination of the first portion from the semiconductor substrate.

Fig. 1A-1B relate to a semiconductor device 500 having a passivation layer 400 formed on a first surface 101 of a semiconductor body 100.

The semiconductor device 500 may be a power semiconductor device, which may be used as a switch or rectifier in a power electronic device. For example, the semiconductor device 500 may be a semiconductor diode. According to an embodiment, the semiconductor device 500 may comprise a plurality of substantially identical transistor cells TC electrically arranged in parallel. For example, the semiconductor device 500 may be a HEMT (high electron mobility transistor), an IGFET (insulated gate field effect transistor) (e.g. MOSFET (metal oxide semiconductor FET) in general, including IGFETs with metal gates and IGFETs with polysilicon gates), JFETs (junction FETs), IGBTs (insulated gate bipolar transistors), MCDs (MOS controlled diodes), or smart power semiconductor devices including CMOS (complementary metal oxide semiconductor) circuits, such as sensor circuits and/or control circuits in addition to power semiconductor switches.

The semiconductor body 100 may be based on a semiconductor crystal having one or more main components. By way of example, the major constituent(s) of the semiconductor crystal may be silicon (Si), germanium (Ge), silicon and germanium (SiGe), silicon and carbon (SiC), gallium and nitrogen (GaN), or gallium and arsenic (GaAs). The semiconductor body 100 may also comprise other materials, for example unintentional impurities and/or intentional additions (for example dopant atoms and/or hydrogen atoms) due to material and process defects.

The first surface 101 defines a front side of the semiconductor device 500. The direction parallel to the first surface 101 is a horizontal direction. The surface normal 104 to the first surface 101 defines a vertical direction.

The passivation layer 400 comprises a first portion 410 in direct contact with the first surface 101 and a second portion 420 formed on the first portion 410, wherein the first portion 410 separates the second portion 420 from the semiconductor body 100. The first portion 410 and the second portion 420 may include silicon and nitrogen as the only major components, or may include a substantial portion of hydrogen, such as at least 10at% hydrogen.

The first portion 410 and the second portion 420 differ with respect to the ratio between silicon and nitrogen and/or may differ with respect to the ratio of Si-H bonds to NH bonds. For example, the silicon to nitride atomic ratio Si: n may be constant in the first portion 410 and may steadily decrease, for example, with increasing distance z to the first surface 101 in the second portion 420. According to another embodiment, the ratio of Si: n may decrease in the first portion 410 at a lower rate than in the second portion 420.

According to another example, Si — H: the N-H ratio may be constant in the first portion 410 and may steadily decrease, for example, with increasing distance z to the first surface 101 in the second portion 420. According to another embodiment, the ratio of Si-H: the N-H ratio may decrease in the first portion 410 at a lower rate than in the second portion 420.

By way of example, the vertical extension d1 of the first portion 410 may be in the range of 50nm to 100 nm. The vertical extension d2 of the second portion 420 may be in the range of 100nm to a few μm, for example 800 nm.

FIG. 1B shows a vertical gradient 491 of silicon content along line B-B' in FIG. 1A and the silicon to nitrogen atomic ratio Si: a vertical gradient 492 of N. In the first portion 410, both the silicon content and the silicon to nitrogen ratio may be constant. For example, in the first portion 410, the atomic ratio Si: n may be about 6. The silicon content in the first portion 410 may be about 85%. In the second portion 420, the atomic ratio Si: n may decrease across a thickness of at least 100nm in the range of 6 to 1.6.

At the top surface 429 of the second portion 420, the atomic ratio Si: n may be at most 1.8, for example, at most 1.6, and the refractive index may be in the range of 1.98 to 2.02 at a wavelength of 673 nm. In a horizontal cross-section of the first portion 410, the refractive index may be at least 2.15, for example about 2.2, at a wavelength of 673 nm.

At least the first portion 410 may include a substantial amount of hydrogen, e.g., at least 10at% hydrogen and at most 14 at% hydrogen, wherein the vertical gradient 491 may indicate an amount of Si-H bonds along line B-B 'in fig. 1A, and the vertical gradient 492 may indicate an amount of Si-H bonds along line B-B' in fig. 1A: the N-H ratio. In the first portion 410, the amount of Si-H bonds and the Si-H: both N-H ratios may be constant. For example, in the first portion 410, Si-H: the N-H ratio may be about 6. In the second portion 420, the ratio Si-H: the N-H may be reduced from about 6 to about 1.6 across a thickness of at least 100 nm. At the top surface 429 of the second portion 420, the Si-H: the N-H ratio may be up to 1.8, for example, up to 1.6.

The "silicon rich" first portion 410 forms an electrically active semi-insulating layer with high voltage blocking capability. The resistivity of the first portion 410 is sufficiently high that it does not adversely affect the operation of the semiconductor device 500. The leakage current through the first portion 410 is negligible. The resistivity of the first portion 410 may be sufficiently low such that charge accumulation in the first portion 410 is negligible over the lifetime of the semiconductor device 500.

At least the top portion of the second portion 420 may form a protective layer having high humidity impermeability, high mechanical stability, and high robustness, wherein the protective layer is corrosion resistant and does not deteriorate when exposed to strong electric fields. The thickness of the first portion 410 can be varied by varying the thickness and atomic ratio Si from "silicon rich" to about 1.6: the length of the transition of N adjusts the electrical and mechanical properties of the passivation layer 400 in a simple manner.

In fig. 2A-2B, the second portion 420 of the passivation layer 400 includes a first sub-portion 421 in contact with the first portion 410 and a second sub-portion 422 in contact with the first sub-portion 421, wherein the first sub-portion 421 separates the second sub-portion 422 from the first portion 410. In the first sub-portion 421 the silicon content may steadily decrease with increasing distance z to the first surface 101. In the second subsection 422, the atomic ratio Si: n may be constant as the distance z to the first surface 101 increases, as shown by line 494 in fig. 2B, or alternatively, the atomic ratio Si: n may decrease at a lower rate than in the first subsection 421 as indicated by line 493 in fig. 2B.

According to an embodiment, the sum of the vertical extension d1 of the first section 410 and the vertical extension d21 of the first subsection 421 may be in the range of 50nm to 100nm, and the vertical extension d22 of the second subsection 422 may be in the range of from 500nm to 1 μm. The first sub-portion 421 of the first portion 410 and the second portion 420 may determine the number and/or density of interface states, and the second sub-portion 422 may define the mechanical strength and barrier properties of the passivation layer 400.

Fig. 3 shows an example of a semiconductor device 500 with a semiconductor body 100 and a passivation layer 400. The semiconductor device 500 may be a MOSFET, an IGBT, or a semiconductor diode. For example, the semiconductor device 500 may be a vertical power semiconductor device, wherein a load current flows between a first load electrode at the front side of the semiconductor body 100, which may comprise the front side metallization 310, and a second load electrode 320 at the back side of the semiconductor body 100. The thickness of the semiconductor body 100 between the first surface 101 at the front side and the second surface 102 at the back side may be in the range of several hundred nm to several hundred μm.

The semiconductor body 100 may be a single crystal containing silicon (Si) or germanium (Ge) as a main component, such as single crystal silicon (Si), single crystal silicon germanium (SiGe), single crystal silicon carbide (SiC) or single crystal silicon (Si).

The semiconductor body 100 may include a doped region 120 formed in the active region 610 between the first surface 101 and the drain/drift structure 130. The drain/drift structure 130 may include at least a lightly doped drift region 131 and a heavily doped contact 139 between the drift region 131 and the second surface 102. The drift region 131 regulates the blocking voltage in the blocking mode of the semiconductor device 500.

The heavily doped contact portion 139 may form an ohmic contact with the second load electrode 320. In case the semiconductor device 500 is a MOSFET or a semiconductor diode, the contact 139 may form a unipolar junction with the drift region 131. In the case where the semiconductor device 500 is or includes a reverse blocking IGBT, the contact portion 139 has the drift region 131 of the opposite conductivity type. In case the semiconductor device 500 is a reverse conducting IGBT, the contact portion 139 may comprise a partition of both conductivity types extending between the drift region 131 and the second surface 102. The contact 139 may directly adjoin the drift region 131 or an additional layer of the conductivity type of the drift region 131, but wherein a higher dopant concentration may be formed between the drift region 131 and the contact 139.

The doped region 120 in the active region 610 may form an emitter region and may include an anode region or a cathode region of the power semiconductor diode, or a body region of the transistor cell, wherein the transistor cells may be electrically connected in parallel.

The edge termination region 690 may surround the central active region 610 and may separate the central active region 610 from a side surface 103 of the semiconductor body 100, wherein the side surface 103 connects the first surface 101 and the second surface 102.

The edge termination region 690 may include an edge termination structure. In the blocking state of the semiconductor device 500, the edge termination structure modulates a lateral electric field caused by a blocking voltage between the emitter region 120 and the drift/drain structure 130.

In the illustrated embodiment, the edge termination structure includes a junction termination extension 125. The junction termination extension 125 may be in direct contact with the emitter region 120. The junction termination extension 125 may be in contact with the first surface 101 or may be spaced apart from the first surface 101. The average dopant concentration in the junction termination extension 125 may be lower than the average dopant concentration in the emitter region 120. The vertical extension of the junction termination extension 125 may be equal to or less than the vertical extension of the doped region 120 in the active region 610.

The edge termination structure may also include a channel stop region 138 formed along an edge between the first surface 101 and the side surface 103. The channel stop region 138 is more heavily doped than the drift region 131 and may form a unipolar junction with the drift region 131.

The passivation layer 400 as described with reference to any of the previous figures is in direct contact with the semiconductor body 100 in the edge termination region 690. The passivation layer 400 may extend across the sidewalls of the front side metallization 316. A portion of the passivation layer 400 may be formed on a portion of the front side metallization 310.

The resistivity of the passivation layer 400 is sufficiently high that no or only negligible leakage current flows across the passivation layer 400. The first portion 410 of the passivation layer 400 may drain away charges that may migrate into the passivation layer 400 during the lifetime of the semiconductor device 500 and may affect the breakdown and avalanche characteristics of the edge termination structure.

Fig. 4 relates to a method of manufacturing a semiconductor device. A semiconductor substrate having a main surface is provided (902). A first portion is formed directly on the major surface, wherein the first portion includes silicon and nitrogen (904). A second portion is formed directly on the first portion, wherein the second portion comprises silicon and nitrogen, and wherein the average silicon content is higher in the first portion than in the second portion. (906).

Fig. 5A schematically illustrates a deposition apparatus 800. The deposition apparatus 800 may be, for example, a CVD (chemical vapor deposition) apparatus (e.g., an APCVD (atmospheric pressure CVD), LPCVD (low pressure CVD), or PECVD (plasma enhanced CVD) apparatus) or an apparatus for PVD (physical vapor deposition).

The semiconductor substrate 700 may be placed in a deposition chamber 885 of the reactor 880. Reactor 880 may include electrodes for generating plasma. A first MFC (mass flow controller) 810 controls the flow F of silicon-containing precursor 891 through a main inlet 881 into a deposition chamber 885_PrSiAnd a second MFC 820 controls the flow F of nitrogen-containing precursor into the deposition chamber 885 through the main inlet 881_PrN. The first and second MFCs 810, 820 may control the flow rate of the gaseous compound or gaseous mixture through the MFC according to a selected set point. For example, an MFC may include a mass flow sensor, a control valve, and an internal control unit that may compare values of gas flow obtained from the mass flow sensor to adjust the control valve in an appropriate manner to achieve a flow rate according to a selected set point.

The processor unit 890 can be data-linked with the first MFC 810 and the second MFC 820. The processor unit 890 may control the deposition apparatus 800 to form a passivation layer 400 having a first portion 410 and a second portion 420 (as described with reference to fig. 1A-3). The processor unit 890 may be an integral part of the deposition apparatus 800 or may comprise a stored program control assigned to the deposition apparatus 800 and data linked to the deposition apparatus 800. The processor unit 890 may be a computer, a server, or a server executing software code and part of a network of computers. The processor unit 890 may perform methods of controlling the first and second MFCs 810, 820 in a manner as described with reference to fig. 5B.

The semiconductor substrate 700 may be placed in a deposition chamber 885 of the reactor 880. Between t =0 and t =1, an etchant may be introduced into the deposition chamber 885, wherein the etchant is adapted to remove native oxide from the major surface 701 at the front side of the semiconductor substrate 700. For example, the etchant may include fluorine radicals. For t1< t < t2, an inert gas (e.g., a noble gas) may purge deposition chamber 885 and may remove fluorine radicals.

For t2<t<t3, a silicon-containing precursor 891 and a nitrogen-containing precursor 892 may be introduced into the deposition chamber 885 at a constant ratio. The silicon-containing precursor may include, for example, silane, e.g., silane SiH₄TCS (trichlorosilane HSiCl)₃) Or tetrachlorosilane HSiCl₄. The nitrogen-containing precursor may include, for example, ammonia (NH)₄) And/or nitrogen (N)₂）。

The ratio of the silicon-containing precursor to the nitrogen-containing precursor can be greater than 3, such as greater than 3.5. According to an embodiment, the flow rate ratio may be between 4.9 and 5.1. By way of example, the temperature in the deposition chamber may be set to about 400 ℃. Reactor 880 may activate a high frequency plasma, wherein energetic electrons in the plasma may ionize or dissociate at least one of the silicon-containing precursor and the nitrogen-containing precursor to generate more chemically reactive radicals. At high deposition powers (e.g., about 2.6W/cm)²) The deposited "silicon-rich" silicon nitride layer may show high voltage blocking capability.

For t3< t < t4, the flow rate ratio of silicon-containing precursor to nitrogen-containing precursor may be steadily decreased. Since the total gas flow varies only to a relatively low degree, the plasma can be applied continuously from at least t3 to t5 or from t2 to t5 without change or without significant change. By applying the plasma continuously, the process can be very stable.

In the example shown, only the mass flow of the silicon-containing precursor is reduced. According to other embodiments, the flow of the nitrogen-containing precursor may also be increased, or the mass flow of the nitrogen-containing precursor may be increased and the mass flow of the silicon-containing precursor may be decreased. the period between t3 and t4 may last at least 2 seconds and last at most 10 seconds. The flow rate of the silicon-containing precursor can vary by up to 100 sccm/s.

According to an embodiment, the silicon-containing precursor is silane SiH₄And the nitrogen-containing precursor is NH₃。NH₃The flow rate may be 100sccm and the flow rate of silane may be reduced from 500 sccm to 300 sccm. Gaseous nitrogen N₂May be supplied at a flow rate of 4000 sccm. The pressure in the deposition chamber 885 can be between 1 torr and 10 torr, while the temperature in the deposition chamber 885 can be between 350 ℃ and 500 ℃.

The flow rate ratio between the silicon-containing precursor and the nitrogen-containing precursor may be held constant for t4< t < t 5. the period between t4 and t5 may last at least 2 seconds and at most 60 seconds and may result in a deposited layer having a thickness of about 800 nm.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.