阅读说明：本技术 半导体装置及制造方法 (Semiconductor device and method of manufacturing the same ) 是由 加藤由晴 白川彻 于 2019-05-28 设计创作，主要内容包括：本发明提供具有势垒金属且阈值电压的偏差小的半导体装置及制造方法。所述半导体装置具备：半导体基板；层间绝缘膜,其配置于半导体基板的上表面；钛层,其设置于层间绝缘膜上；以及氮化钛层,其设置于钛层上,在层间绝缘膜设置有使半导体基板的上表面的一部分露出的开口,钛层和氮化钛层还设置于开口内,与半导体基板接触而配置在开口的底部的钛层全部进行了钛硅化。(The invention provides a semiconductor device having a barrier metal and having a small variation in threshold voltage and a method of manufacturing the same. The semiconductor device includes: a semiconductor substrate; an interlayer insulating film disposed on an upper surface of the semiconductor substrate; a titanium layer provided on the interlayer insulating film; and a titanium nitride layer provided on the titanium layer, wherein the interlayer insulating film is provided with an opening for exposing a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are further provided in the opening, and all of the titanium layers disposed in the bottom of the opening in contact with the semiconductor substrate are titanium-silicided.)

1. A semiconductor device is characterized by comprising:

a semiconductor substrate;

an interlayer insulating film disposed on an upper surface of the semiconductor substrate;

a titanium layer provided on the interlayer insulating film; and

a titanium nitride layer disposed on the titanium layer,

the interlayer insulating film is provided with an opening for exposing a part of the upper surface of the semiconductor substrate,

the titanium layer and the titanium nitride layer are also disposed within the opening,

all the titanium layers disposed in contact with the semiconductor substrate at the bottom of the opening are titanium-silicided.

2. The semiconductor device according to claim 1, further comprising a tungsten plug provided on the titanium nitride layer in the opening.

3. The semiconductor device according to claim 1 or 2, wherein the titanium layer provided over the interlayer insulating film in a region other than the opening is a titanium layer containing no titanium silicide portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the titanium layer provided on the interlayer insulating film in a region other than the opening is 30nm or more and 45nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein at least a part of a side wall of the interlayer insulating film at the opening has a curved surface shape convex upward.

6. The semiconductor device according to claim 5, wherein the semiconductor substrate has:

a plurality of groove portions provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and provided side by side in a predetermined arrangement direction on the upper surface of the semiconductor substrate; and

a mesa portion sandwiched by 2 groove portions in the arrangement direction,

the interlayer insulating film is provided so as to cover at least a part of the upper end of the groove portion,

the opening is provided so that at least a part of an upper surface of the mesa portion is exposed,

the side wall of the interlayer insulating film has the curved surface shape at least above both ends of the mesa portion in the arrangement direction.

7. The semiconductor device according to claim 2, wherein the semiconductor device is further provided with a 2 nd titanium layer, the 2 nd titanium layer being disposed on the titanium nitride layer and on the tungsten plug and not being silicided with titanium.

8. A method of manufacture, comprising:

an insulating film forming step of forming an interlayer insulating film on an upper surface of the semiconductor substrate;

an opening forming step of forming an opening in the interlayer insulating film to expose a part of an upper surface of the semiconductor substrate;

a titanium layer forming step of forming a titanium layer on the interlayer insulating film and in the opening;

a titanium nitride layer forming step of forming a titanium nitride layer on the titanium layer; and

and a titanium silicidation step of siliciding all the titanium layers disposed in contact with the semiconductor substrate and at the bottom of the opening with titanium.

9. The manufacturing method according to claim 8, wherein in the titanium silicidation step, the semiconductor substrate is annealed at 700 ℃ or higher.

10. The manufacturing method according to claim 8 or 9, wherein in the titanium layer forming step, the titanium layer is formed at 30nm or more and 45nm or less.

11. The manufacturing method according to any one of claims 8 to 10, further comprising a tungsten plug forming step of forming a tungsten plug on the titanium nitride layer within the opening,

the temperature for annealing the semiconductor substrate in the titanium silicidation step is higher than the temperature for forming the tungsten film in the tungsten plug forming step.

12. The manufacturing method according to any one of claims 8 to 11, further comprising a hydrogen annealing step of annealing the semiconductor substrate in an atmosphere containing hydrogen before the titanium layer forming step,

the temperature at which the semiconductor substrate is annealed in the titanium silicidation step is higher than the annealing temperature in the hydrogen annealing step.

Technical Field

The invention relates to a semiconductor device and a manufacturing method.

Background

Conventionally, a semiconductor device provided with a transistor such as an Insulated Gate Bipolar Transistor (IGBT) has been known to have a barrier metal structure in which a titanium layer, a titanium nitride layer, and the like are laminated (see, for example, patent documents 1 to 4).

Patent document 1: japanese patent laid-open publication No. 2016-225512

Patent document 2: japanese laid-open patent publication No. 2000-195819

Patent document 3: japanese patent No. 5672719

Patent document 4: japanese laid-open patent publication No. 6-97111

Disclosure of Invention

Technical problem

Defects formed in the semiconductor substrate can be recovered by implanting hydrogen ions into the semiconductor substrate. However, since the titanium layer blocks the passage of hydrogen, if a barrier metal is provided, defects in the semiconductor substrate may not be sufficiently recovered.

Technical scheme

In order to solve the above problem, according to the 1 st aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate. The semiconductor device may include an interlayer insulating film disposed on an upper surface of the semiconductor substrate. The semiconductor device may include a titanium layer provided on the interlayer insulating film. The semiconductor device may include a titanium nitride layer provided on the titanium layer. The interlayer insulating film may be provided with an opening that exposes a portion of the upper surface of the semiconductor substrate. The titanium layer and the titanium nitride layer may also be disposed within the opening. The titanium layer disposed in contact with the semiconductor substrate at the bottom of the opening may be entirely titanium-silicided.

The semiconductor device may include a tungsten plug provided on the titanium nitride layer in the opening.

The titanium layer provided on the interlayer insulating film in the region other than the opening may be a titanium layer containing no titanium silicide portion.

The thickness of the titanium layer provided on the interlayer insulating film in the region other than the opening may be 30nm to 45 nm.

At least a portion of the sidewall of the interlayer insulating film at the opening may have a curved surface shape protruding upward.

The semiconductor substrate may have a plurality of groove portions provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate and provided side by side on the upper surface of the semiconductor substrate in a predetermined arrangement direction. The semiconductor substrate may have a mesa portion sandwiched by 2 groove portions in the arrangement direction. The interlayer insulating film may be provided so as to cover at least a part of the upper end of the groove portion. The opening may be provided so that at least a part of the upper surface of the mesa portion is exposed. The side wall of the interlayer insulating film may have a curved surface shape at least above both ends in the arrangement direction of the mesa portions.

The semiconductor device may include a 2 nd titanium layer that is not titanium-silicided and that is disposed on the titanium nitride layer and on the tungsten plug.

In the 2 nd aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include an insulating film forming step of forming an interlayer insulating film on an upper surface of the semiconductor substrate. The manufacturing method may include an opening forming step of forming an opening in the interlayer insulating film to expose a part of the upper surface of the semiconductor substrate. The manufacturing method may include a titanium layer forming step of forming a titanium layer on the interlayer insulating film and in the opening. The manufacturing method may include a titanium nitride layer forming step of forming a titanium nitride layer on the titanium layer. The manufacturing method may include a titanium silicidation step of siliciding all of the titanium layer disposed in the bottom of the opening in contact with the semiconductor substrate.

In the titanium silicidation step, the semiconductor substrate may be annealed at 700 ℃ or higher.

In the titanium layer forming step, a titanium layer of 30nm to 45nm may be formed.

The manufacturing method may include a tungsten plug forming step of forming a tungsten plug on the titanium nitride layer within the opening. The temperature for annealing the semiconductor substrate in the titanium silicidation step may be higher than the temperature for forming the tungsten film in the tungsten plug formation step.

The manufacturing method may include a hydrogen annealing step of annealing the semiconductor substrate in an atmosphere containing hydrogen before the titanium layer forming step. The temperature at which the semiconductor substrate is annealed in the titanium silicidation step may be higher than the annealing temperature in the hydrogen annealing step.

It should be noted that the above summary of the invention does not list all necessary features of the invention. Moreover, a sub-combination of these feature groups can also be another invention.

Drawings

Fig. 1 is a diagram showing a structure of an upper surface of a semiconductor device 100 according to an embodiment of the present invention.

Fig. 2 is an enlarged view of the vicinity of the region 130 in fig. 1.

Fig. 3 is a view showing an example of a cross section a-a in fig. 2.

Fig. 4 is a cross-sectional view showing an example of the structure of the barrier metal 110.

Fig. 5 is a diagram showing another example of the shape of the contact hole 54.

Fig. 6 is a diagram showing another configuration example of the barrier metal 110.

Fig. 7 is a diagram illustrating a part of the steps in the method for manufacturing the semiconductor device 100.

Fig. 8 is a graph showing a relationship between the annealing temperature in the titanium silicidation step S610 and the variation (3 σ) in the threshold voltage Vth of the semiconductor device 100.

Fig. 9 is a graph showing a relationship between the thickness T1 of the titanium layer 114 and the variation in the threshold voltage Vth.

Description of the symbols

10. semiconductor substrate, 11. well region, 12. emitter region, 14. base region, 15. contact region, 16. accumulation region, 18. drift region, 20. buffer region, 21. upper surface, 22. collector region, 23. lower surface, 24. collector, 25. connection, 30. dummy trench, 32. dummy insulating film, 34. dummy conductive portion, 38. interlayer insulating film, 39. upper position, 40. gate trench, 42. gate insulating film, 44. gate conductive portion, 48. gate runner, 49. gate, 50. gate metal layer, 52. gate contact, 60. side wall, 54. emitter contact, and two side walls, 56. emitter region, 14. base region, 15. contact region, 16. accumulation region, 18. drift region, 20. buffer region, 21. upper surface, 22. collector region, 23. lower surface, 70 · transistor portion, 80 · diode portion, 82 · cathode region, 90 · edge termination structure portion, 92 · guard ring, 100 · semiconductor device, 102 · active region, 104 · gate pad, 106 · emitter pad, 110 · barrier metal, 112 · titanium nitride layer, 114 · titanium layer, 115 · titanium layer, 2 · titanium layer, 116 · titanium silicide layer, 120 · tungsten plug, 130 · region, 140 · peripheral end.

Detailed Description

The present invention will be described below with reference to embodiments of the invention, but the following embodiments do not limit the claimed invention. In addition, all combinations of the features described in the embodiments are not necessarily essential to the solution of the invention.

In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "up", and the other side is referred to as "down". One of the 2 main surfaces of the substrate, layer or other member is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "up" and "down" are not limited to the direction of gravity or the mounting direction to a substrate or the like at the time of mounting of the semiconductor device.

In this specification, technical matters will be described using orthogonal coordinate axes of X, Y, and Z axes. In this specification, a plane parallel to the upper surface of the semiconductor substrate is referred to as an XY plane, and a depth direction perpendicular to the upper surface of the semiconductor substrate is referred to as a Z axis.

In each embodiment, an example in which the conductivity type of each region in the semiconductor substrate is N-type or P-type is shown, but the conductivity type of each region may be opposite. In the present specification, the term "P + -type" (or "N + -type") means a higher doping concentration than the P-type (or "N-type"), and the term "P-type" (or "N-type") means a lower doping concentration than the P-type (or "N-type").

In the present specification, the doping concentration refers to the concentration of a donor or acceptor impurity. In this specification, the difference in the concentration of donors and acceptors is sometimes referred to as the doping concentration. In addition, a peak of the doping concentration distribution in the doped region may be referred to as the doping concentration in the doped region.

Fig. 1 is a diagram showing a structure of an upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 of this example is a silicon substrate, but may be a substrate of another material as long as it is damaged by hydrogen ion recovery. Damage such as crystal defects due to implantation of donor ions or acceptor ions exists inside the semiconductor substrate 10.

In this specification, an end portion of the outer periphery of the semiconductor substrate 10 in a plan view is referred to as an outer peripheral end 140. The plan view is a view viewed from the upper surface side of the semiconductor substrate 10 in parallel with the Z axis. The semiconductor device 100 of this example includes an active region 102 and an edge termination structure 90. The active region 102 is a region in which a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. In other words, the region is a region in which current flows in the semiconductor substrate 10 in the depth direction from the upper surface toward the lower surface of the semiconductor substrate 10 or from the lower surface toward the upper surface.

Transistor portion 70 is provided in active region 102. As shown in fig. 1, a diode portion 80 may be further provided in the active region 102. Transistor portion 70 includes a transistor such as an IGBT. The diode section 80 includes a diode such as a freewheeling diode (FWD). Transistor portions 70 and diode portions 80 are alternately arranged on the upper surface of semiconductor substrate 10 in a predetermined arrangement direction. The alignment direction is the X-axis direction in fig. 1.

Each diode portion 80 is provided with an N + -type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. Diode portion 80 shown by a solid line in fig. 1 is a region where a cathode region is provided on the lower surface of semiconductor substrate 10. In the semiconductor device 100 of this example, the region other than the cathode region in the region in contact with the lower surface of the semiconductor substrate is the P + -type collector region.

Edge termination structure 90 is disposed on the upper surface of semiconductor substrate 10 between active region 102 and outer peripheral end 140 of semiconductor substrate 10. The edge termination structure 90 may be annularly disposed on the upper surface of the semiconductor substrate 10 so as to surround the active region 102. The edge termination structure 90 of this example is disposed along the outer peripheral edge 140 of the semiconductor substrate 10. The edge termination structure 90 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 includes, for example, a guard ring, a field plate, a surface field reducing structure, and a structure in which these are combined.

On the upper surface of the semiconductor substrate 10, a gate metal layer 50 is provided between the edge termination structure 90 and the active region 102. An interlayer insulating film is provided between the gate metal layer 50 and the semiconductor substrate 10, but is omitted in fig. 1.

The gate metal layer 50 may be provided so as to surround the active region 102 when the semiconductor substrate 10 is viewed from above. The gate metal layer 50 is electrically connected to a gate pad 104 disposed outside the active region 102. A gate pad 104 may be disposed between the gate metal layer 50 and the active region 102. More than 1 pad such as emitter pad 106 electrically connected to the emitter may be provided between gate metal layer 50 and active region 102.

The gate metal layer 50 may be formed of aluminum or an aluminum-silicon alloy. The gate metal layer 50 is electrically connected to the transistor portion 70, and supplies a gate voltage to the transistor portion 70.

The semiconductor device 100 may be provided with a gate runner 48. Gate runner 48 is electrically connected to gate metal layer 50 and extends over active region 102. At least one gate runner 48 may be disposed across the active region 102 in the X-axis direction. Gate runner 48 supplies a gate voltage to transistor portion 70. The gate runner 48 may be formed of a semiconductor material such as polysilicon doped with impurities, or may be formed of a metal. The gate runner 48 is provided above or inside the semiconductor substrate 10, and the semiconductor substrate 10 and the gate runner 48 are insulated by an insulating film.

Fig. 2 is an enlarged view of the vicinity of the region 130 in fig. 1. The semiconductor device 100 of this example includes a guard ring 92, a gate trench portion 40, a dummy trench portion 30, a P + -type well region 11, an N + -type emitter region 12, a P-type base region 14, and a P + -type contact region 15, which are provided inside a semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. In this specification, the gate trench portion 40 or the dummy trench portion 30 may be simply referred to as a trench portion. The semiconductor device 100 of this example includes an emitter 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10. The emitter 52 and the gate metal layer 50 are disposed in a separated manner from each other.

An edge termination structure 90 is disposed outside (on the Y-axis direction positive side) the gate metal layer 50. The edge termination structure 90 may have more than 1 guard ring 92 as described above. The guard ring 92 is a P-type region provided inside the semiconductor substrate 10. The guard ring 92 is annularly provided outside the gate metal layer 50 so as to surround the active region 102.

An interlayer insulating film is provided between the emitter 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate 10, but is omitted in fig. 2. In the interlayer insulating film of this example, the contact hole 56, the contact hole 49, and the contact hole 54 are provided so as to penetrate the interlayer insulating film.

Emitter 52 is in contact with emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 through contact hole 54. Further, emitter 52 is connected to the dummy conductive portion in dummy groove portion 30 through contact hole 56. The connection portion 25 made of a conductive material such as impurity-doped polysilicon may be provided between the emitter 52 and the dummy conductive portion. An insulating film such as an oxide film is formed between the connection portion 25 and the upper surface of the semiconductor substrate 10.

Gate metal layer 50 is in contact with gate runner 48 through contact hole 49. In fig. 1, the gate runner 48 in the region 130 is omitted. At the end of the active region 102, the gate metal layer 50 may be connected to the gate trench 40 without the gate runner 48.

The gate runner 48 is formed of polysilicon or the like doped with impurities. The gate runner 48 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy groove portion 30. The gate runner 48 of this example is provided from below the contact hole 49 to the tip end of the gate groove 40.

An insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the tip end of the gate groove 40, a gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. The insulating film above the gate conductive portion is provided with a contact hole for connecting the gate conductive portion to the gate runner 48.

The emitter 52 is formed of a material containing metal. Although a barrier metal including a titanium layer and a titanium nitride layer is provided between the emitter 52 and the semiconductor substrate 10, it is omitted in fig. 2. The barrier metal may be provided in the transistor portion 70, or may be provided in the transistor portion 70 and the diode portion 80. The barrier metal of this example is provided over the entire region where the emitter 52 is disposed.

The 1 or more gate trench portions 40 and the 1 or more dummy trench portions 30 are arranged on the upper surface of the semiconductor substrate 10 at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In transistor portion 70 of the present example, 1 or more gate trench portions 40 and 1 or more dummy trench portions 30 are alternately provided along the array direction. The dummy trench portions 30 are disposed between the gate trench portions 40. In the diode portion 80, the plurality of dummy groove portions 30 are arranged on the upper surface of the semiconductor substrate 10 along the X-axis direction.

Emitter 52 is disposed above gate trench portion 40, dummy trench portion 30, well region 11, emitter region 12, base region 14, and contact region 15. The diffusion depth of well region 11 may be deeper than the depths of gate trench portion 40 and dummy trench portion 30.

The transistor portion 70 and the diode portion 80 are provided with 1 or more mesa portions 60 sandwiched by the groove portions, respectively. The mesa portion 60 is a region on the upper surface side of the semiconductor substrate 10 sandwiched by the groove portions with respect to the deepest bottom portion of the groove portion.

The base region 14 is provided in the mesa portion 60 sandwiched by the groove portions. The base region 14 is of the 2 nd conductivity type (P-type) having a lower doping concentration than the well region 11.

A contact region 15 of the 2 nd conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. On the upper surface of the semiconductor substrate 10, the base region 14 is exposed between the well region 11 and the contact region 15.

In transistor portion 70, emitter region 12 of the 1 st conductivity type having a higher doping concentration than the drift region provided in semiconductor substrate 10 is selectively provided on the upper surface of mesa portion 60.

In mesa portion 60 of transistor portion 70 of this example, contact regions 15 and emitter regions 12 are alternately arranged along the Y-axis direction. The contact region 15 and the emitter region 12 are respectively provided from the adjoining one of the groove portions to the other of the groove portions. In another example, the contact region 15 and the emitter region 12 may be arranged in stripe shapes along the Y-axis direction, respectively. In this case, in the mesa portion 60, the emitter regions 12 may be disposed at both ends in the X-axis direction in contact with the groove portion, and the contact region 15 may be disposed at the center in the X-axis direction of the mesa portion 60 sandwiched by the 2 emitter regions 12.

Of mesa portions 60 of transistor portion 70, 1 or more mesa portions 60 provided at the boundary with diode portion 80 are provided with contact regions 15 having an area larger than that of contact regions 15 of other mesa portions 60.

Base region 14 is disposed on the upper surface of mesa portion 60 of diode portion 80. However, the contact region 15 may be selectively provided in the mesa portion 60.

In each mesa portion 60 of this example, the contact hole 54 is provided above each of the contact region 15, the emitter region 12, and the base region 14. The contact hole 54 of this example is not provided in a region corresponding to the well region 11.

In the diode portion 80, an N + -type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. In fig. 2, the region where the cathode region 82 is provided is indicated by a dotted line. A P + -type collector region may be provided in a region where the cathode region 82 is not provided, among regions in contact with the lower surface of the semiconductor substrate 10.

Fig. 3 is a view showing an example of a cross section a-a in fig. 2. The a-a section is an XZ section through the emitter region 12 in the transistor portion 70.

The semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the barrier metal 110, the emitter 52, and the collector 24 in this cross section. The interlayer insulating film 38 is provided so as to cover at least a part of the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be provided on the entire upper surface 21. The interlayer insulating film 38 may be silicate glass such as PSG or BPSG, or an oxide film or a nitride film.

The interlayer insulating film 38 is provided with an opening such as a contact hole 54. The upper surface 21 of the semiconductor substrate 10 is exposed through the contact hole 54. The contact hole 54 may be disposed at the center of the mesa portion 60 in the X-axis direction. The contact hole 54 is disposed apart from the groove portion in the X-axis direction.

The barrier metal 110 is provided on the interlayer insulating film 38. The barrier metal 110 is also provided inside the contact hole 54, and contacts the upper surface 21 of the semiconductor substrate 10 exposed through the contact hole 54. The barrier metal 110 is continuously provided across 2 or more contact holes 54. The barrier metal 110 of the present example is disposed over the entire region where the emitter 52 is provided.

The emitter 52 is disposed on the barrier metal 110. The emitter 52 may also be disposed inside the contact hole 54. In this example, a tungsten plug 120 is provided on the barrier metal 110 inside the contact hole 54. The tungsten plug 120 of this example is not provided in the region other than the contact hole 54. Emitter 52 is also disposed over tungsten plug 120. By providing tungsten plug 120, even when the width of contact hole 54 is made fine, electrical connection between emitter 52 and semiconductor substrate 10 can be easily obtained.

A protective film of polyimide or the like is formed over outer peripheral ends of emitter 52, gate pad 104, and emitter pad 106, and over edge termination structure 90. The semiconductor device 100 may be used in a state of being placed in a package and covered with a sealing gel or in a state of being resin-molded. At this time, the emitter 52 is in contact with a sealing gel such as silicone gel or a molding resin such as an epoxy resin. If defects or the like occur in the emitter 52, resin ions from the sealing gel or the molding resin sometimes reach the gate insulating film through the emitter 52. If the resin ions are trapped in the gate insulating film, the threshold voltage of the semiconductor device 100 changes. By providing the barrier metal on the entire surface of the emitter 52, resin ions can be prevented from reaching the gate insulating film.

However, if the barrier metal is provided on the entire surface, the passage of hydrogen ions is suppressed. Although there is a damage such as a crystal defect caused by implantation of donor ions or acceptor ions in the semiconductor substrate 10, the damage can be recovered by implantation of hydrogen ions and annealing. Therefore, if the barrier metal is provided on the entire surface, it is difficult to recover the damage inside the semiconductor substrate 10. In the semiconductor device 100 of this example, the barrier metal 110 has a structure described later in fig. 4 and the like, and thus damage of the semiconductor substrate 10 is recovered by passing hydrogen ions.

The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 may not be in integral contact with the lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector 24 are formed of a conductive material such as metal. For example, at least a part of the regions of the emitter 52 and the collector 24 is formed of aluminum or an alloy containing aluminum as a main component. Examples of the alloy containing aluminum as a main component include an aluminum-silicon alloy, an aluminum-copper alloy, and an aluminum-silicon-copper alloy. In this specification, a direction connecting the emitter 52 and the collector 24 is referred to as a depth direction (Z-axis direction).

A P-type base region 14 is provided on the upper surface side of the semiconductor substrate 10. Inside the semiconductor substrate 10, an N-type drift region 18 is disposed below the base region 14.

In each mesa portion 60 of transistor portion 70 of this example, N + -type emitter region 12, P-type base region 14, and N + -type accumulation region 16 are arranged in this order from the upper surface side of semiconductor substrate 10. The accumulation region 16 has a higher doping concentration than the drift region 18. A drift region 18 is provided below the accumulation region 16. By providing the accumulation region 16 with a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier Injection promotion effect (IE effect) can be enhanced, and the on voltage in the transistor portion 70 can be reduced. The accumulation region 16 may be provided in the mesa portion 60 of the diode portion 80, or may not be provided in the mesa portion 60 of the diode portion 80.

In the XZ cross section passing through the contact region 15 of the transistor portion 70, the contact region 15 is provided in place of the emitter region 12 on each mesa portion 60 of the transistor portion 70. The contact region 15 may function as a latch-up inhibiting layer that inhibits latch-up.

In the transistor portion 70, a P + -type collector region 22 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10. In the diode portion 80, an N + -type cathode region 82 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10.

In the semiconductor substrate 10 of this example, N + -type buffer regions 20 are provided between the drift region 18 and the collector region 22 and between the drift region 18 and the cathode region 82. The buffer region 20 has a higher doping concentration than the drift region 18. The buffer region 20 can function as a field stop layer that prevents a depletion layer expanding from the lower surface side of the base region 14 from reaching the P + -type collector region 22 and the N + -type cathode region 82.

On the upper surface 21 side of the semiconductor substrate 10, 1 or more gate groove portions 40 and 1 or more dummy groove portions 30 are provided. Each trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a structure manufactured in the order in which the trench portion is formed after the doped region is formed. Forming the doped region between the trench portions after forming the trench portions is also included in the trench portion through doped region structure.

The gate trench portion 40 includes a gate trench provided on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding a semiconductor of an inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position inside the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 includes a region facing at least the adjacent base region 14 with the gate insulating film 42 interposed therebetween in the depth direction. The gate groove portion 40 at the cross section is covered with the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed of an inversion layer of electrons is formed in a surface layer of an interface in the base region 14 in contact with the gate trench.

The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portions 34 may be formed of the same material as the gate conductive portions 44. The dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portions 34 may have the same length in the depth direction as the gate conductive portions 44. The dummy groove portion 30 at the cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10.

Fig. 4 is a cross-sectional view showing an example of the structure of the barrier metal 110. The barrier metal 110 has a titanium layer 114 and a titanium nitride layer 112. The titanium layer 114 is provided on the interlayer insulating film 38. Titanium nitride layer 112 is disposed on titanium layer 114. In addition, the titanium layer 114 and the titanium nitride layer 112 are also disposed inside the contact hole 54. Inside the contact hole 54, a tungsten plug 120 is provided on the titanium nitride layer 112.

The contact hole 54 of this example has a bottom 55 that exposes the upper surface 21 of the semiconductor substrate 10, and a sidewall 53 that extends upward from the upper surface 21 of the semiconductor substrate 10. Titanium layer 114 is disposed along bottom 55 and sidewalls 53 of contact hole 54. However, all the titanium layer 114 disposed on the bottom portion 55 in contact with the semiconductor substrate 10 is titanium silicide. In fig. 4, titanium layer 114, which is titanium silicide, is used as titanium silicide layer 116. Titanium silicide means a compound of titanium and silicon, with TiSi and/or TiSi₂Etc., these compounds may be present alone or may be present in combination.

The titanium layer 114 is entirely titanium-silicided in the Z-axis direction, i.e., the entire region from the portion in contact with the upper surface 21 of the semiconductor substrate 10 to the portion in contact with the titanium nitride layer 112 is titanium-silicided. In other words, there is no titanium in this region that is not silicided with titanium. However, the titanium layer 114 extending upward along the side wall 53 is titanium-silicided to a predetermined thickness T3 from the portion in contact with the upper surface 21 of the semiconductor substrate 10. The titanium layer 114 disposed along the sidewall 53 may be left without being titanium silicide at an upper side than the thickness T3. Note that the entire titanium nitride layer 112 in this example remains without being silicided with titanium.

The titanium silicide layer 116 may be formed by annealing the semiconductor substrate 10 after the titanium layer 114 is provided. The annealing is performed under conditions that allow titanium silicide to be formed on the titanium layer 114 to a predetermined thickness over the entire thickness direction. For example, the thickness T1 of the titanium layer 114 in the Z-axis direction is 45nm or less, and the annealing temperature is 700 ℃ or higher. The annealing temperature may be 750 ℃ or higher, or 800 ℃ or higher. The annealing time may be 5 minutes or more, 10 minutes or more, and 15 minutes or more.

The thickness of the titanium nitride layer 112 may be 2 times or more the thickness of the titanium layer 114. As an example, the titanium nitride layer 112 is 100nm thick. In addition, the emitter 52 has a thickness of 5 μm as an example. Tungsten plug 120 is thicker than titanium nitride layer 112 and thinner than emitter 52. As an example, the tungsten plug 120 has a thickness of 700 nm.

Titanium nitride layer 112 is more difficult to titanium suicide than titanium layer 114. Therefore, the semiconductor substrate 10 can be annealed under predetermined conditions after the titanium layer 114 and the titanium nitride layer 112 are provided. This enables titanium silicidation of all the titanium layer 114 at the bottom portion 55, and the entire titanium nitride layer 112 can remain. In another example, titanium nitride layer 112 may be formed after titanium silicidation of titanium layer 114 at bottom 55. This can easily leave the entire titanium nitride layer 112. By leaving the entire titanium nitride layer 112, intrusion of aluminum such as the emitter 52 into the semiconductor substrate 10 can be easily suppressed.

By titanium siliciding all of the titanium layer 114 of the bottom portion 55, hydrogen easily passes through the titanium silicide layer 116. Therefore, hydrogen easily enters the inside of the semiconductor substrate 10, and damage due to crystal defects or the like in the inside of the semiconductor substrate 10 is easily recovered. Further, by providing the titanium silicide layer 116, the contact resistance between the barrier metal 110 and the semiconductor substrate 10 can be reduced.

For example, in the step of forming the tungsten plug 120, a large amount of hydrogen may be used to remove fluorine or the like. In such a step, hydrogen ions are implanted into the semiconductor substrate 10 through the titanium silicide layer 116, thereby recovering the damage in the substrate.

The titanium layer 114 provided on the interlayer insulating film 38 may not contain a titanium silicide portion. For example, the titanium layer 114 disposed above both ends 61 of the mesa portion 60 in the X-axis direction does not include a titanium silicide portion. This makes it easy to prevent aluminum such as emitter 52 from entering interlayer insulating film 38.

In the region other than the contact hole 54, the thickness T1 of the titanium layer 114 provided on the interlayer insulating film 38 may be 30nm or more and 45nm or less. Note that the thickness of the titanium layer 114 inside the contact hole 54 is also T1 before titanium silicidation. The thickness T2 of the titanium silicide layer 116 may be the same as the thickness T1 or may be different.

If the thickness T1 of the titanium layer 114 is too large, it is difficult to titanium-silicidize the entire contact portion between the semiconductor substrate 10 and the titanium layer 114. The thickness T1 of the titanium layer 114 may be 40nm or less. This makes it possible to titanium silicide the entire contact portion between the semiconductor substrate 10 and the titanium layer 114 relatively easily. If the thickness T1 of the titanium layer 114 is too small, it is difficult to maintain the uniformity of the film thickness. If thickness T1 is too small, emitter 52 may penetrate barrier metal 110 when a wire or the like is bonded above emitter 52. The thickness T1 may be 35nm or more.

As described above, the titanium layer 114 disposed along the sidewall 53 of the contact hole 54 is titanium-silicided to a predetermined thickness T3 from the upper surface 21 of the semiconductor substrate 10. The thickness T3 may be the same as thickness T2 or may be greater than thickness T2. By increasing the thickness T3 of the titanium silicide layer 116 in the titanium layer 114 along the sidewall 53, hydrogen ions readily pass through the end of the bottom 55 of the contact hole 54. Therefore, hydrogen ions also easily enter a region of the semiconductor substrate 10 adjacent to the bottom portion 55 (i.e., a region near the groove portion). Therefore, defects in the region near the groove portion are easily terminated, and damage of the substrate is easily recovered. As an example, the thickness T2 of the titanium silicide layer 116 is the thickness of the titanium silicide layer 116 in the Z axis direction at the center of the bottom 55 in the X axis direction, and the thickness T3 is the thickness of the titanium silicide layer 116 in the Z axis direction in contact with the side wall 53.

Fig. 5 is a diagram showing another example of the shape of the contact hole 54. In the example of fig. 4, the side wall 53 of the interlayer insulating film 38 at the contact hole 54 has a linear shape. In the example of fig. 5, at least a part of the sidewall 53 of the interlayer insulating film 38 in the contact hole 54 has a curved surface shape convex upward. Therefore, the contact hole 54 has a tapered shape with an opening area that increases as the distance from the upper surface 21 of the semiconductor substrate 10 increases.

The shape of the side wall 53 can be controlled by a process such as reflow after the contact hole 54 is formed. For example, the contact hole 54 in the example of fig. 4 is formed by anisotropic etching such as dry etching. The contact hole 54 in the example of fig. 5 may be formed by melting the interlayer insulating film 38 at a predetermined temperature after forming an opening by anisotropic etching.

In this example, a titanium silicide layer 116 in which all of the titanium layer 114 is titanium silicide is provided on the bottom portion 55 of the contact hole 54. The side wall 53 has a curved shape, so that hydrogen ions easily reach the bottom 55 of the contact hole 54. Therefore, damage caused by crystal defects or the like in the semiconductor substrate 10 is easily recovered.

As an example, the side wall 53 of the interlayer insulating film 38 may have a curved shape above both ends 61 of the mesa portion 60 in the X-axis direction. The side wall 53 may have a curved surface shape from a position in contact with the upper surface 21 of the semiconductor substrate 10 to a position outside the upper position 39 of the both ends 61 of the mesa portion 60.

Fig. 6 is a diagram showing another configuration example of the barrier metal 110. The barrier metal 110 of this example can be applied to any of the examples shown in fig. 4 and 5. The barrier metal 110 of this example has a 2 nd titanium layer 115 in addition to the structure shown in fig. 4 or 5.

Titanium layer 2 115 is disposed on titanium nitride layer 112 and on tungsten plug 120. Titanium layer 2 layer 115 has no portion that is titanium silicided.

Titanium layer 2 115 of this example is formed after tungsten plug 120. Therefore, the damage of the semiconductor substrate 10 is recovered before the 2 nd titanium layer 115 is provided. By providing the 2 nd titanium layer 115, the strength of the barrier metal 110 can be further improved, and intrusion of hydrogen into a gate insulating film or the like can be suppressed during actual use or the like. Therefore, the temporal change of the characteristics can be suppressed.

Fig. 7 is a diagram illustrating a part of the steps in the method for manufacturing the semiconductor device 100. The manufacturing method of this example includes an insulating film forming step S600. In the insulating film forming step S600, the interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10. Another film such as an oxide film may be provided between the upper surface 21 and the interlayer insulating film 38.

The manufacturing method of this example includes an opening forming step S602 after the insulating film forming step S600. The opening forming step S602 may include a process of forming a predetermined mask pattern on the interlayer insulating film 38, a process of etching the interlayer insulating film 38 using the mask pattern, and a process of removing the mask pattern. Thereby, the contact hole 54 and the like are opened.

The manufacturing method of this example includes a hydrogen annealing step S604 after the opening forming step S602. The hydrogen annealing step S604 may also be performed before the insulating film forming step S600 if there is no ion implantation process after the insulating film forming step S600. In the hydrogen annealing step S604, the semiconductor substrate 10 is annealed in an atmosphere containing hydrogen. The hydrogen annealing step S604 may be performed after forming doped regions such as emitter region 12, contact region 15, base region 14, and well region 11. This can recover at least a part of the damage of the semiconductor substrate 10 generated when the doped regions are formed.

The manufacturing method of this example includes a titanium layer forming step S606 after the hydrogen annealing step S604. In the titanium layer forming step S606, the titanium layer 114 is formed on the interlayer insulating film 38 and within the opening. The titanium layer 114 can be formed by sputtering or the like. The thickness T1 of the titanium layer 114 may be 30nm or more and 45nm or less.

The manufacturing method of this example includes a titanium nitride layer forming step S608 after the titanium layer forming step S606. In the titanium nitride layer forming step S608, the titanium nitride layer 112 is formed on the titanium layer 114. The titanium nitride layer 112 may be formed by sputtering or the like.

The manufacturing method of this example includes a titanium silicidation step S610 after the titanium nitride layer formation step S608. In the titanium silicidation step S610, all the titanium layers 114 disposed in contact with the semiconductor substrate 10 and at the bottom 55 of the opening are titanium silicided.

The manufacturing method of this example includes a tungsten plug forming step S612 after the titanium silicidation step S610. In the tungsten plug forming step S612, the tungsten plug 120 is formed on the titanium nitride layer 112 within the opening. The tungsten plug 120 may be formed by a CVD method or the like in an atmosphere containing hydrogen. In the tungsten plug forming step S612, hydrogen ions are implanted into the semiconductor substrate 10 through the titanium silicide layer 116, and damage to the semiconductor substrate 10 is recovered.

In addition, hydrogen ions may be implanted into the semiconductor substrate 10 in a step other than the tungsten plug forming step S612. The manufacturing method may include a step of implanting hydrogen ions into the interior of the semiconductor substrate 10 and annealing after the titanium silicidation step S610.

Through such a process, damage in the semiconductor substrate 10 can be recovered. For example, the damage remaining in the hydrogen annealing step S604 and the damage generated after the hydrogen annealing step S604 can be recovered. For example, sputtering or the like may cause damage to the inside of the semiconductor substrate 10.

The temperature at which the semiconductor substrate 10 is annealed in the titanium silicidation step S610 may be higher than the temperature at which tungsten is film-formed in the tungsten plug formation step S612. The annealing temperature in the titanium silicidation step S610 is, for example, 700 ℃. The film formation temperature in the tungsten plug formation step S612 is, for example, 500 ℃. By raising the annealing temperature in the titanium silicidation step S610, the titanium layer 114 is easily titanium silicidized in its entirety. The annealing time in the titanium silicidation step S610 may be longer than the film formation time in the tungsten plug formation step S612. The annealing time in the titanium silicidation step S610 is, for example, 5 minutes or more. The annealing time may be 10 minutes or more, or 15 minutes or more. The film formation time in the tungsten plug formation step S612 is, for example, 3 minutes or less.

The temperature at which the semiconductor substrate 10 is annealed in the titanium silicidation step S610 may be higher than the annealing temperature in the hydrogen annealing step S604. The annealing temperature in the hydrogen annealing step S604 is, for example, 500 ℃. The annealing time in the titanium silicidation step S610 may be shorter than the annealing time in the hydrogen annealing step S604 or longer than the annealing time in the hydrogen annealing step S604. The annealing time in the hydrogen annealing step S604 is, for example, 10 minutes or less.

The manufacturing method may include a contact plug forming step of forming a contact plug region of a P type having a higher doping concentration than the contact region 15 on the upper surface of the semiconductor substrate 10 exposed through the contact hole 54. The contact plug region may be provided only in the transistor portion 70, or may be provided in the transistor portion 70 and the diode portion 80.

The contact plug region may be formed by implanting impurity ions into a region shallower than the contact region 15. By forming the contact plug region, the contact resistance between the barrier metal 110 and the semiconductor substrate 10 can be reduced. The contact plug forming step may be performed between the opening forming step S602 and the titanium layer forming step S606. As described above, the damage generated in the contact plug region forming step can also be recovered in the tungsten plug forming step S612 and the like.

As illustrated in fig. 5, the manufacturing method may further include a reflow step of making the side wall 53 of the interlayer insulating film 38 into a curved shape. The reflow step is performed after the opening forming step S602. The reflow step may be performed between the opening forming step S602 and the contact plug forming step.

As illustrated in fig. 6, the manufacturing method may further include a 2 nd titanium layer forming step of forming the 2 nd titanium layer 115. The 2 nd titanium layer forming step is performed after the tungsten plug forming step S612. In the 2 nd titanium layer forming step, the 2 nd titanium layer 115 may be formed by sputtering or the like.

Fig. 8 is a graph showing a relationship between the annealing temperature in the titanium silicidation step S610 and the variation (3 σ) in the threshold voltage Vth of the semiconductor device 100. The thickness of the titanium layer 114 in this example is 40 nm. The annealing time was 10 minutes. The threshold voltage Vth varies according to damage such as crystal defects in the semiconductor substrate 10. If the damage of the semiconductor substrate 10 is not sufficiently recovered, the degree of recovery of the damage varies, and the variation in the threshold voltage Vth increases. Thus, residual damage such as crystal defects affects the characteristics of the semiconductor device 100.

As shown in fig. 8, if the annealing temperature reaches 700 ℃, the deviation of the threshold voltage Vth is suppressed. In addition, even if the annealing temperature is higher than 700 ℃, the variation of the threshold voltage Vth does not change. This is considered to be because the titanium layer 114 in contact with the upper surface 21 of the semiconductor substrate 10 is entirely titanium silicided by setting the annealing temperature to 700 ℃.

Note that, when neither the titanium silicidation step S610 nor the tungsten plug formation step S612 (i.e., the step of implanting hydrogen after the titanium silicidation step S610) is performed, the variation in the threshold voltage Vth is not reduced. Therefore, it is considered that the damage of the semiconductor substrate 10 by the hydrogen ions passing through the titanium silicide layer 116 is recovered.

Fig. 9 is a graph showing a relationship between the thickness T1 of the titanium layer 114 and the variation in the threshold voltage Vth. The annealing time in this example was 10 minutes. Fig. 9 shows the case where the annealing temperature is 660 ℃ and the case where the annealing temperature is 700 ℃.

In the case where the annealing temperature is 700 ℃, if the thickness T1 of the titanium layer 114 is 45nm or less, the variation in threshold voltage Vth becomes relatively small. Further, if the thickness T1 of the titanium layer 114 is 40nm or less, the variation in the threshold voltage Vth is substantially constant. It is considered that in the region where the thickness T1 is 40nm or less, all the titanium layer 114 in contact with the upper surface 21 of the semiconductor substrate 10 is titanium silicided. For example, the thickness T1 of the titanium layer 114 may be 40nm or less, and the annealing temperature may be 700 ℃ or more.

Note that, when the annealing temperature is 660 ℃, even if the thickness T1 of the titanium layer 114 is 40nm, the variation in the threshold voltage Vth is not reduced. Under these conditions, titanium remains in the titanium layer 114 in contact with the semiconductor substrate 10, and is not silicided with titanium. However, when the side wall 53 of the interlayer insulating film 38 is formed in a curved shape as shown in fig. 5, the variation in the threshold voltage Vth is reduced even if the annealing temperature is 660 ℃.

The tensile strength test of the emitter 52 was performed at annealing temperatures of 650 ℃, 700 ℃, and 750 ℃. In the tensile strength test, the lead is bonded to the emitter 52 and is pulled, and whether or not peeling of the emitter 52 occurs is tested. Even if the annealing temperature is raised to 700 ℃ or 750 ℃, no decrease in tensile strength is observed.

The present invention has been described above with reference to the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes and modifications can be made in the above embodiments. The embodiments obtained by various modifications and improvements are also included in the technical scope of the present invention as apparent from the description of the claims.

It should be noted that the execution order of the operations, sequences, steps, and stages of the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not particularly clear as "before … …", "before … …", and the like, and may be implemented in any order as long as the results of the previous processes are not used in the subsequent processes. Even if the workflows in the claims, the specification, and the drawings are described using "first", "next", and the like for convenience, it does not necessarily mean that they are executed in this order.