阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 任京彬 金圣协 金孝柱 李镐昌 罗正玟 于 2019-06-17 设计创作，主要内容包括：一种半导体器件包括衬底、穿透衬底的通孔、沿着通孔的内壁形成的通孔绝缘膜以及填充通孔的芯塞,其中,通孔绝缘膜的残余应力为60MPa至-100MPa。(A semiconductor device includes a substrate, a via hole penetrating the substrate, a via hole insulating film formed along an inner wall of the via hole, and a core plug filling the via hole, wherein a residual stress of the via hole insulating film is 60MPa to-100 MPa.)

1. A semiconductor device, comprising:

a substrate;

a through hole penetrating the substrate;

a via insulating film formed along an inner wall of the via; and

a core plug filling the through-hole,

wherein the residual stress of the via hole insulating film is 60MPa to-100 MPa.

2. The semiconductor device according to claim 1, wherein the via insulating film comprises a silicon oxide film or a silicon oxynitride film.

3. The semiconductor device according to claim 2, wherein a ratio of O-H bonds to Si-O bonds in the via insulating film is 2 to 13.

4. The semiconductor device of claim 1, wherein the substrate comprises Si.

5. The semiconductor device according to claim 1, wherein the hardness of the through-hole insulating film is 5.0 to 7.2.

6. The semiconductor device of claim 1, wherein the residual stress is measured by raman spectroscopy.

7. The semiconductor device of claim 1, further comprising:

and a barrier metal formed between the via insulating film and the core plug.

8. The semiconductor device of claim 7, wherein the barrier metal comprises W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

9. The semiconductor device according to claim 1, wherein the via insulating film is conformally formed along an inner wall of the via.

10. A semiconductor device, comprising:

a package substrate;

a first semiconductor substrate stacked on the package substrate; and

a first through-silicon via TSV structure penetrating the first semiconductor substrate and electrically connected to the package substrate, the first TSV structure including a first through-via penetrating the first semiconductor substrate, a first via insulating film formed along an inner wall of the first through-via, and a first core plug filling the first through-via,

wherein a ratio of O-H bond and Si-O bond in the first via hole insulating film is 2 to 13.

11. The semiconductor device of claim 10, further comprising:

a second semiconductor substrate stacked on the first semiconductor substrate; and

a second TSV structure penetrating the second semiconductor substrate and electrically connected to the first semiconductor substrate or the package substrate.

12. The semiconductor device according to claim 11, wherein the second TSV structure includes a second through via penetrating the second semiconductor substrate, a second via insulating film formed along an inner wall of the second through via, and a second core plug filling the second through via.

13. The semiconductor device according to claim 12, wherein a ratio of O-H bonds to Si-O bonds in the second via insulating film is 2 to 13.

14. The semiconductor device according to claim 10, wherein a residual stress of the first via insulating film is 60MPa to-100 MPa.

15. The semiconductor device according to claim 10, wherein a hardness of the first via insulating film is 5.0 to 7.2.

16. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first through via penetrating the substrate in the first region;

a second through via penetrating the substrate in the second region;

a first through-hole insulating film formed along an inner wall of the first through-hole;

a second through-hole insulating film formed along an inner wall of the second through-hole;

a first core plug filling the first through via; and

a second core plug filling the second through via hole,

wherein a residual stress of the first via hole insulating film is smaller than a residual stress of the second via hole insulating film.

17. The semiconductor device according to claim 16, wherein a ratio of O-H bonds and Si-O bonds in the first via insulating film is smaller than a ratio of O-H bonds and Si-O bonds in the second via insulating film.

18. The semiconductor device according to claim 16, wherein a hardness of the first via insulating film is greater than a hardness of the second via insulating film.

19. The semiconductor device of claim 16, further comprising:

a first exclusion region formed in the substrate around the first through via; and

a second exclusion zone formed in the substrate around the second through via,

wherein the first exclusion area and the second exclusion area are areas in which a semiconductor pattern is not formed.

20. The semiconductor device of claim 19, wherein an area of the first exclusion zone is less than an area of the second exclusion zone.

Technical Field

The present inventive concept relates to a semiconductor device and a method of manufacturing the same.

Background

In developing a three-dimensional (3D) package in which a plurality of semiconductor chips are mounted in a single semiconductor package, a Through Silicon Via (TSV) structure may be used to communicatively connect the semiconductor chips to each other. The TSV structures may penetrate the substrate or die to vertically form electrical connections between the semiconductor chips.

The formation of TSV structures may result in stresses being applied to nearby regions. Accordingly, a semiconductor pattern is formed at a distance from the TSV structure. Thus, the semiconductor pattern can be protected from such stress. The region between the semiconductor pattern and the TSV structure may be referred to as an exclusion region. The performance and efficiency of the semiconductor device may be improved if the size of the exclusion zone can be minimized.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including a substrate, a via hole penetrating the substrate, a via hole insulating film formed along an inner wall of the via hole, and a core plug filling the via hole, wherein a residual stress of the via hole insulating film is 60MPa to-100 MPa.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including: a package substrate; a first semiconductor substrate stacked on the package substrate; and a first through-silicon via (TSV) structure penetrating the first semiconductor substrate and electrically connected to the package substrate, the first TSV structure including a first through-via penetrating the first semiconductor substrate, a first via insulating film formed along an inner wall of the first through-via, and a first core plug filling the first through-via, wherein a ratio of O-H bonds and Si-O bonds in the first via insulating film is 2 to 13.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including: a substrate including a first region and a second region; a first through via penetrating the substrate in the first region; a second through via penetrating the substrate in the second region; a first through-hole insulating film formed along an inner wall of the first through-hole; a second through-hole insulating film formed along an inner wall of the second through-hole; a first core plug filling the first through via; and a second core plug filling the second through via, wherein a residual stress of the first via insulating film is smaller than a residual stress of the second via insulating film.

According to an exemplary embodiment of the inventive concept, there is provided a method of manufacturing a semiconductor device, the method including: forming a through hole in a substrate; forming a via hole insulating film covering a bottom surface and a side surface of the via hole by Atomic Layer Deposition (ALD); forming a core plug filling the via hole on the via hole insulating film; performing annealing; exposing upper surfaces of the via insulating film and the core plug by planarization; and removing a lower portion of the substrate to reveal the core plug at the bottom of the via.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device including: a substrate having a first region and a second region; a first exclusion zone disposed adjacent to the first zone; a second exclusion zone disposed adjacent to the second zone; a first via insulating film disposed adjacent to the first exclusion region; a second via insulating film disposed adjacent to the second exclusion area; a first barrier metal disposed adjacent to the first via insulating film; a second barrier metal disposed adjacent to the second via insulating film; and a core plug disposed between the first barrier metal and the second barrier metal, wherein a residual stress of each of the first via insulating film and the second via insulating film is +60MPa to-100 MPa.

Drawings

The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

fig. 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1;

fig. 3 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 4 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 5 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 are diagrams for explaining an intermediate stage of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept; and

fig. 19, 20, 21, 22, and 23 are diagrams for explaining intermediate stages of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Detailed Description

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 1 and 2.

Fig. 1 is a sectional view for explaining a semiconductor device according to an exemplary embodiment of the inventive concept, and fig. 2 is a sectional view taken along line a-a' in fig. 1.

Referring to fig. 1 and 2, a semiconductor device according to an exemplary embodiment of the inventive concept includes a substrate 100 and a Through Silicon Via (TSV) structure 230.

The first direction X may be one direction along the horizontal direction. The second direction Y may be another direction in the horizontal direction intersecting the first direction X. For example, the first direction X may be perpendicular to the second direction Y.

The third direction Z may be a direction intersecting both the first direction X and the second direction Y. The third direction Z may, for example, be perpendicular to both the first direction X and the second direction Y. The third direction Z may be, for example, a vertical direction.

The first direction X, the second direction Y and the third direction Z may all be orthogonal to each other.

The substrate 100 may be a semiconductor wafer. In an exemplary embodiment of the inventive concept, the substrate 100 includes silicon (Si). In other exemplary embodiments of the inventive concept, the substrate 100 may include an elemental semiconductor such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In an exemplary embodiment of the inventive concept, the substrate 100 may have a silicon-on-insulator (SOI) structure. For example, the substrate 100 may include a Buried Oxide (BOX) layer.

TSV structures 230 may be included in substrate 100. The substrate 100 may also include an exclusion zone 110 adjacent to the TSV structure 230. The exclusion area 110 may be a region of the substrate 100 where a semiconductor pattern is not formed.

For example, the exclusion area 110 may be a region in which a semiconductor element such as a transistor is not formed. The exclusion zone 110 is provided to protect semiconductor elements near the TSV structure 230 from adverse effects of stress.

For example, since stress may be transferred to the periphery of the TSV structure 230 during the formation of the TSV structure 230, the mobility of carriers in the substrate at the periphery of the TSV structure 230 may be changed.

Accordingly, the semiconductor element formed adjacent to the TSV structure 230 may perform an operation that is not originally different therefrom. In this case, the reliability of the entire semiconductor device may be significantly reduced. And thus includes exclusion zone 110.

In other words, the exclusion zone 110 is a region adjacent to the TSV structure 230 in which the mobility of carriers may vary with stress. Therefore, the semiconductor element may not be formed in the exclusion area 110.

The exclusion zone 110 may surround the periphery of the TSV structure 230. The exclusion area 110 is an area defined by a preset standard, and may be an area where the mobility of carriers is changed by a certain value or more due to stress. The setting of the exclusion zone 110 may be based on previously obtained experimental data. The previous experimental data may be data on the mobility of specific carriers.

However, the semiconductor device according to the exemplary embodiment of the inventive concept is not limited thereto. For example, the setting of the exclusion zone 110 may be performed based on various criteria. In other words, the method of disposing the exclusion zone 110 is not limited as long as it can determine that the size of the region around the TSV structure 230 is large enough to keep the adjacent semiconductor elements from being affected by stress.

Since the TSV structure 230 completely penetrates the substrate 100, it may be formed deep along the third direction Z. For example, the TSV structures 230 may have a depth of 1 μm to 120 μm in the third direction Z.

The TSV structure 230 may include a through via 201, a via insulating film 200, a barrier metal 210, and a core plug 220.

The through via 201 may be formed on the substrate 100 in the third direction Z. The through via 201 may completely penetrate the substrate 100. The cross section of the penetration through-hole 201 in the horizontal direction may be circular, but the inventive concept is not limited thereto. For example, the cross section of the penetration through-hole 201 in the horizontal direction may be elliptical.

In fig. 1 and 2, the diameter of the penetration through-hole 201 is shown to be constant in the third direction Z, but the inventive concept is not limited thereto. For example, the diameter of the penetration through-hole 201 may be narrowed in the downward direction. In other words, the through-hole 201 may be tapered. In this case, the penetrating through-hole 201 may be tapered as a whole, or may be partially tapered as an inlet portion.

The via insulating film 200 may be formed along the inner wall of the penetration via 201. The via insulating film 200 may be conformally formed along the inner wall of the penetration via 201. The via insulating film 200 may be formed by Atomic Layer Deposition (ALD) or plasma-enhanced ALD (PE-ALD). Therefore, the thickness of the via insulating film 200 can be uniform along the inner wall of the penetration via 201. The via insulating film 200 may include an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

Since the via insulating film 200 is formed along the inner wall of the penetration via 201, the horizontal cross section of the via insulating film 200 may have a ring shape. In other words, the through-hole insulating film 200 may be formed in a cylindrical structure filling only a part of the through-hole 201 and having a hollow center.

The barrier metal 210 may be formed along the inner wall of the hollow via insulating film 200 in the penetration via 201. The barrier metal 210 may include a conductor. The barrier metal 210 may include, for example, W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

The barrier metal 210 may be positioned between the core plug 220 and the via insulating film 200 to enhance the interface characteristics between the core plug 220 and the via insulating film 200.

Since the barrier metal 210 is formed along the inner wall of the via insulating film 200, the horizontal cross section of the barrier metal 210 may have a ring shape like the via insulating film 200. In other words, the barrier metal 210 fills only a portion of the penetration through-hole 201, and may be formed of a cylindrical structure having a hollow center.

The core plug 220 may completely fill the through-penetration hole 201. The core plug 220 may be formed on the barrier metal 210. Since the inside of the core plug 220 is not hollow, it may be in the form of a rod. The horizontal cross-section of the core plug 220 may have a circular shape.

Since the core plug 220 serves as a wiring, the core plug 220 may include a conductor. The core plug 220 may be made of, but not limited to, Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloy.

In the semiconductor device according to an exemplary embodiment of the inventive concept, the barrier metal 210 and the core plug 220 may be formed by, but not limited to, a Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process.

The core plug 220 may also be formed by electroplating after a seed layer is first formed.

In this embodiment, although the TSV structures 230 are illustrated as being formed in the substrate 100, the inventive concept is not limited thereto. For example, the TSV structures 230 may also be formed in a structure such as an interlayer insulating film instead of the substrate 100.

Since the via insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD instead of CVD, the via insulating film 200 may have a residual stress lower than that of an insulating film formed by CVD.

For example, the residual stress of the via insulating film 200 of the TSV structure 230 according to this embodiment may be +60MPa to-100 MPa. Here, the direction of the residual stress may determine whether it is tensile stress or compressive stress. The tensile stress may be a stress in a first direction (e.g., a pulling direction) due to contraction of the material, and the compressive stress may be a stress in a second direction (e.g., a pushing direction) due to expansion of the material.

In contrast, in the case of a via insulating film formed by CVD, the via insulating film may have a residual stress of about +180 MPa. In other words, the via insulating film 200 of the semiconductor device according to the exemplary embodiment of the inventive concept may have very low residual stress compared to a via insulating film formed by CVD.

When the substrate 100 is a silicon substrate, such residual stress may be checked by raman measurement of the substrate 100 around the TSV structure 230. In other words, since the degree of shift of the silicon peak is proportional to the applied stress, the residual stress can be measured by using the raman spectrum. For example, the residual stress may be measured by measuring the peak position of silicon in an unstressed state and comparing the degree of shift of the peak position due to stress.

Since the via insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD, not by CVD, it may have a bonding configuration different from that of an insulating film formed by CVD.

For example, the via insulating film 200 may include a silicon oxide film or a silicon oxynitride film. In this case, the ratio of the O-H bond and the Si-O bond (for example, the number of O-H bonds/the number of Si-O bonds) in the via hole insulating film 200 may be 13 to 2.0.

In contrast, the ratio of the O-H bond and the Si-O bond in the via hole insulating film formed by CVD may be about 15.9. In other words, in the via insulating film 200 of the semiconductor device according to the exemplary embodiment of the inventive concept, the ratio of O-H bonds and Si-O bonds may be smaller than that of the via insulating film formed by CVD.

The ratio of O-H bonds and Si-O bonds in the via insulating film can be checked by Fourier transform infrared (FT-IR) spectral measurement. FT-IR spectroscopy may be a method using white light in the infrared range, where the white light may be phase modulated using an interferometer.

Since the through-hole insulating film 200 of the TSV structure 230 according to the present embodiment is formed by ALD or PE-ALD, not by CVD, the through-hole insulating film 200 may have a hardness different from that of an insulating film formed by CVD. In other words, the hardness of the via insulating film 200 of the TSV structure 230 according to this embodiment may be greater than that of an insulating film formed by CVD.

For example, the hardness of the via insulating film 200 of the TSV structure 230 according to this embodiment may be 5.0 to 7.2 based on vickers hardness. In contrast, the hardness of the via insulating film formed by CVD may be about 4.6. In other words, the via insulating film 200 of the TSV structure 230 according to the present embodiment may be harder than the via insulating film formed by CVD.

The hardness can be checked by indentation tests. In other words, the local resistance exhibited by a material when the surface of the material is pressed with a constant load in a certain press-in body may be hardness.

Generally, the exclusion zone 110 formed around the TSV structure 230 may be disposed to eliminate the influence of stress variation due to the formation process of the TSV structure 230. The stress change may be mainly caused by a difference in Coefficient of Thermal Expansion (CTE) between the via insulating film 200, the core plug 220, and the substrate 100 and contraction of the via insulating film 200.

In other words, in a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept described later, annealing may be performed to increase conductivity of the core plug 220. In this case, since the thermal expansion coefficients of the core plug 220, the via insulating film 200, and the substrate 100 are different from each other, they may expand at different rates and may shrink when cooled again, and thus residual stress may be formed in such a process.

Further, due to the above annealing, the via hole insulating film formed by CVD may be greatly shrunk. Therefore, the space in which the core plug can expand during annealing can be further increased, which can further greatly contribute to stress changes after future annealing.

In the semiconductor device according to the present embodiment, the through-hole insulating film 200 may be formed by ALD or PE-ALD to prevent shrinkage of the through-hole insulating film. Therefore, in the through-hole insulating film 200 of the semiconductor device according to the present embodiment, the shrinkage due to annealing can be significantly reduced as compared with the degree of shrinkage of the through-hole insulating film formed by CVD.

Accordingly, stress variation of the substrate 100 adjacent to the TSV structure 230 of the semiconductor device is minimized, and the size of the exclusion zone 110 may also be minimized. Therefore, the integration degree and reliability of the semiconductor device can be greatly increased.

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 3. The repetitive parts of the above description of fig. 1 and 2 will be simplified or omitted.

Fig. 3 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 3, a semiconductor device according to an exemplary embodiment of the inventive concept includes a substrate 100, a front-end-of-line (FEOL) structure 130, and a back-end-of-line (BEOL) structure 140.

The TSV structure 230 may include a core plug 220 penetrating the substrate 100 and the FEOL structure 130 and a barrier metal 210 surrounding the core plug 220.

The substrate 100 may be a semiconductor wafer. In exemplary embodiments of the inventive concept, the substrate 100 may include Si, Ge, SiC, GaAs, InAs, or InP. Alternatively, the substrate 100 may have an SOI structure. However, the inventive concept is not limited thereto.

In exemplary embodiments of the inventive concept, the substrate 100 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. In addition, the substrate 100 may have various element isolation structures, such as a Shallow Trench Isolation (STI) structure.

The bottom surface 120B of the substrate 100 may be covered with a lower insulating film 122. The lower insulating layer 122 may include a silicon oxide layer, a silicon nitride layer, a polymer, or a combination thereof.

The FEOL structure 130 includes a plurality of various individual devices 132 and an interlayer insulating film 134. The plurality of individual devices 132 may include various microelectronic devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), system large scale integrated circuits (LSIs), image sensors such as CMOS Imaging Sensors (CIS), micro-electromechanical systems (MEMS), active devices, passive devices, and the like.

A plurality of individual devices 132 may be electrically connected to conductive regions of substrate 100. In addition, each of the plurality of individual devices 132 may be electrically isolated from other devices by the interlayer insulating film 134.

In fig. 3, the barrier metal 210, the via insulating film 200, and the core plug 220 may include a first portion covered by the substrate 100 and a second portion covered by the interlayer insulating film 134.

The BEOL structure 140 includes a multi-layer wiring structure 146, the multi-layer wiring structure 146 including a plurality of metal wiring layers 142 and a plurality of contact plugs 144. The multi-layer wiring structure 146 may be connected to the TSV structure 230.

In exemplary embodiments of the inventive concept, the BEOL structure 140 may also include other multi-layer wiring structures including a plurality of metal wiring layers and a plurality of contact plugs located in other areas on the substrate 100.

The BEOL structure 140 may include a plurality of wiring structures for connecting individual devices 132 included in the FEOL structure 130 to other wiring. The multilayer wiring structure 146 included in the BEOL structure 140 and other wiring structures in the BEOL structure 140 may be insulated from each other by the inter-metal insulating film 148.

In exemplary embodiments of the inventive concept, the BEOL structure 140 may further include a seal ring for protecting the plurality of wiring structures in the BEOL structure 140 and other structures below the BEOL structure 140 from external impact or moisture.

The top surface 30T of the TSV structure 230, which passes through the substrate 100 and the FEOL structure 130, is connected to the metal wiring layer 142 of the multi-layer wiring structure 146 included in the BEOL structure 140.

An upper insulating film 150 is formed on the inter-metal insulating film 148. The upper insulating film 150 may be a silicon oxide layer, a silicon nitride layer, a polymer, or a combination thereof.

A hole 150H is formed in the upper insulating film 150, through which a bonding pad 152 connected to the multilayer wiring structure 146 is exposed. The bonding pad 152 may be connected to the upper connection terminal 154 via the hole 150H. The bottom surface 30B of the TSV structure 230 is connected to the lower connection terminal 156.

The upper connection terminal 154 and the lower connection terminal 156 are not limited to the shape illustrated in fig. 3, and may have the shape of a solder ball, a solder bump, a rewiring structure, or a connection pad, respectively. In an exemplary embodiment of the inventive concept, at least one of the upper and lower connection terminals 154 and 156 may be omitted.

The process of forming the BEOL structure 140, the upper connection terminal 154, and the lower connection terminal 156 is performed after the TSV structures 230 are formed. The process of forming the BEOL structure 140, the upper connection terminals 154, or the lower connection terminals 156 may involve a thermal process.

For example, during the formation of the multilayer wiring structure 146 included in the BEOL structure 140, or during the formation of the upper connection terminal 154 or the lower connection terminal 156, a thermal budget may be applied to the via insulating film 200 wrapping the periphery of the core plug 220, and a thermal stress may be applied thereto.

In the semiconductor device according to the present embodiment, the through-hole insulating film 200 is formed by ALD or PE-ALD, and the volume change of the through-hole insulating film 200 may not be large despite the thermal budget. Accordingly, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 may be minimized.

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 4. The repetitive parts of the above description of fig. 1 to 3 will be simplified or omitted.

Fig. 4 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 4, the TSV structure 230 of the semiconductor device according to an exemplary embodiment of the inventive concept is formed after forming the FEOL structure 130 and the BEOL structure 140. Accordingly, the TSV structure 230 is formed to penetrate the substrate 100, the interlayer insulating film 134 of the FEOL structure 130, and the inter-metal insulating film 148 of the BEOL structure 140. The core plug 220, the via insulating film 200, and the barrier metal 210 of the TSV structure 230 include a first portion surrounded by the substrate 100, a second portion surrounded by the interlayer insulating film 134, and a third portion surrounded by the metal interlayer insulating film 148.

To electrically connect the TSV structures 230 and the upper connection terminals 154, upper wiring 158 extends between the TSV structures 230 and the upper connection terminals 154 on the BEOL structure 140. The TSV structures 230 may be connected to the upper wirings 158 through the upper insulating film 150, and may be connected to the upper connection terminals 154 through the upper wirings 158.

The process of forming the upper wiring 158, the upper connection terminal 154, and the lower connection terminal 156 is performed after the TSV structure 230 is formed, and the process of forming the upper wiring 158, the upper connection terminal 154, or the lower connection terminal 156 may involve a thermal process. In performing such a thermal process, a thermal budget is applied to the via insulating film 200 around the periphery of the core plug 220, and a thermal stress may be applied thereto.

In the semiconductor device according to the present embodiment, the through-hole insulating film 200 is formed by ALD or PE-ALD, and the volume change of the through-hole insulating film 200 may not be large despite the thermal budget. Accordingly, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 may be minimized.

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 5. The repetitive parts of the above description of fig. 1 to 4 will be simplified or omitted.

Fig. 5 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, in the semiconductor device according to an exemplary embodiment of the inventive concept, the TSV structures 230 extend to penetrate the substrate 100. After the TSV structures 230 are formed, FEOL structures 130 and BEOL structures 140 are formed on the TSV structures 230 and the substrate 100. The TSV structures 230 may be connected to the multi-layer wiring structure 146 of the BEOL structure 140 via the connection wirings 136 and 138 included in the FEOL structure 130.

In the manufacturing process of the semiconductor device according to the exemplary embodiment of the inventive concept, the via insulating film 200 may be formed by ALD or PF-ALD. Therefore, although heat treatment (e.g., annealing) is subsequently performed, the volume change of the via insulating film 200 may not be large. Accordingly, the magnitude of the volume change of the core plug 220 is reduced, and thus the size of the exclusion zone 110 adjacent to the TSV structure 230 may be minimized.

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 6. The repetitive parts of the above description of fig. 1 to 5 will be simplified or omitted.

Fig. 6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 6, a semiconductor device according to an exemplary embodiment of the inventive concept may include a package substrate 1210 and integrated circuit elements 100a and 100b mounted on the package substrate 1210.

In some embodiments of the inventive concept, the package substrate 1210 may be a printed circuit board in which the wiring structure 212 is formed.

Although fig. 6 shows a semiconductor device in which two integrated circuit elements 100a and 100b are mounted, the present invention is not limited thereto. For example, various numbers of integrated circuit elements 100a and 100b may be mounted vertically or horizontally on the package substrate 1210.

In fig. 6, the integrated circuit elements 100a and 100b are shown with some components omitted for convenience. However, at least one of the integrated circuit elements 100a and 100b may have at least one of the semiconductor device structures shown in fig. 1 to 5.

The package substrate 1210 is formed with a plurality of connection terminals 214 connected to the internal wiring structure 212 for electrical connection with the outside. In an exemplary embodiment of the inventive concept, the plurality of connection terminals 214 may be formed of solder balls, but is not limited thereto.

The electrical connection between the package substrate 1210 and the integrated circuit element 100b, or between two adjacent integrated circuit elements 100a and 100b, may be performed by a core plug 220 formed in the integrated circuit element 100 b. The TSV structure 230 is composed of a core plug 220, a barrier metal 210 surrounding the core plug 220, and a via insulating film 200 surrounding the barrier metal 210.

The semiconductor device according to an exemplary embodiment of the inventive concept may include a molding film 1220 for molding at least one of the integrated circuit elements 100a and 100 b. In exemplary embodiments of the inventive concept, the molding film 1220 may be formed of a polymer. For example, the molding film 1220 may be made of an Epoxy Molding Compound (EMC).

Hereinafter, a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 1, 2, and 7. Some of the above-described duplicated portions will be simplified or omitted.

Fig. 7 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 7, a semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 100, a first TSV structure 230, a second TSV structure 630, and an exclusion area 110.

The substrate 100 may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be adjacent to each other, or may be spaced apart from each other.

The first TSV structure 230 of the first region R1 may be the same as the TSV structure 230 described in fig. 1 and 2. The first TSV structure 230 may include a first through via 201, a first via insulating film 200, a first barrier metal 210, and a first plug 220.

The first through via 201, the first via insulating film 200, the first barrier metal 210, and the first core plug 220 may have the same structures as those of the through via 201, the via insulating film 200, the barrier metal 210, and the core plug 220 of fig. 1 and 2, respectively.

The fourth, fifth, and sixth directions X1, Y1, and Z1 of the first region R1 may be the same directions as the first, second, and third directions X, Y, and Z of fig. 1 and 2, respectively.

The seventh direction X2 of the second region R2 may be one direction along the horizontal direction. The eighth direction Y2 of the second region R2 may be another direction in the horizontal direction that intersects the seventh direction X2. For example, the seventh direction X2 may be perpendicular to the eighth direction Y2.

The ninth direction Z2 of the second region R2 may be a direction intersecting both the seventh direction X2 and the eighth direction Y2. The ninth direction Z2 may, for example, be perpendicular to both the seventh direction X2 and the eighth direction Y2. The ninth direction Z2 may be, for example, a vertical direction.

The seventh direction X2, the eighth direction Y2, and the ninth direction Z2 may all be orthogonal to each other.

The seventh direction X2, the eighth direction Y2, and the ninth direction Z2 of the second region R2 may be the same as or different from the fourth direction X1, the fifth direction Y1, and the sixth direction Z1 of the first region R1, respectively.

The second through via 601 of the second region R2 may be formed in the same size as the first through via 201 of the first region R1. In other words, the width of the second through via 601 in the seventh direction X2 may be the same as the width of the first through via 201 in the fourth direction X1.

The second through hole insulating film 600 may be formed along the inner wall of the second through hole 601. The second via insulating film 600 may be formed of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

In exemplary embodiments of the inventive concept, the second via insulating film 600 may be formed using a CVD process. For example, the second via insulating film 600 may be formed to have about 1000 to

Is measured. However, the present embodiment is not limited thereto.

For example, the second via insulating film 600 may be formed of ozone/tetraethylorthosilicate (O) formed by a sub-atmospheric pressure (sub-atmospheric) CVD process₃TEOS) High Aspect Ratio Process (HARP) oxide film formation. However, the present embodiment is not limited thereto.

The first via insulating film 200 may be formed by ALD or PE-ALD and has a first thickness T1. The second via insulating film 600 may be formed by CVD and has a second thickness T2 greater than the first thickness T1. Accordingly, the volume of the remaining region of the first through via 201 may be greater than the volume of the remaining region of the second through via 601. However, the present embodiment is not limited thereto.

The second barrier metal 610 may be formed along an inner wall of the hollow second via insulating film 600 in the second through via 601. The second barrier metal 610 may include a conductor. The second barrier metal 610 may include, for example, W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

The second core plug 620 may completely fill the second through via 601. The second core plug 620 may be formed on the second barrier metal 610. The second core plug 620 may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloy, but is not limited thereto.

The first core plug 220 may have a fifth thickness T5 and the second core plug 620 may have a sixth thickness T6. The fifth thickness T5 may be greater than the sixth thickness T6. This can be attributed to the fact that: although the first and second through holes 201 and 601 have the same width, the first and second thicknesses T1 and T2 are different from each other. However, the present embodiment is not limited thereto.

The exclusion region 110 of the first region R1 may be formed to have a third thickness T3 from the first TSV structure 230. The exclusion region 110 of the second region R2 may be formed to have a fourth thickness T4 from the second TSV structure 630. The fourth thickness T4 may be greater than the third thickness T3. The size of the exclusion zone 110 may be determined by the mobility of carriers in the substrate 100. Therefore, the configuration in which the exclusion zone 110 of the first region R1 is smaller than the exclusion zone 110 of the second region R2 may mean that the region in the substrate 100 in which the mobility of carriers is affected is narrower in the first region R1 than in the second region R2.

This can be attributed to the difference in characteristics between the first via insulating film 200 and the second via insulating film 600. For example, the first via insulating film 200 may have a lower residual stress than the second via insulating film 600. The residual stress of the first via insulating film 200 may be +60MPa to-100 MPa. In contrast, the residual stress of the second via insulating film 600 may be +180 MPa.

Further, the ratio of the O-H bond and the Si-O bond (for example, the number of O-H bonds/the number of Si-O bonds) of the first via insulating film 200 may be 13 to 2.0. In contrast, the ratio of the O — H bond to the Si — O bond of the second via insulating film 600 may be about 15.9.

Further, the hardness of the first via insulating film 200 may be 5.0 to 7.2. In contrast, the hardness of the second via insulating film 600 may be about 4.6.

These characteristics can be attributed to the fact that: the first via insulating film 200 is formed by ALD or PE-ALD, and the second via insulating film 600 is formed by CVD.

In the semiconductor device according to the present embodiment, since the first via insulating film 200 is formed by ALD or PE-ALD, stress variation of the substrate 100 adjacent to the TSV structures 230 in the first region R1 is minimized, and thus the size of the exclusion zone 110 may be minimized. Therefore, the integration degree and reliability of the semiconductor device can be greatly increased.

However, the second region R2 may be relatively less important than the first region R1 in view of the size of the exclusion zone 110. In this case, the second via insulating film 600 may be formed by CVD.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 8 to 18. The repetitive parts of the above description of fig. 1 to 7 will be simplified or omitted.

Fig. 8 to 18 are diagrams for explaining intermediate stages of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 8, after forming the FEOL structure 130 on the substrate 100 and forming the first polish stop layer 135 on the FEOL structure 130, a mask pattern 137 is formed on the first polish stop layer 135. A hole 137H for partially exposing the upper surface of the first polish stop layer 135 may be formed in the mask pattern 137.

In exemplary embodiments of the inventive concept, the first polishing stop layer 135 may be made of a silicon nitride film or a silicon oxynitride film. The first polishing stop layer 135 may be formed to have a thickness of about 200 to about 200Is measured. However, the inventive concept is not limited thereto. The first polish stop layer 135 may be formed using a CVD process.

The mask pattern 137 may be made of a photoresist film.

An exclusion zone 110 may be provided in the substrate 100 and FEOL structure 130. The exclusion area 110 may be a region in which semiconductor elements such as the plurality of individual devices 132 are not formed.

Next, referring to fig. 9, the first polish stop layer 135 and the interlayer insulating film 134 are etched using the mask pattern 137 (see fig. 8) as an etching mask, and then the substrate 100 is etched to form a via hole 201. The through-hole 201 includes a first hole 201a formed in the substrate 100 at a predetermined depth and a second hole 201b formed through the interlayer insulating film 134 to communicate with the first hole 201 a.

The via 201 may be formed using an anisotropic etching process. In exemplary embodiments of the inventive concept, the via hole 201 may be formed to have a width 22W of about 10 μm or less from a sidewall of the substrate 100. In exemplary embodiments of the inventive concept, the via hole 201 may be formed to have a depth 22D of about 50 to 100 μm from the upper surface of the interlayer insulating film 134. However, the width 22W and the depth 22D of the through-hole 201 are not limited thereto, and may be formed in various sizes.

The substrate 100 is exposed through the first hole 201a of the through-hole 201, and the interlayer insulating film 134 is exposed through the second hole 201b of the through-hole 201. In other embodiments of the inventive concept, the via 201 may be formed using a laser drilling technique.

After the via hole 201 is formed, the mask pattern 137 is removed to expose the upper surface of the first polish stop layer 135.

Subsequently, referring to fig. 10, a via insulating film 200 for covering the inner side wall and the bottom surface of the via 201 is formed.

The via insulating film 200 is formed to cover the surface of the substrate 100 and the surface of the interlayer insulating film 134 exposed within the via 201 and the surface of the first polishing stopper 135.

The via insulating film 200 may be formed by ALD or PE-ALD. The via insulating film 200 may be conformally formed along the inner wall of the via 201. The thickness of the via insulating film 200 may be a seventh thickness Ta.

Subsequently, referring to fig. 11, a barrier metal 210 is formed on the via insulating film 200 inside and outside the via 201.

The barrier metal 210 may be formed using a PVD process or a CVD process.

In exemplary embodiments of the inventive concept, the barrier metal 210 may include a single film formed of one material or a multi-film formed of at least two materials. In exemplary embodiments of the inventive concept, the barrier metal 210 may include W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or SiB. For example, the barrier metal 210 may have a thickness of about 50 a to

And a TaN film of about 1000 to thickness

A stacked structure of the Ta film of (1).

Subsequently, referring to fig. 12, a seed film 220S is formed on the barrier metal 210 inside and outside the via hole 201.

The seed film 220S may be used as a plating seed for forming a core plug later.

The seed film 220S may be formed of Cu, Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu. The seed film 220S may be formed using a PVD process. However, the inventive concept is not limited thereto.

Subsequently, referring to fig. 13, a core film 220P is formed on the barrier metal 210 for filling the remaining space of the via hole 201.

The process of forming the core film 220P may be performed in-situ with the process of forming the barrier metal 210 described with reference to fig. 12. However, the pressure when the barrier metal 210 is formed may be different from the pressure when the core film 220P is formed.

The core film 220P may be formed to cover the barrier metal 210 inside and outside the via hole 201.

The core film 220P may be formed by an electroplating process. In other words, a metal film is grown from the seed film 220S, and a core film 220P for filling the via hole 201 is formed on the barrier metal 210.

The host material of the core film 220P may be formed of Cu or W. In exemplary embodiments of the inventive concept, the core film 220P may be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloy, but is not limited thereto.

The core film 220P may be formed by an electroplating process. The plating process may be performed at each temperature of about 10 to 65 ℃. For example, the electroplating process may be performed at room temperature.

Subsequently, referring to fig. 14 and 15, an anneal 50 may be performed.

The annealing 50 may be a heat treatment process for increasing the conductivity of the core film 220P. For example, since the core film 220P is formed by an electroplating process, the size of the crystal grains is small and the conductivity may be low.

Since the core film 220P is later used as a wiring to the core plug 220, higher conductivity is required. Therefore, the size of the crystal grains can be increased by recrystallizing the core film 220P by the annealing 50. Therefore, grain boundaries of crystals of the core film 220P are reduced, and the conductivity of the core film 220P can be greatly increased.

By such annealing 50, the thickness of the via insulating film 200 can be reduced. For example, the seventh thickness Ta may be reduced to an eighth thickness Tb. At this time, since the through-hole insulating film 200 is an insulating film formed by ALD or PE-ALD, shrinkage can occur relatively less than an insulating film formed by CVD.

Graph (a) in fig. 15 may be the via insulating film 200 before the annealing 50, and graph (b) in fig. 15 may be the via insulating film 200 after the annealing 50. By the annealing 50, additional bonding can be performed in the dangling bonds and porous regions of the via insulating film 200 before the annealing 50. Therefore, the configuration of the through-hole insulating film 200 can become denser and hardened.

Since the through-hole insulating film 200 of the method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept is formed by ALD or PE-ALD, the through-hole insulating film 200 may be relatively harder and denser than a through-hole insulating film formed by CVD. In addition, the degree of shrinkage caused by the annealing 50 may be lower.

Subsequently, referring to fig. 16, the resultant product of fig. 14 including the core film 220P is polished by a Chemical Mechanical Polishing (CMP) process using the first polishing stop layer 135 as a stop point, thereby revealing the first polishing stop layer 135.

Thus, the portions of the via insulating film 200, the barrier metal 210, and the core film 220P located outside the via 201 are removed, and the core plug 220 as a part of the core film 220P remains on the barrier metal 210 in the via 201.

Subsequently, referring to fig. 17, the first polishing stop layer 135 (see fig. 16) may be removed.

Examples of performing CMP after performing the anneal 50 are provided in fig. 14 through 16, but the inventive concept is not limited thereto. It is also possible to perform CMP and then anneal 50.

In other words, the resultant structure obtained by forming the core plug 220 in the through-hole 201 is annealed. Therefore, the metal particles constituting the core plug 220 are grown by the heat treatment, and the roughness on the exposed surface of the core plug 220 may be deteriorated. The portion of the metal particles grown by the heat treatment protruding out of the via hole 201 may be removed again by the CMP process.

At this time, the first polishing stop layer 135 (see fig. 16) is also removed, and the upper surface of the interlayer insulating film 134 of the FEOL structure 130 may be exposed. In exemplary embodiments of the inventive concept, the heat treatment may be performed at a temperature of about 300 to 500 ℃.

The TSV structure 230 including the core plug 220, the barrier metal 210 surrounding the core plug 220, and the via insulating film 200 is left in the via 201.

Subsequently, referring to fig. 18, a lower portion of the substrate 100 is removed to form a through via 201.

The lower portion of the substrate 100 may be a portion forming the bottom surface of the through-hole 201. When the lower portion of the substrate 100 is removed, the through-hole 201 may become a through-hole 201 penetrating the substrate 100.

At this time, lower portions of the via insulating film 200, the barrier metal 210, and the core plug 220 located below the via 201 may also be removed. Therefore, the bottom surfaces of the via insulating film 200, the barrier metal 210, and the core plug 220 may be exposed to the outside.

In the method of manufacturing a semiconductor device according to the present embodiment, by forming the through-hole insulating film 200 in ALD or PE-ALD, the shrinkage of the through-hole insulating film 200 due to the annealing 50 can be minimized. Therefore, the setting of the exclusion area 110 can be minimized. Accordingly, the integration degree and reliability of the semiconductor device can be increased.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to fig. 8 to 10 and 19 to 23. Some of the above-described duplicated portions will be simplified or omitted.

Fig. 19 to 23 are diagrams for explaining intermediate stages of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

The steps corresponding to fig. 8 to 10 are the same as those described previously for fig. 8 to 10. Therefore, for convenience, description will be made from steps subsequent to fig. 10.

Referring to fig. 19, pre-annealing 51 is performed on the via insulating film 200.

The pre-annealing 51 may shrink the via insulating film 200 of the seventh thickness Ta to the ninth thickness Tc. By the pre-annealing 51, the space inside the via hole 201 can become wider than before.

Next, referring to fig. 20, a barrier metal 210 is formed on the via insulating film 200 inside and outside the via 201.

The barrier metal 210 may be formed using a PVD process or a CVD process. In exemplary embodiments of the inventive concept, the barrier metal 210 may include W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB.

Subsequently, referring to fig. 21, a seed film 220S is formed on the barrier metal 210 inside and outside the via hole 201. The seed film 220S may be formed of Cu, Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu. The seed film 220S may be formed using a PVD process. However, the inventive concept is not limited thereto.

Subsequently, referring to fig. 22, a core film 220P is formed on the barrier metal 210 for filling the remaining space of the via hole 201. The host material of the core film 220P may be formed of Cu or W. In exemplary embodiments of the inventive concept, the core film 220P may be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloy, but is not limited thereto. The core film 220P may be formed by an electroplating process.

Subsequently, referring to fig. 23, an anneal 50 may be performed.

The annealing 50 may be a heat treatment process for increasing the conductivity of the core film 220P. For example, since the core film 220P is formed by an electroplating process, the size of the crystal grains is small and the conductivity may be low.

By the annealing 50, the via insulating film 200 can be shrunk from the ninth thickness Tc to the tenth thickness Td. However, since the via insulating film 200 is in a state of having been shrunk by the pre-annealing 51, the shrinkage due to the annealing 50 may not be large.

Therefore, the degree of expansion of the core film 220P may be not more than the case where the pre-annealing 51 is not performed. This is because, without the pre-annealing 51, the core film 220P is formed in a state where the via insulating film 200 is not shrunk to the ninth thickness Tc. Therefore, the through-hole insulating film 200 is largely contracted by the annealing 50, and the core film 220P can be expanded by a space corresponding to the contraction of the through-hole insulating film 200. However, at the time of performing the pre-annealing 51, since the via insulating film 200 has shrunk to the ninth thickness Tc, the core film 220P may be formed larger than the case without the pre-annealing 51.

Therefore, the expansion rate when annealing 50 is performed later may be lower, and the degree of re-shrinkage may be lower when the temperature drops after annealing 50. Since the stress at which the TSV structures 230 are formed is proportional to the degree of shrinkage, in the method of manufacturing a semiconductor according to the present embodiment, a lower stress may be applied to minimize the exclusion area 110.

Subsequently, similarly to fig. 16 to 18, a CMP process and a process of forming the through via 201 may be performed.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.