阅读说明：本技术 用于先进封装应用的再分布层形成的方法 (Method of redistribution layer formation for advanced packaging applications ) 是由 陈翰文 史蒂文·韦尔韦贝克 罗曼·古科 关惠见 于谷 阿尔文·桑德拉扬 于 2018-06-06 设计创作，主要内容包括：本公开内容的实施方式总体描述使用压印光刻形成一个或多个装置端子再分布层的方法。本文公开的方法使得能够以低于常规光刻和蚀刻工艺的成本形成高深宽比的互连结构。另外,本文所述的工艺和方法令人满意地去除、减少和/或大体上消除在聚合物沉积工艺期间或在聚合物沉积工艺之后形成的周围聚合物层中的空隙。(Additionally, the processes and methods described herein satisfactorily remove, reduce, and/or substantially eliminate voids in surrounding polymer layers formed during or after a polymer deposition process.)

A method for forming a redistribution layer of the type , comprising the steps of:

depositing a polymer onto a surface of a reconstituted substrate, the reconstituted substrate comprising a plurality of devices disposed in a molding compound;

heating the polymer to between about 120 ℃ and about 150 ℃;

imprinting a pattern into the polymer to form a plurality of openings in the polymer; and

heating the polymer to between about 250 ℃ and about 400 ℃ after imprinting the pattern.

2. The method of claim 1, wherein the polymer comprises polyimide.

3. The method of claim 2, wherein the step of imprinting the pattern into the polymer comprises the steps of: the imprint stamp is heated to between about 200 ℃ and about 300 ℃.

4. The method of claim 1, wherein the polymer comprises a photosensitive polyimide.

5. The method of claim 4, wherein the step of imprinting the pattern into the polymer comprises the steps of: exposing the polymer to ultraviolet radiation through the imprint stamp.

6. The method of claim 1, wherein the reconstituted substrate further comprises a previously formed redistribution layer disposed on the plurality of devices, the previously formed redistribution layer comprising a dielectric polymer layer having a plurality of metal interconnects disposed therein, wherein a surface of the previously formed redistribution layer has been planarized to remove portions of seed layers and metal layers from the surface of the previously formed redistribution layer.

7. The method of claim 6, wherein the dielectric polymer layer comprises polyimide.

8, A packaging method, comprising the steps of:

depositing a polymer onto the th surface of the carrier substrate;

imprinting a pattern into the polymer to form a polymer layer having a plurality of openings through the polymer layer; and

forming a plurality of metal interconnects in the polymer layer, comprising:

depositing a seed layer onto the carrier substrate and the polymer layer formed on the carrier substrate;

forming a copper layer on the seed crystal layer; and

removing portions of the seed layer and the copper layer from the second surface of the polymer layer.

9. The method of claim 8, wherein the polymer layer comprises polyimide.

10. The method of claim 9, further comprising the step of heating the polymer layer to between about 250 ℃ and about 400 ℃ after imprinting the pattern.

11. The method of claim 9, wherein the carrier substrate comprises: a structural substrate formed of glass or a rigid polymer; a release layer disposed on the structural substrate, and the polymer is deposited on the release layer.

12. The method of claim 9, wherein the step of imprinting the polymer comprises the steps of: the imprint stamp is heated to greater than about 340 ℃.

A packaging method of , comprising the steps of:

depositing a polyimide onto a substrate;

heating the polyimide to between about 120 ℃ and about 150 ℃;

imprinting the polyimide to form a dielectric layer having a plurality of openings through the dielectric layer; and

heating the dielectric layer to between about 250 ℃ and about 400 ℃ after imprinting the polyimide.

14. The method of claim 13, wherein the step of imprinting the polyimide comprises the steps of: heating the imprint stamp to between about 200 ℃ and about 300 ℃, and wherein the step of imprinting the polyimide occurs in an environment of less than about atmospheric pressure.

15. The method of claim 14, wherein the step of imprinting the polyimide comprises the steps of: exposing the polyimide to ultraviolet radiation through the imprint stamp.

Technical Field

Embodiments described herein relate generally to the field of semiconductors, and more particularly, to methods of packaging semiconductor devices.

Background

With the increasing circuit density and decreasing device size of the next generations of semiconductor devices, providing external connections (i.e., wiring) to these devices requires advanced packaging techniques such packaging techniques are wafer level packaging.

Wafer level packaging simplifies the manufacturing and packaging processes of semiconductor devices by integrating device manufacturing, package assembly (packaging), electrical testing, and reliability testing (burn-in) at the wafer level, where forming the top and bottom layers of the package, creating I/O connections, and testing the packaged devices are all performed prior to singulating the devices into individual packaged components.

The fan-out wafer level packaging process requires that the surface area of the I/O terminal redistribution layer for each individual die be larger than the surface area of the individual die itself, however, because it is desirable to maximize the number of devices (die) on the wafer to minimize cost during device fabrication, the space between individual devices (dicing lines) is typically only large enough to accommodate the width of a dicing saw used to dice the wafer into individual die of the wafer method of creating the desired additional surface area outside the die surface is to form a new wafer with die redistributed in a spaced apart pattern, referred to as a reconstituted substrate.

Typically, to form a reconstituted substrate, a wafer is singulated into individual dies, which are then positioned spaced apart from each other on a molding board (carrier substrate) and temporarily secured thereto by an adhesive layer, a molding compound is dispensed onto the carrier substrate and the dies secured thereto and then cured, which embeds the spaced apart dies in the molding compound to form the reconstituted substrate, the terminal sides of the dies are then exposed by removing the adhesive layer, and a redistribution layer is then formed on the reconstituted substrate, having interconnects disposed therein, to redistribute some or all of the of the I/O terminals of the device to areas outside the surface of the dies, which increases the area available for I/O connections and thus the number of possible I/O terminals.

Process defects associated with forming the reconstituted substrate, such as unwanted position changes of the die within the reconstituted substrate from the original placement position of the die on the adhesive layer, also referred to as die displacement, result in misalignment between the via interconnects in the subsequently formed redistribution layer and the electrical contacts on the die. Additionally, the redistribution layer is typically formed using conventional photolithography and etching processes, which are expensive, equipment intensive, and time consuming.

Accordingly, there is a need in the art for methods of forming a reconstituted substrate and redistribution layers disposed thereon for fan-out wafer level packaging schemes.

Disclosure of Invention

Embodiments herein relate generally to device packaging processes and, in particular, to methods of forming redistribution layers on a reconstituted substrate in a fan-out wafer level packaging process.

In embodiments, a method for forming a redistribution layer is provided that includes depositing a polymer onto a surface of a reconstituted substrate comprising a plurality of devices disposed in a molding compound, heating the polymer to between about 120 ℃ and about 150 ℃, imprinting a pattern into the polymer to form a plurality of openings in the polymer, and heating the polymer to between about 250 ℃ and about 400 ℃ after imprinting the pattern.

In another embodiment, a method of packaging is provided, the method including depositing a polymer onto a th surface of a carrier substrate, imprinting a pattern into the polymer to form a polymer layer having a plurality of openings through the polymer layer, and forming a plurality of metal interconnects disposed in the polymer layer.

In another embodiment, another packaging method is provided, the packaging method comprising depositing a polyimide onto a substrate, heating the polyimide to between about 120 ℃ and about 150 ℃, imprinting the polyimide to form a dielectric layer having a plurality of openings through the dielectric layer, and heating the dielectric layer to between about 250 ℃ and about 400 ℃ after imprinting the polyimide.

In another embodiment, a method of forming a redistribution layer using a micro-imprint lithography (MIL) process is provided in which a polymer layer (such as a non-photosensitive polyimide) is dispensed onto a substrate (such as a reconstituted substrate), an opening is formed in the polymer layer using a MIL stamp, and a metal interconnect is formed in the opening using a plating and planarization process.

Brief description of the drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings, .

Fig. 1A-1G illustrate the formation of redistribution layer interconnects using conventional photolithography processes according to the prior art.

Fig. 2A-2F illustrate forming one or more redistribution layers according to the method described in fig. 3.

Fig. 3 is a flow diagram illustrating a method of forming a redistribution layer according to embodiments disclosed herein.

Fig. 4A-4B illustrate forming a second redistribution layer according to the prior art.

Fig. 5A-5B illustrate forming a second redistribution layer according to embodiments disclosed herein.

Fig. 6A-6C illustrate forming a high aspect ratio interconnect structure for use in a fan-out wafer level package redistribution layer according to embodiments described herein.

Fig. 7 is a flow diagram illustrating a method of forming one or more redistribution layers in a panel fan-out packaging process according to an alternative embodiment.

Fig. 8 is a panel having one or more redistribution layers formed thereon according to the method described in fig. 7.

Detailed Description

Embodiments of the present disclosure generally describe methods of forming or more device terminal redistribution layers using imprint lithography.

Conventionally, redistribution layers of fan-out wafer level packaging schemes are formed using time-consuming and expensive photolithography and etching processes (such as the processes illustrated in fig. 1A-1G).

Fig. 1A-1G illustrate the formation of a redistribution layer interconnect using a conventional lithographic process according to the prior art fig. 1A-1G show portions of a single device 104 embedded in a reconstituted substrate (not shown) as shown in fig. 1A, a dielectric layer 106, such as a photopolymer, is deposited onto the reconstituted substrate and the device 104 embedded in the reconstituted substrate, the device 104 including an active portion 101 and a passivation layer 105, the active portion 101 having a metal layer, the passivation layer 105 being disposed on the active portion 101. typically, an opening is formed in the passivation layer 105 to expose a contact pad 103 of the metal layer below the passivation layer 105. then, a via opening 107 (shown in fig. 1B) is formed in the dielectric layer 106 using conventional lithographic and etching processes, in which a pattern is exposed onto the photopolymer, then the photopolymer is etched to form a via opening 107. , a seed layer 109 (shown in fig. 1C) is deposited onto the reconstituted substrate and features formed on the reconstituted substrate to facilitate the formation of the subsequently deposited metal layer and interconnect structures, in order to form a thicker interconnect structure, the multiple lithographic and electroplating processes, the multiple via openings are formed using a higher lithographic and electroplating process to remove the multiple lithographic processes, thus the multiple lithographic process the higher yield of the higher lithographic process is achieved as described herein, and the electroplating process is required to form the multiple lithographic process for the higher lithographic process for forming the multiple lithographic process for forming the higher yield of the interconnect layer 111, and the interconnect structures, and the higher lithographic process for the interconnect structures, and electroplating the interconnect structures, the higher lithographic process for the higher yield of the interconnect structures, and the higher lithographic process for the interconnect structures, and the higher lithographic process for the higher cost of the interconnect structures, and the higher lithographic process for the interconnect structures, and the higher cost of the higher etch of the interconnect structures, the higher cost of the interconnect structures, and the interconnect structures, and.

Fig. 2A-2F illustrate the formation of one or more redistribution layers according to the method described in fig. 3 is a flow chart illustrating a method of forming a redistribution layer according to embodiments disclosed herein fig. 3 begins with act 305, depositing a polymer layer 221, such as a dielectric polymer layer, such as a polyimide layer, onto a surface of a reconstituted substrate (not shown), herein, depositing the polymer layer 221 using spin coating and soft bake methods, in which a polyimide precursor is dispensed onto a rotating reconstituted substrate until a uniform polyimide precursor layer is formed on the reconstituted substrate, heating the reconstituted substrate and a polyimide precursor disposed on the reconstituted substrate to between about 120 ℃ and about 150 ℃ (soft bake) to remove only a portion of the solvent contained in the polyimide precursor, such that the polymer layer 221 is suitable for subsequent imprinting fig. 2A illustrates a portion of a device 204 embedded in the reconstituted substrate (not shown), the reconstituted substrate having disposed thereon the polymer layer 221, the device 204 including an active portion 201 having a metal layer and a passivation layer 205 disposed on the active portion 201 and an opening 203 in the passivation layer 205, the opening exposing the metal layer 205, disposed below the passivation layer 205.

Method 300 proceeds to act 310 and physically imprints a pattern into polymer layer 221 using a micro-imprint lithography (MIL) stamp, such as MIL stamp 228 shown in fig. 2B. In this embodiment, act 310 comprises a hot stamping process in which the MIL stamp 228 is heated and the polymer layer 221 comprises a non-photosensitive polyimide. In other embodiments, act 310 comprises an Ultraviolet (UV) MIL process in which polymer layer 221 comprises a photosensitive polyimide.

In this context, the MIL stamp 228 includes an interconnect pattern for repeatedly forming fan-out redistribution layers over or more individual dies of the reconstituted substrate in the step and in another area process in other embodiments, the MIL stamp 228 includes a plurality of patterns for forming a plurality of fan-out redistribution interconnects over a plurality of dies in a single imprint, in embodiments, a single MIL stamp is used to form a plurality of openings in the polymer layer 221 over the entire reconstituted substrate in a single imprint, herein, the MIL stamp 228 is heated to between about 200 ℃ and about 300 ℃ and the openings in the polymer layer 221 are formed over the entire reconstituted substrate in a single imprintPressing into the polymer layer 221, the polymer layer 221 displaces around the pattern of the MIL stamp 228, then the MIL stamp 228 is cooled and removed from the polymer layer 221, leaving a trench in a via opening (such as opening 225 shown in fig. 2C) formed in the polymer layer 221 moving the MIL stamp 228 over another die on the reconstituted substrate and repeating the process until an opening 225 is formed in the polymer layer 221 over all desired die on the reconstituted substrate in embodiments using a UV MIL process, the MIL stamp 228 comprises a UV transparent material (such as quartz), and exposing the polymer layer 221 comprising a photosensitive polyimide to UV radiation via the stamp, wherein the UV radiation is comprised at 200mJ/cm²Next approximately 365nm at , in some embodiments, act 310 occurs in a low pressure atmosphere, such as in a processing system that maintains a processing volume at a pressure less than atmospheric pressure (such as half of atmospheric pressure) or less than approximately 400 torr (e.g., less than approximately 300 torr.) physically imprinting a pattern into polymer layer 221 using heated MIL stamp 228 in a low pressure atmosphere satisfactorily removes, reduces, and/or substantially eliminates voids (not shown) formed in polymer layer 221 during formation of polymer layer 221 and/or after formation of polymer layer 221.

After forming the openings 225, the reconstituted substrate is thermally cured in a nitrogen ambient at between about 250 ℃ and 400 ℃, such as between about 250 ℃ and 350 ℃ or between about 325 ℃ and 400 ℃, for example, at about 300 ℃ (for a thermal MIL process) and about 375 ℃ (for a UVMIL process).

The method 300 proceeds to act 315, depositing a seed layer 209 over the polymer layer 221 and the opening 225 disposed in the polymer layer 221. The seed layer 209 enables subsequent electroplating of a metal layer (herein copper) and provides a barrier to prevent copper atoms from diffusing from the subsequently formed metal layer into the surrounding polymer layer 221 and contact pad 203. Herein, the seed layer 209 comprises tantalum, tantalum nitride, tungsten, titanium tungsten (titanium tungsten), titanium nitride, tungsten nitride, titanium copper (titanium copper), or a combination thereof, and the seed layer 209 is deposited using any suitable method, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or a combination thereof.

The method 300 proceeds to act 320 and forms a metal layer, such as the metal layer 217 shown in fig. 2E, on the seed layer 209 using an electroplating process. Herein, the metal layer 217 includes copper. In other embodiments, the metal layer 217 and subsequently formed metal interconnects comprise copper, nickel, gold, antimony silver, or combinations thereof.

The method 300 ends with act 325 of planarizing a surface of the reconstituted substrate to remove portions of the metal layer 217 and the seed layer 209 disposed on the surface of the polymer layer 221 to form or more interconnect structures 227 in the redistribution layer 214, as shown in fig. 2F planarizing the surface of the reconstituted substrate is accomplished using a Chemical Mechanical Polishing (CMP) and/or grinding process.

In addition to the fewer process operations in forming each redistribution layer (which improves yield and reduces manufacturing costs), the thermal MIL process described in method 300 enables the use of non-photosensitive polyimides for the polymer layer 221 that are different from photosensitive polymers (such as photosensitive polyimides used in conventional photolithography and etching processes). generally, among polyimide precursors suitable for use as the polymer layer 221, non-photosensitive polyimide precursors are known to have superior mechanical, electrical, and thermo-mechanical seed layer properties compared to photosensitive polyimide precursors, including stronger adhesion to metal layers and layers, lower curing temperatures, less shrinkage during the curing process, and lower dielectric constants.

Figures 4A-4B illustrate forming a second redistribution layer according to the prior art figures 5A-5B illustrate forming a second redistribution layer according to embodiments described herein as shown in figures 4A-4B, the topography of the deposited second polymer layer 411 inherent to conventional lithographic and etching processes predictably results in a non-uniform second polymer layer 411 after forming via and/or trench openings 425. the variation in surface topography causes misalignment problems due to poor depth of focus during photo patterning operations in subsequent operations.a sufficient margin (margin) to compensate for these alignment problems means to limit the number of redistribution levels (levels) in a given area, to increase the size of interconnect structures to ensure increased resistance (tolerance), and to increase the space between these interconnect structures to limit the number of interconnect structures and the number of I/O terminals in a manner that the resulting interconnection layer 214 of figure 5A formed according to the method 300 described in figure 3 has a planar surface due to the self-planarizing properties of the MIL process, or has a planar surface area and a planar surface area, and a lower pressure than the otherwise desirable surface of the conventional lithographic and etching process such as a planar polymer layer 533, or a lower than the conventional lithographic and etching process 300, to achieve a reduced interconnect formation of a more uniform interconnect structures such as a less than the formation of a planar polymer layer 70, or more desirable interconnect structures in a less than the conventional lithographic process such as a planar substrate forming a via, which may occur in a high-100, such as a via, such as a high-100, a via, a high-wafer, a wafer, such as a wafer, a wafer.

6A-6C illustrate forming a high aspect ratio interconnect structure for use in a fan-out wafer level package redistribution layer according to embodiments described herein, in FIGS. 6A-6C, an MIL method in a low pressure atmosphere environment is used to remove, reduce, and/or substantially eliminate an undesirable void 609 formed during deposition of a second polymer layer 631. FIG. 6A shows a plurality of copper pillars 607 disposed on a device 604, where the device 604 is embedded in a reconstituted substrate (not shown). the device 604 includes an active portion 601 having a metal layer and a passivation layer 605 disposed on the active portion 601 and a plurality of openings formed in the passivation layer 605 exposing the metal layer below the passivation layer 605. A second contact pad 603 is disposed on the plurality of pads 603. a seed layer (not shown) is disposed between each of the copper pillars 607 and 603 at a plurality of locations 603. the copper pillars 607, where the copper pillars 607, are formed using conventional lithography and etching processes and have a depth to be greater than about 2:1, such as greater than about 3:1, a depth to an aspect ratio (H: W) shown in FIG. 6B. FIG. 6B. the shown in FIG. 6B, a second polymer layer 631 is disposed on a high pressure atmosphere environment, and a post 631, where the post 631 is formed using a post 631, and a post 631, where the post 631 is formed using a post 631, and a post 631, where the post 631 is formed in a post 631, and a post 631, where the post 631 is formed using a post 631, and a post 631 is formed using a post 631, and a post 631, where the post 631 is formed using a post 631, where the post 631, and a post 631, where the post 631 is formed using a post 631, where the post 631, and a post formed using a post formed in a post formed using a post formed in a post formed using a post formed in a post formed.

FIG. 7 is a flow chart illustrating a method for forming or more redistribution layers in a panel fan-out package process according to an alternative embodiment FIG. 8 is a panel having or more redistribution layers formed thereon according to the method described in FIG. 7. method 700 begins with act 705, forming a th polymer layer 805, such as a non-photosensitive polyimide layer, on a carrier substrate 801. herein, the carrier substrate 801 comprises a structural base 800, such as a rectangular panel formed of a rigid material (such as silicon, glass, or a rigid polymer), and has a release layer 802, such as a thermal release layer, such as a tape (tape) or a film, disposed on the structural base 800. polymer layer 805 is herein formed by any suitable method (such as spin coating) or by dispensing polymer droplets onto the substrate surface. in embodiments, a th polymer layer 805 is formed directly on the structural base 800.

The method 700 proceeds to act 710 where a pattern is imprinted into the th polymer layer 805 using the MIL process described herein to form a plurality of openings in the th polymer layer 805 in embodiments, the MIL stamp is heated above the glass transition temperature of the polymer, such as greater than about 340 ℃ (for polyimide) in embodiments, imprinting the pattern into the th polymer layer 805 occurs in a low pressure atmosphere environment, such as less than atmospheric pressure, less than about half atmospheric pressure, or less than about 400 torr, such as less than about 300 torr.

The method 700 proceeds to act 715 where a seed layer (not shown in fig. 8) is deposited over the polymer layer 805 to enable a copper layer to be subsequently formed on the seed layer using an electroplating process at act 720.

The method 700 proceeds to act 725 where the surface of the substrate is planarized using a CMP and/or grinding process to remove the copper layer and a portion of the seed layer from the surface of the substrate to form a redistribution layer 810, the redistribution layer 810 including a polymer layer 805 and a plurality of metal interconnects 812 disposed in the polymer layer 805.

once the desired number of redistribution layers have been formed, the method proceeds to act 730, where the plurality of individual devices 804 are bonded to the metal contact pads of the metal interconnects 812 of the finally formed redistribution layer 816.

The method ends in act 735 by dispensing and curing the molding compound 815 over the plurality of individual devices to form the reconstituted substrate 814, and then peeling the reconstituted substrate 814 and the redistribution layer disposed on the reconstituted substrate 814 from the carrier substrate 801.

The method 700 allows for low cost and high throughput redistribution layer formation in a panel fan-out packaging scheme.

While the foregoing is directed to embodiments of the present disclosure, other and further -step embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.