Test structure of pattern deviation, forming method thereof and detection method of pattern deviation
阅读说明：本技术 图形偏移的测试结构及其形成方法、图形偏移的检测方法 (Test structure of pattern deviation, forming method thereof and detection method of pattern deviation ) 是由 眭小超 王珏 钟荣祥 周旭 钟志鸿 于 2019-09-26 设计创作，主要内容包括：本发明提供了一种图形偏移的测试结构及其形成方法、图形偏移的检测方法。本发明提供的图形偏移的测试结构中,多个串联元件的端部依次靠近导电连接线,从而当对应于导电连接线的第二图案层相对于对应于串联元件的第一图案层存在由于对准偏差而产生的图形偏移时,即会导致连接至导电连接线上的串联元件的数量发生变化,进而可以根据串联元件的数量变化,推断出第二图案层相对于第一图案层的对准偏差。即,本发明提供的测试结构中,可以根据连接至导电连接线上的串联元件的数量变化,更为明显、直观的体现出各个图案层之间由于对准偏差所产生的图形偏移状况。(The invention provides a test structure of pattern deviation, a forming method thereof and a detection method of pattern deviation. In the test structure for pattern deviation provided by the invention, the end parts of the plurality of series elements are sequentially close to the conductive connecting line, so that when the second pattern layer corresponding to the conductive connecting line has pattern deviation caused by alignment deviation relative to the first pattern layer corresponding to the series elements, the number of the series elements connected to the conductive connecting line is changed, and further, the alignment deviation of the second pattern layer relative to the first pattern layer can be deduced according to the change of the number of the series elements. In other words, the test structure provided by the invention can obviously and intuitively reflect the pattern offset condition caused by the alignment deviation among the pattern layers according to the change of the number of the series elements connected to the conductive connecting line.)
1. A pattern shifting test structure, said test structure having at least one test cell, said test cell comprising:
the test chain is formed in the first pattern layer and provided with X serial elements which are sequentially arranged along a preset direction, and the end parts of the 1 st serial element to the Xth serial element extend and protrude in the same direction sequentially, wherein X is a positive integer greater than or equal to 2;
a conductive connection line formed in the second pattern layer, the conductive connection line extending along an arrangement direction of the series elements on a side of the test chain corresponding to a protruding end of the series elements; and the number of the first and second groups,
the test chain comprises a first signal end and a second signal end, wherein the 1 st serial element of the test chain is electrically connected to the first signal end, and the conductive connecting line is connected to the second signal end.
2. The offset pattern test structure of claim 1, wherein ends of the 1 st to the X-th series elements in the test chain are sequentially adjacent to the electrically conductive connection line, wherein none of the series elements arranged before a predetermined series element is connected to the electrically conductive connection line, and none of the series elements arranged after the predetermined series element is connected to the electrically conductive connection line.
3. The offset pattern test structure of claim 1, wherein in the test chain, the ends of the 1 st to X-th series elements far from the electrically conductive connection line are aligned in the extending direction of the test chain, and the ends of the 1 st to X-th series elements near to the electrically conductive connection line are sequentially extended and protruded.
4. The offset patterned test structure of claim 1, wherein the length dimension of each series element in the test chain is the same, and wherein the 1 st to the xth series elements are sequentially shifted in the same direction by a predetermined dimension.
5. The offset patterned test structure of claim 1, wherein the projecting ends of the 2 nd through xth series elements in said test chain project with the same extension in sequence.
6. The pattern-shifted test structure of claim 1, wherein each series element in the test chain corresponds to the same voltage-current characteristic curve.
7. The test structure of pattern offsets according to claim 1, characterized in that the equivalent resistance value of said series element is at least 30 times larger than the contact resistance between said series element and said electrically conductive connection line.
8. The pattern shifted test structure of claim 1, wherein the series elements in the test chain comprise a PN junction structure, the PN structure comprising a P block and an N block.
9. The pattern-shifting test structure of claim 8, wherein the PN junction structure is formed in a recess of a substrate, and the recess is filled with a P-doped semiconductor layer and an N-doped semiconductor layer to form the P block and the N block.
10. The pattern shifting test structure of claim 1, wherein the test structure comprises at least two test cells, each test chain of the at least two test cells extending in a same direction.
11. The offset pattern test structure of claim 10, wherein two test units of said at least two test units that are adjacent to each other constitute a test group, and two test units of said test group are symmetrically disposed.
12. The pattern shifted test structure of claim 1, wherein the test structure comprises at least two test cells, the at least two test cells comprising: the test chain includes test cells extending along a first direction, and test cells extending along a second direction.
13. A method for performing pattern misalignment detection using the test structure of any of claims 1-12, comprising:
applying a first electric signal to a first signal end and a second signal end in a test structure, and acquiring a second electric signal fed back;
setting a reference value range, and judging whether the signal value of the second electric signal is within the reference value range; if the signal value of the second electrical signal is within the reference value range, determining that the second pattern layer has no pattern offset relative to the first pattern layer; and if the signal value of the second electric signal exceeds the reference value range, determining that the second pattern layer has pattern deviation relative to the first pattern layer.
14. The method for detecting a pattern shift according to claim 13, wherein the first electric signal is a current signal and the second electric signal is a voltage signal.
15. The method for detecting the misalignment of claim 13, wherein after determining that the second pattern layer has a pattern shift with respect to the first pattern layer, the method further comprises:
and obtaining the number of the series elements connected to the conductive connecting line in the test chain according to the deviation value of the signal value of the second electric signal relative to the reference value range so as to obtain the pattern deviation of the second pattern layer relative to the first pattern layer.
16. A method of forming a test structure with pattern shifting, comprising:
providing a substrate;
forming a first pattern layer on the substrate, wherein the first pattern layer comprises X series elements, the X series elements are sequentially arranged along a preset direction, the end parts of the 1 st series element to the Xth series element sequentially extend and protrude towards the same direction, and X is a positive integer greater than or equal to 2; and the number of the first and second groups,
and forming a second pattern layer above the first pattern layer, wherein the second pattern layer comprises a conductive connecting line, the conductive connecting line extends along the arrangement direction of the series elements on one side of the series elements corresponding to the protruding end, and the bottom of the conductive connecting line extends to the first pattern layer.
17. The method of forming offset patterned test structures of claim 16, wherein said method of forming series elements comprises:
forming X first grooves in the substrate, wherein the X first grooves are sequentially arranged along a preset direction, and the end parts of the 1 st first groove to the Xth first groove sequentially extend and protrude towards the same direction;
filling a semiconductor layer of a first doping type in each first groove;
forming a second groove in each of the first doping type semiconductor layers; and the number of the first and second groups,
and filling a second doping type semiconductor layer in each second groove, wherein the first doping type semiconductor layer and the second doping type semiconductor layer form a PN junction structure.
18. The method of forming offset patterned test structures of claim 16, wherein said conductive link is formed by a method comprising:
forming an interlayer dielectric layer on the surface of the substrate, and forming a groove extending along a preset direction in the interlayer dielectric layer; and the number of the first and second groups,
and filling a conductive material in the groove to form the conductive connecting line.
19. The method of forming offset patterned test structures of claim 16, further comprising, after forming said series elements:
forming an interlayer dielectric layer on the surface of the substrate, and forming a plurality of contact windows in the interlayer dielectric layer, wherein the series elements are exposed in the contact windows;
filling a conductive material in the contact window to form a contact plug; and the number of the first and second groups,
and forming an interconnection line on the interlayer dielectric layer, wherein the interconnection line is connected with the contact plugs in the adjacent series elements so as to connect the X series elements in series.
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure of pattern deviation, a forming method of the test structure and a detection method of the pattern deviation.
Background
In the field of semiconductor technology, it is common to form a corresponding semiconductor device by sequentially stacking a plurality of film layers. With the continuous development of semiconductor technology, devices are reduced, and thus the requirement for alignment accuracy between multiple film layers is higher and higher. In order to monitor the offset condition of the upper pattern layer relative to the lower pattern layer in time during the manufacturing process of the semiconductor device, a test structure with pattern offset is usually formed in the test region.
Fig. 1 is a schematic diagram of a conventional test structure with pattern offset, as shown in fig. 1, the test structure includes:
a lower pattern layer in which a first
and an upper pattern layer in which a
When the upper pattern layer is shifted from the lower pattern layer, the contact area of the
However, it should be appreciated that the contact resistance between the contact plug and the conductive block is small, and even if there is a pattern shift, the amount of change in the contact resistance generated at this time is extremely small, and the shift of the pattern cannot be reflected with high accuracy. In particular, as semiconductor devices are being scaled down, the requirement for detection accuracy is becoming increasingly unsatisfied based on the variation in contact resistance between the contact plugs and the conductive blocks. Further, the factors affecting the contact resistance between the contact plug and the conductive block are also complicated, and therefore, it is not possible to clearly infer whether there is a pattern deviation from only the change in the contact resistance.
Disclosure of Invention
The invention aims to provide a test structure for pattern offset, which aims to solve the problems of insensitive and unstable detection results of the conventional test structure.
To solve the above technical problem, the present invention provides a test structure for pattern shift, the test structure having at least one test unit, the test unit comprising:
the test chain is formed in the first pattern layer and provided with X serial elements which are sequentially arranged along a preset direction, and the end parts of the 1 st serial element to the Xth serial element extend and protrude in the same direction sequentially, wherein X is a positive integer greater than or equal to 2;
a conductive connection line formed in the second pattern layer, the conductive connection line extending along an arrangement direction of the series elements on a side of the test chain corresponding to a protruding end of the series elements; and the number of the first and second groups,
the test chain comprises a first signal end and a second signal end, wherein the 1 st serial element of the test chain is electrically connected to the first signal end, and the conductive connecting line is connected to the second signal end.
Optionally, in the test chain, the ends of the 1 st to the xth series elements are sequentially close to the conductive connection line, wherein none of the series elements arranged before the predetermined series element is connected to the conductive connection line, and all of the series elements arranged after the predetermined series element is connected to the conductive connection line.
Optionally, in the test chain, the ends of the 1 st to xth series elements far away from the conductive connection line are aligned in the extending direction of the test chain, and the ends of the 1 st to xth series elements near the conductive connection line extend and protrude in sequence.
Optionally, the length of each series element in the test chain is the same, and the 1 st series element to the xth series element are sequentially shifted by a predetermined size in the same direction.
Optionally, in the test chain, the protruding ends of the 2 nd to the xth serial elements extend and protrude in sequence with the same size.
Optionally, each series element in the test chain corresponds to the same voltage-current characteristic curve.
Optionally, the equivalent resistance value of the series element is at least 30 times greater than the contact resistance between the series element and the electrically conductive connection line.
Optionally, the series elements in the test chain include a PN junction structure, and the PN structure includes P blocks and N blocks.
Optionally, the PN junction structure is formed in a groove of a substrate, and a P-doped semiconductor layer and an N-doped semiconductor layer are filled in the groove to form a P block and an N block of the PN junction structure.
Optionally, the test structure includes at least two test units, and each test chain of the at least two test units extends along the same direction.
Optionally, in the at least two test units, two adjacent test units in pairs form a test group, and the two test units in the test group are symmetrically arranged.
Optionally, the test structure includes at least two test units, and the at least two test units include: the test chain includes test cells extending along a first direction, and test cells extending along a second direction.
The invention also provides a detection method for executing pattern deviation by using the test structure, which comprises the following steps:
applying a first electric signal to a first signal end and a second signal end in a test structure, and acquiring a second electric signal fed back;
setting a reference value range, and judging whether the signal value of the second electric signal is within the reference value range; if the signal value of the second electrical signal is within the reference value range, determining that the second pattern layer has no pattern offset relative to the first pattern layer; and if the signal value of the second electric signal exceeds the reference value range, determining that the second pattern layer has pattern deviation relative to the first pattern layer.
Optionally, the first electrical signal is a current signal, and the second electrical signal is a voltage signal.
Optionally, after determining that the second pattern layer has a pattern offset with respect to the first pattern layer, the method further includes:
and obtaining the number of the series elements connected to the conductive connecting line in the test chain according to the deviation value of the signal value of the second electric signal relative to the reference value range so as to obtain the pattern deviation of the second pattern layer relative to the first pattern layer.
In addition, the invention also provides a method for forming a test structure with pattern offset, which comprises the following steps:
providing a substrate;
forming a first pattern layer on the substrate, wherein the first pattern layer comprises X series elements, the X series elements are sequentially arranged along a preset direction, the end parts of the 1 st series element to the Xth series element sequentially extend and protrude towards the same direction, and X is a positive integer greater than or equal to 2; and the number of the first and second groups,
and forming a second pattern layer above the first pattern layer, wherein the second pattern layer comprises a conductive connecting line, the conductive connecting line extends along the arrangement direction of the series elements on one side of the series elements corresponding to the protruding end, and the bottom of the conductive connecting line extends to the first pattern layer.
Optionally, the method for forming the series element includes:
forming X first grooves in the substrate, wherein the X first grooves are sequentially arranged along a preset direction, and the end parts of the 1 st first groove to the Xth first groove sequentially extend and protrude towards the same direction;
filling a semiconductor layer of a first doping type in each first groove;
forming a second groove in each of the first doping type semiconductor layers; and the number of the first and second groups,
and filling a second doping type semiconductor layer in each second groove, wherein the first doping type semiconductor layer and the second doping type semiconductor layer form a PN junction structure.
Optionally, the method for forming the conductive connection line includes:
forming an interlayer dielectric layer on the surface of the substrate, and forming a groove extending along a preset direction in the interlayer dielectric layer; and the number of the first and second groups,
and filling a conductive material in the groove to form the conductive connecting line.
Optionally, after forming the series element, the method further includes:
forming an interlayer dielectric layer on the surface of the substrate, and forming a plurality of contact windows in the interlayer dielectric layer, wherein the series elements are exposed in the contact windows;
filling a conductive material in the contact window to form a contact plug; and the number of the first and second groups,
and forming an interconnection line on the interlayer dielectric layer, wherein the interconnection line is connected with the contact plugs in the adjacent series elements so as to connect the X series elements in series.
In the test structure of pattern offset provided by the invention, a plurality of series elements which sequentially extend and protrude are formed in the first pattern layer, so that the end parts of the plurality of series elements are sequentially close to the conductive connecting line in the second pattern layer. In this way, when the second pattern layer corresponding to the conductive connection line has a pattern offset caused by the alignment offset with respect to the first pattern layer corresponding to the series elements, the number of the series elements connected to the conductive connection line changes, and further, the alignment offset of the second pattern layer with respect to the first pattern layer can be inferred according to the number of the series elements connected to the conductive connection line in the test chain, and the pattern offset can be further obtained in the case of the alignment offset.
Specifically, when the test structure provided by the invention is used for detecting the pattern offset, the number of the series elements connected to the test loop in the test chain can be known according to the first electric signal applied to the test structure and the second electric signal fed back, so that the number of the series elements connected to the conductive connecting line in the test chain can be deduced, whether the pattern offset exists in the second pattern layer relative to the first pattern layer can be further judged, and the pattern offset of the second pattern layer relative to the first pattern layer can be further obtained.
Therefore, compared with the prior art that the pattern offset condition is reflected based on the change of the contact resistance, the pattern offset condition can be more obviously reflected based on the change of the electric signal value corresponding to at least one series element, and the detection precision of the alignment deviation among all pattern layers is improved. Therefore, according to the invention, the alignment deviation among all pattern layers can be more obviously and visually reflected according to the change of the number of the series elements.
Drawings
FIG. 1 is a diagram illustrating a conventional test structure for pattern shifting;
FIG. 2 is a diagram illustrating a test structure for pattern shifting according to a first embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a test structure with pattern offset in aa 'and bb' directions according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a test structure for pattern shifting according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating a test structure for pattern shifting according to a third embodiment of the present invention;
FIG. 6 is a diagram illustrating a test structure of pattern shifting according to a fourth embodiment of the present invention;
fig. 7a to 7f are schematic structural diagrams of the test structure for pattern shift in the fifth embodiment of the present invention during the manufacturing process thereof.
Wherein the reference numbers are as follows:
11-a first conducting block;
12-a second conducting block;
13-a first contact plug;
14-a second contact plug;
100-a test unit;
110-test chain;
111-N blocks;
112-P blocks;
113-a contact plug;
114-interconnect lines;
115-a barrier layer;
120-conductive connection lines;
131-a first signal terminal;
132-a second signal terminal;
200-a substrate;
300-interlayer dielectric layer;
310-a trench;
320-a contact window;
l1 — first pattern layer;
l2 — second pattern layer.
Detailed Description
The test structure of pattern shift and the forming method thereof, and the detecting method of pattern shift proposed by the present invention are further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
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