阅读说明：本技术 一种扇出型半导体封装结构 (Fan-out type semiconductor packaging structure ) 是由 孙德瑞 于 2019-10-15 设计创作，主要内容包括：本发明提供了一种扇出型半导体封装结构,本发明的扇出型半导体封装结构采用布线金属层的宽部或者冗余金属线防止布线金属层在裸芯与塑封材料层的交界面的断裂,可以实现封装良品率的提高,且工艺简单,最大程度的控制了成本。(The invention provides a fan-out semiconductor packaging structure, which adopts a wide part of a wiring metal layer or a redundant metal wire to prevent the wiring metal layer from being broken at an interface of a bare chip and a plastic packaging material layer, can realize the improvement of packaging yield, has simple process and controls the cost to the greatest extent.)

1. A fan-out semiconductor package structure, comprising:

a bare chip with a bonding pad on the top surface;

the plastic packaging material layer covers the top surface and the side surface of the bare chip;

the through hole is embedded in the plastic packaging material layer and is electrically connected with the bonding pad;

the wiring metal layer is arranged on the plastic packaging material layer and is electrically connected with the through hole;

the wiring metal layer is characterized by having a wide part crossing the interface of the bare chip and the plastic packaging material layer.

2. The fan-out semiconductor package structure of claim 1, wherein: further comprising an insulating layer covering the wiring metal layer; the wiring metal layer has an opening that exposes a portion of the wiring metal layer.

3. The fan-out semiconductor package structure of claim 1, wherein: further comprising an Under Bump Metallurgy (UBM) formed in the opening; the bump is formed on the under bump metallurgy layer.

4. The fan-out semiconductor package structure of claim 1, wherein: the wiring metal layer further comprises two narrow portions on both sides of the wide portion, one of the narrow portions extends only above the molding compound layer, and the other of the narrow portions extends above the molding compound layer and the bare chip.

5. The fan-out semiconductor package structure of claim 4, wherein: the extension line of one of the two coincides with the other.

6. The fan-out semiconductor package structure of claim 4, wherein: the extension line of one of the two is parallel to the other but does not overlap.

7. The fan-out semiconductor package structure of claim 4, wherein: the width of one of the two is different from the width of the other.

8. The fan-out semiconductor package structure of claim 1, wherein: the wide portion has a dividing channel dividing the wide portion into a plurality of parallel lines that cross the interface.

9. The fan-out semiconductor package structure of claim 8, wherein: and elastic materials are filled in the dividing channels.

10. A fan-out semiconductor package structure, comprising:

a bare chip with a bonding pad on the top surface;

the plastic packaging material layer covers the top surface and the side surface of the bare chip;

the through hole is embedded in the plastic packaging material layer and is electrically connected with the bonding pad;

a wiring metal layer disposed on the plastic package material layer and electrically connected to the through hole, the wiring metal layer having a first portion crossing an interface between the die and the plastic package material layer;

characterized in that it further comprises at least two redundant metal lines parallel to said first portion and crossing said interface.

Technical Field

The invention relates to the field of semiconductor packaging, in particular to a fan-out type semiconductor packaging structure.

Background

The fan-out wafer level package is one of the advanced packaging methods with more input/output ports (I/O) and better integration flexibility, compared with the conventional wafer level package, the fan-out wafer level package has the unique advantages of flexible ① I/O distance and no dependence on the size of a chip, ② only uses an effective bare chip (die) and improves the product yield, ③ has a flexible 3D packaging path, namely, a pattern of any array can be formed on the top, ④ has better electrical performance and thermal performance, ⑤ is applied in high frequency, and ⑥ is easy to realize high-density wiring in a rewiring layer (RDL).

Currently, a fan-out semiconductor package structure is shown in fig. 5, referring to fig. 5(a) and 5(b), a bare chip 10 is encapsulated by an encapsulating material 11, a through hole 13 is electrically connected to a pad 12 of the bare chip 10, a metal wiring layer 14 is disposed on the encapsulating material 11, the metal wiring layer 14 is connected to the through hole 13 as a redistribution layer, an insulating layer 15 covers the metal wiring layer 14, an opening is left at the position of a bump 17 and a UBM16, and a back surface protection layer 18 is further disposed on the back surface of the bare chip 10. In the structure, the metal wiring layer 14 needs to cross the interface position of the bare chip 10 and the plastic package material 11, the stress difference of the package body at the interface position is large, the metal wiring layer 14 is easy to break to form a broken part C, the yield is greatly reduced, and the package cost is not reduced.

Disclosure of Invention

Based on solving the above problems, the present invention provides a fan-out type semiconductor package structure, which includes:

a bare chip with a bonding pad on the top surface;

the plastic packaging material layer covers the top surface and the side surface of the bare chip;

the through hole is embedded in the plastic packaging material layer and is electrically connected with the bonding pad;

the wiring metal layer is arranged on the plastic packaging material layer and is electrically connected with the through hole;

the wiring metal layer is characterized by having a wide part crossing the interface of the bare chip and the plastic packaging material layer.

The wiring metal layer is covered by an insulating layer; the wiring metal layer has an opening that exposes a portion of the wiring metal layer.

Wherein, the device also comprises an Under Bump Metallurgy (UBM) formed in the opening; the bump is formed on the under bump metallurgy layer.

The wiring metal layer further comprises two narrow parts on two sides of the wide part, one of the narrow parts only extends above the plastic package material layer, and the other narrow part extends above the plastic package material layer and the bare chip.

Wherein an extension of said one coincides with said other.

Wherein the extension line of one of the two is parallel to but does not overlap with the other one.

Wherein the width of the one is different from the width of the other.

Wherein the wide portion has a dividing street dividing the wide portion into a plurality of parallel lines, the lines crossing the interface.

And elastic materials are filled in the dividing channels.

In another embodiment, the present invention provides another fan-out semiconductor package structure, comprising:

a bare chip with a bonding pad on the top surface;

the plastic packaging material layer covers the top surface and the side surface of the bare chip;

the through hole is embedded in the plastic packaging material layer and is electrically connected with the bonding pad;

a wiring metal layer disposed on the plastic package material layer and electrically connected to the through hole, the wiring metal layer having a first portion crossing an interface between the die and the plastic package material layer;

characterized in that it further comprises at least two redundant metal lines parallel to said first portion and crossing said interface.

The invention has the following advantages:

the fan-out semiconductor packaging structure provided by the invention adopts the wide part of the wiring metal layer or the redundant metal wire to prevent the wiring metal layer from being broken at the interface of the bare chip and the plastic packaging material layer, can realize the improvement of the packaging yield, and has the advantages of simple process and furthest cost control.

Drawings

Fig. 1 is (a) a sectional view and (b) a top view of a fan-out type semiconductor package structure of a first embodiment;

fig. 2 is (a) a cross-sectional view and (b) a top view of a fan-out semiconductor package structure of a second embodiment;

fig. 3 is (a) a cross-sectional view and (b) a top view of a fan-out semiconductor package structure of a third embodiment;

fig. 4 is (a) a cross-sectional view and (b) a top view of a fan-out semiconductor package structure of a fourth embodiment;

fig. 5 is a (a) cross-sectional view and (b) top view of a prior art fan-out type semiconductor package structure.

Detailed Description

The fan-out semiconductor packaging structure can prevent the breakage of the wiring metal layer at the interface of the bare chip and the plastic packaging material layer, so that the yield is improved, and the low cost is ensured.

First embodiment

Referring to fig. 1(a), the fan-out semiconductor package structure of the embodiment includes a bare chip 20, where the bare chip 20 may be a single chip cut from a single wafer and has a pad 22 on its top surface; the substrate material of the bare chip 20 can be silicon, arsenic, gallium arsenide, etc., and the back surface of the bare chip 20 has a protection layer 28. The molding compound layer 21 covers the side surfaces and the top surface of the bare chip 20, and has a certain thickness on the top surface of the bare chip 20, and the molding compound layer 21 is generally a polymer material, such as epoxy resin, silicone resin, PI, PBO, or the like.

And drilling a hole in the plastic packaging material layer 21 to form an opening, and filling metal to form a through hole 23, wherein the through hole 23 is electrically connected with the bonding pad. The drilling is realized by mechanical drilling and laser drilling, and the top surface of the through hole 23 is flush with the top surface of the plastic packaging material layer 21.

Depositing a metal layer on the plastic packaging material layer 21, and patterning to form a wiring metal layer 24, wherein the wiring metal layer 24 is electrically connected with the through hole 23; the wiring metal layer 24 and the bump 23 are made of the same material, and may be selected from copper, aluminum, gold, silver, tungsten, and alloys thereof. Referring to fig. 1(b), the routing metal layer 24 has a wide portion 242 across an interface of the die 20 and the molding compound layer 21, and first and second narrow portions 241, 243 on both sides of the wide portion, the first narrow portion 241 extending above the molding compound layer 21 and the die 20, and the second narrow portion 243 extending only above the molding compound layer 21. The wide portion 242 may be subjected to greater stresses which may ensure reliability of the electrical connection in the event of certain cracks. Also, an extension line of the first narrow portion 241 coincides with the second narrow portion 243. In other cases, the first narrow portion 241 and the second narrow portion 243 may have different widths, for example, the second narrow portion 243 has a wider width on the molding compound layer 21.

Wherein, also include the insulating layer 25, it covers said wiring metal layer 24, said insulating layer 25 can be the polymer material or inorganic material; the insulating layer 25 has an opening that exposes a portion of the wiring metal layer 24. An Under Bump Metallurgy (UBM)26 formed in the opening; a bump 27 is formed on the under bump metallurgy 26.

Second embodiment

In the first embodiment, since the stress is mainly concentrated on the wide portion 242, cracks may occur. To this end, the present invention provides a second embodiment, see fig. 2(a) and 2(b), in which the wide portion 242 has a dividing channel 244, the dividing channel 244 dividing the wide portion into a plurality of parallel lines 240, the lines 240 crossing the interface. The dividing channel 244 is filled with an elastic material, which is a rubber or silicone material, and can buffer the stress at the edge and prevent the edge from breaking due to an excessive stress difference.

Third embodiment

Referring to fig. 3(a) and 3(b), this embodiment is similar to the first embodiment except that the wide portion 246 extends across and along the interface and the extension of the first narrow portion 247 is parallel to but does not overlap the second narrow portion 245. Of course, the width of the first narrow portion 247 is different from the width of the second narrow portion 245.

Fourth embodiment

Referring to fig. 4(a) and 4(b), in this embodiment, the wiring metal layer of the package structure does not include a wide portion, the wiring metal layer is a metal wire layer with a uniform width, and spans the interface between the die 20 and the molding compound layer 21, the spanning portion has a plurality of redundant metal wires 248 on both sides, and the redundant metal wires 248 are parallel to the first portion and span the interface; the redundant metal lines 248 include two, four, or more. The redundant metal line 248 is formed in the same step and process as the routing metal layer and has a width wider than the routing metal layer. The redundant metal lines 248 may withstand most of the stress to prevent the narrower routing metal layers from breaking.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.