阅读说明：本技术 一种半导体器件、芯片封装结构以及电子设备 (Semiconductor device, chip packaging structure and electronic equipment ) 是由 张磊 陈遵淼 盛兰平 王菁 于 2019-03-28 设计创作，主要内容包括：本申请实施例提供一种半导体器件、芯片封装结构以及电子设备,涉及半导体技术领域,以在不增加半导体器件的尺寸的前提下,容纳更多数量的I/O接口。该半导体器件中第一数字逻辑电路设置于第一裸芯的有源表面上。第一I/O接口设置有源表面上临近有源表面的第一边的边缘位置。第一I/O接口与第一数字逻辑电路电连接。第二I/O接口设置于有源表面上与第一数字逻辑电连接,且位于第一I/O接口与的第一边之间。第二I/O接口与第一边的垂直距离小于第一I/O接口与第一边的垂直距离,且第二I/O接口在第一边上的垂直投影与第一I/O接口在第一边上的垂直投影至少存在部分重叠。第一I/O接口与第二I/O接口绝缘,且第一I/O接口的驱动和功耗与第二I/O接口的驱动和功耗不同。(The embodiment of the application provides a semiconductor device, a chip packaging structure and electronic equipment, and relates to the technical field of semiconductors, so that on the premise of not increasing the size of the semiconductor device, a larger number of I/O interfaces are accommodated. The first digital logic circuit in the semiconductor device is arranged on the active surface of the first bare chip. The first I/O interface is provided with an edge location on the source surface adjacent the first edge of the active surface. The first I/O interface is electrically connected to the first digital logic circuit. The second I/O interface is arranged on the active surface, electrically connected with the first digital logic and positioned between the first I/O interface and the first edge. The vertical distance between the second I/O interface and the first edge is smaller than that between the first I/O interface and the first edge, and the vertical projection of the second I/O interface on the first edge at least partially overlaps with the vertical projection of the first I/O interface on the first edge. The first I/O interface is insulated from the second I/O interface, and a driving and power consumption of the first I/O interface is different from a driving and power consumption of the second I/O interface.)

A semiconductor device, comprising:

a first die;

a first digital logic circuit disposed on an active surface of the first die;

a first input/output I/O interface disposed on the active surface at an edge location adjacent a first edge of the active surface; the first I/O interface is electrically connected with the first digital logic circuit;

a second I/O interface disposed on the active surface, the second I/O interface electrically connected to the first digital logic circuit, and the second I/O interface located between the first I/O interface and the first edge; the vertical distance between the second I/O interface and the first edge is smaller than that between the first I/O interface and the first edge, and the vertical projection of the second I/O interface on the first edge at least partially overlaps with the vertical projection of the first I/O interface on the first edge;

the first I/O interface is insulated from the second I/O interface, and the driving and power consumption of the first I/O interface is different from the driving and power consumption of the second I/O interface.

The semiconductor device according to claim 1, wherein at least one first signal bump is provided in the first I/O interface; at least one second signal bump is arranged in the second I/O interface;

the first digital logic circuit is electrically connected with the first signal bump;

the semiconductor device further includes a register group;

the register set is located on the active surface of the first die and between the first I/O interface and the second I/O interface;

the register group is electrically connected with the first digital logic circuit and the second signal bump and is used for buffering the logic signals transmitted between the first digital logic circuit and the second signal bump.

The semiconductor device according to claim 1,

the first I/O interface is rectangular, and the long side of the first I/O interface is parallel to the first side;

the second I/O interface is rectangular, and the long side of the second I/O interface is parallel to the first side.

The semiconductor device of claim 2, wherein the first die further comprises:

a first digital power plane; the first digital logic circuit is positioned in the first digital power supply plane and is electrically connected with the first digital power supply plane;

the first digital ground plane is stacked and insulated from the first digital power supply plane and is electrically connected with the first digital logic circuit;

a second digital power plane; the register set is positioned in the second digital power supply plane and is electrically connected with the second digital power supply plane;

and the second digital ground plane is stacked and insulated with the second digital power supply plane and is electrically connected with the register group.

The semiconductor device according to any one of claims 1 to 4, wherein at least one first power supply bump is provided in the first I/O interface; at least one second power supply bump is arranged in the second I/O interface;

the first die further includes:

a first interface power plane; the first I/O interface is located in the first interface power plane, and the first power bump is electrically connected with the first interface power plane;

a second interface power plane, wherein the second I/O interface is located within the second interface power plane, and the second power bump is electrically connected to the second interface power plane;

wherein the first interface power plane and the second interface power plane are isolated.

The semiconductor device according to claim 5, wherein at least one first ground bump is provided in the first I/O interface; at least one second grounding lug is arranged in the second I/O interface;

the first die further includes:

the first interface ground plane is stacked and insulated from the first interface power supply plane and is electrically connected with the first ground lug;

the second interface ground plane is stacked and insulated on the second interface power supply plane and is electrically connected with the second ground lug;

wherein the first interface ground plane and the second interface ground plane are isolated.

The semiconductor device of claim 5, wherein the first die further comprises a first digital power plane and a second digital power plane;

the first digital power plane is isolated from the first interface power plane;

the second digital power plane is isolated from the first interface power plane;

the first digital power plane is isolated from the second interface power plane;

the second digital power plane is isolated from the second interface power plane.

The semiconductor device of claim 6, wherein the first die further comprises a first digital ground plane and a second digital ground plane;

the first digital ground plane is isolated from the first interface ground plane;

the second digital ground plane is isolated from the first interface ground plane;

the first digital ground plane is isolated from the second interface ground plane;

the second digital ground plane is isolated from the second interface ground plane.

A chip packaging structure is characterized by comprising a first packaging substrate, a first plastic packaging layer and a first functional device arranged on the first packaging substrate;

a first accommodating cavity is formed between the first packaging substrate and the first plastic packaging layer, and the first functional device is arranged in the first accommodating cavity;

the first functional device is a semiconductor device as claimed in any one of claims 1 to 8.

The chip package structure according to claim 9, further comprising a second functional device disposed on the first package substrate and in the first receiving cavity;

the second functional device comprises a second die and a third I/O interface located on an active surface of the second die;

at least one third signal bump, at least one third power bump and at least one third ground bump are arranged in the third I/O interface;

and one first signal bump in the first I/O interface of the first functional device is electrically connected with one third signal bump in the third I/O interface of the second functional device through the first packaging substrate.

The chip package structure according to claim 10,

the third power supply bump in the third I/O interface of the second functional device, the first power supply bump in the first I/O interface of the first functional device, and the same power supply plane on the first package substrate are electrically connected;

the third ground bump in the third I/O interface of the second functional device and the first ground bump in the first I/O interface of the first functional device are electrically connected to the same ground plane on the first package substrate.

The chip package structure according to claim 10 or 11,

a second signal bump and a second power supply bump in a second I/O interface of the first functional device are suspended;

or the second signal bump and the second power bump in the second I/O interface of the first functional device are grounded.

An electronic device is characterized by comprising a first packaging substrate, a first plastic packaging layer, a first functional device and a circuit board, wherein the first functional device is arranged on the first packaging substrate;

a first accommodating cavity is formed between the first packaging substrate and the first plastic packaging layer, and the first functional device is arranged in the first accommodating cavity;

the first functional device is electrically connected with the circuit board through a via hole in the first package substrate;

the first functional device is a semiconductor device as claimed in any one of claims 1 to 8.

The electronic device of claim 13, further comprising a second package substrate, a second molding compound, a third functional device disposed on the second package substrate;

the second packaging substrate and the first packaging substrate are positioned on the same side of the circuit board;

a second accommodating cavity is formed between the second packaging substrate and the second plastic packaging layer, and the third functional device is arranged in the second accommodating cavity;

the third functional device is electrically connected with the circuit board through a via hole in the second packaging substrate;

the third functional device comprises a third die and a fourth I/O interface located on an active surface of the third die;

at least one fourth signal bump, at least one fourth power bump and at least one fourth ground bump are arranged in the fourth I/O interface;

a second signal bump in a second I/O interface of the first functional device is electrically connected with the first package substrate; the fourth signal bump in the fourth I/O interface of the third functional device is electrically connected to the second package substrate.

The electronic device of claim 14,

a second power supply bump in a second I/O interface of the first functional device is electrically connected to the same power supply plane on the circuit board through a via hole in the first package substrate, and a fourth power supply bump in a fourth I/O interface of the third functional device is electrically connected to the same power supply plane on the circuit board through a via hole in the second package substrate, respectively;

and a second grounding lug in a second I/O interface of the first functional device is electrically connected with the same grounding plane on the circuit board through a via hole in the first packaging substrate and a fourth grounding lug in a fourth I/O interface of the third functional device through a via hole in the second packaging substrate respectively.

The electronic device of claim 14 or 15,

a first signal bump and a first power supply bump in a first I/O interface of the first functional device are suspended;

or, the first signal bump and the first power bump in the first I/O interface of the first functional device are grounded.