阅读说明：本技术 半导体结构及其制造方法 (Semiconductor structure and manufacturing method thereof ) 是由 李岱萤 李明修 于 2020-04-02 设计创作，主要内容包括：本发明公开了一种半导体结构及其制造方法。该半导体结构包括一栓塞元件及一通孔元件。栓塞元件包括一钨栓塞。栓塞元件具有一横方向上的一栓塞尺寸。通孔元件电性连接在栓塞元件上。通孔元件相对于栓塞元件在一纵方向上延伸的一中心线呈非对称配置。通孔元件具有横方向上的一通孔尺寸。栓塞尺寸大于通孔尺寸。(The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a plug element and a via element. The plug element comprises a tungsten plug. The plug member has a plug dimension in a transverse direction. The through hole element is electrically connected to the plug element. The through-hole element is disposed asymmetrically with respect to a center line extending in a longitudinal direction of the plug element. The via member has a via dimension in the transverse direction. The plug size is larger than the via size.)

1. A semiconductor structure, comprising:

a plug element including a tungsten plug and having a plug size in a transverse direction; and

a through hole element electrically connected to the plug element and asymmetrically configured with respect to a center line of the plug element extending in a longitudinal direction, the through hole element having a through hole size in the transverse direction, the plug size being larger than the through hole size.

2. The semiconductor structure of claim 1, wherein the via element does not pass through the centerline.

3. The semiconductor structure of claim 1, further comprising a gap inside said tungsten plug, wherein said centerline passes through said gap.

4. A semiconductor structure, comprising:

a plug element including a tungsten plug and including a first side plug surface and a second side plug surface opposite to each other; and

a through hole element electrically connected to the plug element and including a first side through hole surface and a second side through hole surface opposite to each other, wherein the first side plug surface and the second side plug surface are respectively outside the first side through hole surface and the second side through hole surface, and a first distance between the first side plug surface and the first side through hole surface in a transverse direction is different from a second distance between the second side plug surface and the second side through hole surface in the transverse direction.

5. The semiconductor structure of claim 4, wherein the first side plug surface and the second side plug surface are outer plug surfaces of the plug element, the plug element further comprising an inner plug surface, the semiconductor structure further comprising a gap in the inner plug surface, wherein the via element is not aligned with the gap.

6. The semiconductor structure of claim 4, further comprising a dielectric film on the inner plug surface, the gap being defined by the dielectric film.

7. The semiconductor structure of claim 1 or 4, wherein a lower via surface of the via element contacts only an upper plug surface of the plug element.

8. The semiconductor structure of claim 1 or 4, comprising a memory device comprising:

a lower electrode including the plug element and the via element;

an upper electrode; and

a memory material layer electrically connected between the lower electrode and the upper electrode, and the through hole element electrically connected between the plug element and the memory material layer.

9. A method of fabricating a semiconductor structure, comprising:

forming an opening in a dielectric layer;

forming a tungsten plug in the opening;

forming a dielectric film on the tungsten plug;

forming a hole in the dielectric film, the hole being smaller than the opening and not aligned with a center line of the opening; and

forming a through hole element in the hole, wherein the through hole element is electrically connected to the tungsten plug.

10. The method according to claim 9, wherein an inner plug surface of the tungsten plug defines a gap, the dielectric film is on the inner plug surface exposed by the gap and on an upper plug surface of the tungsten plug, and the centerline passes through the gap.

Technical Field

The invention relates to a semiconductor structure and a manufacturing method thereof.

Background

In recent years, the size of semiconductor devices has been gradually reduced. In semiconductor technology, the reduction of feature size, improvement of speed, performance, density, and cost per unit integrated circuit are important goals. In practical applications, the device size is reduced while maintaining the electrical characteristics of the device to meet commercial requirements. For example, damaged layers and devices have a considerable impact on electronic performance, and thus how to reduce or avoid damage to layers and devices is one of the important issues facing manufacturers. Generally, semiconductor devices with good electronic performance require components with complete profiles (profiles).

Disclosure of Invention

The invention discloses a semiconductor structure and a manufacturing method thereof.

According to one aspect of the present invention, a semiconductor structure is provided, which includes a plug element and a via element. The plug element comprises a tungsten plug. The plug member has a plug dimension in a transverse direction. The through hole element is electrically connected to the plug element. The through-hole element is disposed asymmetrically with respect to a center line extending in a longitudinal direction of the plug element. The via member has a via dimension in the transverse direction. The plug size is larger than the via size.

According to another aspect of the present invention, a semiconductor structure is provided, which includes a plug element and a via element. The plug element comprises a tungsten plug. The plug element comprises a first side plug surface and a second side plug surface which are opposite. The through hole element is electrically connected to the plug element. The through hole element comprises a first side through hole surface and a second side through hole surface which are opposite. The first side plug surface and the second side plug surface are respectively arranged outside the first side through hole surface and the second side through hole surface. A first distance between the first side plug surface and the first side through hole surface in a transverse direction is different from a second distance between the second side plug surface and the second side through hole surface in the transverse direction.

According to yet another aspect of the present invention, a method for fabricating a semiconductor structure is provided, which includes the following steps. An opening is formed in a dielectric layer. Forming a tungsten plug in the opening. Forming a dielectric film on the tungsten plug. Forming a hole in the dielectric film. The hole is smaller than the opening and is not aligned with a center line of the opening. Forming a through hole device in the hole. The through hole element is electrically connected to the tungsten plug.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 illustrates a vertical cross-sectional view of a conductive structure of a semiconductor structure according to one embodiment.

Fig. 2 shows a longitudinal cross-sectional view of a memory device of a semiconductor structure according to an embodiment.

FIG. 3 is a longitudinal cross-sectional view of a memory device having a semiconductor structure according to another embodiment.

Fig. 4A to 4E illustrate a method of fabricating a semiconductor structure according to an embodiment.

FIG. 5 illustrates a method of fabricating a semiconductor structure according to one embodiment.

Fig. 6A-6F illustrate a method of fabricating a semiconductor structure according to one embodiment.

FIG. 7 illustrates a method of fabricating a semiconductor structure according to one embodiment.

FIG. 8 is a cross-sectional view of a semiconductor structure of a comparative example.

FIG. 9 is a cross-sectional view of a semiconductor structure of a comparative example

[ notation ] to show

110: conductive structure

230: plug element

230U: upper plug surface

236: barrier layer

236M: first side plug surface

236N: second side plug surface

240: tungsten plug

240K: inner plug surface

240M: first side plug surface

240N: second side plug surface

240U: upper plug surface

240W: plug size

241: gap

350: through-hole element

350U: upper through hole surface

350W: size of

360: barrier film

360B: lower via surface

360M: first side through hole surface

360N: second side through hole surface

360W: size of through hole

370: conducting hole

480,580,680: memory device

482,582: layer of memory material

482W: size of

484: upper electrode

486: dielectric film

486K: inner dielectric surface

486U: upper dielectric surface

487: gap

488: dielectric layer

488U: upper dielectric surface

489: opening holes

491: hole(s)

492: layer of conductive material

582U: upper storage surface

582W: size of

590: interfacial layer

693: dielectric film

694: notch (S)

695: masking layer

696: dielectric film

696U: upper dielectric surface

697: hole(s)

C: center line

D1: transverse direction

D2: longitudinal direction

MW: first interval

NW: second pitch

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

Some examples are described below. It should be noted that the present invention is not intended to show all possible embodiments, and that other embodiments not set forth herein may also be applicable. Moreover, the dimensional proportions shown in the drawings are not to scale with actual products. Accordingly, the description and drawings are only for the purpose of illustrating embodiments and are not to be construed as limiting the scope of the invention. Moreover, the descriptions of embodiments, such as local structures, process steps, material applications, etc., are provided for illustrative purposes only and are not intended to limit the scope of the present disclosure. The details of the steps and structures of the embodiments may be varied and modified as required by the actual implementation of the process without departing from the spirit and scope of the invention. The following description will be given with the same/similar reference numerals as used for the same/similar elements.

FIG. 1 illustrates a vertical cross-sectional view of a conductive structure 110 of a semiconductor structure according to one embodiment. The conductive structure 110 includes a plug (plug) element 230 and a via (via) element 350.

The plug element 230 may include a barrier layer 236 and a tungsten plug 240. Tungsten plug 240 is on barrier layer 236. In one embodiment, the tungsten plug 240 may include an inner plug surface 240K, the inner plug surface 240K defining a gap (seam/void) 241.

The via member 350 is electrically connected to the plug member 230. The via element 350 may include a barrier film 360 and a via 370. The via 370 is on the barrier film 360. The lower via surface 360B of the barrier film 360 of the via element 350 may be in electrical contact only on the upper plug surface of the plug element 230. For example, the lower via surface 360B of the barrier film 360 may be in electrical contact only on the upper plug surface 240U of the tungsten plug 240.

The barrier layer 236 includes opposing first and second side plug surfaces 236M, 236N. The first side plug surface 236M and the second side plug surface 236N are outer plug surfaces of the plug element 230. The tungsten plug 240 includes opposing first and second side plug surfaces 240M and 240N. The first side plug surface 240M and the second side plug surface 240N are outer plug surfaces of the tungsten plug 240.

The barrier film 360 includes opposing first and second side via surfaces 360M and 360N. The first side via surface 360M and the second side via surface 360N are outer side via surfaces of the via element 350. The first side plug surfaces 236M, 240M are on the same side of the conductive structure 110 as the first side via surface 360M, and the second side plug surfaces 236N, 240N are on the same side of the conductive structure 110 as the second side via surface 360N. The first side plug surfaces 236M, 240M and the second side plug surfaces 236N, 240N are outside the first side via surface 360M and the second side via surface 360N, respectively.

The plug element 230 has a plug size in the transverse direction D1. The via element 350 has a via dimension in the transverse direction D1. The plug size is larger than the via size. For example, the tungsten plug 240 may define a plug dimension 240W between the first side plug surface 240M and the second side plug surface 240N of 100nm to 400nm, such as 300 nm. The via dimension 360W defined by the via element 350 between the first side via surface 360M and the second side via surface 360N of the barrier film 360 may be 50nm to 200nm, e.g., 100 nm.

In an embodiment, the through-hole element 350 is asymmetrically configured with respect to a centerline C extending in the longitudinal direction D2 of the plug element 230. Therefore, the problem that the through-hole member 350 collapses or the upper through-hole surface 350U is uneven due to the through-hole member 350 corresponding to the slit 241 in the plug member 230 can be avoided. The via element 350 can have the structural features desired to be complete and flat with the upper via surface 350U. Thereby ensuring the electrical connection between the conductive structure 110 and the devices formed thereon, and improving the yield and operation efficiency of the product. The via elements 350 are not aligned with the center line C. The via element 350 is offset from the centerline C. The centerline C does not pass through the via member 350. In one embodiment, the centerline C may pass through the slit 241. The via elements 350 are not aligned with the slots 241. A first spacing MW of the first side plug surface 236M and the first side via surface 360M in the lateral direction D1 is different from a second spacing NW of the second side plug surface 236N and the second side via surface 360N in the lateral direction D1. In this disclosure, the lateral direction D1 (e.g., X direction) may be substantially perpendicular to the longitudinal direction D2 (e.g., Y direction).

Fig. 2 shows a vertical cross-sectional view of a memory device 480 having a semiconductor structure according to an embodiment. Memory device 480 may include conductive structure 110 serving as a bottom electrode, memory material layer 482, and top electrode 484. The memory material layer 482 is electrically connected between the conductive structure 110 (lower electrode) and the upper electrode 484. The via element 350 is electrically connected between the plug element 230 and the memory material layer 482. In this embodiment, the memory material layer 482 may be on the upper via surface 350U of the via element 350 and the upper dielectric surface 486U of the dielectric film 486. A dimension 482W of the memory material layer 482 in the transverse direction D1 is greater than a dimension 350W of the via element 350 in the transverse direction D1. An upper electrode 484 may be on the memory material layer 482.

Memory device 480 may be a Phase Change Memory (PCM) device. In one embodiment, memory material layer 482 comprises a phase change memory material, which may include GeSbTe (GST), and the like.

The barrier layer 236 may be in the dielectric layer 488. The dielectric film 486 may extend from the inner plug surface 240K of the tungsten plug 240 to the upper plug surface 230U of the plug element 230 and the upper dielectric surface 488U of the dielectric layer 488. Dielectric film 486 may define a gap 487. The slit 487 is in the tungsten plug 240.

Figure 3 shows a vertical cross-sectional view of a memory device 580 of a semiconductor structure according to another embodiment. The differences between memory device 580 of figure 3 and memory device 480 of figure 2 are explained as follows. The memory device 580 may include a layer of memory material 582 and an interface layer 590. A layer 582 of memory material is on the upper via surface 350U of the via element 350. The interface layer 590 is on the upper storage surface 582U of the layer 582 of storage material and the upper dielectric surface 486U of the dielectric film 486. The upper electrode 484 is on the interface layer 590. The memory material layer 582 is electrically connected between the conductive structure 110 (lower electrode) and the upper electrode 484. The via element 350 is electrically connected between the plug element 230 and the memory material layer 582.

A dimension 582W of the memory material layer 582 in the lateral direction D1 may be equal to a dimension 350W of the via element 350 in the lateral direction D1. For example, the area of the memory material layer 582 may be equal to the area of the via element 350. Alternatively, the area of the memory material layer 582 may be equal to the area of the via hole 370. In one embodiment, memory device 580 may be a resistive-random-access memory (ReRAM) device. The memory material layer 582 includes a programmable resistive memory material, such as a metal oxide, e.g., TiON, WO_x、HfO_x、TaON、TiO_x、TaO_x、SiO_xAnd the like.

Fig. 4A to 4E illustrate a method of fabricating a semiconductor structure according to an embodiment.

Referring to fig. 4A, a dielectric layer 488 is provided. The material of the dielectric layer 488 can include SiO₂、SiN、SiON、Al₂O₃And the like. An opening 489 is formed in dielectric layer 488. The aperture 489 can have a centerline C. For example, the distances from the centerline C to the opposing inner sidewalls of the opening 489 are substantially the same. The barrier layer 236 may be formed in the opening 489. Barrier layer 236 may comprise a metal barrier material, including, for example, TiN, Ta, Co, Ti, TaN, Si, Mn, etc. Tungsten plug 240 may be formed on barrier layer 236 within opening 489. In one embodiment, the barrier layer 236 and the conductive material layer are deposited in the opening 489 and on the upper surface 488U of the dielectric layer 488. Then, portions of the barrier layer 236 and the layer of conductive material on the upper dielectric surface 488U of the dielectric layer 488 may be removed, leaving portions of the barrier layer 236 and the layer of conductive material within the openings 489, thereby forming the plug elements 230. The portion of the conductive material layer within the opening 489 is the conductive plug. This removal may be performed by chemical mechanical polishing or other suitable etching. In one embodiment, the conductive material layer is tungsten, and the conductive plug is a tungsten plug 240. In one embodiment, the tungsten plug 240 does not completely fill the opening 489, and the tungsten plug 240 has an inner plug surface 240K defining a gap 241. The centerline C may pass through the slit 241. In another embodiment, the tungsten plug 240 may completely fill the opening 489, and there is no gap (not shown) in the tungsten plug 240.

Referring to fig. 4B, a dielectric film 486 may be formed on the inner plug surface 240K of the tungsten plug 240 exposed by the gap 241 and extending to the upper plug surface 230U of the plug element 230 and the upper dielectric surface 488U of the dielectric layer 488. In one embodiment, the dielectric film 486 does not completely fill the gap 241, and the dielectric film 486 has an inner dielectric surface 486K defining a gap 487. The centerline C may pass through the slit 487. In another embodiment, the dielectric film 486 may completely fill the gap 241, and there is no gap (not shown) in the dielectric film 486. The dielectric film 486 can have a thickness of 200 to 2000 angstroms, such as 1000 angstroms. Dielectric film 486 material may comprise SiO₂、SiN、SiON、Al₂O₃And the like.

Referring to fig. 4C, a hole 491 may be formed in the dielectric film 486 by, for example, photolithography. The holes 491 are smaller than the apertures 489 and are not aligned with the centerline C. The centerline C does not pass through the hole 491. The bottom of the hole 491 may expose only the upper plug surface 230U of the plug member 230. For example, the bottom of the hole 491 may only expose the upper plug surface 240U of the tungsten plug 240.

Referring to fig. 4D, a barrier film 360 may be formed on the upper plug surface 230U (upper plug surface 240U) of the plug element 230 (e.g., tungsten plug 240) exposed in the hole 491 and the side dielectric surfaces of the dielectric film 486, and on the upper dielectric surface 486U of the dielectric film 486. The barrier film 360 may comprise a metal barrier material, including, for example, TiN, Ta, Co, Ti, TaN, Si, Mn, etc. A layer 492 of conductive material may be formed on the barrier film 360. The conductive material layer 492 may include a metal, including, for example, TiN, Ti, Ta, TaN, W, Si, Cu, etc.

Referring to fig. 4E, the portions of the barrier film 360 and the conductive material layer 492 on the upper dielectric surface 486U of the dielectric film 486 are removed, and portions of the barrier film 360 and the conductive material layer 492 in the holes 491 are left, thereby forming the via 350. The portion of the conductive material layer 492 in the hole 491 is a via 370. This removal may be performed by chemical mechanical polishing or other suitable etching.

Next, referring to fig. 2, a memory material layer 482 is formed overlying the via 350 and the dielectric film 486, and an upper electrode 484 is formed overlying the memory material layer 482, and then the memory material layer 482 and the upper electrode 484 are patterned by photolithography. As such, a memory device 480 as shown in FIG. 2 may be formed. The material of the upper electrode 484 may include W, TiN, TaN, Ti, Ta, Hf, Pt, Ru, Ir, Cu, and the like, which are suitable conductive materials.

In another embodiment, the steps shown in FIG. 5 may be performed after the steps described with reference to FIG. 4E. Referring to fig. 5, a memory material layer 582 may be formed on the upper via surface 350U of the via element 350. In one embodiment, memory material layer 582 is a metal oxide layer formed by oxidation from upper via surface 350U of via element 350, including, for example, TiON, WO_x、HfO_x、TaON、TiO_x、TaO_x、SiO_xAnd the like.The oxidation treatment may include using oxygen (O)₂) Or ozone (O)₃) But not limited to, an oxidation process or a plasma process.

Then, referring to fig. 3, an interface layer 590 is formed overlying the via 350 and the dielectric film 486, and an upper electrode 484 is formed overlying the interface layer 590, and the interface layer 590 and the upper electrode 484 are patterned by photolithography. As such, memory device 580 as shown in fig. 3 may be formed. The material of the interface layer 590 may include Ti, Ta, TiN, TaN, Si, etc.

Fig. 6A-6F illustrate a method of fabricating a semiconductor structure according to one embodiment.

In one embodiment, the steps shown in FIG. 6A may be performed after the steps described with reference to FIG. 4C. Referring to fig. 6A, a dielectric film 693 is formed in the holes 491 of the dielectric film 486 and extends to the upper dielectric surface 486U of the dielectric film 486. The dielectric film 693 defines recesses 694 corresponding to the holes 491. Dielectric film 696 includes dielectric film 486 and dielectric film 693. The dielectric film 693 can have a thickness of 500 angstroms to 2500 angstroms, such as 1500 angstroms.

Referring to fig. 6B, a mask layer 695 can be formed on the dielectric film 693. In one embodiment, the material of the mask layer 695 may include a metal barrier material, such as, but not limited to, TiN, TaN, Ti, Ta, Si, etc., and other suitable mask materials may be used. The mask layer 695 can be 10 angstroms to 100 angstroms thick, such as 25 angstroms thick.

Referring to fig. 6C, the portion of the mask layer 695 on the upper dielectric surface of the dielectric film 693 can be removed, for example, by anisotropic etching or other suitable etching methods, while leaving portions on the side dielectric surfaces of the dielectric film 693.

Referring to fig. 6D, an etching step is performed using the mask layer 695 as an etching mask to remove the recess 694 to expose the dielectric film 693 of the underlying dielectric film 696, thereby forming a hole 697. In one embodiment, the mask layer 695 can be removed after the holes 697 are formed. In another embodiment, the mask layer 695 may not be removed.

Referring to fig. 6E, a via 350 including a barrier film 360 and a via 370 is formed in the hole 697.

Referring to fig. 6F, a memory material layer 482 is formed over the via 350 and the dielectric film 696. An upper electrode 484 is formed on the memory material layer 482.

In this embodiment, the holes 697 formed by the method described in fig. 6A-6D may be smaller than the holes 491 shown in fig. 4C. Accordingly, dimension 350W of via element 350 of memory device 680 of fig. 6F may be less than dimension 350W of via element 350 of fig. 2.

Referring to fig. 6F, in an embodiment, the tungsten plug 240 may have a plug dimension 240W defined between the first side plug surface 240M and the second side plug surface 240N of 100nm to 400nm, for example, 300 nm. The via dimension 360W defined by the via element 350 between the first side via surface 360M and the second side via surface 360N of the barrier film 360 may be 10nm to 50nm, for example 30 nm. But the invention is not limited thereto. For example, the value of the plug dimension 240W divided by the via dimension 360W may be greater than 4.

In another embodiment, the steps shown in FIG. 7 may be performed after the steps described with reference to FIG. 6E. Referring to fig. 7, a memory material layer 582 may be formed on the upper via surface 350U of the via element 350. Then, an interface layer 590 is formed on the upper storage surface 582U of the storage material layer 582 and the upper dielectric surface 696U of the dielectric film 696. The upper electrode 484 is formed on the interface layer 590.

Fig. 8 and 9 are cross-sectional views of a semiconductor structure of a comparative example, which is different from the above-mentioned embodiment in that a center line C passes through a via element 350. As can be seen from fig. 8, the difference may cause the via 370 of the via 350 to fill the gap 487 to cause collapse or the upper via surface 350U to be uneven, which may be caused by the compressive force applied to the conductive material layer 492 during the cmp step as described with reference to fig. 4D and 4E, for example. In fig. 9, via elements 350 having smaller dimensions may electrically isolate tungsten plug 240 by dielectric film 486, and via elements 350 and plug elements 230 are electrically disconnected from each other. This can lead to problems with electrical defects in the devices formed on the conductive structure.

In the embodiment, the through-hole component 350 is asymmetrically configured with respect to the center line C of the plug component 230, so that the problem that the through-hole component 350 collapses or the upper through-hole surface 350U is not flat due to the gap between the through-hole component 350 and the plug component 230 can be avoided. The via element 350 can have the structural features desired to be complete and flat with the upper via surface 350U. Thereby ensuring the electrical connection between the conductive structure 110 and the devices formed thereon, and improving the yield and operation efficiency of the product.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.