阅读说明：本技术 一种多中介层互联的集成电路 (Integrated circuit with multiple interconnected intermediate layers ) 是由 陶军磊 赵南 张晓东 王晨 于 2019-01-18 设计创作，主要内容包括：一种多中介层互联的集成电路,涉及电子技术领域,用于提高不同硅中介层互联时,传输的信号质量。所述多中介层互联的集成电路包括：采用低损耗连接器(304)将第一半导体中介层(301)和第二半导体中介层(302)中的互联电路形成电连接以实现不同半导体中介层之间的互联,由于低损耗连接器(304)的损耗较小,从而使得不同半导体中介层上设置的裸片之间的信号传输路径上的传输损耗较小,进而提高了该传输路径上的信号质量。(An integrated circuit with interconnection of multiple interposers relates to the technical field of electronics, and is used for improving the quality of signals transmitted when different silicon interposers are interconnected. The multi-interposer interconnected integrated circuit comprises: the interconnection circuits in the first semiconductor interposer (301) and the second semiconductor interposer (302) are electrically connected by adopting the low-loss connector (304) to realize interconnection between different semiconductor interposers, and because the loss of the low-loss connector (304) is smaller, the transmission loss on a signal transmission path between dies arranged on different semiconductor interposers is smaller, and the signal quality on the transmission path is further improved.)

A multi-interposer interconnected integrated circuit, the integrated circuit comprising: a first semiconductor interposer, a second semiconductor interposer, a substrate, and a low-loss connector; the first semiconductor interposer, the second semiconductor interposer and the low-loss connector are disposed on a same side of the substrate; wherein the content of the first and second substances,

at least one first die is arranged on one side of the first semiconductor interposer, which is opposite to the substrate, and first interconnection circuits are arranged in the first semiconductor interposer;

at least one second bare chip is arranged on one side, back to the substrate, of the second semiconductor interposer, and second interconnection circuits are arranged in the second semiconductor interposer;

one of the at least one first die is electrically connected with one of the at least one second die through the first interconnect circuitry, the low-loss connector, and the second interconnect circuitry.

The integrated circuit of claim 1, wherein the low-loss connector comprises a substrate and an interconnect layer disposed on one side of the substrate, the at least one first die and the at least one second die being connected in particular by the interconnect layer in the low-loss connector.

The integrated circuit of claim 2, wherein a trace width of the interconnect layer matches a trace width of the first interconnect circuit and the second interconnect circuit.

The integrated circuit of claim 3, wherein the lowest line width/pitch of the low loss connector is equal to 0.4um/0.4 um.

The integrated circuit of any of claims 2 to 4, wherein the substrate is a plastic molding material.

The integrated circuit of claim 5, wherein the structure of the low loss connector is a hybrid of an organic dielectric and a redistribution layer.

The integrated circuit of any of claims 2 to 4, wherein the substrate is a silicon substrate.

The integrated circuit of any of claims 2 to 4, wherein the substrate is a glass substrate.

The integrated circuit of any of claims 1 to 8, wherein the at least one first die is a plurality of first dies and the at least one second die is a plurality of second dies, the first semiconductor interposer is further provided with the first interconnect circuitry, the second semiconductor interposer is further provided with the second interconnect circuitry, the first interconnect circuitry is further configured to form electrical connections between each first die, and the second interconnect circuitry is further configured to form electrical connections between each second die.

The integrated circuit of claim 9, wherein the at least one first die and the at least one second die each comprise an Application Specific Integrated Circuit (ASIC) and a High Bandwidth Memory (HBM).

The integrated circuit of any of claims 1-10, wherein the first and second semiconductor interposers are silicon interposers; or the structure of the first semiconductor interposer and the second semiconductor interposer is a mixed structure of an organic medium and a redistribution layer.

A terminal device comprising a printed circuit board, PCB, and a multi-interposer interconnect integrated circuit as claimed in any one of claims 1-11 disposed on one side of the PCB and in electrical connection with the PCB.