阅读说明：本技术 半导体装置以及相关方法与系统 (Semiconductor device and related method and system ) 是由 彭士玮 林威呈 曾健庭 于 2020-09-18 设计创作，主要内容包括：本发明实施例涉及半导体装置以及相关方法与系统。一种半导体装置包含衬底、晶体管层、电介质层及电网结构。所述晶体管层形成于所述衬底的第一侧上且包含用于形成晶体管的多个主动区域。所述电介质层形成于所述晶体管层上且包含安置于第一主动区域上且朝向第二主动区域延伸的导电条用于信号连接。所述电网结构形成于与所述第一侧对置的所述衬底的第二侧上且经布置以将电源导引到所述晶体管层。(Embodiments of the invention relate to semiconductor devices and related methods and systems. A semiconductor device includes a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is formed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is formed on the transistor layer and includes conductive strips disposed on the first active region and extending toward the second active region for signal connection. The power grid structure is formed on a second side of the substrate opposite the first side and is arranged to direct a power source to the transistor layer.)

1. A semiconductor device, comprising:

a substrate;

a transistor layer on a first side of the substrate, the transistor layer including a plurality of active regions for forming transistors;

a dielectric layer on the transistor layer, the dielectric layer including conductive strips disposed on the first active region and extending toward the second active region for signal connection; and

a power grid structure on a second side of the substrate opposite the first side, the power grid structure arranged to direct a power source to the transistor layer.

Technical Field

Embodiments of the invention relate to semiconductor devices and related methods and systems.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in IC generations where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (e.g., the number of interconnects per chip area) has generally increased, while the geometry (e.g., the smallest component or line that can be created using a process) has decreased. Due to this size reduction, the metal wiring inevitably has insufficient space.

Disclosure of Invention

According to an embodiment of the present invention, a semiconductor device includes: a substrate; a transistor layer on a first side of the substrate, the transistor layer including a plurality of active regions for forming transistors; a dielectric layer on the transistor layer, the dielectric layer including conductive strips disposed on the first active region and extending toward the second active region for signal connection; and a power grid structure on a second side of the substrate opposite the first side, the power grid structure arranged to direct a power source to the transistor layer.

According to an embodiment of the present invention, a method of manufacturing a semiconductor device includes: providing a substrate; forming a transistor layer on a first side of the substrate, the transistor layer including a plurality of active regions for forming transistors; forming a conductive strip extending towards the second active region on the first active region for signal connection; forming a dielectric layer covering the connecting strips on the transistor layer; and forming a power grid structure on a second side of the substrate opposite the first side, the power grid structure arranged to direct a power source to the transistor layer.

According to an embodiment of the invention, a system comprises: a storage device arranged to store program code; and a processor, when executed and loaded by the processor, the program code instructing the processor to: providing a substrate; forming a transistor layer on a first side of the substrate, wherein the transistor layer includes a plurality of active regions for forming terminals of transistors; forming a conductive strip extending towards the second active region on the first active region for signal connection; forming a dielectric layer on the transistor layer to cover the conductive strips; and forming a power grid structure on a second side of the substrate opposite the first side, wherein the power grid structure is arranged to direct a power source to the transistor layer.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1C are diagrams illustrating a cell according to an embodiment of the invention.

Fig. 2A and 2B are diagrams illustrating isolation layers according to embodiments of the invention.

Fig. 3A and 3B are diagrams illustrating a unit according to a first embodiment of the present invention.

Fig. 4 is a drawing illustrating a unit according to a second embodiment of the present invention.

Fig. 5A and 5B are diagrams illustrating a unit according to a third embodiment of the present invention.

Fig. 6A and 6B are diagrams illustrating a unit according to a fourth embodiment of the present invention.

Fig. 7A and 7B are diagrams illustrating two units according to a fifth embodiment of the present invention.

FIG. 7C is a diagram illustrating cells having different cell heights, according to an embodiment of the invention.

Fig. 8A and 8B are diagrams illustrating two units according to a sixth embodiment of the present invention.

Fig. 9A and 9B are diagrams illustrating two units according to a seventh embodiment of the present invention.

Fig. 10 is a diagram illustrating routing of conductive strips according to an embodiment of the invention.

Fig. 11 is a diagram illustrating routing of conductive strips according to another embodiment of the invention.

Fig. 12 is a diagram illustrating routing of conductive strips according to yet another embodiment of the invention.

Fig. 13A and 13B are diagrams illustrating connections between conductive strips and gate regions according to an embodiment of the invention.

Fig. 14 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 15 is a diagram illustrating a system according to an embodiment of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such are merely examples and are not intended to be limiting. For example, in the following description, forming a first member over or on a second member may include embodiments in which the first and second members are formed in direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe an element or component's relationship to another element(s) or component(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean, as considered by one of ordinary skill in the art. Except in the operating/working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages disclosed herein (e.g., of materials, durations, temperatures, operating conditions, quantitative ratios, and the like) are to be understood as modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary as desired. Finally, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from an endpoint to another endpoint, or between two endpoints. Unless otherwise indicated, all ranges disclosed herein are inclusive of the endpoints.

As technology advances, the need to create smaller Integrated Circuit (IC) devices increases. Strategies that have been employed include the use of multiple gate transistors, otherwise known as finfets. Typical FinFET devices are fabricated using silicon fins that protrude from a semiconductor substrate. The channel of the device is formed in the fin and the gate is provided over (e.g., surrounding) the fin and in contact with, for example, the top and sidewalls of the fin. The benefits of gate-around channels (e.g., fins) are: this configuration allows control of the channels from three sides. In addition to FinFET structures, gate-all-around (GAA) structures are also widely employed to create smaller ICs.

Another strategy that has been adopted involves the use of back side power rails. A typical semiconductor device using backside electrical rails has one or more conductive rails, which may be located below the semiconductor substrate and electrically connected to the source, gate and/or drain regions of the semiconductor device.

Semiconductor devices utilizing the above-described FinFET technology, GAA technology, and back side rail technology have been successfully reduced in size. However, due to this size reduction, metal wiring for signal connection thereof is inevitably insufficient in source. Accordingly, the present disclosure addresses the problems by providing a semiconductor device, a method of manufacturing a semiconductor device, and a system including a semiconductor device.

Fig. 1A-1C are diagrams illustrating a cell 1 according to an embodiment of the invention. Fig. 1A is a schematic top view. FIG. 1B is a cross-sectional view taken along line A-A' in FIG. 1A. FIG. 1C is a cross-sectional view taken along line B-B' in FIG. 1. In this embodiment, cell 1 is part of a semiconductor device utilizing FinFET technology and back side rail technology as described above. However, this is not a limitation of the present disclosure. In other embodiments, cell 1 is part of a semiconductor device utilizing the GAA technology and the back side rail technology described above.

The cell 1 comprises a substrate 10. In an embodiment, the substrate 10 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 10 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 10 may optionally include a silicon-on-insulator (SOI) structure.

Furthermore, the cell 1 further comprises a transistor layer 20 on the first side of the substrate 10. The transistor layer 20 includes active regions in which one or more transistors are formed. For example, transistor layer 20 includes gate regions 111 and 112 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 121, 122, and 123 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

In addition, the cell 1 further comprises a dielectric layer 30 on the transistor layer 20. Dielectric layer 30 comprises conductive segments formed over active areas. The conductive segments on the source/drain regions are referred to herein as MD. For example, dielectric layer 30 includes MD 131 on source/drain region 121, MD132 on source/drain region 122, and MD 133 on source/drain region 123.

Furthermore, cell 1 further comprises a plurality of metal strips in first metal layer 40 (which is referred to herein as M0 layer 40). For example, cell 1 includes a metal strip 151 over MD 131. To transmit signals from the MD to the metal strip, a contact path is provided between the dielectric layer 30 and the M0 layer 40 in cell 1. For example, cell 1 includes contact vias 141 connected between MD 131 and metal strip 151.

The unit 1 further comprises a grid structure 50 on a second side of the substrate 10. The grid structure 50 is arranged to direct power to the transistor layer 20. In particular, the grid structure 50 directs power to the source/drain regions 122 via contact vias 161 that penetrate the substrate 10.

As shown in fig. 1B, since the grid structure 50 is formed on the backside of the substrate 10, power is directed to the source/drain regions 122 from the backside of the substrate 10 rather than the top of the source/drain regions 122. Thus, the source of metal wiring for signal connection over the source/drain regions 122 can be released. For example, MD132 above source/drain regions 122 may be released for signal connection.

To utilize MD132 for signal connection, an isolation layer is needed to isolate MD132 from source/drain regions 122. Reference is made to fig. 2A, which is a diagram illustrating a cell 2 according to an embodiment of the invention. Cell 2 is similar to cell 1 in fig. 1A-1C, except that cell 2 further includes isolation layer 172 between source/drain regions 122 and MD 132. MD132 may be used for signal connections due to isolation layer 172. For example, MD132 may further extend in the y-direction for signal connections.

However, the location of the isolation layer 172 is not a limitation of the present disclosure, as long as the isolation layer 172 can isolate the MD132 and the source/drain regions 122 for signal connection.

Reference is made to fig. 2B, which is a diagram illustrating a cell 2' according to an embodiment of the invention. The cell 2' is similar to the cell 2 except for the location of the spacer layer. In particular, cell 2 'includes isolation layer 172' located between MDs 132 and dividing MD132 into upper MD132_1 and lower MD132_ 2. The upper MD132_1 may thus be used for signal connection. For example, the upper MD132_1 may further extend in the y-direction for signal connection.

In view of the above embodiments, the semiconductor device may use the MD for signal connection and thus provide additional resources for signal connection. The following paragraphs describe exemplary embodiments utilizing MD for signal connection.

Fig. 3A and 3B are diagrams illustrating a unit 3 according to a first embodiment of the present invention. Fig. 3A is a schematic top view, and fig. 3B is a cross-sectional view taken along line C-C' in fig. 3A.

The cell 3 comprises a substrate 11. In an embodiment, the substrate 11 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 11 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 11 may optionally include an SOI structure.

Furthermore, the cell 3 further comprises a transistor layer 12 on the first side of the substrate 11. The transistor layer 12 includes active regions in which one or more transistors are formed. For example, transistor layer 12 includes gate regions 211 and 212 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 221 and 222 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

In addition, the cell 3 further comprises a dielectric layer 13 on the transistor layer 12. The dielectric layer 13 includes conductive strips formed on the active area as the MD. For example, dielectric layer 13 includes conductive strips 231 formed on source/drain regions 221 and extending toward source/drain regions 222. More specifically, conductive strip 231 is connected between source/drain regions 221 and 222 for signal connection.

In the embodiment of fig. 3A and 3B, conductive strips 231 are arranged to carry signals between source/drain regions 221 and 222. Therefore, there is no isolation layer between the conductive strip 231 and the source/drain region 221 (or 222). With such a configuration, conductive strip 231 bridges between source/drain regions 221 and 222.

In the embodiment of fig. 3A and 3B, conductive strips 231 are configured as straight strips. However, this is not a limitation of the present disclosure. Fig. 4 is a drawing illustrating a unit 4 according to a second embodiment of the present invention. The cell 4 comprises a substrate 21. In an embodiment, the substrate 21 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 21 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 21 may optionally include an SOI structure.

Furthermore, the cell 4 further comprises a transistor layer 22 on the first side of the substrate 21. The transistor layer 22 includes active regions in which one or more transistors are formed. For example, transistor layer 22 includes a gate region (not shown in fig. 4) for depositing polysilicon gate material to form a gate terminal of the transistor, and source/drain regions 321 and 322 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistor.

In addition, the cell 4 further comprises a dielectric layer 23 on the transistor layer 22. The dielectric layer 23 includes conductive strips formed on the active area as the MD described above. For example, dielectric layer 23 includes conductive strips 331 formed on source/drain regions 321 and extending toward source/drain regions 322. More specifically, conductive strip 231 is connected between source/drain regions 321 and 322 for signal connection. In this embodiment, conductive strips 331 are routed through two corners between source/drain regions 321 and 322, which provides greater flexibility in signal connection.

Fig. 5A and 5B are diagrams illustrating a cell 5 according to a third embodiment of the present invention. Fig. 5A is a schematic top view, and fig. 5B is a cross-sectional view taken along line D-D' in fig. 5A.

The cell 5 comprises a substrate 31. In an embodiment, the substrate 31 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 31 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 31 may optionally include an SOI structure.

Furthermore, the cell 5 further comprises a transistor layer 32 on the first side of the substrate 31. Transistor layer 32 includes active regions in which one or more transistors are formed. For example, transistor layer 32 includes gate regions 411 and 412 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 421 and 422 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

In addition, the cell 5 further comprises a dielectric layer 33 on the transistor layer 32. The dielectric layer 33 includes conductive strips formed on the active area as the MD. For example, dielectric layer 33 includes conductive strips 431 formed on source/drain regions 422 and extending toward source/drain regions 421. Furthermore, the cell 5 further comprises a first metal layer 34 on the dielectric layer 33. The first metal layer 34 comprises metal strips 451 extending in the x-direction. More specifically, one end of conductive strip 431 is connected to metal strip 451 through contact via 441, and the other end of conductive strip 431 is connected to source/drain region 422.

In the embodiment of fig. 5A and 5B, conductive strips 431 are arranged to transfer signals between source/drain regions 422 and metal strips 451. Thus, isolation layer 461 is present between conductive strip 431 and source/drain region 421 to isolate conductive strip 431 from source/drain region 421.

Fig. 6A and 6B are diagrams illustrating a unit 6 according to a fourth embodiment of the present invention. Fig. 6A is a schematic top view, and fig. 6B is a cross-sectional view taken along line E-E' in fig. 6A.

The cell 6 comprises a substrate 41. In an embodiment, substrate 41 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 41 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 41 may optionally include an SOI structure.

Furthermore, the cell 6 further comprises a transistor layer 42 on the first side of the substrate 41. Transistor layer 42 includes active regions in which one or more transistors are formed. For example, transistor layer 42 includes gate regions 511 and 512 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 521 and 522 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

In addition, the cell 6 further comprises a dielectric layer 43 on the transistor layer 42. The dielectric layer 43 includes conductive strips formed on the active area as the MD described above. For example, the dielectric layer 43 contains conductive strips 531. Furthermore, the cell 6 further comprises a first metal layer 44 on the dielectric layer 43. The first metal layer 44 includes metal strips 551 and 552 extending in the x-direction. More specifically, the ends of conductive strips 531 are connected to metal strip 551 via contact vias 541, and the other ends of conductive strips 531 are connected to metal strip 552 via contact vias 542.

In the embodiment of fig. 6A and 6B, conductive strips 531 are arranged to transfer signals between metal strips 551 and 552. Thus, a separation layer 561 is present between the conductive strip 531 and the source/drain region 521 to separate the conductive strip 531 from the source/drain region 521. An isolation layer 562 is present between the conductive strip 531 and the source/drain regions 522 to isolate the conductive strip 531 from the source/drain regions 522.

Fig. 7A and 7B are diagrams illustrating a cell 7 and a cell 8 according to a fifth embodiment of the present invention. Fig. 7A is a schematic top view, and fig. 7B is a cross-sectional view taken along line F-F' in fig. 7A. Cells 7 and 8 are arranged in the y-direction and integrated in the semiconductor device.

Cell 7 and cell 8 share substrate 51. In an embodiment, the substrate 51 comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 51 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 51 may optionally include an SOI structure.

Furthermore, the cell 7 comprises a transistor layer 52 on a first side of the substrate 51. Transistor layer 52 includes active regions in which one or more transistors are formed. For example, transistor layer 52 includes gate regions 611 and 612 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 621 and 622 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

Cell 8 includes a transistor layer 62 on a first side of substrate 51, where transistor layer 62 and transistor layer 52 are coplanar. Transistor layer 62 includes active regions in which one or more transistors are formed. For example, transistor layer 62 includes gate regions 711 and 712 for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 721 and 722 include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

Additionally, cell 7 further includes a dielectric layer 53 on transistor layer 52, and cell 8 further includes a dielectric layer 63 on transistor layer 62. Dielectric layer 53 and dielectric layer 63 are coplanar. Each of the dielectric layers 53 and 63 includes conductive strips formed on the active areas as MD described above. In this embodiment, conductive strip 631 extends in the y-direction across the boundary BD between cells 7 and 8. In particular, conductive strip 631 is connected between source/drain region 621 and source/drain region 722 for signal connection.

In this embodiment, each of cells 7 and 8 includes two source/drain regions, i.e., the cell heights of cells 7 and 8 are equal. With this configuration, boundary BD is defined as the boundary between cells located in close proximity and having equal cell heights.

However, in other embodiments, the cell may include more source/drain regions for a particular function. Thus, the cell height may be longer. Referring to fig. 7C, cell height H70 of cell 70 is twice cell height H80 of cell 80 because cell 70 contains more source/drain regions than cell 80. With this arrangement, a boundary is defined as a boundary between cells that are located in close proximity and have different cell heights.

In the embodiment of fig. 7A and 7B, conductive strip 631 is arranged to transfer signals between source/drain region 621 and source/drain region 722. Therefore, an isolation layer 661 is disposed between the conductive strip 631 and the source/drain regions 622 to isolate the conductive strip 631 from the source/drain regions 622. In addition, an isolation layer 761 is present between the conductive strip 631 and the source/drain region 721 to isolate the conductive strip 631 from the source/drain region 721.

Fig. 8A and 8B are diagrams illustrating a cell 7 'and a cell 8' according to a sixth embodiment of the present invention. Fig. 8A is a schematic top view, and fig. 8B is a cross-sectional view taken along line G-G' in fig. 8A. Cell 7 'and cell 8' are arranged in the y-direction and integrated in the semiconductor device.

Cell 7' and cell 8' share substrate 51 '. In an embodiment, the substrate 51' comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 51' may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 51' may optionally comprise an SOI structure.

Furthermore, the cell 7' comprises a transistor layer 52' on a first side of the substrate 51 '. Transistor layer 52' includes active regions in which one or more transistors are formed. For example, transistor layer 52' includes gate regions 611' and 612' for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 621' and 622' include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

Cell 8' includes a transistor layer 62' on a first side of substrate 51', where transistor layer 62' and transistor layer 52' are coplanar. The transistor layer 62' includes active regions in which one or more transistors are formed. For example, transistor layer 62' includes gate regions 711' and 712' for depositing polysilicon gate material to form gate terminals of the transistors, and source/drain regions 721' and 722' include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

In addition, cell 7 'further includes a dielectric layer 53' on transistor layer 52', and cell 8' further includes a dielectric layer 63 'on transistor layer 62'. Dielectric layer 53 'and dielectric layer 63' are coplanar. Each of the dielectric layers 53 'and 63' includes conductive strips formed on the active areas as the MD described above. In this embodiment, conductive bar 631 'extends across the boundary BD' between cell 7 'and cell 8' in the y-direction.

Furthermore, cell 7 'includes a first metal layer 54' on dielectric layer 53', and cell 8' includes a first metal layer 64 'on dielectric layer 63', wherein first metal layer 54 'and first metal layer 64' are coplanar. Each of first metal layer 54 'and first metal layer 64' includes a metal strip extending in the x-direction. For example, the first metal layer 54 'includes metal strips 651' extending in the x-direction. Specifically, an end of conductive strip 631' is connected to metal strip 651' via contact via 641', and the other end of conductive strip 631' is connected to source/drain region 722 '.

In the embodiment of fig. 8A and 8B, the conductive strip 631' is arranged to transfer signals between the source/drain regions 722' and the metal strip 651 '. Therefore, an isolation layer 662' is present between the conductive strip 631' and the source/drain region 621' to isolate the conductive strip 631' from the source/drain region 621 '. In addition, an isolation layer 661' is disposed between the conductive strip 631' and the source/drain regions 622' to isolate the conductive strip 631' from the source/drain regions 622 '. In addition, an isolation layer 761' is present between the conductive strip 631' and the source/drain region 721' to isolate the conductive strip 631' from the source/drain region 721 '.

Fig. 9A and 9B are diagrams illustrating a unit 7 "and a unit 8" according to a seventh embodiment of the present invention. Fig. 9A is a schematic top view, and fig. 9B is a cross-sectional view taken along line H-H' in fig. 9A. Cell 7 "and cell 8" are arranged in the y-direction and integrated in the semiconductor device.

Cell 7 "and cell 8" share substrate 51 ". In an embodiment, the substrate 51 "comprises a silicon substrate. Other elemental semiconductors, such as germanium and diamond, may also be included. Alternatively, the substrate 51 "may comprise a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Further, the substrate 51 "may optionally include an SOI structure.

Furthermore, cell 7 "comprises a transistor layer 52" on a first side of substrate 51 ". Transistor layer 52' includes active regions in which one or more transistors are formed. For example, transistor layer 52 "includes gate regions 611" and 612 "used to deposit polysilicon gate material to form gate terminals of the transistors, and source/drain regions 621" and 622 "include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming source/drain terminals of the transistors.

Cell 8 "includes a transistor layer 62" on a first side of substrate 51 ", where transistor layer 62" and transistor layer 52 "are coplanar. Transistor layer 62 "includes active regions in which one or more transistors are formed. For example, transistor layer 62 "includes gate regions 711" and 712 "used to deposit polysilicon gate material to form the gate terminals of the transistors, and source/drain regions 721" and 722 "that include epitaxial silicon, epitaxial silicon germanium, and/or other epitaxial materials suitable for forming the source/drain terminals of the transistors.

In addition, cell 7 "further includes dielectric layer 53" on transistor layer 52 ", and cell 8" further includes dielectric layer 63 "on transistor layer 62". Dielectric layer 53 "and dielectric layer 63" are coplanar. Each of the dielectric layers 53 "and 63" includes conductive strips formed on the active areas as MD described above. In this embodiment, conductive strip 631 "extends across the boundary BD" between cell 7 "and cell 8" in the y-direction.

Furthermore, cell 7 "includes first metal layer 54" on dielectric layer 53 ", while cell 8" includes first metal layer 64 "on dielectric layer 63", wherein first metal layer 54 "and first metal layer 64" are coplanar. Each of first metal layer 54 "and first metal layer 64" includes a metal strip extending in the x-direction. For example, the first metal layer 54 "includes a metal strip 651" extending in the x-direction, while the first metal strip includes a metal strip 751 "extending in the x-direction. In particular, an end of conductive strip 631 "is connected to metal strip 651" via contact via 641 "and the other end of conductive strip 631" is connected to metal strip 751 "via contact via 741".

In the embodiment of fig. 9A and 9B, the conductive strip 631 "is arranged to transfer signals between the metal strip 651" and the metal strip 751 ". Thus, isolation layer 662 "is present between conductive strip 631" and source/drain region 621 "to isolate conductive strip 631" from source/drain region 621 ". Also, an isolation layer 661 "is present between conductive strip 631" and source/drain regions 622 "to isolate conductive strip 631" from source/drain regions 622 ". In addition, an isolation layer 761 "is present between conductive strip 631" and source/drain region 721 "to isolate conductive strip 631" from source/drain region 721 ". In addition, an isolation layer 762 "is present between conductive strip 631" and source/drain region 722 "to isolate conductive strip 631" from source/drain region 722 ".

In the above embodiments, the conductive strips extend across the boundary between two cells for signal connection. However, this is not a limitation of the present disclosure. In other embodiments, the conductive strips may extend across more than two cells.

Fig. 10 is a diagram illustrating routing of conductive strips 1001 in accordance with an embodiment of the present invention. As shown in fig. 10, conductive strip 1001 is routed through two corners and spans three cells, with conductive strip 1001 connected between two source/drain regions for signal connection. The embodiment of fig. 10 should be readily understood by one of ordinary skill in the art after reading the embodiments of fig. 4, 7A, and 7B.

Fig. 11 is a diagram illustrating routing of a conductive strip 1101 according to another embodiment of the present invention. As shown in fig. 11, conductive strip 1101 is routed through two corners and spans three cells, with an end of conductive strip 1101 connected to metal strip 1102 via contact via 1103 and the other end of conductive strip 1101 connected to the source/drain region for signal connection. The embodiment of fig. 11 should be readily understood by one of ordinary skill in the art after reading the embodiments of fig. 8A and 8B.

Fig. 12 is a diagram illustrating routing of a conductive strip 1201 according to yet another embodiment of the present invention. As shown in fig. 12, the conductive strip 1201 is routed through two corners and across three cells, with the end of the conductive strip 1201 connected to the metal strip 1202 via contact via 1203 and the other end of the conductive strip 1201 connected to the metal strip 1204 for signal connection via contact via 1205. The embodiment of fig. 12 should be readily understood by one of ordinary skill in the art after reading the embodiments of fig. 9A and 9B.

Fig. 13A and 13B are diagrams illustrating connections between conductive strips and gate regions according to an embodiment of the invention. As shown in fig. 13A, the conductive strips 1301 are connected to the gate regions 1302 by metal strips 1303 that are bridges. In particular, ends of metal strips 1303 are connected to conductive strips 1301 via contact vias 1304, and the other ends of metal strips 1303 are connected to gate regions 1302 via contact vias 1305.

As shown in fig. 13B, the conductive strips 1306 are connected to the gate regions 1307 by metal strips 1308 which act as bridges. In particular, ends of the metal strips 1308 are connected to the conductive strips 1306 via contact vias 1309, while the other ends of the metal strips 1308 are connected to the gate regions 1307 via contact vias 1310.

The embodiment of fig. 13A and 13B proposes a connection between the conductive strips and the gate region, which provides greater flexibility in circuit design.

Fig. 14 is a flow chart illustrating a method 1400 of fabricating a semiconductor device according to an embodiment of the invention. If the results are substantially the same, the operations in FIG. 14 need not be performed in the exact order. Method 1400 may be summarized as follows.

In operation 1401, a substrate is provided.

In operation 1402, a transistor layer is formed on a first side of a substrate, wherein the transistor layer includes a plurality of active regions for forming transistors.

In operation 1403, a conductive strip is formed on the first active region, where the conductive strip extends toward the second active region for signal connection.

In operation 1404, a dielectric layer is formed on the transistor layer covering the connection bars.

In operation 1405, a power grid structure is formed on a second side of the substrate opposite the first side, wherein the power grid structure is arranged to direct a power source to the transistor layer.

The method 1400 should be readily understood by one of ordinary skill in the art after reading the above-described embodiments. A detailed description of the method 1400 is omitted herein for the sake of brevity.

Fig. 15 is a diagram illustrating a system 1500 according to an embodiment of the invention. The system 1500 includes a storage device 1501 and a processor 1502. The storage device 1501 is arranged to store program code PROG. When loaded and executed by the processor 1502, the program code instructs the processor 1502 to perform the following operations: providing a substrate; forming a transistor layer on a first side of a substrate, wherein the transistor layer includes a plurality of active regions for forming terminals of transistors; forming a conductive strip extending towards the second active region on the first active region for signal connection; forming a dielectric layer covering the conductive strips on the transistor layer; and forming a grid structure on a second side of the substrate opposite the first side, wherein the grid structure is arranged to direct power to the transistor layer.

The operation of the system 1500 should be readily understood by one of ordinary skill in the art after reading the above-described embodiments. A detailed description of the system 1500 is omitted herein for the sake of brevity.

In some embodiments, a semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is disposed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is disposed on the transistor layer and includes conductive strips disposed on the first active region and extending toward the second active region for signal connection. The grid structure is disposed on a second side of the substrate opposite the first side and is arranged to direct a power source to the transistor layer.

In some embodiments, a method of manufacturing a semiconductor device is disclosed. The method comprises the following steps: providing a substrate; forming a transistor layer on a first side of the substrate, wherein the transistor layer includes a plurality of active regions for forming terminals of transistors; forming a conductive strip extending towards the second active region on the first active region for signal connection; forming a dielectric layer covering the connecting strips on the transistor layer; and forming a power grid structure on a second side of the substrate opposite the first side, wherein the power grid structure is arranged to direct a power source to the transistor layer.

In some embodiments, a system is disclosed. The system includes a storage device and a processor. The storage device is arranged to store program code PROG. When loaded and executed by the processor, the program code instructs the processor to: providing a substrate; forming a transistor layer on a first side of the substrate, wherein the transistor layer includes a plurality of active regions for forming terminals of transistors; forming a conductive strip extending towards the second active region on the first active region for signal connection; forming a dielectric layer on the transistor layer to cover the conductive strips; and forming a power grid structure on a second side of the substrate opposite the first side, wherein the power grid structure is arranged to direct a power source to the transistor layer.

Description of the symbols

1: unit

2: unit

2' unit

3: unit

4: unit

5: unit

6: unit

7: unit

7' unit

7' unit

8: unit

8' unit

8' unit

10 substrate

11 substrate

12 transistor layer

13 dielectric layer

20 transistor layer

21: substrate

22 transistor layer

23 dielectric layer

30 dielectric layer

31 substrate

32 transistor layer

33 dielectric layer

34 first metal layer

40 first metal layer/M0 layer

41 substrate

42 transistor layer

43 dielectric layer

44 first metal layer

50: electric network structure

51 substrate

51' substrate

51' substrate

52 transistor layer

52' transistor layer

52' transistor layer

Dielectric layer 53

Dielectric layer 53

Dielectric layer 53 ″

54' first metal layer

54 first metal layer

62 transistor layer

62' transistor layer

62' transistor layer

63 dielectric layer

63' dielectric layer

63' dielectric layer

64' first metal layer

64' first metal layer

70 unit

80 unit

111: gate region

112 gate region

121 source/drain region

122 source/drain regions

123 source/drain region

131:MD

132:MD

132_1: upper MD

132_2 lower MD

133:MD

141 contact vias

151 metal strip

161 contact vias

172 barrier layer

172' isolating layer

211 gate region

212 gate region

221 source/drain region

222 source/drain region

231 conductive strip

321 source/drain regions

322 source/drain region

331 conducting bar

411 gate region

412 gate region

421 source/drain region

422 source/drain region

431 conductive strip

441 contact via

451 metal strip

461 isolating layer

511 gate region

512 gate region

521 source/drain region

522 source/drain region

531 conducting bar

541 contact via

542 contact path

551 metal strip

552 metal strip

561 isolating layer

562 insulating layer

611 gate region

611' gate region

611' gate region

612 gate region

612' gate region

612' gate region

621 source/drain region

621' source/drain region

621' source/drain region

622 source/drain regions

622' source/drain region

622 ". Source/Drain region

631 conductive strip

631' conducting strip

631 conducting bar

641' contact via

641' contact via

651' metal strip

651 ″: metal strip

661 isolating layer

661' isolating layer

661 isolating layer

662' isolating layer

662 isolating layer

711 Gate region

711' gate region

711' gate region

712 gate region

712' gate region

712' gate region

721 source/drain region

721' source/drain regions

721 source/drain region

722 source/drain region

722' source/drain region

Source/drain regions 722 ″

741 contacting the via

751' metal strip

761 isolation layer

761' isolating layer

761 isolating layer

762 isolating layer

1001 conducting bar

1101 conducting strip

1102 metal strip

1103 contact via

1201 conducting bar

1202 metal strip

1203 contact vias

1204 metal strip

1205 contact path

1301: conducting bar

1302 a gate region

1303. metal strip

1304 contact vias

1305 contact vias

1306 conducting strip

1307 Gate region

1308 Metal strip

1309 contact vias

1310 contact vias

1400A method

1401 operation

1402 operation

1403 operation

1404 operation of

1405 operation

1500 System

1501 storage device

1502 processor

Boundary of BD

Boundary of BD

Boundary of BD

H70 cell height

H80 cell height

PROG program code