阅读说明：本技术 半导体元件及其制备方法 (Semiconductor element and method for manufacturing the same ) 是由 简荣兴 于 2020-10-29 设计创作，主要内容包括：本公开提供一种半导体元件及该半导体元件的制备方法。该半导体元件具有一基底、一垫结构以及一上凹槽,该垫结构位在该基底上,该上凹槽位在该垫结构的一顶表面上。该半导体元件的该制备方法包括形成一垫结构在一基底上以及形成一上凹槽在该垫结构的一顶表面上。(The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device has a substrate, a pad structure on the substrate, and an upper trench on a top surface of the pad structure. The method of fabricating the semiconductor device includes forming a pad structure on a substrate and forming an upper recess on a top surface of the pad structure.)

1. A semiconductor component, comprising:

a substrate;

a pad structure on the substrate; and

an upper recess is located on a top surface of the pad structure.

2. The semiconductor device as defined in claim 1, wherein the pad structure comprises a lower pad and an upper pad, the lower pad is on the substrate, the upper pad is on the lower pad, and the upper recess is on a top surface of the upper pad.

3. The semiconductor device as defined in claim 2, further comprising a lower groove on a top surface of the lower pad, wherein the upper pad is located on the lower groove and the lower pad.

4. The semiconductor device of claim 1, further comprising two spacers attached to two sides of the pad structure.

5. The semiconductor device as claimed in claim 2, wherein the upper recess is disposed adjacent to an edge of the top surface of the upper pad.

6. The semiconductor device of claim 1, wherein the pad structure comprises a lower pad on the substrate, a middle pad on the lower pad, and an upper pad on the middle pad, and the upper recess is on a top surface of the upper pad.

7. The semiconductor device as defined in claim 6, further comprising a lower groove and a middle groove, the lower groove being located on a top surface of the lower pad, the middle groove being located on a top surface of the middle pad, wherein the middle pad is located on the lower groove and the lower pad, and the upper pad is located on the middle groove and the middle pad.

8. The semiconductor device as claimed in claim 1, wherein a ratio of a depth of the upper recess to a thickness of the pad structure is between 1: 10 and 1: 20.

9. The semiconductor device of claim 1, further comprising a redistribution layer on the substrate, wherein the pad structure is on the redistribution layer.

10. The semiconductor device of claim 9, wherein the pad structure comprises a lower pad on the redistribution layer and an upper pad on the lower pad, and the upper recess is on a top surface of the upper pad.

11. The semiconductor device of claim 10, further comprising a base groove on a top surface of the redistribution layer and a lower groove on a top surface of the lower pad directly above the base groove, wherein the lower pad is on the base groove and the redistribution layer, the upper pad is on the lower groove and the lower pad, and the upper groove is directly above the lower groove.

12. The semiconductor device as claimed in claim 9, wherein a ratio of a depth of the upper recess to a thickness of the pad structure is between 1: 10 and 1: 20.

13. The semiconductor device of claim 9, further comprising a stress relief structure directly under said pad structure.

14. The semiconductor device as claimed in claim 13, wherein the stress relieving structure comprises a conductive frame directly under the pad structure and a plurality of isolation sections within the conductive frame.

15. The semiconductor device of claim 13, further comprising a stress buffer layer between said stress relief structure and said pad structure, wherein said stress buffer layer is made of a material having a coefficient of thermal expansion of less than about 20ppm/° c and a young's modulus of less than about 15 GPa.

16. A method for manufacturing a semiconductor device includes:

providing a substrate;

forming a pad structure on the substrate; and

an upper recess is formed on a top surface of the pad structure.

17. The method of claim 16, wherein the step of forming the pad structure on the substrate comprises:

forming a lower pad on the substrate; and

forming an upper pad on the lower pad;

wherein the upper groove is formed on a top surface of the upper pad.

18. The manufacturing method of a semiconductor element according to claim 16, further comprising:

forming a plurality of passivation layers on the substrate; and

forming a pad opening through the plurality of passivation layers;

wherein the pad structure is formed in the pad opening.

19. The manufacturing method of a semiconductor element according to claim 18, further comprising:

a passivation process is performed that includes wetting the pad opening with a precursor, wherein the precursor is trimethylsilyl dimethylamine () or tetramethylsilane ().

20. The manufacturing method of a semiconductor element according to claim 18, further comprising:

a cleaning process is performed, wherein the cleaning process includes applying a remote plasma to the pad opening.

Technical Field

This application claims priority and benefit of us official application No. 16/674,367, filed on 5.11.2019, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, to a semiconductor device having a recess and a method for fabricating the semiconductor device having the recess.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the process of shrinking the dimensions, different problems are added and the final electronic characteristics, quality and yield are affected. Thus, there is a continuing challenge to achieve improved quality, yield, and reliability.

The above description of "prior art" is merely provided as background, and is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is prior art to the present disclosure.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, including: a substrate; a pad structure on the substrate; and an upper recess on a top surface of the pad structure.

In some embodiments of the present disclosure, the pad structure includes a lower pad on the substrate and an upper pad on the lower pad, with the upper groove on a top surface of the upper pad.

In some embodiments of the present disclosure, the semiconductor device further includes a lower groove on a top surface of the lower pad, wherein the upper pad is located on the lower groove and the lower pad.

In some embodiments of the present disclosure, the semiconductor device further includes two spacers attached to two sides of the pad structure.

In some embodiments of the present disclosure, the upper groove is disposed adjacent to an edge of the top surface of the upper pad.

In some embodiments of the present disclosure, the pad structure includes a lower pad on the substrate, a middle pad on the lower pad, and an upper pad on the middle pad, the upper groove on a top surface of the upper pad.

In some embodiments of the present disclosure, the semiconductor device further includes a lower groove and a middle groove, the lower groove is located on a top surface of the lower pad, the middle groove is located on a top surface of the middle pad, wherein the middle pad is located on the lower groove and the lower pad, and the upper pad is located on the middle groove and the middle pad.

In some embodiments of the present disclosure, the semiconductor device further includes a redistribution layer on the substrate, wherein the pad structure is on the redistribution layer.

In some embodiments of the present disclosure, the pad structure includes a lower pad on the redistribution layer and an upper pad on the lower pad, with the upper groove on a top surface of the upper pad.

In some embodiments of the present disclosure, the semiconductor device further includes a base groove on a top surface of the redistribution layer and a lower groove on a top surface of the lower pad and directly above the base groove, wherein the lower pad is on the base groove and the redistribution layer, the upper pad is on the lower groove and the lower pad, and the upper groove is directly above the lower groove.

In some embodiments of the present disclosure, a ratio of a depth of the upper groove to a thickness of the pad structure is between 1: 10 and 1: 20.

In some embodiments of the present disclosure, the semiconductor device further includes a stress relief structure directly below the pad structure.

In some embodiments of the present disclosure, the stress relief structure includes a conductive frame directly under the pad structure and a plurality of isolation sections within the conductive frame.

In some embodiments of the present disclosure, the semiconductor device further comprises a stress buffer layer between the stress relief structure and the pad structure, wherein the stress buffer layer is made of a material having a coefficient of thermal expansion of less than about 20 ppm/deg.C and a Young's modulus of less than about 15 GPa.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a substrate; forming a pad structure on the substrate; and forming an upper recess on a top surface of the pad structure.

In some embodiments of the present disclosure, the method of manufacturing a semiconductor element further includes: forming a plurality of passivation layers on the substrate; and forming a pad opening through the plurality of passivation layers; wherein the pad structure is formed in the pad opening.

In some embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes: a passivation process is performed that includes wetting the pad opening with a precursor, wherein the precursor is trimethylsilyl dimethylamine (dmac) or tetramethylsilane (tetramethylsilane).

In some embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes: a cleaning process is performed, wherein the cleaning process includes applying a remote plasma to the pad opening.

Due to the design of the semiconductor device of the present disclosure, the upper recess may serve as a guide for a probe tip to prevent the sliding probe tip from moving out of the upper recess. Therefore, the semiconductor ambient can remain intact even if the probe tip slips. As a result, the yield of the semiconductor device can be improved, and the performance of the semiconductor device can be improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure may be more fully understood by reference to the following description of embodiments taken together with the claims, in which like reference numerals refer to like elements.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view taken along section line A-A' of FIG. 1 according to the present disclosure.

Fig. 3 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 4 is a schematic cross-sectional view taken along section line A-A' of FIG. 3 according to the present disclosure.

Fig. 5 to 8 are schematic top views of semiconductor devices according to an embodiment of the present disclosure.

Fig. 9 is a top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 10 is a schematic cross-sectional view taken along section line A-A' of FIG. 9 according to the present disclosure.

FIG. 11 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present disclosure.

Fig. 12 is a top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 13 is a schematic cross-sectional view taken along section line A-A' of FIG. 12 according to the present disclosure.

Fig. 14 is a flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 15 is a top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 16 is a schematic cross-sectional view taken along section line A-A' of FIG. 15 according to the present disclosure.

Fig. 17 is a top view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 18 is a schematic cross-sectional view taken along section line A-A' of FIG. 17 according to the present disclosure.

Fig. 19-24 are cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 25 and 26 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 27-29 are cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

FIG. 30 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

FIG. 31 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 32 is a top view of an intermediate-stage semiconductor device in accordance with an embodiment of the present disclosure.

FIG. 33 is a schematic cross-sectional view taken along section line A-A' of FIG. 32 according to the present disclosure.

Fig. 34-36 are cross-sectional views of a portion of a process for fabricating a semiconductor device according to another embodiment of the present disclosure.

Fig. 37 and 38 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Wherein the reference numerals are as follows:

10: preparation method

100A: semiconductor device with a plurality of semiconductor chips

100B: semiconductor device with a plurality of semiconductor chips

100C: semiconductor device with a plurality of semiconductor chips

100D: semiconductor device with a plurality of semiconductor chips

100E: semiconductor device with a plurality of semiconductor chips

100F: semiconductor device with a plurality of semiconductor chips

100G: semiconductor device with a plurality of semiconductor chips

100I: semiconductor device with a plurality of semiconductor chips

100J: semiconductor device with a plurality of semiconductor chips

101: substrate

103: insulating layer

105: active region

107: word line

107-1: word line isolation layer

107-2: character line electrode

107-3: word line cap

109: doped region

109-1: first doped region

109-2: second doped region

111: contact point

111-1: first contact point

111-2: second contact point

113: bit line contact

115: bit line

117: embolism

119: capacitor structure

119-1: capacitor bottom electrode

119-2: capacitor isolation layer

119-3: capacitor top electrode

121: a first conductive via

123: first conductive layer

123-1: first basic groove

125: second conductive via

127: redistribution layer

127-1: second basic groove

129: stress buffer layer

201: first pad structure

201-1: first pad opening

203: first lower cushion

203-1: first lower groove

205: a first upper pad.

205-1: first upper groove

207: first middle cushion

207-1: first middle groove

209: interstitial sublayers

209-1: spacer

301: stress releasing structure

301-1: stress relief structure opening

303: conductive frame

305: isolation zone

401: second pad structure

401-1: second pad opening

403: second lower cushion

403-1: second lower groove

405: second upper pad

405-1: second upper groove

501: first isolation film

503: second isolation film

505: third isolation film

507: fourth barrier film

509: fifth barrier film

511: sixth barrier film

513: seventh barrier film

515: eighth barrier film

601: first passivation layer

603: second passivation layer

605: a third passivation layer

607: a fourth passivation layer

701: cleaning process

703: passivation process

D1: depth of field

D2: thickness of

D3: depth of field

D4: thickness of

S11: step (ii) of

S13: step (ii) of

S15: step (ii) of

S17: step (ii) of

S19: step (ii) of

S21: step (ii) of

W: direction of rotation

X: direction of rotation

Y: direction of rotation

Detailed Description

Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These repetitions are for simplicity and clarity and do not, in themselves, represent a particular relationship between the various embodiments and/or configurations discussed, unless specifically stated in the context.

Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

It will be understood that forming one element over (on), connecting to (connecting to), and/or coupling to (connecting to) another element may include embodiments in which the elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the elements such that the elements are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Unless otherwise indicated in the context, when representing orientation (orientation), layout (layout), location (location), shape (shapes), size (sizes), quantity (amounts), or other measurements (measures), then terms (metrics), such as "same (same)," equal (equal), "" flat (planar), "or" coplanar "(coplanar)," as used herein, do not necessarily mean an exactly identical orientation, layout, location, shape, size, quantity, or other measurement, but mean that within an acceptable difference, including more or less exactly the same orientation, layout, location, shape, size, quantity, or other measurement, that may occur, for example, as a result of manufacturing processes. The term "substantially" may be used herein to convey this meaning. Such as, for example, substantially identical (substitionally the same), substantially equal (substitionally equivalent), or substantially flat (substitional planar), being exactly identical, equal, or flat, or being the same, equal, or flat within acceptable differences that may occur, for example, as a result of a manufacturing process.

In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics (semiconductor characteristics), and an electro-optical device (electro-optical device), a light-emitting display device (light-emitting display device), a semiconductor circuit (semiconductor circuit), and an electronic device (electronic device) are included in the category of semiconductor devices.

It should be understood that in the description of the present disclosure, the upper (above) is the direction corresponding to the Z-direction arrow, and the lower (below) is the opposite direction corresponding to the Z-direction arrow.

Fig. 1 is a schematic top view of a semiconductor device 100A according to an embodiment of the present disclosure. Fig. 2 is a schematic cross-sectional view of the semiconductor device 100A taken along the cross-sectional line a-a' of fig. 1 according to the present disclosure. For clarity of presentation, some components of the semiconductor element 100A of the present disclosure are not shown in fig. 1.

Referring to fig. 1 and 2, in the embodiment, the semiconductor device 100A may include a substrate 101, an insulating layer 103, a plurality of word lines 107, a plurality of doped regions 109, a plurality of contact points 111, a plurality of bit lines 115, a plurality of plugs 117, a plurality of capacitor structures 119, a first conductive via 121, a first conductive layer 123, a plurality of isolation films, a plurality of passivation layers, and a first pad structure 201.

Referring to fig. 1 and 2, in the embodiment, the substrate 101 may be formed of the following materials, for example: silicon, germanium, silicon germanium (silicon germanium), silicon carbide (silicon carbon), silicon germanium carbide (silicon germanium carbon), gallium arsenide (gallium arsenide), indium arsenide (indium arsenide), indium phosphide (indium phosphide), or other group IV, group III, or group II-VI semiconductor materials. The insulating layer 103 may be disposed in an upper portion of the substrate 101. (two insulating layers 103 are shown in the cross-sectional view of fig. 2, but other numbers of insulating layers may be used in other embodiments.) for example, the insulating layer 103 may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicon (fluorine-doped silicon). The insulating layer 103 may define a plurality of active regions 105 of the substrate 101.

It should be understood that in the present disclosure, silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

Referring to fig. 1 and 2, in the embodiment, a plurality of word lines 107 are disposed in an upper portion of the substrate 101 and spaced apart from each other. Each active region 105 extends through two of the word lines 107. The word lines 107 may include word line isolation layers 107-1, word line electrodes 107-2, and word line caps 107-3, the word line isolation layers 107-1 are disposed inward in the substrate 101, the word line electrodes 107-2 are respectively disposed on the word line isolation layers 107-1, and the word line caps 107-3 are respectively disposed on the word line electrodes 107-2.

Referring to fig. 1 and 2, in the illustrated embodiment, for example, the plurality of word line isolation layers 107-1 may be made of an isolation material having a dielectric constant of about 4.0 or greater. (unless otherwise indicated, all dielectric constants mentioned herein are relative to a vacuum.) the barrier material having a dielectric constant of about 4.0 or greater can be hafnium oxide (hafnium oxide), zirconium oxide (zirconia oxide), aluminum oxide (aluminum oxide), titanium oxide (titanium oxide), lanthanum oxide (lanthanum oxide), titanium strontium titanate (strontium titanate), lanthanum aluminate (lanthanum aluminate), yttrium oxide (yttrium oxide), germanium oxide (gallium (iii) trioxide), gadolinium gallium oxide (gadolinium gallium titanate), lead zirconate titanate (lead zirconate titanate), barium strontium titanate (barium titanate), or mixtures thereof. Alternatively, in other embodiments, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

Referring to fig. 1 and 2, in the illustrated embodiment, for example, the plurality of word line electrodes 107-2 may be made of a conductive material, such as doped polysilicon, silicon germanium, a metal alloy, a metal silicide, a metal nitride, a metal carbide, or a multilayer containing combinations thereof. The metal may be aluminum, copper, tungsten, or cobalt. The metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. For example, the plurality of wordline caps 107-3 may be made of an isolation material having a dielectric constant of about 4.0 or greater.

Referring to fig. 1 and 2, in the embodiment, a plurality of doped regions 109 may be disposed in the substrate 101. The doped regions 109 may be doped with a dopant (dopant), such as phosphorous, arsenic or antimony (antimony). The doped regions 109 may include a first doped region 109-1 and two second doped regions 109-2. The first doped region 109-1 may be disposed between two of the word lines 107. Each of the second doped regions 109-2 may be disposed between a plurality of word lines 107 and the insulating layer 103.

Referring to fig. 1 and 2, in the embodiment, a plurality of isolation films may be disposed on the substrate 101. For example, the plurality of isolation films may be made of: silicon nitride, silicon oxide, silicon oxynitride, flowable oxide (flowable oxide), a fire-resistant silazane (silicone tile), undoped silicate glass (undoped silicate glass), borosilicate glass (borosilicate glass), phosphosilicate glass (phosphosilicate glass), borophosphosilicate glass (borophosphosilicate glass), plasma-enhanced tetraethoxysilane (plasma enhanced tetra ethyl silicate), fluorosilicate glass (fluoride silicate), carbon-doped silicon oxide (carbon-doped silicon oxide), xerogel (xerogel), aerogel (aerogel), amorphous fluorinated carbon (amorphous fluorinated carbon), organic silicate glass (organic silicate glass), parylene (para-xylene), bis-benzocyclobutene (benzocyclobutene-styrene), polyimide (polyimide), polymeric materials or combinations thereof. The plurality of isolation films may be made of the same material, but not limited thereto. The plurality of isolation films may include a first isolation film 501, a second isolation film 503, a third isolation film 505, a fourth isolation film 507, a fifth isolation film 509, a sixth isolation film 511, and a seventh isolation film 513.

Referring to fig. 1 and 2, in the embodiment, a first isolation film 501 may be disposed on the substrate 101. A plurality of contact points 111 may be provided in the first separation film 501. The plurality of contacts 111 may be made of a conductive material, such as doped polysilicon, metal nitride, or metal silicide. For each active region 105, the plurality of contact points 111 may include a first contact point 111-1 and two second contact points 111-2. A first contact 111-1 may be disposed at the first doped region 109-1. The two second contact points 111-2 may be respectively disposed on the two second doping regions 109-2.

Referring to fig. 1 and 2, in the embodiment, the second isolation film 503 may be disposed on the first isolation film 501. A plurality of bit line contacts 113 may be disposed in the second isolation film 503 and in the plurality of active regions 105. (only one bit line contact 113 is shown in the cross-sectional view of FIG. 2.) for each active region 105, a bit line contact 113 may be disposed on the first contact 111-1. The plurality of bit line contacts 113 may be made of the same material as the first contact 111-1, but not limited thereto. The third isolation film 505 may be disposed on the second isolation film 503. A plurality of bit lines 115 may be disposed in the third isolation film 505. (only one bit line 115 is shown in the cross-sectional view of FIG. 2.) for each active region 105, a bit line 115 may be disposed on a corresponding bit line contact 113. The plurality of bit lines 115 may be made of a conductive material, such as tungsten, aluminum, nickel, or cobalt.

Referring to fig. 1 and 2, in the embodiment, a fourth isolation film 507 may be disposed on the third isolation film 505. A plurality of capacitor plugs 117 may be disposed to penetrate through the fourth isolation film 507, the third isolation film 505, and the second isolation film 503. For each active region 105, two of the capacitor plugs 117 may be disposed on the two second contact points 112-2, respectively. The plurality of capacitive plugs 117 may be made of: doped polysilicon, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or aluminum alloy. A fifth isolation film 509 may be disposed on the fourth isolation film 507. A plurality of capacitor structures 119 may be disposed in the fifth isolation film 509 and respectively disposed on the plurality of capacitor plugs 117.

Referring to fig. 1 and 2, in the embodiment, the plurality of capacitor structures 119 may include a plurality of capacitor bottom electrodes 119-1, a capacitor isolation layer 119-2 and a capacitor top electrode 119-3, the plurality of capacitor bottom electrodes 119-1 are disposed inward in the fifth isolation film 509, the capacitor isolation layer 119-2 may be disposed on the plurality of capacitor bottom electrodes 119-1, and the capacitor top electrode 119-3 may be disposed on the capacitor isolation layer 119-2. The plurality of capacitor bottom electrodes 119-1 may be made of doped polysilicon, metal, or metal silicide. The capacitive isolation layer 119-2 may be formed from a single layer comprising an isolation material having a dielectric constant of about 4.0 or greater. The capacitive top electrode 119-3 may be made of doped polysilicon or metal. Alternatively, in another embodiment, the capacitor isolation layer 119-2 may be formed of a stack of layers consisting of silicon oxide, silicon nitride and silicon oxide.

Referring to fig. 1 and 2, in the embodiment, a sixth isolation film 511 may be disposed on the capacitor top electrode 119-3. The seventh separation film 513 may be disposed on the sixth separation film 511. The first conductive via 121 may be disposed in the sixth isolation film 511 and located on the capacitive top electrode 119-3. For example, the first conductive via 121 may be made of a metal, a metal alloy, a silicate, a silicide, a polysilicon, an amorphous silicon (amorphous silicon), or other semiconductor compatible conductive material. The first conductive layer 123 may be disposed in the seventh isolation film 513 and located on the first conductive via 121. For example, the first conductive layer 123 can be made of a conductive material, such as doped polysilicon, metal nitride, or metal silicide.

Referring to fig. 1 and 2, in the embodiment, a plurality of passivation layers may be disposed on the seventh isolation film 513. The plurality of passivation layers may include a first passivation layer 601 and a second passivation layer 603. The first passivation layer 601 may be disposed on the seventh isolation film 513. For example, the first passivation layer 601 may be made of silicon oxide or phosphosilicate glass. The second passivation layer 603 may be disposed on the first passivation layer 601, and may be made of silicon nitride, silicon oxynitride, or silicon oxynitride, for example. The first passivation layer 601 may function as a stress buffer (stress buffer) between the second passivation layer 603 and the seventh isolation film 513. To prevent moisture from entering from above, the second passivation layer 603 may be used as a high vapor barrier (high vapor barrier).

Referring to fig. 1 and 2, in the embodiment, a first pad structure 201 may be disposed in the first passivation layer 601 and the second passivation layer 603. The first pad structure 201 may be disposed on the first conductive layer 123 and may be electrically connected to the first conductive layer 123. The first pad structure 201 may include a first lower pad 203, a first upper pad 205, and a first upper recess 205-1.

Referring to fig. 1 and 2, in the embodiment, the first lower pad 203 may be disposed in the first passivation layer 601 and located on the first conductive layer 123. The first lower pad 203 may be electrically connected to the first conductive layer 123. A thickness of the first under pad 203 may be less than a thickness of the first passivation layer 601. The first lower pad 203 may contain nickel. The first upper pad 205 may be disposed in the first passivation layer 601 and the second passivation layer 603. The first upper pad 205 may be disposed on the first lower pad 203 and electrically connected to the first lower pad 203. A top surface of the first upper pad 205 may be flush with a top surface of the second passivation layer 603. The first upper pad 205 may contain platinum (palladium), cobalt (cobalt), or a combination thereof. The first upper groove 205-1 may be disposed inwardly on the top surface of the first upper pad 205. The first upper groove 205-1 may be disposed adjacent to an edge of the top surface of the first upper pad 205 in a top view. The edge of the top surface of the first upper pad 205 may be located near a central region of the semiconductor device 100A, and the semiconductor device 100A includes a plurality of logic elements (logic elements). In other words, the first upper groove 205-1 may be asymmetrically disposed on the top surface of the first upper pad 205. A ratio of a depth D1 of the first upper groove 205-1 to a thickness D2 of the first pad structure 201 may be in a range of 1: 10to 1: 20, respectively.

In order to ensure the quality of a semiconductor device, an inspection process may be performed by using a probe tip (probe tip) disposed on a cantilever (cantilever) to directly contact a top surface of a pad structure and measure electrical signals. However, due to air exposure of the pad structure, a native oxide layer may be formed on the top surface of the pad structure; therefore, when performing the inspection process, the probe tips may have to penetrate the native oxide layer to measure electrical signals. In addition, during operation of the probe tip, a slip (slippage) may occur, and the penetrating probe tip may slip off the top surface of the pad structure and damage the surrounding passivation or isolation layer. Moisture may enter the interior of the semiconductor device from the damaged passivation or isolation layer and may lose the integrity of the semiconductor device. As a result, the semiconductor device may become more fragile and may affect the quality, yield, and performance of the semiconductor device.

Referring to fig. 1 and 2, in the embodiment, when a probe tip slip occurs, the first upper groove 205-1 may serve as a guide (guide) for the probe tip to prevent the slipping probe tip from moving out of the first upper groove 205-1. Thus, even if slippage of the probe tip occurs, the surrounding passivation layer may remain intact. As a result, the quality, yield and performance of the semiconductor device 100A may be improved. In addition, the first upper recess 205-1 may be disposed near the edge of the top surface of the first upper pad 205, which is located near the central region of the semiconductor element 100A. The central region of the semiconductor element 100A may include a plurality of logic components. In other words, the first upper recess 205-1 can be disposed close to the logic components of the semiconductor device 100A and can effectively prevent a probe tip from sliding toward the central area of the semiconductor device 100A.

Fig. 3 is a schematic top view of a semiconductor device 100B according to an embodiment of the present disclosure. Fig. 4 is a schematic cross-sectional view of the semiconductor device 100B of fig. 3 taken along the cross-sectional line a-a' according to the present disclosure. For clarity of presentation, some components of the semiconductor element 100B of the present disclosure are not shown in fig. 3.

Referring to fig. 3 and 4, in the embodiment, the first upper groove 205-1 may be disposed at a center of the top surface of the first upper pad 205. The first upper groove 205-1, which is disposed in the center of the top surface of the first upper pad 205, prevents a probe tip from slipping toward the central region or a peripheral region of the semiconductor device 100B.

Fig. 5 to 8 are schematic top views of semiconductor devices 100C, 100D, 100E, 100F according to an embodiment of the present disclosure.

Referring to fig. 5, the semiconductor device 100C may include a first middle pad 207. In particular, the first pad structure 201 can include a first middle pad 207. The first middle pad 207 may be disposed between the first upper pad 205 and the first lower pad 203. For example, the first middle pad 207 may be made of nickel. For example, the first lower pad 203 may be made of gold, while the first upper pad 205 may be made of copper, for example.

Referring to fig. 6, the semiconductor device 100D may include two spacers 209-1. In particular, the first pad structure 201 can include two spacers 209-1. Two spacers 209-1 may be attached to both sides of the first pad structure 201.

Referring to fig. 7, the semiconductor device 100E may include a first base groove (first base groove)123-1 and a first lower groove 203-1. The first base groove 123-1 may be inwardly disposed on the top surface of the first conductive layer 123. The first lower pad 203 may be disposed on the first conductive layer 123 and the first base groove 123-1. The first lower groove 203-1 may be disposed inwardly on the top surface of the first lower pad 203 and directly above the first base groove 123-1. The first upper pad 205 may be disposed on the first lower pad 203 and the first lower groove 203-1. First upper groove 205-1 may be located directly above first lower groove 203-1.

Referring to fig. 8, the semiconductor device 100F may include a first middle recess 207-1. The first middle pad 207 may be disposed on the first lower pad 203 and the first lower groove 203-1. The first middle groove 207-1 may be inwardly disposed on a top surface of the first middle pad 207. The first upper pad 205 may be disposed on the first middle pad 207 and the first middle groove 207-1.

Fig. 9 is a schematic top view of a semiconductor device 100G according to an embodiment of the present disclosure. Fig. 10 is a cross-sectional view of the semiconductor device 100G taken along the cross-sectional line a-a' of fig. 9 according to the present disclosure. For clarity of presentation, some components of the semiconductor element 100G of the present disclosure are not shown in fig. 10.

Referring to fig. 9 and 10, in the embodiment, the semiconductor device may include a second conductive via 125, a redistribution layer 127, a stress relief structure 301, a second pad structure 401, an eighth isolation film 515, a third passivation layer 605, and a fourth passivation layer 607.

Referring to fig. 9 and 10, in the embodiment, a stress relief structure (stress relief structure)301 may be disposed in the first passivation layer 601 and the second passivation layer 603 and be away from the first pad structure 201. The stress relieving structure 301 may include a conductive frame 303 and a plurality of insulating segments 305. The conductive frame 303 may be disposed away from the first pad structure 201 and may have a mesh shape (mesh shape). That is, the components of the conductive cage 303 may be connected to each other. For example, the conductive frame 303 may be made of a conductive material, such as metal, metal nitride, or metal silicide. A plurality of isolation sections 305 may be disposed within the conductive frame 303 and may have a square shape. The plurality of isolation sections 305 may be made of the same material as the seventh isolation film 513, but not limited thereto. Alternatively, in other embodiments, the isolation segments 305 may be made of a material including polyimide (polyimide) or epoxy-based (epoxy-based) materials. The stress relief structure 301 may be used as a shock pad (cushion) to reduce a stress (stress) of a wiring process.

Referring to fig. 9 and 10, in the embodiment, the eighth isolation film 515 may be disposed on the second passivation layer 603 and may be made of the same material as the seventh isolation film 513, but not limited thereto. The second conductive via 125 may be disposed in the eighth isolation film 515 and located on the first upper pad 205. The second conductive via 125 may be made of the same material as the first conductive via 121, but is not limited thereto. The redistribution layer 127 may be disposed on the eighth separation film 515. The redistribution layer 127 may be disposed over the first pad structure 201 and the stress relieving structure 301. For example, the redistribution layer 127 may be made of tin, nickel, copper, gold, aluminum, or alloys thereof. The redistribution layer 127 may be electrically connected to the second conductive via 125.

Referring to fig. 9 and 10, in the embodiment, a third passivation layer 605 may be disposed on the eighth isolation film 515 and the redistribution layer 127. The third passivation layer 605 may be made of the same material as the first passivation layer 601, but is not limited thereto. The fourth passivation layer 607 may be disposed on the third passivation layer 605 and may be made of the same material as the second passivation layer 603, but is not limited thereto. The second pad structure 401 may be disposed in the fourth passivation layer 607 and the third passivation layer 605. The second pad structure 401 may be disposed on the redistribution layer 127. The second pad structure 401 may be disposed directly above the stress relieving structure 301 and higher than the first pad structure 201. The second pad structure 401 may be electrically connected to the redistribution layer 127 and electrically coupled to the first pad structure 201. The second pad structure 401 may include a second lower pad 403, a second upper pad 405, and a second upper recess 405-1.

Referring to fig. 9 and 10, in the embodiment, the second under-pad 403 may be disposed in the third passivation layer 605 and located on the redistribution layer 127. The second lower pad 403 may be made of the same material as the first lower pad 203, but is not limited thereto. The second upper pad 405 may be disposed in the third and fourth passivation layers 605, 607. A second upper pad 405 may be disposed on the second lower pad 403. A top surface of the second upper pad 405 may be flush with a top surface of the fourth passivation layer 607. The second upper pad 405 may be made of the same material as the first upper pad 205, but is not limited thereto. The second upper groove 205-1 may be disposed inwardly on the top surface of the second upper pad 405. A ratio of a depth D3 of the second upper groove 405-1 to a thickness D4 of the second pad structure 401 may be between 1: 10 and 1: 20.

Fig. 11 is a schematic cross-sectional view of another semiconductor device 100I according to an embodiment of the present disclosure.

Referring to fig. 11, the semiconductor device 100I may include a second base groove 127-1 and a second lower groove 403-1. The second base groove 127-1 may be disposed inwardly on a top surface of the redistribution layer 127. The second under-pad 403 may be disposed on the redistribution layer 127 and the second base groove 127-1. The second lower groove 403-1 may be disposed inwardly on a top surface of the second lower pad 403 and directly above the second base groove 127-1. A second upper pad 405 may be disposed on the second lower pad 403 and the second lower groove 403-1. The second upper groove 405-1 may be located directly above the second lower groove 403-1.

Fig. 12 is a schematic top view of a semiconductor device 100J according to an embodiment of the present disclosure. Fig. 13 is a cross-sectional view of the semiconductor device 100J taken along the cross-sectional line a-a' of fig. 12 according to the present disclosure. For clarity of presentation, some components of the semiconductor element 100J of the present disclosure are not shown in fig. 13.

Referring to fig. 12, the semiconductor device 100J may include a stress buffer layer 129. The stress buffer layer 129 may be disposed in the eighth isolation film 515 and between the redistribution layer 127 and the stress relief structure 301. The stress buffer layer 129 may be disposed directly under the second pad structure 401. The stress buffer layer 129 may be used to absorb and redistribute stress concentrated in the lower layers caused by shear stresses (thermal stresses) and normal stresses (normal stresses) due to a wiring process. For example, the stress buffer layer 129 may be made of a material having a Coefficient of Thermal Expansion (CTE) of less than about 20 ppm/deg.C and a Young's Modulus of less than about 15 GPa. In particular, the stress buffer layer 129 may be made of a material including polyimide (polyimide) or epoxy-based (epoxy-based) materials. The stress buffer layer 129 may have a thickness of aboutAndin the meantime. Preferably, the thickness of the stress buffer layer 129 can be withinAndin the meantime.

Fig. 14 is a flow chart illustrating a method 10 for fabricating a semiconductor device 100A according to an embodiment of the present disclosure. Fig. 15 is a top view of a semiconductor device 100A according to an embodiment of the present disclosure. FIG. 16 is a schematic cross-sectional view taken along section line A-A' of FIG. 15 according to the present disclosure. For clarity of presentation, some components of the semiconductor element of the present disclosure are not shown in fig. 16.

Referring to fig. 14 to 16, in step S11, in the embodiment, a substrate 101 is provided, and an insulating layer 103, a plurality of word lines 107 and a plurality of doped regions 109 are formed in the substrate 101. The insulating layer 103 may define a plurality of active regions 105. The plurality of active regions 105 may be disposed at intervals from each other and extend along a direction W in a top view. The plurality of word lines 107 may extend in a direction X that is inclined (or diagonal) with respect to the direction W. Each active region 105 may extend through two of the word lines 107. The plurality of word lines 107 may include a plurality of word line isolation layers 107-1, a plurality of word line electrodes 107-2, and a plurality of word line caps 170-3. A plurality of word line isolation layers 107-1 may be formed inwardly in the substrate 101. A plurality of word line electrodes 107-2 are formed on the word line isolation layers 107-1, respectively. A plurality of word line caps 107-3 may be formed on the plurality of word line electrodes 107-2. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to fig. 16, the doped regions 109 may include a first doped region 109-1 and two second doped regions 109-2. The first doped region 109-1 may be formed between a plurality of word lines 107. Each second doped region 109-2 may be formed between the insulating layer 103 and one of the word lines 107.

Fig. 17 is a top view of a semiconductor device 100A according to an embodiment of the present disclosure. Fig. 18 is a schematic cross-sectional view of a portion of the process flow of fig. 17 taken along section line a-a' for fabricating a semiconductor device 100A according to the present disclosure. For clarity of presentation, some components of the semiconductor element of the present disclosure are not shown in fig. 18. Fig. 19-24 are schematic cross-sectional views of a portion of a process flow for fabricating a semiconductor device 100A according to an embodiment of the present disclosure.

Referring to fig. 14, 17 and 18, in step S13, in the embodiment, a plurality of bit lines 115 may be formed over the substrate 101. A first isolation film 501, a second isolation film 503 and a third isolation film 505 may be sequentially formed on the substrate 101. For each active region 105, a first contact 111-1 and two second contacts 111-2 may be formed in the first isolation film 501. A first contact 111-1 may be formed on the first doped region 109-1. Two second contact points 111-2 may be correspondingly formed on the two second doping regions 109-2, respectively. A plurality of bit line contacts 113 may be formed in the second isolation film 503. The bit line contacts 113 are respectively disposed on the first contacts 111-1. A plurality of bit lines 115 may be formed in the third isolation film 505. The plurality of bit lines 115 may extend in a direction Y that is inclined (or diagonal) with respect to the direction W and perpendicular to the direction X. The plurality of bit lines 115 may be implemented as wavy lines. A plurality of bit lines 115 may be disposed at intervals. In a top view, each bit line 115 may extend through one of the active regions 105. The plurality of bit lines 115 may be electrically connected to the plurality of bit line contacts 113.

Referring to fig. 14 and 19, in step S15, in the embodiment, a plurality of capacitor structures 119 may be formed on the substrate 101. A fourth isolation film 507 may be formed on the third isolation film 505. A plurality of plugs 117 may be formed to penetrate through the fourth isolation film 507, the third isolation film 505, and the second isolation film 503. For each active region 105, a plurality of plugs 117 may be disposed on the two second contact points 111-2, respectively.

Referring to fig. 19, a fifth isolation film 509 may be formed on the fourth isolation film 507. The plurality of capacitor structures 119 may include a plurality of capacitor bottom electrodes 119-1, a capacitor isolation layer 119-2, and a capacitor top electrode 119-3. A plurality of capacitor bottom electrodes 119-1 may be inwardly formed in the fifth isolation film 509. A capacitive isolation layer 119-2 may be formed on the plurality of capacitive bottom electrodes 119-1. The capacitive top electrode 119-3 may be formed on the capacitive isolation layer 119-2. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

Referring to fig. 14 and 20, in step S17, in the embodiment, a first conductive layer 123, a first passivation layer 601 and a second passivation layer 603 may be formed over the substrate 101, and a first pad opening 201-1 may be formed to pass through the first passivation layer 601 and the second passivation layer 603. A sixth isolation film 511 and a seventh isolation film 513 may be sequentially formed on the capacitive top electrode 119-3. A first conductive via 121 may be formed in the sixth isolation film 511 and located on the capacitive top electrode 119-3.

The first conductive layer 123 may be formed in the seventh isolation film 513 and located on the first conductive via 121. The first passivation layer 601 and the second passivation layer 603 may be sequentially formed on the seventh isolation film 513. A photolithography process may be performed to define the location of the first pad opening 201-1. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form the first pad opening 201-1. A portion of the top surface of the first conductive layer 123 may be exposed through the first pad opening 201-1.

Referring to fig. 14, 21 and 22, in step S19, in the illustrated embodiment, a cleaning process 701 and a passivation process 703 may be performed on the first pad opening 201-1. Referring to fig. 21, after the etching process, a cleaning process 701 may be performed. The cleaning process 701 may include using a mixture of hydrogen and argon as a remote plasma source (remote plasma source) in the presence of a process temperature between 250 ℃ and 350 ℃, a process pressure between 1Torr and 10Torr, and a bias energy (bias energy) supplied to the apparatus performing the cleaning process 701. The bias energy may be between 0W and 200W. The cleaning process 701 removes oxide on the top surface of the first conductive layer 123 without compromising the conductive performance of the first conductive layer 123, which oxide originates from the oxidation of oxygen in air.

Referring to fig. 22, a passivation process 703 may be performed on the second passivation layer 603 and the first pad opening 201-1. The passivation process 703 may include impregnating the semiconductor device in a precursor, such as trimethylsilyl dimethylamine (dimethylsilyl dimethylamine), tetramethylsilane (tetramethylsilane), or the like, at a process temperature between 200 ℃ and 400 ℃. An ultraviolet energy may be used to facilitate passivation process 703. The passivation process 703 passivates the sidewalls of the second passivation layer 603 and the first passivation layer 601 exposed through the first pad opening 201-1 by sealing surface pores thereof to reduce undesirable sidewall growth, which may affect the electronic performance of the semiconductor device during subsequent processing steps. Therefore, the performance and reliability of the semiconductor device can be improved.

Referring to fig. 14, 23 and 24, in step S21, in the illustrated embodiment, a first pad structure 201 may be formed in the first pad opening 201-1, and a first upper recess 205-1 may be formed on a top surface of the first pad structure 201. The first pad structure 201 may include a first lower pad 203, a first upper pad 205, and the first upper recess 205-1. Referring to fig. 23, a first lower pad 203 may be formed on the first conductive layer 123 at the first pad opening 201-1 by electroplating or electroless plating (electroless plating). The first lower pad 203 may contain nickel and may serve as a barrier (barrier) between the first conductive layer 123 made of copper and the first upper pad 205. The first upper pad 205 may be formed on the first lower pad 203 at the first pad opening 201-1 by electroplating or electroless plating. The first upper pad 205 may contain platinum, cobalt, or a combination thereof. A photolithography process may be performed to define the location of the first upper recess 205-1. After the photolithography process, an etching process may be performed to form a first upper groove 205-1 on the top surface of the first upper pad 205.

Fig. 25 and 26 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device 100D according to an embodiment of the present disclosure.

Referring to fig. 25, an intermediate stage semiconductor device may be fabricated by a process similar to that illustrated in fig. 15-20. A gap sub-layer 209 may be formed on a top surface of the second passivation layer 603 and in the first pad opening 201-1 by a deposition process, such as chemical vapor deposition, physical vapor deposition, or the like. After the deposition process, an etching process, such as an anisotropic dry etching process, may be performed to remove the spacer layer 209 formed at the top surface of the second passivation layer 603 and a portion of a bottom of the first pad opening 201-1 and simultaneously form the two spacers 209-1. Two spacers 209-1 may be formed to fit to the respective sidewalls of the first pad opening 201-1. Referring to fig. 26, a first lower pad 203 may be formed on the first conductive layer 123 and located between two spacers 209-1. A first upper pad 205 may be formed on the first lower pad 203 and located between the two spacers 209-1. A first upper recess 205-1 may be formed on the top surface of the first upper pad and disposed adjacent to one of the spacers 209-1. Alternatively, in other embodiments, the first upper groove 205-1 may be disposed away from the two spacers 209-1.

Fig. 27-29 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device 100E according to an embodiment of the present disclosure.

Referring to fig. 27, an intermediate stage semiconductor device may be fabricated by a process similar to that illustrated in fig. 15-20. A photolithography process may be performed to define the location of the first base recess 123-1. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form the first basic recess 123-1 on the top surface of the first conductive layer 123. After the formation of the first basic recess 123-1, a cleaning process 701 and a passivation process 703 may be performed.

Referring to fig. 28, the first under pad 203 may be formed on the first conductive layer 123 and the first base groove 123-1 by electroplating or electroless plating. Due to the existence of the first base groove 123-1, a portion of the first under pad 203 may sink into the first base groove 123-1 and simultaneously form a first under groove 203-1 on a top surface of the first under pad 203. Referring to fig. 29, the first upper pad 205 may be formed on the first lower pad 203 and the first lower groove 203-1 by electroplating or electroless plating. Due to the presence of the first lower groove 203-1, a portion of the first upper pad 205 may sink into the first lower groove 203-1 and simultaneously form a first upper groove 205-1 on a top surface of the first upper pad 205.

Fig. 30 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device 100F according to an embodiment of the present disclosure.

Referring to fig. 30, an intermediate stage semiconductor device may be fabricated by a process similar to that illustrated in fig. 27 and 28. A first middle pad 207 may be formed on the first lower pad 203 and the first lower groove 203-1 by electroplating or electroless plating. Due to the presence of the first lower groove 203-1, a portion of the first middle pad 207 may sink into the first lower groove 203-1 and simultaneously form a first middle groove 207-1 on a top surface of the first middle pad 207. A first upper pad 205 may be formed on the first middle pad 207 and the first middle groove 207-1 by electroplating or electroless plating. Due to the presence of the first middle groove 207-1, a portion of the first upper pad 205 may sink into the first middle groove 207-1 and simultaneously form a first upper groove 205-1 on a top surface of the first upper pad 205.

Fig. 31 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device 100G according to an embodiment of the present disclosure. Fig. 32 is a top view of an intermediate-stage semiconductor device 100G according to an embodiment of the present disclosure. FIG. 33 is a schematic cross-sectional view taken along section line A-A' of FIG. 32 according to the present disclosure. For clarity of presentation, some components of the semiconductor element 100G of the present disclosure are not shown in fig. 32. Fig. 34 to 36 are schematic cross-sectional views of a part of a process for manufacturing a semiconductor device 100G according to another embodiment of the present disclosure.

Referring to fig. 31, an intermediate stage semiconductor device may be fabricated by a process similar to that illustrated in fig. 15-23. A photolithography process may be performed to define the location of a stress relief structure opening 301-1. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form the stress relief structure opening 301-1 through the second passivation layer 603 and the first passivation layer 601. The stress relief structure openings 301-1 may be disposed away from the first pad structure 201.

Referring to fig. 32 and 33, a stress relief structure 301 may be formed in the stress relief structure opening 301-1. The stress relieving structure 301 may include a conductive frame 303 and a plurality of isolation segments 305. In particular, a conductive layer may be formed to fill the stress relief structure opening 301-1. A first planarization process, such as chemical mechanical polishing, may be performed to expose the top surface of the second passivation layer 603. A photolithography process may be performed to define the locations of the isolation segments 305. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of openings in the conductive layer and simultaneously convert the conductive layer into a conductive frame 303. A filling layer may be formed to fill the plurality of openings. A second planarization process, such as chemical mechanical polishing, may be performed to expose the top surface of the second passivation layer 603 and simultaneously form the plurality of isolation segments 305.

Referring to fig. 34, an eighth isolation film 515 may be formed on the second passivation layer 603. A second conductive via 125 may be formed in the eighth isolation film 515 and located on the first pad structure 201. A redistribution layer 127 may be formed on the eighth isolation film 515 and on the second conductive via 125. A third passivation layer 605 may be formed on the eighth isolation film 515 and the redistribution layer 127. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps. A fourth passivation layer 607 may be formed on the third passivation layer 605. A second pad opening 401-1 may be formed to pass through the fourth passivation layer 607 and the third passivation layer 605. A portion of a top surface of the redistribution layer 127 may be exposed through the second pad opening 401-1. Referring to fig. 35 and 36, a second pad structure 401 having a second upper recess 405-1 may be formed by a process similar to that illustrated in fig. 20-24.

Fig. 37 and 38 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device 100I according to an embodiment of the present disclosure.

Referring to fig. 37, an intermediate stage semiconductor device may be fabricated by a process similar to that illustrated in fig. 31-34. A photolithography process may be performed to define the location of a second base recess 127-1 on a top surface of the redistribution layer 127. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form the second basic recess 127-1. After the formation of the second basic recess 127-1, a cleaning process 701 and a passivation process 703 may be performed. Referring to fig. 38, a second lower pad 403, a second lower groove 403-1, a second upper pad 405, and a second upper groove 405-1 may be sequentially formed by a process similar to that illustrated in fig. 27 to 29.

Due to the design of the semiconductor device of the present disclosure, the first upper recess 205-1 or the second upper recess 405-1 may serve as a guide (guide) for a probe tip to prevent the sliding probe tip from moving out of the first upper recess 205-1 or the second upper recess 405-1. Thus, the surrounding passivation layer remains intact even if the probe tip slips. As a result, the yield of the semiconductor device can be improved, and the performance of the semiconductor device can be improved. In addition, the passivation layer 703 can reduce poor sidewall growth of multiple passivation layers. Furthermore, the stress relief structure 301 can dissipate a stress of a wiring process; therefore, delamination (delamination) of the plurality of isolation layers or the plurality of passivation layers may be reduced. As a result, the yield of the semiconductor device can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this application.