阅读说明：本技术 半导体装置及制造半导体装置的方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 李南宰 于 2020-05-22 设计创作，主要内容包括：半导体装置及制造半导体装置的方法。半导体装置包括：第一芯片,其包括第一基板、第一单元阵列、第一金属布线和第一接合结构,其中第一接合结构包括穿过第一金属布线的第一贯穿部和形成在第一基板中的第一接合部；以及第二芯片,其接合至第一芯片,包括第二基板、第二单元阵列、第二金属布线和第二接合结构,其中第二接合结构包括穿过第二金属布线的第二贯穿部和形成在第二基板中的第二接合部。第一芯片的第一接合部被配置为接合至第二芯片的第二贯穿部。(A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure, wherein the first bonding structure includes a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate; and a second chip bonded to the first chip, including a second substrate, a second cell array, a second metal wiring, and a second bonding structure, wherein the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The first bonding portion of the first chip is configured to be bonded to the second penetrating portion of the second chip.)

1. A semiconductor device, comprising:

a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure, wherein the first bonding structure includes a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate; and

a second chip bonded to the first chip, the second chip including a second substrate, a second cell array, a second metal wiring, and a second bonding structure, wherein the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate,

wherein the first bonding portion of the first chip is configured to be bonded to the second penetrating portion of the second chip.

2. The semiconductor device according to claim 1, wherein a width of the first junction portion is wider than a width of the first penetration portion, and wherein

Wherein a width of the second engaging portion is wider than a width of the second penetrating portion.

3. The semiconductor device according to claim 1, wherein the first chip further comprises an insulating spacer interposed between the first bonding portion and the first substrate.

4. The semiconductor device according to claim 1, wherein a width of the first bonding portion is wider than a width of the second penetrating portion.

5. The semiconductor device according to claim 1, wherein the first cell array is formed on a front surface of the first substrate, and the first bonding portion is exposed to an outside of the first chip through a rear surface of the first substrate.

6. The semiconductor device according to claim 1, wherein the first substrate is located between the first cell array and the second cell array.

7. The semiconductor device according to claim 1, wherein the second metal wiring is located between the first substrate and the second substrate.

8. The semiconductor device according to claim 1, wherein the second chip further comprises an interlayer insulating film covering the second metal wiring,

wherein the first substrate includes a front surface on which the first cell array is formed,

wherein the first substrate includes a rear surface on an opposite side of the front surface, and

wherein the interlayer insulating film and the rear surface of the first substrate are bonded to each other.

9. The semiconductor device according to claim 1, wherein the first chip further comprises a first peripheral circuit.

10. The semiconductor device according to claim 1, wherein the first cell array comprises a memory string.

11. A semiconductor device, comprising:

a first chip including a first substrate, a first metal wiring, a first bonding structure, and a first interlayer insulating film, wherein the first metal wiring and the first interlayer insulating film are formed on a front surface of the first substrate, and the first bonding structure includes a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate and exposed to an outside of the first chip through a rear surface of the first substrate; and

a second chip bonded to the first chip, the second chip including a second substrate, a second metal wiring, a second bonding structure, and a second interlayer insulating film, wherein the second metal wiring and the second interlayer insulating film are formed on a front surface of the second substrate, and the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate and exposed to an outside of the second chip through a rear surface of the second substrate,

wherein the rear surface of the first substrate and the second interlayer insulating film are bonded to each other at a bonding interface between the first chip and the second chip, and the first bonding portion is bonded to the second penetration portion.

12. The semiconductor device according to claim 11, wherein a width of the first junction portion is wider than a width of the first penetration portion, and wherein

Wherein a width of the second engaging portion is wider than a width of the second penetrating portion.

13. The semiconductor device according to claim 11, wherein the first bonding portion has rounded sidewalls.

14. The semiconductor device of claim 11, wherein the first and second bonding structures comprise a conductive material.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a first cell array on a front surface of a first substrate;

forming a first metal wiring on the front surface of the first substrate;

forming a first interlayer insulating film on the first metal wiring;

forming a first opening through the first interlayer insulating film and the first metal wiring to expose the front surface of the first substrate;

forming a second opening connected to the first opening, wherein the second opening is formed in the first substrate;

forming a first engagement structure comprising a first through portion in the first opening and a first engagement portion in the second opening; and

exposing the first bonding structure through a rear surface of the first substrate.

16. The method of claim 15, further comprising the steps of:

forming a second cell array on a front surface of a second substrate;

forming a second metal wiring on the front surface of the second substrate;

forming a second interlayer insulating film on the second metal wiring;

forming a third opening through the second interlayer insulating film and the second metal wiring to expose the front surface of the second substrate;

forming a fourth opening connected to the third opening, wherein the fourth opening is formed in the second substrate;

forming a second engagement structure comprising a second through portion in the third opening and a second engagement portion in the fourth opening; and

exposing the second bonding structure through a rear surface of the second substrate.

17. The method of claim 16, further comprising the steps of:

bonding the first bonding portion of the first bonding structure to the second penetrating portion of the second bonding structure.

18. The method according to claim 17, wherein the rear surface of the first substrate is bonded to the second interlayer insulating film when the first bonding portion is bonded to the second penetrating portion.

19. The method of claim 17, wherein the first engaging portion has a width that is wider than a width of the second through portion.

20. The method of claim 15, further comprising the steps of:

a first peripheral circuit is formed on the front surface of the first substrate.

21. The method of claim 15, wherein the first array of cells comprises a memory string.

22. The method of claim 15, wherein the step of forming the second opening is performed by an isotropic etching process.

23. The method of claim 15, wherein the width of the second opening is wider than the width of the first opening.

24. The method of claim 15, further comprising the steps of:

forming a protective spacer on an inner wall of the first opening before forming the second opening; and

removing the protective spacer after forming the second opening.

25. The method of claim 15, further comprising the steps of:

forming an insulating spacer in the second opening before forming the first bonding structure.

26. The method of claim 15, wherein exposing the first bonding structure comprises grinding the back surface of the first substrate to expose the first bond.

27. A method of manufacturing a semiconductor device, the method comprising:

forming a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure, wherein the first bonding structure includes a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate;

forming a second chip bonded to the first chip, the second chip including a second substrate, a second cell array, a second metal wiring, and a second bonding structure, wherein the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate; and

bonding the first chip bond to the second chip to bond the first bonding portion of the first chip to the second through portion of the second chip.

28. The method of claim 27, wherein the first chip further comprises first peripheral circuitry.

29. The method of claim 27, wherein the first engaging portion has a width that is wider than a width of the first penetrating portion.

30. The method of claim 27, wherein forming the first chip comprises grinding a back surface of the first substrate to expose the first bonding portion of the first bonding structure.

31. The method of claim 27, wherein the second chip further comprises an interlayer insulating film covering the second metal wiring, and the first chip is bonded to the second chip such that the interlayer insulating film and the rear surface of the first substrate are in contact with each other.

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the same.

Background

A non-volatile memory element is one that retains stored data regardless of whether the power supply is on or off. It has been difficult to increase the integration density of a two-dimensional nonvolatile memory device in which a single layer of memory cells is formed on a substrate. Therefore, a three-dimensional nonvolatile memory device in which memory cells are stacked on a substrate in a vertical direction has been proposed.

The three-dimensional nonvolatile memory element includes interlayer insulating films and gate electrodes stacked in an alternating manner. The three-dimensional nonvolatile memory element further includes a channel film passing through the interlayer insulating film, and memory cells stacked along the channel film. Various structures and manufacturing methods have been developed to improve the operational reliability of the nonvolatile memory element having such a three-dimensional structure.

Disclosure of Invention

The semiconductor device according to an embodiment of the present disclosure may include: a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure, wherein the first bonding structure includes a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate; and a second chip bonded to the first chip, including a second substrate, a second cell array, a second metal wiring, and a second bonding structure, wherein the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The first bonding portion of the first chip is configured to be bonded to the second penetrating portion of the second chip.

A semiconductor device according to an embodiment of the present disclosure may include a first chip including a first substrate, a first metal wiring, a first bonding structure, and a first interlayer insulating film, wherein the first metal wiring and the first interlayer insulating film are formed on a front surface of the first substrate, and the first bonding structure includes a first penetration portion passing through the first metal wiring and a first bonding portion formed in the first substrate and exposed to an outside of the first chip through a rear surface of the first substrate; and a second chip bonded to the first chip, including a second substrate, a second metal wiring, a second bonding structure, and a second interlayer insulating film, wherein the second metal wiring and the second interlayer insulating film are formed on a front surface of the second substrate, and the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate and exposed to an outside of the second chip through a rear surface of the second substrate. The rear surface of the first substrate and the second interlayer insulating film are bonded to each other at a bonding interface between the first chip and the second chip. The first engaging portion may be engaged to the second through portion.

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include: forming a first cell array on a front surface of a first substrate; forming a first metal wiring on a front surface of a first substrate; forming a first interlayer insulating film on the first metal wiring; forming a first opening through the first interlayer insulating film and the first metal wiring to expose the front surface of the first substrate; forming a second opening connected to the first opening, wherein the second opening is formed in the first substrate; forming a first engagement structure including a first through portion in the first opening and a first engagement portion in the second opening; and exposing the first bonding structure through the rear surface of the first substrate.

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include: forming a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure, wherein the first bonding structure includes a first through portion passing through the first metal wiring and a first bonding portion formed in the first substrate; forming a second chip bonded to the first chip, the second chip including a second substrate, a second cell array, a second metal wiring, and a second bonding structure, wherein the second bonding structure includes a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate; and bonding the first chip junction to the second chip to bond the first bonding portion of the first chip to the second through portion of the second chip.

Drawings

Fig. 1A to 1C are sectional views illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

Fig. 2A to 2D are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

Fig. 3 is a flowchart for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 4A to 4G are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 5A to 5C are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 6 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

Fig. 7 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

Fig. 8 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

FIG. 9 is a block diagram illustrating a computing system in accordance with embodiments of the present disclosure.

Detailed Description

Only the specific structural or functional descriptions of the embodiments according to the concepts disclosed in the present specification or application are illustrated to describe the embodiments according to the concepts of the present disclosure. Embodiments according to the disclosed concept may be implemented in various forms, and the description is not limited to the embodiments described in the present specification or application.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present disclosure.

In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

A semiconductor device having a stable structure and improved reliability can be provided. In addition, in manufacturing a semiconductor device, process difficulty can be reduced, a process can be simplified, and cost can be reduced.

Fig. 1A to 1C are sectional views illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 1A, the semiconductor apparatus may include a CHIP. The CHIP may include a substrate SUB, a metal wiring ML, and a bonding structure BS. In addition, the CHIP may further include at least one of a main structure MS, an interlayer insulating film IL, and an insulating spacer SP.

The CHIP may include a main region MR and a bonding pad region BR. The main structure MS may be located in the main region MR, and the bonding structure BS may be located in the bonding pad region BR. The metal wiring ML and the interlayer insulating film IL may be located in the main region MR and the bonding pad region BR.

The substrate SUB may be a semiconductor substrate. The substrate SUB may include a front surface FS and a rear surface RS on an opposite side of the front surface FS. The main structure MS and the interlayer insulating film IL may be formed on the front surface FS of the substrate SUB. The interlayer insulating film IL may be a single film or a multilayer film. The interlayer insulating film IL may include an insulating material such as an oxide or a nitride. The main structure MS and the metal wiring ML may be formed in the interlayer insulating film IL.

The main structure MS may include a cell array, a peripheral circuit, or a combination thereof. In addition, the main structure MS may further include an interconnection structure electrically connected to the cell array or the peripheral circuit. The interconnect structure may include contact plugs, wires, and the like.

The cell array may include memory cells stacked on a substrate SUB. For example, a cell array includes memory strings connected between bit lines and source lines. The memory string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor all connected in series. Alternatively, the memory string may include at least one drain select transistor, a plurality of drain-side memory cells, at least one pipe transistor, a plurality of source-side memory cells, and at least one source select transistor all connected in series. The peripheral circuits are used to drive the memory strings and may include transistors, capacitors, resistors, inductors, amplifiers, logic circuits, and the like.

The CHIP may be a unit CHIP, a peripheral circuit CHIP, a memory CHIP, or the like, based on the type, function, and other characteristics of the main structure MS included in the CHIP. When the main structure MS includes a cell array, the CHIP may be a cell CHIP. When the main structure MS includes a peripheral circuit, the CHIP may be a peripheral circuit CHIP. When the main structure MS includes both the cell array and the peripheral circuit, the CHIP may be a memory CHIP. In addition, a plurality of CHIP CHIPs may be bonded to each other.

The bonding structures BS may bond the CHIPs CHIP and provide electrical connections between the CHIPs CHIP. The bonding structure BS may pass through the CHIP by passing through the interlayer insulating film IL and the substrate SUB.

The bonding structure BS may include a penetration portion TP and a bonding portion BP. The penetrating portion TP may penetrate the interlayer insulating film IL and may penetrate the metal wiring ML. The penetration portion TP may be electrically connected to the metal wiring ML. The bonding portion BP may be formed in the substrate SUB and may be exposed to the outside of the CHIP through the rear surface RS of the substrate SUB.

The CHIP may include a first surface S1 and a second surface S2 on the opposite side of the first surface S1. Here, the first surface S1 may be an upper surface of the CHIP, and the second surface S2 may be a lower surface of the CHIP. However, the upper surface and the lower surface are relative terms, and based on a perspective view, the first surface S1 may be the lower surface and the second surface S2 may be the upper surface. The penetration portion TP may be exposed to the outside of the CHIP through the first surface S1 of the CHIP, and the bonding portion BP may be exposed to the outside of the CHIP through the second surface S2 of the CHIP.

The engagement portion BP may have rounded sidewalls. The sidewall of the engagement portion BP may have a curvature. The engagement portion BP may have an upper surface adjacent to the front surface FS, a lower surface coplanar with the rear surface RS, and a sidewall coupling the upper and lower surfaces. In a cross-sectional view, the joint BP may have a rounded corner where the upper surface and the sidewall meet. The joint BP may have a rounded corner where the front surface FS of the substrate SUB and the side wall of the joint BP meet. In addition, an insulating spacer SP may be interposed between the joint portion BP and the substrate SUB. The insulating spacer SP may include an insulating material such as an oxide or a nitride. The joint portion BP and the substrate SUB may be insulated from each other by an insulating spacer SP.

The penetration portion TP and the engagement portion BP may have substantially the same width or may have different widths. The engagement portion BP may have a width wider than that of the penetration portion TP. The penetration portion TP may have a first width W1 at the first surface S1, and the joint portion BP may have a second width W2 at the second surface S2. The second width W2 may be substantially the same as the first width W1 or may be wider than the first width W1.

The bonding structure BS may be a single film or a multilayer film. The penetration portion TP and the joining portion BP may be integrally connected single films. The bonding structure BS may include a conductive material, and may include a metal such as copper.

Referring to fig. 1B and 1C, the semiconductor apparatus may include a first CHIP _1 and a second CHIP _ 2. The second CHIP _2 may be bonded to the first CHIP _1, and a bonding interface IF may exist between the first CHIP _1 and the second CHIP _ 2.

The first CHIP _1 may include a first substrate SUB _1, a first metal wiring ML1, a first bonding structure BS1, a first main structure MS1, a first interlayer insulating film IL1, and a first insulating spacer SP 1. The first bonding structure BS1 may include a first penetration portion TP1 and a first bonding portion BP 1. The first substrate SUB1 may include a first front surface FS1 and a first rear surface RS 1. The first bonding part BP1 may be exposed to the outside of the first CHIP _1 from the first rear surface RS1 of the first base plate SUB _ 1.

The second CHIP _2 may include a second substrate SUB _2, a second metal wiring ML2, a second bonding structure BS2, a second main structure MS2, a second interlayer insulating film IL2, and a second insulating spacer SP 2. The second bonding structure BS2 may include a second penetration portion TP2 and a second bonding portion BP 2. The second substrate SUB2 may include a second front surface FS2 and a second rear surface RS 2. The second bonding portion BP2 may be exposed to the outside of the second CHIP _2 from the second rear surface RS2 of the second substrate SUB _ 2.

The first substrate SUB1 may be located between the first main structure MS1 and the second main structure MS 2. The second main structure MS2 may be located between the first substrate SUB _1 and the second substrate SUB _ 2. The second metal wiring line ML2 may be located between the first substrate SUB _1 and the second substrate SUB _ 2. For reference, fig. 1B illustrates a structure in which a first CHIP _1 is located on a second CHIP _ 2. However, the second CHIP _2 may be located on the first CHIP _ 1.

The first and second through portions BP1 and TP2 may be joined to each other at a joint interface IF. The first and second junctions BP1 and TP2 may be in direct contact with each other and may be electrically connected to each other. In addition, the first rear surface RS1 of the first substrate SUB1 and the second interlayer insulating film IL2 may be bonded to each other at a bonding interface IF. For example, the first rear surface RS1 of the first substrate SUB1 and the second interlayer insulating film IL2 may be bonded to each other by Van der Waals force (Van der Waals force).

The structure in the first CHIP _1 and the structure in the second CHIP _2 may be positioned to correspond to each other. Based on the bonding interface IF, the first main structure MS1 and the second main structure MS2 may be aligned with each other and may be arranged one above the other. Based on the bonding interface IF, the first bonding structure BS1 and the second bonding structure BS2 may also be positioned in alignment with each other and may be arranged one above the other. Referring to fig. 1B, the first bonding structure BS1 and the second bonding structure BS2 may be arranged such that centers of the first bonding structure BS1 and the second bonding structure BS2 are aligned.

Referring to fig. 1C, the first CHIP _1 and the second CHIP _2 may not be aligned, and the first bonding structure BS1 and the second bonding structure BS2 may be arranged such that centers of the first bonding structure BS1 and the second bonding structure BS2 may not be aligned. Since the first bonding portion BP1 is wider than the second penetration portion TP2, the first CHIP _1 and the second CHIP _2 may be electrically connected to each other even if the first CHIP _1 and the second CHIP _2 are not aligned.

According to the above structure, the joint portions BP1 and BP2 are formed in the first substrate SUB1 and the second substrate SUB2, respectively. In addition, the first CHIP _1 and the second CHIP _2 may be electrically connected to each other using the first bonding structure BS1 and the second bonding structure BS 2. Accordingly, since no additional structure such as a bump or a non-conductive film (NCF) is interposed between the first CHIP _1 and the second CHIP _2, the height of the package may be reduced.

Since the width of the first joint portion BP1 is wider than the width of the second penetration portion TP2 at the joint interface IF, the error margin of alignment can be increased. In addition, since the arrangement of the power lines is free when the wiring is arranged, the speed of the semiconductor device can be increased.

Fig. 2A to 2D are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 2A, the first CHIP _1 may include a first substrate SUB _1, a first metal wiring ML1, and a first bonding structure BS 1. In addition, the first CHIP _1 may further include at least one of the first main structure MS1, the first interlayer insulating film IL1, and the first insulating spacer SP 1.

The first main structure MS1 may include a cell array CA and a peripheral circuit PR. The cell array CA may include a stack ST and a channel structure CH. The laminate ST may include conductive films 21 and insulating films 22 stacked in an alternating manner. The channel structure CH may include a channel film 24 passing through the laminate ST and a memory film 23 interposed between the channel film 24 and the conductive film 21. The memory film 23 may further include at least one of a charge blocking film, a data storage film, and a tunnel insulating film. The trench film 24 may have a tubular structure, and a gap-filling insulating film (not shown) may be formed inside the trench film 24. The peripheral circuit PR may include a transistor TR, and the transistor TR may include a gate electrode 26 and a gate insulating film 25. The peripheral circuit PR may be located at the same level as the cell array or may be located at a different level from the cell array.

In addition, the first main structure MS1 may further include an interconnect structure IT connected to the cell array CA or the peripheral circuit PR. The interconnect structure IT may include contact plugs 27, wirings 28, and the like.

The second CHIP _2 may include a second substrate SUB _2, a second metal wiring ML2, and a second bonding structure BS 2. In addition, the second CHIP _2 may further include at least one of a second main structure MS2, a second interlayer insulating film IL2, and a second insulating spacer SP 2.

The second main structure MS2 may include a cell array CA and a peripheral circuit PR. In addition, the second main structure MS2 may further include an interconnect structure IT connected to the cell array CA or the peripheral circuit PR. Since the detailed configuration of the second main structure MS2 is similar to that of the first main structure MS1, a repetitive description thereof will be omitted.

Referring to fig. 2B, the first CHIP _1 may include a first main structure MS1, and the first main structure MS1 may include a cell array CA. In addition, the first main structure MS1 may further include an interconnect structure connected to the cell array CA.

The second CHIP _2 may include a second main structure MS2, and the second main structure MS2 may include a peripheral circuit PR. In addition, the second main structure MS2 may further include an interconnect structure connected to the peripheral circuit PR.

Referring to fig. 2C, the first CHIP _1 may include a first main structure MS1, and the first main structure MS1 may include a cell array CA. In addition, the first main structure MS1 may further include an interconnect structure connected to the cell array CA.

The second CHIP _2 may include a second main structure MS2, and the second main structure MS2 may include a cell array CA. In addition, the second main structure MS2 may further include an interconnect structure IT connected to the cell array CA. For reference, although not shown in this drawing, a third CHIP including peripheral circuits may be further bonded to the first CHIP _1 or the second CHIP _ 2.

Referring to fig. 2D, the first CHIP _1 may include a first main structure MS1, and the first main structure MS1 may include a cell array CA. In addition, the first main structure MS1 may further include an interconnect structure connected to the cell array CA.

The second CHIP _2 may include a second main structure MS2, and the second main structure MS2 may include a cell array CA and a peripheral circuit PR. In addition, the second main structure MS2 may further include an interconnect structure connected to the cell array CA or the peripheral circuit PR.

According to the above structure, a plurality of chips can be bonded to each other. The bonded chips may have the same main structure or may have different main structures. The bonded chips may be electrically connected to each other and may share a portion of the main structure. For example, some of the bonded chips may include peripheral circuitry, and in another embodiment, the chips may share peripheral circuitry.

Fig. 3 is a flowchart for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

First, the FAB process is performed (S310). Here, the FAB process is also referred to as a wafer level process or an in-line (in-line) process. The FAB process requires repeated patterning of the wafer to form the die with integrated circuits. Here, the die may be a chip or a semiconductor chip. The FAB process may include a process of forming a cell array on a substrate, a process of forming a peripheral circuit on a substrate, or a process of forming a cell array and a peripheral circuit on a substrate. In addition, the FAB process may include a process of forming an interconnect connected to a cell array or a peripheral circuit.

The FAB process may further include wafer testing. Wafer testing is used to test the electrical characteristics of the die. Wafer testing can determine bad die and normal die. In addition, the FAB process may further include a process of forming a bonding structure. For example, the bonding structure may be formed after the interconnect is formed. Alternatively, the bonding structure may be formed after performing wafer testing.

Next, a packaging process is performed (S320). The packaging process requires the connection of electrical wiring so that the chip can receive external power or communicate with external devices. The packaging process may also require packaging the chip to protect the chip from physical shock or chemical reaction. The packaging process may include a grinding process, a dicing process, a bonding process, a marking process, a molding process, and the like. Here, the bonding process may include a process of bonding the chip and the chip to each other, a process of bonding the chip and the wafer to each other, a process of bonding the wafer and the wafer to each other, a wire bonding process, and the like.

According to the above process, the bonding structure is formed before the packaging process. For example, the bonding structure is formed in the FAB process in advance. Therefore, it is not necessary to form bumps, a non-conductive film (NCF), and the like in the packaging process. In addition, the chips may be physically and electrically connected to each other at the same time through a bonding process. Therefore, the packaging process can be simplified and the cost can be reduced.

Fig. 4A to 4G are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, a repetitive description will be omitted.

Referring to fig. 4A, a main structure MS is formed on a substrate 40. The substrate 40 may be a semiconductor substrate including a semiconductor material such as silicon. The substrate 40 may be a wafer. The substrate 40 may include a main region MR and a bonding pad region BR. The main region MR may include a cell array region CAR and a peripheral circuit region PRR. For reference, the main region MR may include only the cell array region CAR or only the peripheral circuit region PRR.

Next, the main structure MS is formed on the front surface FS of the substrate 40. The main structure MS may be formed in the main region MR, and may include at least one of a cell array and a peripheral circuit. A cell array may be formed in the cell array region CAR, and peripheral circuits may be formed in the peripheral circuit region PRR.

The cell array CA may include a stack ST and a channel structure CH. The laminate ST may include conductive films 51 and insulating films 52 stacked in an alternating manner. The channel structure CH may include a channel film 54 passing through the laminate ST and a memory film 53 interposed between the channel film 54 and the conductive film 51. The memory film 53 may further include at least one of a charge blocking film, a data storage film, and a tunnel insulating film. The trench film 54 may have a tubular structure, and a gap-filling insulating film (not shown) may be formed inside the trench film 54. The peripheral circuit PR may include a transistor TR, and the transistor TR may include a gate electrode 56 and a gate insulating film 55.

In addition, the main structure MS may further include at least one of an interconnect structure IT connected to the cell array CA and an interconnect structure IT connected to the peripheral circuit PR. The interconnect structure IT may include contact plugs 57, wirings 58, and the like.

The first interlayer insulating film 41 may be formed in the main region MR and the bonding pad region BR. The first interlayer insulating film 41 may include an insulating material such as an oxide or a nitride. The first interlayer insulating film 41 may be a single film or a multilayer film. A main structure MS such as a cell array, a peripheral circuit, and an interconnect structure may be formed in the first interlayer insulating film 41. The first interlayer insulating film 41 may be formed before or after forming a cell array, a peripheral circuit, or an interconnect structure.

Next, the metal wiring 42 is formed on the first interlayer insulating film 41. The metal wiring 42 may be formed in the main region MR and the bonding pad region BR. For example, after a metal film is formed on the interlayer insulating film 41, a mask pattern is formed on the metal film. Next, the metal film is etched by using the mask pattern as an etching barrier to form the metal wiring 42. After the metal wiring 42 is formed, the mask pattern may be removed, and a cleaning process may be performed. The metal wiring 42 may include a metal such as aluminum.

Referring to fig. 4B, a second interlayer insulating film 43 is formed on the metal wiring 42. After depositing an insulating material on the metal wiring 42, a planarization process may be performed to form the second interlayer insulating film 43. The planarization process may be performed by a Chemical Mechanical Polishing (CMP) method. The second interlayer insulating film 43 may include an insulating material such as an oxide or a nitride. For example, the second interlayer insulating film 43 may include an oxide film formed by a method of High Density Plasma (HDP).

Next, the first opening OP1 passing through the second interlayer insulating film 43, the metal wiring 42, and the first interlayer insulating film 41 and exposing the substrate 40 is formed. The first opening OP1 may be formed by using an etching process. First, a mask pattern 44 for forming a junction structure is formed on the second interlayer insulating film 43. The mask pattern 44 may cover the cell array region CAR and the peripheral circuit region PRR and partially expose the landing pad region BR. Next, the first opening OP1 is formed by etching the second interlayer insulating film 43, the metal wiring 42, and the first interlayer insulating film 41 using the mask pattern 44 as an etching barrier. After the first opening OP1 is formed, the mask pattern 44 may be removed and a cleaning process may be performed.

The first opening OP1 may be formed to a depth to expose the substrate 40. The first opening OP1 may pass through the metal wiring 42, and the metal wiring 42 may be exposed through the first opening OP 1.

Referring to fig. 4C, the protective spacer 45 is formed in the first opening OP 1. The protective spacer 45 protects the first interlayer insulating film 41, the metal wiring 42, and the second interlayer insulating film 43 in a subsequent process. The protective spacer 45 may include a material having a high etch selectivity with respect to the substrate 40. When the substrate 40 includes silicon, the protective spacer 45 may include nitride. In an embodiment, after the spacer material is formed along the inner surface of the first opening OP1, an etch-back process is performed. The spacer material formed on the lower surface of the first opening OP1 may be etched by an etch-back process, and the protective spacer 45 may be formed.

Next, the substrate 40 is etched to form a second opening OP 2. The second opening OP2 may be connected to the first opening OP 1. The second opening OP2 may be wider than the first opening OP 1. The second opening OP2 may be formed by using an isotropic etching process. For example, the second opening OP2 is formed by using a dry cleaning process, a wet etching process, or a combination thereof. In a cross-sectional view, the second opening OP2 may have corners between the upper surface and the sidewall and between the lower surface and the sidewall. In addition, at least one corner may have a rounded shape. For example, the second opening OP2 may have the shape of a sphere.

Referring to fig. 4D, the insulating spacer 46 is formed in the second opening OP 2. The bonding structure and the substrate 40 formed in the subsequent process may be insulated from each other by the insulating spacer 46. The insulating spacers 46 may comprise an insulating material such as an oxide or nitride. The insulating spacer 46 may be formed along an inner surface of the second opening OP 2. For example, the surface of the second substrate 40 exposed through the second opening OP2 is oxidized to form the insulating spacer 46. Since the metal wiring 42 exposed through the first opening OP1 is protected by the protective spacer 45, the metal wiring 42 may be prevented from being oxidized in the oxidation process.

Referring to fig. 4E, the protective spacer 45 is removed. Next, the engaging structure 47 is formed in the first opening OP1 and the second opening OP 2. The engagement structure 47 may include a through portion 47A in the first opening OP1 and an engagement portion 47B in the second opening OP 2. The penetrating portion 47A may be in contact with the metal wiring 42. The engaging portion 47B may be formed in the substrate 40 and may be in contact with the insulating spacer 46.

The bonding structure 47 may include a metal such as copper, and may be formed by a deposition method. The bonding structure 47 is formed, for example, by an Electroless Plating (EP) deposition method. After forming a metal film to fill the first opening OP1 and the second opening OP2, the bonding structure 47 may be formed by planarizing the metal film. The planarization process may be performed based on a Chemical Mechanical Polishing (CMP) method.

Referring to fig. 4F, the substrate 40 is turned upside down so that the rear surface RS of the substrate 40 is on top. Next, the substrate 40 is partially removed until the bonding structure 47 is exposed. Therefore, the bonding structures 47 may be exposed on the rear surface RS of the substrate 40. Specifically, the engaging portion 47B may be exposed on the rear surface RS of the substrate 40. In an embodiment, the substrate 40 may be partially removed by using a back grinding method, a Chemical Mechanical Polishing (CMP) method, or a wet etching process, or a combination thereof. In the process of partially removing the substrate 40, a part of the bonding portion 47B and a part of the insulating spacer 46 may be removed. In addition, the width of the remaining bonding portion 47B may be adjusted according to the amount of the substrate 40 removed.

Referring to fig. 4G, the first CHIP _1 and the second CHIP _2 are bonded to each other. The first CHIP _1 and the second CHIP _2 may be prepared by repeating the processes of fig. 4A to 4F. In addition, in order to prepare the first CHIP _1 and the second CHIP _2, a process of cutting the wafer into CHIP units may be further performed. For example, the substrate 40 on which the main structure MS, the bonding structures 47, and the like are formed is cut and separated into a plurality of chips.

The first CHIP _1 and the second CHIP _2 may include the same main structure MS or may include different main structures MS. Two or more chips may be bonded to each other. In addition to bonding the chips and the chips to each other, the wafer and the wafer or the wafer and the chips may be bonded to each other.

The second interlayer insulating film 43 of the first CHIP _1 and the substrate 40 of the second CHIP _2 may be bonded to each other through a bonding process. For example, the rear surface RS of the substrate 40 of the second CHIP _2 may be in contact with the second interlayer insulating film 43 of the first CHIP _1 and bonded to the second interlayer insulating film 43 of the first CHIP _ 1.

The bonding structure 47 of the first CHIP _1 and the bonding structure 47 of the second CHIP _2 may be bonded to each other. For example, the through portion 47A of the first CHIP _1 and the bonding portion 47B of the second CHIP _2 may be bonded to each other. Accordingly, the bonding structure 47 of the first CHIP _1 and the bonding structure 47 of the second CHIP _2 may be electrically connected to each other, and the first CHIP _1 and the second CHIP _2 may be electrically connected to each other. In addition, since the bonding portion 47B of the second CHIP _2 is wider than the penetrating portion 47A of the first CHIP _1, it is possible to increase an error margin for alignment between the first CHIP _1 and the second CHIP _ 2.

Next, although not shown in this figure, additional packaging processes such as wire bonding, molding, and labeling may be performed.

Among the above methods, fig. 4A to 4E may correspond to the FAB process S310 of fig. 3, and fig. 4F and 4G may correspond to the packaging process S320 of fig. 3. According to the above method, the bonding structure can be formed in the FAB process. Therefore, it is not necessary to form a bump, a non-conductive film (NCF), or the like. In addition, the physical connection and the electrical connection between the first CHIP _1 and the second CHIP _2 may be simultaneously performed. Therefore, the packaging process can be simplified and the cost can be reduced.

Fig. 5A to 5C are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, and relate to a method of forming a bonding structure. Hereinafter, a repetitive description will be omitted.

Referring to fig. 5A, a second opening OP2 located in the substrate 60 and a first opening OP1 passing through the second interlayer insulating film 63, the metal wiring 62, and the first interlayer insulating film 61 are formed.

Next, the insulating material 64 is formed in the first opening OP1 and the second opening OP 2. For example, an insulating material is deposited along inner surfaces of the first and second openings OP1 and OP 2. An insulating material 64 may also be formed on the second interlayer insulating film 63. Insulating material 64 may include an oxide.

Referring to fig. 5B, the insulating material 64 is partially etched to expose the metal wiring 62 in the first opening OP 1. In order to partially etch the insulating material 64, a sacrificial film 65 and a mask pattern 66 may be used. First, a sacrificial film 65 and a mask pattern 66 are formed. The sacrificial film 65 may be formed to fill the second opening OP2 and to at least partially fill the first opening OP 1. The sacrificial film 65 may include a flowable material such as spin-on-carbon (SOC). A sacrificial film 65 may also be formed on the second interlayer insulating film 63.

Next, the insulating material 64 is etched using the mask pattern 66 as an etching barrier. Accordingly, the metal wiring 62 is exposed, and the insulating spacer 64A is formed. Next, the mask pattern 66, the sacrificial film 65, and the insulating material 64 may be removed, and a cleaning process may be performed.

Referring to fig. 5C, a bonding structure 67 is formed. The bonding structure 67 may include a penetrating portion 67A that contacts the metal wiring 62 and a bonding portion 67B formed in the substrate 60. The insulating spacer 64A may be interposed between the joint 67B and the substrate 60 to insulate the joint 67B and the substrate 60 from each other. In addition, the insulating spacer 64A may extend to a portion of the sidewall of the penetration portion 67A, and may be formed to surround a portion of the sidewall of the penetration portion 67A. The insulating spacer 64A may be interposed between the penetrating portion 67A and the first interlayer insulating film 61. However, the insulating spacer 64A is not interposed between the penetrating portion 67A and the metal wiring 62. Next, although not shown in this figure, the processes described above with reference to fig. 4F and 4G may be further performed.

According to the above-described manufacturing method, the insulating spacer 64A may be formed using a deposition process.

Fig. 6 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

Referring to fig. 6, the memory system 1000 includes a memory device 1200 and a controller 1100.

The memory device 1200 is used to store various data types such as text, graphics, and software code. The memory device 1200 may be a non-volatile memory. In addition, the memory device 1200 may have the structure described above with reference to fig. 1A to 5C. The memory device 1200 may be manufactured based on the manufacturing method described with reference to fig. 1A to 5C. As an embodiment, the memory device 1200 may include a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure. The first bonding structure may include a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate. The second chip may include a second substrate, a second cell array, a second metal wiring, and a second bonding structure. The second bonding structure may include a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The second chip may be bonded to the first chip. Specifically, the first bonding portion of the first chip and the second through portion of the second chip may be bonded to each other. Since the structure of the memory device 1200 and the method of manufacturing the memory device 1200 are the same as those described with reference to fig. 1A to 5C, a detailed description thereof will be omitted.

The controller 1100 is connected to a host and the memory device 1200 and is configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 is configured to control read operations, write operations, erase operations, background operations, and the like of the memory device 1200.

The controller 1100 includes a Random Access Memory (RAM)1110, a Central Processing Unit (CPU)1120, a host interface 1130, an error correction code circuit 1140, a memory interface 1150, and the like.

Here, the RAM 1110 may be used as an operation memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, and the like. For reference, a Static Random Access Memory (SRAM), a Read Only Memory (ROM), or the like may be used instead of the RAM 1110.

The CPU 1120 is configured to control the overall operation of the controller 1100. For example, CPU 1120 is configured to operate firmware such as a Flash Translation Layer (FTL) stored in RAM 1110.

The host interface 1130 is configured to perform interfacing with a host. For example, the controller 1100 communicates with the host through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a multi-media card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

The ECC circuit 1140 is configured to detect and correct errors contained in data read from the memory device 1200 using an Error Correction Code (ECC).

The memory interface 1150 is configured to perform an interface with the memory device 1200. The memory interface 1150 includes a NAND interface or a NOR interface, for example.

For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. Here, the buffer memory may be used to temporarily store data transferred to the outside through the host interface 1130 or to temporarily store data transferred from the memory device 1200 through the memory interface 1150. Further, the controller 1100 may further include a ROM storing code data for interfacing with a host.

As described above, since the memory system 1000 according to the embodiment of the present disclosure includes the memory device 1200 having an improved integration degree and improved characteristics, the integration degree and characteristics of the memory system 1000 may also be improved.

Fig. 7 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure. Hereinafter, a repetitive description will be omitted.

Referring to fig. 7, a memory system 1000 'includes a memory device 1200' and a controller 1100. In addition, the controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

Memory device 1200' may be a non-volatile memory. The memory device 1200' may have the structure described above with reference to fig. 1A to 5C, and may be manufactured according to the manufacturing method described with reference to fig. 1A to 5C. As an embodiment, the memory device 1200' may include a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure. The first bonding structure may include a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate. The second chip may include a second substrate, a second cell array, a second metal wiring, and a second bonding structure. The second bonding structure may include a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The second chip may be bonded to the first chip. Specifically, the first bonding portion of the first chip and the second through portion of the second chip may be bonded to each other. Since the structure of the memory device 1200 'and the method of manufacturing the memory device 1200' are the same as those described with reference to fig. 1A to 5C, a detailed description thereof will be omitted.

In addition, the memory device 1200' may be a multi-chip package configured by a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, and the plurality of groups are configured to communicate with the controller 1100 through the first to k-th channels CH1 to CHk. In addition, the memory chips belonging to a group are configured to communicate with the controller 1100 through a common channel. For reference, the memory system 1000' may be modified such that one memory chip is connected to one channel.

As described above, since the memory system 1000' according to the embodiment of the present disclosure includes the memory device 1200' having an improved integration degree and improved characteristics, the integration degree and characteristics of the memory system 1000' may also be improved. In particular, by configuring the memory device 1200 'in a multi-chip package, the data storage capacity of the memory system 1000' may be increased, and the driving speed may be increased.

Fig. 8 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. Hereinafter, a repetitive description will be omitted.

Referring to fig. 8, the computing system 2000 includes a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, and the like.

The memory device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, and the like. In addition, the memory device 2100 is electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like through the system bus 2600. For example, the memory device 2100 may be connected to the system bus 2600 by a controller (not shown) or may be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be executed by the CPU 2200, the RAM 2300, or the like.

Here, the memory device 2100 may be a nonvolatile memory. The memory device 2100 may have the structure described above with reference to fig. 1A to 5C, and may be manufactured according to the manufacturing method described with reference to fig. 1A to 5C. As an embodiment, the memory device 2100 may include a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure. The first bonding structure may include a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate. The second chip may include a second substrate, a second cell array, a second metal wiring, and a second bonding structure. The second bonding structure may include a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The second chip may be bonded to the first chip. Specifically, the first bonding portion of the first chip and the second through portion of the second chip may be bonded to each other. Since the structure of the memory device 2100 and the method of manufacturing the memory device 2100 are the same as those described with reference to fig. 1A to 5C, a detailed description thereof will be omitted.

In addition, the memory device 2100 may be a multi-chip package including a plurality of memory chips, as described with reference to fig. 7.

The computing system having such a configuration may be a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, and a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, and the like.

As described above, since the computing system 2000 according to the embodiment of the present disclosure includes the memory device 2100 having improved integration and improved characteristics, characteristics of the computing system 2000 may also be improved.

FIG. 9 is a block diagram illustrating a computing system in accordance with embodiments of the present disclosure.

Referring to FIG. 9, the computing system 3000 includes software layers including an operating system 3200, applications 3100, a file system 3300, a translation layer 3400, and the like. In addition, computing system 3000 includes hardware layers such as memory device 3500.

The operating system 3200 may manage software, hardware resources, etc. of the computing system 3000 and may control program execution by the central processing unit. The applications 3100 may be various application programs that execute on the computing system 3000, and may be entities executed by the operating system 3200.

File system 3300 refers to a logical structure for managing data, files, and the like that exist in computing system 3000. File system 3300 may organize files or data to be stored in memory device 3500 based on rules. The file system 3300 may be determined based on the operating system 3200 used in the computing system 3000. For example, when operating system 3200 is a Microsoft corporation's Windows system, file system 3300 may be a File Allocation Table (FAT), NT file system (NTFS), or the like. In addition, when the operating system 3200 is a Unix/Linux system, the file system 3300 may be an extended file system (EXT), a Unix File System (UFS), a Journaling File System (JFS), or the like.

Although the operating system 3200, the application 3100, and the file system 3300 are shown as separate blocks in this figure, the application 3100 and the file system 3300 may be included in the operating system 3200.

The translation layer 3400 translates an address suitable for a form of the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 translates logical addresses generated by the file system 3300 to physical addresses of the memory device 3500. Here, mapping information of the logical address and the physical address may be stored in the address translation table. For example, the translation layer 3400 may be a Flash Translation Layer (FTL), a universal flash link layer (ULL), or the like.

Memory device 3500 may be a non-volatile memory. In addition, the memory device 3500 may have the structure described above with reference to fig. 1A to 5C, and may be manufactured according to the manufacturing method described with reference to fig. 1 to 5C. As an embodiment, the memory device 3500 may include a first chip including a first substrate, a first cell array, a first metal wiring, and a first bonding structure. The first bonding structure may include a first penetration portion penetrating the first metal wiring and a first bonding portion formed in the first substrate. The second chip may include a second substrate, a second cell array, a second metal wiring, and a second bonding structure. The second bonding structure may include a second penetration portion penetrating the second metal wiring and a second bonding portion formed in the second substrate. The second chip may be bonded to the first chip. Specifically, the first bonding portion of the first chip and the second through portion of the second chip may be bonded to each other. Since the structure of the memory device 3500 and the method of manufacturing the memory device 3500 are the same as those described with reference to fig. 1A to 5C, a detailed description thereof will be omitted.

The computing system 3000 having such a configuration can be divided into an operating system layer that is executed in a high-level region and a controller layer that is executed in a low-level region. Here, the application 3100, the operating system 3200, and the file system 3300 may be included in an operating system layer, and may be driven by an operating memory of the computing system 3000. Additionally, the conversion layer 3400 may be included in an operating system layer or in a controller layer.

As described above, since the computing system 3000 includes the memory device 3500 having improved integration and improved characteristics, the characteristics of the computing system 3000 can also be improved.

Although the technical spirit of the present disclosure has been described specifically according to the embodiments, it should be noted that the above embodiments are for descriptive purposes and not limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the technical spirit of the present disclosure.

Cross Reference to Related Applications

This application claims priority from korean patent application No.10-2019-0140874, filed in the korean intellectual property office at 11/6/2019, which is hereby incorporated by reference in its entirety.