阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 仓田稔 于 2020-02-27 设计创作，主要内容包括：实施方式提供一种不易形成因树脂填充不足所导致的间隙的半导体装置及其制造方法。实施方式的半导体装置具有：衬底；第1半导体芯片,搭载在所述衬底面上,与所述衬底电连接；多个间隔件,在所述衬底面上,于所述第1半导体芯片的周围隔着空隙相互隔开,且隔着第1非导电性材设置；第2半导体芯片,隔着所述多个间隔件从所述第1半导体芯片相对于所述衬底面朝上方向隔开设置,且与所述衬底电连接；以及突出部,在所述空隙之一部分具有从所述衬底面上朝上方向突出的形状。(Embodiments provide a semiconductor device and a method of manufacturing the same, in which a gap due to insufficient resin filling is not easily formed. The semiconductor device of the embodiment includes: a substrate; a1 st semiconductor chip mounted on the substrate surface and electrically connected to the substrate; a plurality of spacers which are provided on the substrate surface, are spaced apart from each other around the 1 st semiconductor chip by a gap, and are provided by a1 st non-conductive material; a2 nd semiconductor chip which is provided apart from the 1 st semiconductor chip in a face-up direction with respect to the substrate via the plurality of spacers and is electrically connected to the substrate; and a protrusion portion having a shape protruding upward from the substrate surface at a part of the gap.)

1. A semiconductor device is characterized by comprising:

a substrate;

a1 st semiconductor chip mounted on the substrate surface and electrically connected to the substrate;

a plurality of spacers that are provided on the substrate surface, are spaced apart from each other around the 1 st semiconductor chip by a gap, and are provided by a1 st non-conductive material;

a2 nd semiconductor chip which is provided apart from the 1 st semiconductor chip in a face-up direction with respect to the substrate via the plurality of spacers and is electrically connected to the substrate; and

and a protrusion having a shape protruding upward from the substrate surface at a part of the gap.

2. The semiconductor device according to claim 1, wherein: and a resin is provided between the substrate and the 2 nd semiconductor chip.

3. The semiconductor device according to claim 2, wherein: the semiconductor device includes a3 rd semiconductor chip, wherein the 3 rd semiconductor chip is provided on the substrate surface in the upper direction of the 2 nd semiconductor chip with a2 nd non-conductive material interposed therebetween and is electrically connected to the substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein: the protrusion includes a plurality of bond wires.

5. The semiconductor device according to any one of claims 1 to 3, wherein: the protrusion includes a solder resist disposed on the substrate.

6. The semiconductor device according to any one of claims 1 to 3, wherein: the protrusion includes a potting resin disposed on the substrate.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a1 st semiconductor chip on the substrate surface;

forming a plurality of spacers on the substrate surface, the spacers being spaced apart from each other around the 1 st semiconductor chip by a gap and having a non-conductive material interposed therebetween;

forming a protrusion having a shape protruding upward from the substrate surface at a portion of the gap;

forming a2 nd semiconductor chip spaced apart from the 1 st semiconductor chip with respect to the substrate surface toward the upward direction with the plurality of spacers interposed therebetween;

electrically connecting the 2 nd semiconductor chip with the substrate; and

filling resin between the substrate and the 2 nd semiconductor chip.

Technical Field

Embodiments of the invention relate to a semiconductor device and a method of manufacturing the same.

Background

After the semiconductor chip is mounted on the substrate, the periphery of the semiconductor chip is molded with a resin. If there is a gap in the semiconductor package due to insufficient resin filling, there is a possibility that defects such as cracking of the semiconductor package may occur.

Disclosure of Invention

Embodiments provide a semiconductor device and a method of manufacturing the same, in which a gap due to insufficient resin filling is not easily formed.

The semiconductor device of the embodiment includes: a substrate; a1 st semiconductor chip mounted on the substrate surface and electrically connected to the substrate; a plurality of spacers which are provided on the substrate surface, are spaced apart from each other around the 1 st semiconductor chip by a gap, and are provided by a1 st non-conductive material; a2 nd semiconductor chip which is provided apart from the 1 st semiconductor chip in a face-up direction with respect to the substrate via the plurality of spacers and is electrically connected to the substrate; and a protrusion portion having a shape protruding upward from the substrate surface at a part of the gap.

Drawings

Fig. 1 is a plan view of a semiconductor device according to an embodiment.

Fig. 2 is an assembly diagram of the semiconductor device of the embodiment.

Fig. 3 is a front view of the semiconductor device of the embodiment.

Fig. 4 is a view showing the resin immersion direction in the case where the substrate on which a plurality of semiconductor chips are mounted is immersed in the liquid resin according to the embodiment.

Fig. 5 is a diagram showing the flow of resin in the embodiment.

Fig. 6 is a diagram for explaining a moving state of the distal end surface when the resin of the embodiment is immersed in each arrow direction.

Fig. 7 is a diagram for explaining the positions of the confluence points of the respective distal end surfaces of the resins according to the embodiment.

Fig. 8 is a diagram for explaining the positions of the confluence points of the respective distal end surfaces of the resins according to the embodiment.

Fig. 9 is a diagram for explaining the positions of the confluence points of the respective distal end surfaces of the resins according to the embodiment.

Fig. 10 is a diagram for explaining the positions of the confluence points of the respective distal end surfaces of the resins according to the embodiment.

Fig. 11 is a perspective view of a substrate in which a resin resistance portion is formed of a solder resist according to a variation of the embodiment.

Fig. 12 is a perspective view of a substrate in which a resin resistance portion is formed of potting resin according to a modification of the embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. Note that the drawings are schematic drawings, and the relationship between the thickness and the width of each member, the ratio of the thicknesses of the members, and the like are different from the actual ones, and naturally, the drawings include portions having different dimensional relationships and ratios from each other.

(constitution)

Fig. 1 is a plan view of the semiconductor device of this embodiment. Fig. 2 is an assembly diagram of the semiconductor device. Fig. 3 is a front view of the semiconductor device. The semiconductor device 1 of the present embodiment is a semiconductor package in which a plurality of semiconductor chips are stacked on a substrate in a resin, and which has a group of external terminals electrically connected to the respective semiconductor chips inside.

The substrate 11 of the semiconductor device 1 is a BGA (Ball Grid Array) package substrate having a rectangular upper surface 11 a. Here, the substrate 11 is an interposer made of glass epoxy. The substrate 11 is connected to a plurality of electrodes on a circuit board, not shown, via a plurality of solder balls 11c on the lower substrate surface 11 b.

In order to incorporate each semiconductor chip into a thin semiconductor package, the back surface of a semiconductor wafer on which a semiconductor circuit is formed is ground. On the back surface of the thinned semiconductor wafer after grinding, a DAF (Die Attachment Film) for adhering to the substrate 11 is attached, and the semiconductor wafer is diced along with the DAF as an adhesive agent and divided into semiconductor chips.

The semiconductor chip 12 is heated and fixed to the upper surface 11a of the substrate 11 by DAF. A plurality of semiconductor chips are stacked on the substrate 11, but the semiconductor chip 12 is disposed at the lowermost stage, and a large semiconductor chip is mounted above the semiconductor chip 12.

When a semiconductor package is used for a mobile phone or the like, the package size is limited, and particularly, the height needs to be suppressed. In general, when a plurality of semiconductor chips are stacked, a large chip is often mounted on a lower stage and a small chip is often mounted on an upper stage. However, when the wiring of the interposer is limited, or when the chip size is small like a controller chip of a NAND (Not AND) memory, the number of bonding wires is large, AND wire bonding is performed on the side of the chip in 3 or 4 directions, the small semiconductor chip is mounted on the lowermost stage, AND the large memory chip is provided on the upper stage.

As shown in fig. 1, a plurality of pads on the upper surface 12a of the semiconductor chip 12 are connected to a plurality of electrodes provided on the upper surface of the substrate 11 by wire bonding of gold or the like via a plurality of bonding wires 12 b. As described above, the semiconductor chip 12 is mounted on the substrate 11, and is electrically connected to the substrate 11 via the plurality of bonding wires 12 b.

In order to secure a predetermined gap above the lowermost semiconductor chip 12, a plurality of spacer members are provided on the substrate 11. On the upper surface 11a of the substrate 11 around the semiconductor chip 12 provided with the plurality of bonding wires 12B, 4 spacer chips 13A, 13B, 13C, and 13D as spacers are mounted. Hereinafter, all of the 4 or any 1 or more spacer chips are referred to as spacer chips 13. Here, the 4 spacer chips 13 are silicon wafers, have the same size, and have the same rectangular parallelepiped shape.

As shown in fig. 1, a semiconductor chip 12 is disposed in the center of a rectangular substrate 11, and 4 spacer chips 13 are disposed at 4 corners of the substrate 11. The spacer chips 13A and 13B are arranged along the longitudinal axis direction D1 of the substrate 11, and the spacer chips 13C and 13D are also arranged along the longitudinal axis direction D1 of the substrate 11. The spacer chips 13A and 13C are arranged along the short side axis direction D2 of the substrate 11, and the spacer chips 13B and 13D are also arranged along the short side axis direction D2 of the substrate 11. Each spacer chip 13 is adhered and fixed on the substrate 11 by an adhesive such as DAF.

As shown in fig. 3, a height h1 from the upper surface 11a of the substrate 11 to the upper surface 12a of the semiconductor chip 12 is lower than a height h2 of each spacer chip 13.

The semiconductor chip 14A is mounted on the spacer chips 13A and 13C. Similarly, the semiconductor chip 14B is mounted on the spacer chips 13B and 13D. As shown in fig. 1, the semiconductor chips 14A and 14B have a rectangular shape. The semiconductor chips 14A and 14B are adhered and fixed on the spacer chips 13A, 13C and 13B, 13D by an adhesive such as DAF.

The semiconductor chip 14A is mounted on the spacer chips 13A and 13C along the short side axis direction D2 of the substrate 11 such that the long side axis of the semiconductor chip 14A is parallel to the short side axis direction D2 of the substrate 11. Similarly, the semiconductor chip 14B is mounted on the spacer chips 13B and 13D along the short side axis direction D2 of the substrate 11 such that the long side axis of the semiconductor chip 14B is parallel to the short side axis direction D2 of the substrate 11. The semiconductor chips 14A and 14B are placed on the 2 spacer chips 13 and fixed by an adhesive so that the lower surfaces of the two end portions in the longitudinal axis direction of the semiconductor chips 14A and 14B are supported by the upper surfaces of the 2 spacer chips 13.

Further, as described above, since the height h1 of the semiconductor chip 12 is lower than the height h2 of each spacer chip 13, the lower surfaces of the semiconductor chips 14A and 14B are not in contact with the semiconductor chip 12 and the plurality of bonding wires 12B. In other words, a gap is formed between the lower surface of each of the semiconductor chips 14A and 14B and the upper surface 12a of the semiconductor chip 12. As described above, the plurality of spacer chips 13 are mounted around the semiconductor chip 12 on the substrate 11, and the semiconductor chips 14A and 14B are provided spaced apart from the semiconductor chip 12 via the plurality of spacer chips 13 provided on the substrate 11.

Further, a semiconductor chip 15 is mounted on the semiconductor chips 14A and 14B. As shown in fig. 1, the semiconductor chip 15 has a rectangular shape. Here, the semiconductor chip 15 is disposed to be offset to one side (lower side in fig. 1) in the longitudinal axis direction of the semiconductor chips 14A and 14B (the short axis direction D2 of the substrate 11).

The semiconductor chip 15 is mounted on the semiconductor chips 14A and 14B along the longitudinal axis direction D1 of the substrate 11 such that the longitudinal axis of the semiconductor chip 15 is parallel to the longitudinal axis direction D1 of the substrate 11. The semiconductor chip 15 is adhered and fixed on the semiconductor chips 14A and 14B by an adhesive such as DAF. The semiconductor chips 15 are mounted on the 2 semiconductor chips 14 so that the lower surfaces of both ends in the longitudinal axis direction thereof are supported by the upper surfaces of the 2 semiconductor chips 14, and are fixed by an adhesive. As described above, the semiconductor chip 15 is provided on a plurality of (here, 2) semiconductor chips 14A, 14B.

The semiconductor chips 14A and 14B are connected to a plurality of electrodes provided on the upper surface 11a of the substrate 11 via a plurality of bonding wires 14A and 14B, respectively. The plurality of bonding wires 14A and 14B are connected to a plurality of electrodes provided on the upper surface 11a of the substrate 11 at one edge portion (upper portion in fig. 1) of each of the semiconductor chips 14A and 14B.

The semiconductor chip 15 is connected to a plurality of electrodes provided on the substrate 11 via a plurality of bonding wires 15 a. The plurality of bonding wires 15a are connected to a plurality of electrodes provided on the upper surface 11a of the substrate 11 at one edge portion (lower portion in fig. 1) of the semiconductor chip 15.

Further, a resin resistance portion 21 is formed on the substrate 11 between the spacer chips 13A and 13C. The resin resistance portion 21 is a portion that generates resistance to the flow of resin during resin filling and reduces the flow rate of the resin. As shown in fig. 2, the resin resistance portion 21 is formed by a plurality of joining lines 21 a. As shown in fig. 2, each bonding wire 21a has a circular arc shape.

Specifically, each bonding wire 21a is connected between 2 points on the upper surface 11a in the longitudinal axis direction D1 by a wire bonding machine, and each bonding wire 21a is formed in an arc shape with its central portion spaced from the upper surface 11 a. The height of the central portion of each bonding wire 21a is lower than the height h12 of the spacer chip 13. In addition, the plurality of bonding wires 21a are formed at a prescribed interval between the side surface 13Ab of the spacer chip 13A and the side surface 13Cb of the spacer chip 13C along the short-side axis direction D2. As described above, the resin resistance portions 21 constitute protruding portions that are provided between adjacent 2 of the plurality of spacer chips 13 (corresponding to the gaps) in such a manner as to protrude from the substrate 11. The protruding portion contains a plurality of bonding wires 21 a.

As described above, the semiconductor chip 12 is mounted on the substrate 11, and after the resin resistance portion 21 is formed on the substrate 11, the plurality of semiconductor chips 14A and the like are mounted. Thereafter, the peripheries of the plurality of semiconductor chips 12, 14, and 15 and the plurality of spacer chips 13 are molded with resin. As shown in fig. 3, the periphery of the plurality of semiconductor chips on the substrate 11 is filled with a resin 16.

The resin is filled by immersing the resin in a liquid state dissolved in a mold having a predetermined concave shape in a vacuum state. The dissolved resin covers the plurality of semiconductor chips 12 and the like and is cured.

As shown in fig. 1 and 3, the substrate 11 on which the plurality of semiconductor chips 12 and the like are stacked is immersed in the liquid resin so that the plurality of semiconductor chips 12 and the like are located downward in the direction of gravity with respect to the substrate 11. Fig. 4 is a view showing the resin immersion direction when the substrate 11 on which a plurality of semiconductor chips are mounted is immersed in a liquid resin.

An arrow a1 indicates the direction of immersion of the resin between the spacer chips 13A and 13B. Arrow a2 indicates the direction of immersion between spacer chips 13C and 13D. Arrow a3 indicates the direction of immersion between spacer chips 13A and 13C. Arrow a4 indicates the direction of immersion between spacer chips 13B and 13D. The resin from the direction of the arrow a1 flows into the semiconductor chip 12 through the opening OP1 between the side surface 13Aa of the spacer chip 13A and the side surface 13Ba of the spacer chip 13B. Further, the resin from the direction of the arrow a1 also enters from the gap between the semiconductor chips 14A and 14B.

The resin from the direction of the arrow a2 flows in from the opening OP2 formed on the side face 13Ca of the spacer chip 13C and the side face 13Da of the spacer chip 13D. The resin from the direction of arrow a2 enters semiconductor chip 12 through a tunnel-like gap formed by being surrounded by upper surface 11a of substrate 11, lower surface 15B of semiconductor chip 15, side surfaces 14Aa and 14Ba of semiconductor chips 14A and 14B, and side surfaces 13Ca and 13Da of spacer chips 13C and 13D.

The resin from the direction of the arrow a3 flows in from the opening OP3 formed on the side face 13Ab of the spacer chip 13C and the side face 13Cb side of the spacer chip 13C. The resin from the direction of arrow a3 enters into semiconductor chip 12 through a tunnel-like gap surrounded by upper surface 11a of substrate 11, lower surface 14Ab of semiconductor chip 14A, side surface 13Ab of spacer chip 13A, and side surface 13Cb of spacer chip 13C.

The resin from the direction of the arrow a4 flows in from the opening OP4 formed on the side face 13Bb of the spacer chip 13B and the side face 13Db of the spacer chip 13D. The resin from the direction of arrow a4 enters into semiconductor chip 12 through a tunnel-like gap surrounded by upper surface 11a of substrate 11, lower surface 14Bb of semiconductor chip 14B, side surface 13Bb of spacer chip 13B, and side surface 13Db of spacer chip 13D. That is, a plurality of tunnel-like gaps are formed around the semiconductor chip 12, and the resin penetrates into the semiconductor chip 12 through the plurality of tunnel-like gaps.

A plurality of semiconductor chip portions, on which a plurality of semiconductor chips 12, 14, and 15 are stacked, as shown in fig. 3 are provided on one large substrate 11, and the large substrate 11 is immersed in a liquid resin so that the semiconductor chip portion side is positioned downward in the gravity direction.

After the resin is cured, the plurality of solder balls 11c are attached to the substrate 11 by heating the substrate 11 in a state where the plurality of solder balls are placed at a plurality of predetermined positions on the lower surface 11b of the substrate 11. Thereafter, the semiconductor chips are cut out in units of a semiconductor chip portion by dicing, thereby forming 1 semiconductor device as shown in fig. 3, that is, 1 semiconductor package.

In the present embodiment, as described above, the small semiconductor chip 12 is disposed on the lowest stage of the plurality of stacked chip portions, and the large semiconductor chips 14A, 14B, and 15 are disposed on the semiconductor chip 12 with gaps therebetween.

In addition, the plurality of bonding wires 12b are not equally arranged around the semiconductor chip 12.

(action)

The lowermost semiconductor chip 12 is molded with resin by passing the resin through a plurality of tunnel-like gaps around the resin, but the resin must mold the periphery of the semiconductor chip 12 and the periphery of all the bonding wires 12b without gaps.

Further, as shown in fig. 1, there is no component in the space between the spacer chips 13A and 13B. Thus, the elongated ellipses of the two-dot chain lines indicate the openings OP1, OP2, OP3, OP4 into which the resin flows, but at the opening OP1, the resin also flows from the space between the semiconductor chips 14A and 14B.

Next, the flow direction of the resin will be explained. Fig. 5 is a view showing a flow direction of the resin. Fig. 5 and 6 described below show an example in which a plurality of bonding wires 12b provided around the semiconductor chip 12 are provided symmetrically and equally with respect to the longitudinal axis and the end hand axis of the semiconductor chip 12.

The resin from the direction of the arrow a1 hits the side surface of the semiconductor chip 12, and is divided into 2 directions. The 2 directions are 2 directions along flow directions fl1 and fl2 shown in dashed lines. The flow direction fl1 is a flow direction of the resin between the side surface 13Ab of the spacer chip 13A and the side surface 13Cb of the spacer chip 13C in the resin from the direction of the arrow a 1. The flow direction fl2 is a flow direction of the resin from the direction of the arrow a1 toward the space between the side surface 13Bb of the spacer chip 13B and the side surface 13Db of the spacer chip 13D.

The resin from the direction of the arrow a2 hits the side surface of the semiconductor chip 12, and is divided into 2 directions. The 2 directions are 2 directions along flow directions fl3 and fl4 shown in dashed lines. The flow direction fl3 is a flow direction of the resin between the side surface 13Ab of the spacer chip 13A and the side surface 13Cb of the spacer chip 13C in the resin from the direction of the arrow a 2. The flow direction fl4 is a flow direction of the resin from the direction of the arrow a2 toward the space between the side surface 13Bb of the spacer chip 13B and the side surface 13Db of the spacer chip 13D.

The flow direction fl5 shown by a dotted line indicates the flow direction of the resin from the arrow A3 toward the semiconductor chip 12. The flow direction fl6 shown by a dotted line indicates the flow direction of the resin from the arrow a4 toward the semiconductor chip 12.

Further, since there is a gap between the upper surface 12a of the semiconductor chip 12 and the 2 lower surfaces of the semiconductor chips 14A, 14B, the resin from each arrow direction also penetrates into the gap between the upper surface 12a of the semiconductor chip 12 and the 2 lower surfaces 14Ab, 14Bb of the semiconductor chips 14A, 14B.

Fig. 6 is a diagram for explaining a moving state of the distal end surface when the resin is impregnated from each arrow direction. In fig. 6, the chain double-dashed lines indicate resin tip end faces when the resin is immersed from each arrow direction.

The resin passes through the space between the side surface 13Aa of the spacer chip 13A and the side surface 13Ba of the spacer chip 13B from the direction of the arrow a1, and then passes through the space between the semiconductor chip 12 and the side surface 13Ab of the spacer chip 13A. As shown in fig. 6, the leading end face fs1 of the resin along the flow direction fl1 moves in the direction opposite to the arrow A3. Similarly, the resin passes through the space between the side surface 13Ca of the spacer chip 13C and the side surface 13Da of the spacer chip 13D from the direction of the arrow a2, and then passes through the space between the semiconductor chip 12 and the side surface 13Cb of the spacer chip 13C. As shown in fig. 6, the leading end face fs3 of the resin along the flow direction fl3 moves in the direction opposite to the arrow A3. The resin front face fs5 moves in the flow direction fl5 from the direction of arrow A3.

The resin leading end face fs2 in the flow direction fl2, the resin leading end face fs4 in the flow direction fl4, and the resin leading end face fs6 in the flow direction fl6 shown in fig. 6 also move like the above-mentioned leading end faces fs1, fs3, and fs5, respectively, as shown in fig. 6.

The end faces finally come into contact with each other at the confluence point, and as a result, the semiconductor chip 12 is completely molded with resin in the semiconductor device 1.

However, the flow directions fl5 and fl6 are faster than those fl1, fl2, fl3 and fl4, and therefore the confluence of the front end faces fs1, fs3 and fs5 and the confluence of the front end faces fs2, fs4 and fs6 may be close to the side faces of the semiconductor chip 12.

Fig. 7 to 10 are diagrams for explaining the positions of the confluence points of the respective leading end surfaces of the resins. Fig. 7 and 8 are diagrams for explaining examples of positions of junction points in the case where the plurality of bonding wires 12b are unevenly arranged around the semiconductor chip 12 as shown in fig. 1, 2, and 4. In fig. 7 and 8, the number of bonding wires 12b on the arrow a4 side of the semiconductor chip 12 is smaller than the number of bonding wires 12b on the arrow A3 side of the semiconductor chip 12.

Fig. 9 and 10 are diagrams for explaining examples of positions of junction points in the case where the plurality of bonding wires 12b are arranged uniformly around the semiconductor chip 12 as shown in fig. 5 and 6. Each confluence point is predicted from experiments, simulations, and the like based on the length of a tunnel-like gap into which the resin is immersed.

In fig. 7, the resin resistance portion 21 is not provided on the substrate 11. In fig. 7, the merging point P1 of the predicted end faces fs1, fs3, and fs5 and the merging point P2 of the predicted end faces fs2, fs4, and fs6 are denoted by X. However, in actually attempting the manufacturing, there are cases where: due to the influence of the bonding wires 12b of the semiconductor chip 12, the resin has a confluence point at the position of RP1 indicated by a circle symbol rather than at the position of P1. In this case, the movement of the resin is hindered by the plurality of joining lines 12b, and a minute gap may be formed in the vicinity of the confluence point RP 1.

This is because the number of the bonding wires 12b on one side (left side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12 is larger than the number of the bonding wires 12b on the other side (right side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12. Therefore, the confluence point RP1 moves near the bonding wire 12b on one side (left side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12, and a minute gap is easily formed near the confluence point RP 1.

On the other hand, the number of the bonding wires 12b on the other side (right side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12 is smaller than the number of the bonding wires 12b on the one side (left side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12. Therefore, the vicinity of the bonding wire 12b on the other side (right side in fig. 7) in the longitudinal axis direction of the many semiconductor chips 12 does not become a confluence point of the tip end surfaces fs2, fs4, and fs65, but a portion separated from the bonding wire 12b becomes a confluence point P2. Therefore, a small gap is not easily formed at the confluence point P2.

Therefore, in fig. 8, as shown in fig. 1 to 4, the resin resistance portion 21 is provided on the substrate 11. The resin resistance portion 21 is provided on the opening OP3 side with respect to the confluence point RP 1. The resin resistance portion 21 reduces the size of the tunnel-like gap into which the resin flows from the arrow a3 direction. In fig. 8, the merge point QP1 of the predicted front faces fs1, fs3, and fs5 is indicated by a triangular symbol. The resin resistance portion 21 slows down the flow of the resin from the opening OP3, and the ac point RP1 moves from the side surface of the semiconductor chip 12 toward the outer peripheral edge side of the substrate 11. Thus, in the case of fig. 8, compared to fig. 7, the merging point of the end faces fs1, fs3, and fs5 is shifted from RP1 to QP 1. Therefore, a small gap is not easily formed at the confluence point QP 1.

That is, when molding, by reducing the size of the tunnel-like gap into which the resin from the arrow A3 direction flows, the inflow speed of the resin from the arrow A3 direction coincides with the inflow speed of the resin from the arrow a4 direction. As a result, the confluence point moves from RP1 to QP1, and a minute gap is not easily formed.

In the case of fig. 9, the resin resistance portion 21 is not provided on the substrate 11. In fig. 9, the merging point P1 of the predicted end faces fs1, fs3, and fs5 and the merging point P2 of the predicted end faces fs2, fs4, and fs6 are denoted by X. However, in actually attempting the manufacturing, there are cases where: due to the influence of the bonding wires 12b of the semiconductor chip 12, the 1 st confluence point is at the position of RP1 shown by a circle mark rather than at the position of P1, and the 2 nd confluence point is at the position of RP2 shown by a circle mark rather than at the position of P2. In this case, the flow of the resin is obstructed by the plurality of joining lines 12b, and a minute gap may be formed near the confluence points RP1 and RP 2.

In fig. 9 and 10, the number of bonding wires 12b on one side (left side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12 is equal to the number of bonding wires 12b on the other side (right side in fig. 7) in the longitudinal axis direction of the semiconductor chip 12. Therefore, as shown in fig. 9, the confluence points RP1 and RP2 move near the bonding wire 12b on both sides (left and right sides in fig. 7) in the longitudinal axis direction of the semiconductor chip 12, and a minute gap is easily formed near the confluence points RP1 and RP 2.

Therefore, in fig. 10, 2 resin resistance portions 21 are provided on the substrate 11. The resin resistance portion 21 is provided on the opening OP3 side with respect to the confluence point RP1 and on the opening OP4 side with respect to the confluence point RP 2. In the case of fig. 10, the merge point QP1 of the predicted leading faces fs1, fs3, and fs5 and the merge point QP2 of the predicted leading faces fs2, fs4, and fs6 are indicated by triangular symbols. The 2 resin resistances 21 slow the flow of the resin from the openings OP3 and OP4, and the ac points RP1 and RP2 move from the side of the semiconductor chip 12 to the outer peripheral edge side of the substrate 11. Thus, in the case of fig. 10, compared to fig. 9, the merging point of the front faces fs1, fs3, and fs5 moves from RP1 to QP1, and the merging point of the front faces fs2, fs4, and fs6 moves from RP2 to QP 2. Therefore, a small gap is not easily formed between the merge points QP1 and QP 2.

That is, when molding, the inflow speed of the resin from the arrow A3 direction and the arrow a4 direction is reduced by reducing the size of the 2 tunnel-like gaps into which the resin from the arrow A3 direction and the arrow a4 direction flows. As a result, the confluence point moves from RP1 to QP1 and from RP2 to QP2, and a minute gap is not easily formed.

The resin has moisture absorption properties. In the case where the semiconductor device having the minute gap inside which the resin cannot be filled absorbs moisture after shipment, moisture may be collected in the minute gap, and the moisture may be broken by the heat generated by the reflow soldering. Therefore, it must be manufactured without a gap in the package. According to the present embodiment, since a minute gap is not easily formed in the semiconductor package, it is possible to prevent the damage due to the reflow soldering after moisture absorption.

As described above, according to the above embodiment, a semiconductor device in which a gap due to insufficient filling of resin is not easily formed can be provided.

In particular, the resin resistance portion 21 adjusts the resistance at the time of the inflow of the resin through the plurality of tunnel-like gaps formed around the semiconductor chip 12 on the lower stage, and the inflow speed of the resin from each opening is made uniform or slow, whereby the position of the confluence point of the resin front end face is moved, and the occurrence of the minute gap is prevented.

In the above embodiment, the resin resistance portion 21 is formed by the plurality of bonding wires 21a, but may be formed by a solder resist or potting (potting) resin as a variation thereof. The potting resin means a resin molded by a potting method.

Fig. 11 is a perspective view of the substrate 11 in which the resin resistance portion is formed of a solder resist. In fig. 11, rectangular solder resist portions 22 protruding from upper surface 11a of substrate 11 are provided as resin resistance portions at the positions of resin resistance portions 21 in fig. 2. That is, the solder resist portion 22 constitutes a protruding portion including a solder resist provided on the substrate 11.

When the substrate 11 is manufactured, the solder resist applied to the upper surface 11a of the substrate 11 may be locally applied in a thick state to form the resin resistance portion. As a result, when molding, the size of the tunnel-like gap into which the resin from the arrow A3 direction flows can be made small, so that the inflow speed of the resin from the arrow A3 direction can be made to coincide with the inflow speed of the resin from the arrow a4 direction.

Fig. 12 is a perspective view of the substrate 11 in which the resin resistance portion is made of potting resin. In fig. 12, a potting resin portion 23 formed by potting a resin of a predetermined thickness on the upper surface 11a of the substrate 11 is provided as the resin resistance portion at the position of the resin resistance portion 21 in fig. 2. That is, the potting resin portion 23 constitutes a protruding portion including the potting resin provided on the substrate 11.

Further, the resin resistance portion may be configured by combining 2 or more of the plurality of bonding wires 21a, the solder resist portion 22, and the potting resin portion 23.

After mounting the semiconductor chip 12 on the upper surface 11a of the substrate 11, a resin resistance portion 23 is formed by forming a resin ridge portion of a predetermined thickness on the upper surface 11a using a potting resin. As a result, when molding, the size of the tunnel-like gap into which the resin from the arrow A3 direction flows can be made small, so that the inflow speed of the resin from the arrow A3 direction can be made to coincide with the inflow speed of the resin from the arrow a4 direction.

As described above, according to the above embodiment and the modifications, a semiconductor device in which a gap due to insufficient resin filling is not easily formed can be provided.

Several embodiments of the present invention have been described, but these embodiments are given as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

[ description of symbols ]

1 semiconductor device

11 substrate

11a upper surface

11b lower surface

11c solder ball

12 semiconductor chip

12a upper surface

12b bonding wire

13A, 13B, 13C, 13D spacer chip

13Aa, 13Ab, 13Ba, 13Bb, 13Ca, 13Cb, 13Da, 13Db side

14. 14A, 14B semiconductor chip

14Aa, 14Ba side

Lower surfaces of 14Ab and 14Bb

14a, 14b bonding wire

15 semiconductor chip

15a bonding wire

15b lower surface

16 resin

21 resin resistance part

21a bonding wire

22 solder resist portion

23 potting resin part