阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 廖俊诚 于 2020-07-08 设计创作，主要内容包括：本发明公开一种半导体装置及其制造方法。一种半导体装置包括一基底、多个插塞设置于该基底的上方、多个气隙相邻设置于该多个插塞以及多个电容结构设置于该基底的上方。(The invention discloses a semiconductor device and a manufacturing method thereof. A semiconductor device comprises a substrate, a plurality of plugs arranged above the substrate, a plurality of air gaps arranged adjacent to the plugs and a plurality of capacitor structures arranged above the substrate.)

1. A semiconductor device, comprising:

a substrate;

a plurality of plugs disposed above the substrate;

a plurality of air gaps are adjacently arranged on the plugs;

a plurality of capacitor structures are disposed above the substrate.

2. The semiconductor device of claim 1, further comprising a plurality of support structures disposed adjacent to the plurality of plugs.

3. The semiconductor device of claim 2, wherein the plurality of air gaps are disposed above the plurality of support structures.

4. The semiconductor device of claim 3, wherein the plurality of support structures comprises a plurality of top support structures disposed below the plurality of air gaps, a plurality of middle support structures disposed below the plurality of top support structures, and a plurality of bottom support structures disposed below the plurality of middle support structures.

5. The semiconductor device of claim 4, further comprising a plurality of word lines, wherein the plurality of word lines extend along a first direction.

6. The semiconductor device of claim 5, wherein adjacent pairs of the plurality of intermediate support structures are interconnected along the first direction.

7. The semiconductor device of claim 6, further comprising a plurality of spacers disposed between the plurality of air gaps and the plurality of plugs.

8. The semiconductor device of claim 7, wherein said plurality of word lines comprises a plurality of word line insulating layers recessed in said substrate, a plurality of word line electrodes disposed on said plurality of word line insulating layers, and a plurality of word line capping layers disposed on said plurality of word line electrodes.

9. The semiconductor device of claim 7, further comprising a plurality of bit lines disposed above the substrate and extending along a second direction, wherein the second direction is perpendicular to the first direction.

10. The semiconductor device of claim 9, wherein the plurality of bit lines have an elongated stripe shape.

11. The semiconductor device of claim 9, further comprising a plurality of bit line contact plugs disposed under the plurality of bit lines.

12. The semiconductor device of claim 7, wherein said plurality of capacitor structures comprise a plurality of capacitor bottom electrodes concavely disposed above said plurality of plugs, a capacitor insulating layer disposed on said plurality of capacitor bottom electrodes and a capacitor top electrode disposed on said capacitor insulating layer.

13. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a plurality of plugs above the substrate;

forming a plurality of air gaps adjacent to the plurality of plugs;

a plurality of capacitor structures are formed over the substrate.

14. The method of claim 13, further comprising forming a plurality of support structures adjacent to the plurality of plugs.

15. The method of claim 14, wherein the plurality of air gaps are formed over the plurality of support structures.

16. The method of claim 15, wherein the plurality of support structures comprises a plurality of top support structures formed below the plurality of air gaps, a plurality of middle support structures formed below the plurality of top support structures, and a plurality of bottom support structures formed below the plurality of middle support structures.

17. The method of claim 16, further comprising forming a plurality of word lines on the substrate, wherein the plurality of word lines extend along a first direction.

18. The method of claim 17, wherein adjacent pairs of the plurality of intermediate support structures are interconnected along the first direction.

19. The method of claim 18, further comprising forming a plurality of spacers between the plurality of air gaps and the plurality of plugs.

20. The method according to claim 19, wherein the plurality of word lines includes a plurality of word line insulating layers formed in a recess in the substrate, a plurality of word line electrodes formed on the plurality of word line insulating layers, and a plurality of word line capping layers formed on the plurality of word line electrodes.

Technical Field

The present invention claims priority and benefit from us official application No. 16/582,289, filed on 25/09/2019, the contents of which are incorporated herein by reference in their entirety.

The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having an air gap and a method for fabricating the same.

Background

Semiconductor devices are used in applications of various electronic apparatuses such as personal computers, cellular phones, digital cameras, and other electronic apparatuses. To meet the ever-increasing demand for computing power, semiconductor devices are continually being scaled down. However, the process of miniaturizing semiconductor devices has encountered various problems in their manufacture that affect the ultimate electrical characteristics, quality and yield of the semiconductor devices. Accordingly, challenges remain in improving the performance, quality, yield, performance, and reliability of semiconductor devices.

The above description of "prior art" merely provides background and is not an admission that the above description of "prior art" discloses subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as an admission that it forms part of the present invention.

Disclosure of Invention

One aspect of the present disclosure provides a semiconductor device including a substrate, a plurality of plugs disposed over the substrate, a plurality of air gaps disposed adjacent to the plurality of plugs, and a plurality of capacitor structures disposed over the substrate.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of support structures disposed adjacent to the plurality of plugs.

In some embodiments of the present disclosure, the plurality of air gaps are disposed above the plurality of support structures.

In some embodiments of the present disclosure, the plurality of support structures includes a plurality of top support structures disposed below the plurality of air gaps, a plurality of middle support structures disposed below the plurality of top support structures, and a plurality of bottom support structures disposed below the plurality of middle support structures.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of word lines, wherein the plurality of word lines extend along a first direction.

In some embodiments of the present disclosure, adjacent pairs of the plurality of intermediate support structures are interconnected along the first direction.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of spacers disposed between the plurality of air gaps and the plurality of plugs.

In some embodiments of the present disclosure, the plurality of word lines includes a plurality of word line insulating layers concavely disposed on the substrate, a plurality of word line electrodes disposed on the plurality of word line insulating layers, and a plurality of word line capping layers disposed on the plurality of word line electrodes.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of bit lines disposed above the substrate and extending along a second direction, wherein the second direction is perpendicular to the first direction.

In some embodiments of the present disclosure, the plurality of bit lines have a stripe shape.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of bit line contact plugs disposed under the plurality of bit lines.

In some embodiments of the present disclosure, the plurality of capacitor structures includes a plurality of capacitor bottom electrodes concavely disposed above the plurality of plugs, a capacitor insulating layer disposed on the plurality of capacitor bottom electrodes, and a capacitor top electrode disposed on the capacitor insulating layer.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, including providing a substrate, forming a plurality of plugs over the substrate, forming a plurality of air gaps adjacent to the plurality of plugs, and forming a plurality of capacitor structures over the substrate.

In some embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes forming a plurality of support structures adjacent to the plurality of plugs.

In some embodiments of the present disclosure, the plurality of air gaps are formed over the plurality of support structures.

In some embodiments of the present disclosure, the plurality of support structures includes a plurality of top support structures formed below the plurality of air gaps, a plurality of middle support structures formed below the plurality of top support structures, and a plurality of bottom support structures formed below the plurality of middle support structures.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of word lines formed over the substrate, wherein the plurality of word lines extend along a first direction.

In some embodiments of the present disclosure, adjacent pairs of the plurality of intermediate support structures are interconnected along the first direction.

In some embodiments of the present disclosure, the semiconductor device further comprises forming a plurality of spacers between the plurality of air gaps and the plurality of plugs.

In some embodiments of the present disclosure, the plurality of word lines includes a plurality of word line insulating layers concavely formed on the substrate, a plurality of word line electrodes formed on the plurality of word line insulating layers, and a plurality of word line capping layers formed on the plurality of word line electrodes.

Due to the design of the semiconductor device of the present disclosure, the parasitic capacitance of the semiconductor device will be reduced, and thus the performance of the semiconductor device will be improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that constitute the present disclosure will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure.

Drawings

A more complete understanding of the present disclosure may be derived by referring to the embodiments when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.

Fig. 1 is a schematic top view of a semiconductor device in an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view taken along A-A of the semiconductor device of FIG. 1;

FIG. 3 is a schematic cross-sectional view taken along line B-B of the semiconductor device of FIG. 1;

FIG. 4 is a schematic diagram illustrating a flowchart of a method of fabricating a semiconductor device according to one embodiment of the present disclosure;

FIG. 5 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure;

FIGS. 6 and 7 are schematic diagrams illustrating a partial flow, in cross-section, of a method of fabricating a semiconductor device according to one embodiment of the present disclosure, wherein FIG. 7 is a schematic cross-sectional view taken along line C-C in FIG. 5;

FIG. 8 is a schematic diagram illustrating, in cross-section, a portion of a process flow for fabricating a semiconductor device in one embodiment of the present disclosure;

fig. 9 is a schematic top view of a semiconductor device in an embodiment of the present disclosure;

fig. 10 to 13 are schematic views, wherein fig. 13 is a cross-sectional view taken along D-D in fig. 9, illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 14 is a schematic top view of a semiconductor device in an embodiment of the present disclosure;

FIG. 15 is a schematic cross-sectional view taken along line E-E of FIG. 14 illustrating a partial flow of a method of fabricating a semiconductor device in accordance with one embodiment of the present disclosure;

fig. 16 is a schematic top view of a semiconductor device in an embodiment of the present disclosure;

fig. 17 and 18 are schematic diagrams, wherein fig. 17 is a schematic cross-sectional view taken along F-F in fig. 16, and fig. 18 is a schematic cross-sectional view taken along G-G in fig. 16, illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

FIG. 19 is a schematic top view of a semiconductor device in accordance with an embodiment of the present disclosure;

FIGS. 20 and 21 are schematic diagrams, wherein FIG. 20 is a schematic diagram illustrating a cross-sectional view taken along H-H in FIG. 19, and FIG. 18 is a schematic diagram illustrating a cross-sectional view taken along I-I in FIG. 19, illustrating a partial flow of a method for fabricating a semiconductor device in accordance with an embodiment of the present disclosure in cross-section;

fig. 22 is a schematic top view of a semiconductor device in accordance with an embodiment of the present disclosure;

fig. 23 and 24 are schematic diagrams, wherein fig. 23 is a schematic cross-sectional view taken along J-J in fig. 22, and fig. 24 is a schematic cross-sectional view taken along K-K in fig. 22, illustrating a partial flow of a method for manufacturing a semiconductor device in accordance with an embodiment of the present disclosure in cross-section;

FIG. 25 is a schematic top view of a semiconductor device in accordance with an embodiment of the present disclosure;

fig. 26 to 28 are schematic diagrams, wherein fig. 27 is a schematic cross-sectional view taken along L-L in fig. 25, and fig. 28 is a schematic cross-sectional view taken along M-M in fig. 25, illustrating a partial flow of a method for manufacturing a semiconductor device in accordance with another embodiment of the present disclosure in cross-sectional view;

fig. 29 is a schematic top view of a semiconductor device in accordance with an embodiment of the present disclosure;

fig. 30 is a schematic view, wherein fig. 30 is a schematic cross-sectional view along N-N illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 31 to 38 are schematic views illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in cross-section.

Description of reference numerals:

10 method

101 base

103 isolating layer

105 active region

107 doped region

109 first doped region

111 second doped region

201 word line

203 word line trench

205 word line insulating layer

207 word line electrode

209 word line cap

211 bit line contact plug

213 bit line

301 supporting structure

303 top support structure

305 intermediate support structure

307 bottom support Structure

401 bottom insulating layer

403 intermediate insulating layer

405 top insulating layer

407 trench in Process

409 sacrificial liner

411 etched space

413 plug trench

415 plug

417 spacer layer

419 spacer

421 air gap

501 capacitor structure

503 capacitor trench

505 bottom electrode of capacitor

507 capacitor insulating layer

509 capacitor Top electrode

601 first insulating layer

603 second insulating layer

605 sealing layer

607 third insulating layer

701 mask layer

703 sacrificial layer

W is the direction

X is the direction

Y is the direction

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure can include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the present disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details.

In the present disclosure, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Such as electro-optical devices, light emitting display devices, semiconductor circuits and electronic devices, will be included in the category of semiconductor devices. More specifically, the semiconductor device in the embodiment of the present disclosure is a dynamic random access memory.

In the description of the present disclosure, the upper side corresponds to the arrow direction of the Z-axis, and the lower side corresponds to the opposite direction of the arrow of the Z-axis.

FIG. 1 is a schematic top view of a semiconductor device according to one embodiment; FIG. 2 is a schematic cross-sectional view taken along A-A of the semiconductor device of FIG. 1; fig. 3 is a schematic cross-sectional view along B-B of the semiconductor device in fig. 1. For simplicity, some elements of the semiconductor device are not shown in fig. 1.

Referring to fig. 1 to 3, a semiconductor device includes a substrate 101, an isolation layer 103, a plurality of doped regions 107, a plurality of word lines 201, a plurality of bit line contact plugs 211, a plurality of bit lines 213, a plurality of support structures 301, a bottom insulating layer 401, a middle insulating layer 403, a top insulating layer 405, a plurality of plugs 415, a plurality of spacers 419, a plurality of air gaps 421, a plurality of capacitor structures 501, a first insulating layer 601, a second insulating layer 603, a sealing layer 605, and a third insulating layer 607.

Referring to fig. 1 to 3, in the illustrated embodiment, the substrate 101 is formed of, for example, silicon (silicon), germanium (germanium), silicon germanium (silicon germanium), silicon carbon (silicon carbon), silicon germanium carbon (silicon germanium carbon), gallium (gallium), gallium arsenide (gallium arsenic), indium arsenide (indium arsenic), indium phosphide (indium phosphide), and all other group IV, group III, or group II-VI semiconductor materials, etc. Alternatively, in another embodiment, the substrate may comprise an organic semiconductor or a layered stack of semiconductors such as silicon/silicon germanium, silicon-on-insulator (soi), or silicon germanium-on-insulator (soi). When the substrate 101 is formed of SOI, the substrate 101 will include a top semiconductor layer, a bottom semiconductor layer formed of Si, and a buried insulating layer separating the top semiconductor layer from the bottom semiconductor layer. The buried insulating layer comprises, for example, a crystalline or amorphous oxide, a nitride, or any combination thereof.

Referring to fig. 1 to 3, in the illustrated embodiment, the isolation layer 103 is disposed in the substrate 101. More specifically, the isolation layer 103 is disposed on an upper portion of the substrate 101. The isolation layer 103 is formed of an insulating material. Such as silicon oxide (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), silicon nitride oxide (silicon nitride oxide), or fluorine-doped silicate. The isolation layer 103 defines a plurality of active regions 105 in the substrate 101. The plurality of active regions 105 extend in a direction W.

In the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen, and oxygen, in which the proportion of oxygen is greater than that of nitrogen. Silicon oxynitride refers to a substance comprising silicon, nitrogen and oxygen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

Referring to fig. 1 to 3, in the illustrated embodiment, the doped regions 107 are disposed in an upper portion of the substrate 101. More specifically, the doped regions 107 are disposed in the active regions 105 of the substrate 101. The doped regions 107 are doped with a dopant (dopant) such as phosphorus, arsenic or antimony.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of word lines 201 are disposed in the substrate 101. More specifically, the plurality of word lines 201 extend along a direction X, and the plurality of word lines 201 are spaced apart from each other. The direction W is inclined with respect to the direction X, and the plurality of word lines 201 and the plurality of active regions 105 intersect. Each active region 105 intersects two word lines 201. The doped region 107 in each active region 105 is divided into a first doped region 109 and a plurality of second doped regions 111 by the two word lines 201. The first doped region 109 is disposed between the two word lines 201. The second doped regions 111 are respectively disposed at two ends of each active region 105, in other words, the second doped regions 111 are respectively correspondingly opposite to the first doped regions 109, and the two word lines 201 are respectively correspondingly disposed between the second doped regions 111 and the first doped regions 109.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of word lines 201 include a plurality of word line insulating layers 205, a plurality of word line electrodes 207, and a plurality of word line capping layers 209. The plurality of word line insulating layers 205 are recessed in an upper portion of the substrate 101. The plurality of wordline insulating layers 205 has a thickness between about 0.5 nm and about 10 nm. The bottom of the plurality of word line insulating layers 205 is flat. The plurality of word line insulating layers 205 are formed of an insulating material having a dielectric constant of about 4.0 or greater than 4.0 (unless otherwise noted, all references to dielectric constants relative to vacuum throughout the present disclosure). The insulating material is hafnium oxide (hafnium oxide), zirconium oxide (zirconium oxide), aluminum oxide (aluminum oxide), titanium oxide (titanium oxide), lanthanum oxide (lanthanum oxide), strontium titanate (strontium titanate), lanthanum aluminate (lanthanum aluminate), yttrium oxide (yttrium oxide), gallium (III) oxide, gadolinium gallium oxide (gadolinium titanate), lead zirconium titanate (lead zirconium titanate), barium strontium titanate (barium titanate), or a mixture thereof. Alternatively, as shown in another embodiment, the insulating material is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like.

Referring to fig. 1 to 3, in the illustrated embodiment, the word line electrodes 207 are respectively disposed on the word line insulating layers 205. The word lines 207 are formed of a conductive material such as polysilicon (polysilicon), silicon germanium (sige), metal alloy, metal silicide (metal silicide), metal nitride (metal nitride), metal carbide (metal carbide), or multi-layer structures (multilayers) comprising combinations of the foregoing materials. When each word line electrode 207 is a multilayer structure, a diffusion barrier layer (not shown) may be disposed between layers, and the diffusion barrier layer is made of titanium nitride or tantalum nitride. The metal is aluminum, copper, tungsten or cobalt. The metal silicide is nickel silicide (nickel silicide), platinum silicide (platinum silicide), titanium silicide (titanium silicide), molybdenum silicide (molybdenum silicide), cobalt silicide (cobalt silicide), tantalum silicide (tantalum silicide), tungsten silicide (tungsten silicide) or the like. The plurality of wordline electrodes 207 may have a thickness of about 50 nm to about 500 nm.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of word line caps 209 are respectively disposed on the plurality of word line electrodes 207. The top surfaces of the plurality of word line caps 209 are at the same height as the top surface of the substrate 101. The plurality of word line caps 209 are formed of a single layer structure including an insulating material having a dielectric constant of about 4.0 or greater than 4.0. Alternatively, in another embodiment, each word line cap 209 is a stacked layer (stacked layer) including a bottom cap disposed on the word line electrode 207 and a top stacked layer disposed on the bottom stacked layer. The bottom cap layer is formed of an insulating material having a dielectric constant of about 4.0 or greater than 4.0, and the top surface of the top cap layer is at the same height as the top surface of the substrate 101. The top cap layer is formed of a low dielectric constant material (low-k material) such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicate, or the like. The top cap layer formed of low-k material will reduce the electric field on the top surface of the substrate 101, thereby reducing leakage current (leakage current).

Referring to fig. 1 to 3, in the illustrated embodiment, the first insulating layer 601 is disposed on the substrate 101. The first insulating layer 601 is made of silicon nitride, silicon oxide, silicon oxynitride, flowable oxide (flowable oxide), Donen silazane (ton-silazene), undoped silicate glass (undoped silicate glass), borosilicate glass (borosilicate glass), phosphosilicate glass (phosphosilicate glass), plasma enhanced tetra-ethyl orthosilicate (plasma enhanced tetra-ethyl orthosilicate), fluorosilicate glass (fluoride silicate glass), carbon-doped silicon oxide (carbon-doped silicon oxide), xerogel (Xerogel), aerogel (aerogel), amorphous fluorinated carbon (amorphous carbon), organosilicate glass (organic silicate glass), parylene (parylene), bis-benzocyclobutene (bis-benzocyclobutene), polyimide (polyimide), porous polymeric material (pore polymeric material), or combinations thereof, but is not limited thereto.

Referring to fig. 1 to 3, in the illustrated embodiment, the bit line contact plugs 211 are disposed above the substrate 101. More specifically, the bit line contact plugs 211 are disposed in the first insulating layer 601 and respectively disposed on the first doping regions 109. That is, the bit line contact plugs 211 are respectively disposed at the middle portions of the active regions 105. The bit line contact plugs 211 are formed of a conductive material, such as doped polysilicon (polysilicon), metal nitride or metal silicide. The bit line contact plugs 211 are electrically connected to the first doping regions 109.

Referring to fig. 1 to 3, in the illustrated embodiment, the second insulating layer 603 is disposed on the first insulating layer 601. The second insulating layer 603 and the first insulating layer 601 can be formed of the same material, but not limited thereto.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of bit lines 213 are disposed above the substrate 101. More specifically, the plurality of bit lines 213 are disposed in the second insulating layer 603 and on the plurality of bit line contact plugs 211. The plurality of bit lines 213 extend in a direction Y, and the plurality of bit lines 213 are shaped like a long stripe from above. The direction Y and the direction X are perpendicular to each other, and the direction W is inclined with respect to the direction X and the direction Y. The bit lines 213 respectively intersect the active regions 105. Each active region 105 intersects only one of the plurality of bit lines 213. The bit line contact plugs 211 are respectively disposed below the intersections of the active regions 105 and the bit lines 213. The plurality of bit lines 213 are formed of a conductive material such as tungsten, aluminum, copper, nickel, or cobalt. The bit lines 213 are electrically connected to the bit line contact plugs 211 and the first doping regions 109.

Referring to fig. 1 to 3, in the illustrated embodiment, the bottom insulating layer 401 is disposed on the second insulating layer 603. The middle insulating layer 403 is disposed on the bottom insulating layer 401. The top insulating layer 405 is disposed on the middle insulating layer 403. The bottom insulating layer 401 and the top insulating layer 405 are formed of a first material. The intermediate insulating layer 403 is formed of a second material. The density of the first material is greater than the density of the second material. The first material comprises polysilicon and the second material comprises doped polysilicon. Alternatively, in another embodiment shown, the first material and the second material comprise oxidizable materials (oxidizable materials). Alternatively, in another embodiment shown, the first material comprises an undoped oxidizable material (undoped oxidizable material) or a doped oxidizable material (undoped oxidizable material). The second material comprises a doped material or a doped oxidizable material. Alternatively, in another embodiment shown, the first material is an undoped oxide. The ratio of the thickness of the top insulating layer 405 to the thickness of the middle insulating layer 403 is between 5:1 and 1: 1.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of plugs 415 are disposed above the substrate 101. More specifically, the plugs 415 are correspondingly disposed on the second doping regions 111, respectively, and penetrate through the top insulating layer 405, the middle insulating layer 403, the bottom insulating layer 401, the second insulating layer 603, and the first insulating layer 601. That is, the plugs 415 are correspondingly disposed at two ends of each active region 105. The plugs 415 are formed of doped polysilicon, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or aluminum alloy. The plurality of plugs 415 are electrically connected to the plurality of second doping regions 111.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of spacers 419 are disposed above the substrate 101. More specifically, the spacers 419 are correspondingly disposed on the sidewalls of the plugs 415 and are surrounded by the top insulating layer 405, the middle insulating layer 403, the bottom insulating layer 401, the second insulating layer 603, and the first insulating layer 601. The spacers 419 are formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of support structures 301 are disposed above the substrate 101. The plurality of support structures 301 are respectively disposed adjacent to upper portions of the plurality of plugs 415, and the plurality of spacers 419 are disposed between the plurality of support structures 301 and the plurality of plugs 415. More specifically, the plurality of support structures 301 respectively surround the upper portions of the plurality of plugs 415. That is, the plurality of supporting structures 301 are respectively attached to the outer surfaces of the plurality of spacers 419. The plurality of support structures 301 includes a plurality of top support structures 303, a plurality of middle support structures 305, and a plurality of bottom support structures 307.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of top support structures 303 are disposed in the top insulating layer 405 and respectively surround upper portions of the plurality of plugs 415. In other words, the top support structures 303 are respectively opposite to the plugs 415, and the spacers 419 are disposed between the top support structures 303 and the plugs 415. The plurality of top support structures 303 are formed from a material that is oxidized from the first material.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of middle support structures 305 are disposed in the middle insulating layer 403 and below the plurality of top support structures 303. The plurality of intermediate support structures 305 correspondingly surround the upper portions of the plurality of plugs 415, respectively. Along the direction X, adjacent pairs (adjacent pairs) of the plurality of intermediate support structures 305 are interconnected with each other. The interconnecting intermediate support structure 305 provides additional support for the plugs 415 and spacers 419. Along the direction W, adjacent pairs of the plurality of intermediate support structures 305 are spaced apart from each other by the intermediate insulating layer 403. The plurality of intermediate support structures 305 are formed from a material that is oxidized from the second material. The ratio of the height of the plurality of plugs 415 to the thickness of the plurality of intermediate support structures 305 is between 10:1 and 4: 1.

Referring to fig. 1-3, in the illustrated embodiment, the plurality of bottom support structures 307 are disposed in the bottom insulating layer 401 and below the plurality of middle support structures 305. The bottom support structures 307 respectively surround the upper portions of the plugs 415. In other words, the bottom supporting structures 307 are respectively opposite to the plugs 415, and the spacers 419 are disposed between the bottom supporting structures 307 and the plugs 415. The plurality of bottom support structures 307 are opposite the plurality of top support structures 303, and the plurality of intermediate support structures 305 are between the plurality of top support structures 303 and the plurality of bottom support structures 307. The plurality of bottom support structures 307 are formed from a material that is oxidized from the first material. The plurality of support structures 301 may provide additional mechanical force (mechanical strength) to the plurality of plugs 415 and the plurality of spacers 419; therefore, the structural stability of the semiconductor device can be improved.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of air gaps 421 are disposed in the top insulating layer 405 and respectively disposed above the plurality of top supporting structures 303. The plurality of air gaps 421 are respectively disposed adjacent to upper portions of the plurality of plugs 415, and the plurality of spacers 419 are disposed between the plurality of air gaps 421 and the plurality of plugs 415. More specifically, the plurality of air gaps 421 are respectively adjacent to upper portions of outer surfaces of the plurality of air gaps 421, respectively. The plurality of air gaps 421 are spaces surrounded by the plurality of spacers 419, the top insulating layer 405, and the plurality of capacitor structures 501, and are filled with air. The plurality of air gaps 421 have a lower dielectric constant than a film formed of, for example, silicon oxide. Therefore, the air gaps 421 can significantly reduce parasitic capacitance (parasitic capacitance) between the plugs 415. That is, the plurality of air gaps 421 can significantly mitigate electrical signal interference caused by or that may affect the plurality of plugs 415. Therefore, the performance of the semiconductor device is improved. In addition, the air gaps 421 are adjacent to the upper portions of the plugs 415 only, so that the structural stability of the plugs 415 is not affected.

The sealing layer 605 is disposed on the top insulating layer 405. The sealing layer 605 is formed of an insulating material. Such as silicon oxide, silicon nitride, spin-on glass (spin-on glass), silicon oxynitride, silicon nitride oxide, or the like. The sealing layer 605 has a thickness of between about 1000 angstroms and about 5000 angstroms. The thickness of the sealing layer 605 may be adjusted to an appropriate range according to circumstances.

Referring to fig. 1-3, in the illustrated embodiment, the third insulating layer 607 is disposed on the sealing layer 605. The third insulating layer 607 can be formed of the same material as the first insulating layer 601, but is not limited thereto.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of capacitor structures 501 are disposed above the substrate 101. More specifically, the plurality of capacitor structures 501 are disposed in the sealing layer 605 and the third insulating layer 607. The plurality of capacitor structures 501 are respectively disposed on the plurality of plugs 415, and are electrically connected to the plurality of plugs 415. The plurality of capacitor structures 501 includes a plurality of capacitor bottom electrodes 505, a capacitor insulating layer 507, and a capacitor top electrode 509.

Referring to fig. 1 to 3, in the illustrated embodiment, the plurality of capacitor bottom electrodes 505 are recessed in the third insulating layer 607 and the sealing layer 605. The plurality of capacitor bottom electrodes 505 are respectively disposed on the plurality of plugs 415 correspondingly. The bottoms of the capacitor bottom electrodes 505 respectively cover the top surfaces of the plugs 415 and the air gaps 421. Each capacitor bottom electrode 505 is U-shaped. The plurality of capacitor bottom electrodes 505 are formed of doped polysilicon, metal, or metal silicide.

Referring to fig. 1 to 3, the capacitor insulating layers 507 are correspondingly disposed on the plurality of capacitor bottom electrodes 505, respectively, and cover the top surface of the third insulating layer 607. The capacitor insulating layer 507 is formed of a single layer structure including an insulating material having a dielectric constant of about 4.0 or greater than 4.0, and the capacitor insulating layer 507 has a thickness of between about 1 a and about 100 a. Alternatively, in another embodiment, the capacitor insulating layer 507 is formed of a stack of layers of silicon oxide, silicon nitride, and silicon oxide. The capacitor top electrode 509 is disposed on the capacitor insulating layer 507. Alternatively, the capacitor insulating layer 507 is formed of doped polysilicon or metal.

Fig. 4 is a schematic diagram illustrating a method 10 of manufacturing a semiconductor device in one embodiment of the present disclosure in a flowchart. Fig. 5 is a schematic top view, fig. 6 and fig. 7 are schematic diagrams illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in cross-sectional views, wherein fig. 7 is a schematic cross-sectional view taken along C-C in fig. 5. For simplicity, some elements of the semiconductor device are not shown in fig. 5.

Referring to fig. 4 and 7, in step S11, in the illustrated embodiment, a substrate 101 is provided. Referring to fig. 4, 7 and 5, in step S13, in the illustrated embodiment, an isolation layer 103 is formed on an upper portion of the substrate 101. A photolithography process is performed to define the location in the substrate 101 where the isolation layer 103 is to be formed. After the photolithography process, an etching process is performed to form a plurality of trenches in the upper portion of the substrate 101, wherein the etching process is anisotropic dry etching. An insulating material is deposited in the plurality of trenches via a deposition process. Such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide or a fluorine doped silicate. After the deposition process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes while forming the isolation layer 103. The isolation layer 103 defines a plurality of active regions 105 in the substrate 101. The plurality of active regions 105 extend in a direction W.

Fig. 8 is a schematic diagram illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure in cross-section.

Referring to fig. 4 and 8, in step S15, a plurality of doped regions 107 are formed in the plurality of active regions 105 by an implantation process using a dopant, such as phosphorus, arsenic or antimony.

Fig. 9 is a schematic top view and fig. 10 to 13 are schematic cross-sectional views illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Wherein, FIG. 13 is a schematic cross-sectional view taken along D-D in FIG. 9. For simplicity, some elements of the semiconductor device are not shown in fig. 9.

Referring to fig. 4 and 9-13, in step S17, in the illustrated embodiment, a plurality of word lines 201 are formed in the substrate 101. Referring to FIG. 10, in the illustrated embodiment, a photolithography process is performed to pattern the substrate 101 to define the locations where the plurality of word lines 201 are to be formed. After the photolithography process, an etching process is performed to form a plurality of word line trenches 203 in the upper portion of the substrate 101, wherein the etching process is an anisotropic dry etching. The plurality of word line trenches 203 extend along a direction X, and the plurality of word line trenches 203 are spaced apart from each other. The direction W is inclined with respect to the direction X, and the plurality of word line trenches 203 and the plurality of active regions 105 intersect. Each active region 105 intersects two wordline trenches 203. The doped region 107 in each active region 105 is divided into a first doped region 109 and a plurality of second doped regions 111 by the two wordline trenches 203. The first doped region 109 is disposed between the two wordline trenches 203. The second doping regions 111 are correspondingly disposed at two ends of each active region 105.

Referring to fig. 11, in the illustrated embodiment, the wordline insulating layers 205 are formed in the wordline trenches 203 respectively by a deposition process. A planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processing.

Referring to fig. 12, a plurality of wordline electrodes 207 are correspondingly formed on the wordline insulating layer 205 and in the wordline trenches 203, respectively. A deposition process is performed to deposit the plurality of wordline electrodes 207. An etch-back process is performed such that the top surfaces of the word line electrodes 207 are lower than the top surface of the substrate 101.

Referring to fig. 9 and 12, in the illustrated embodiment, the plurality of wordline caps 209 are formed on the plurality of wordline electrodes 207 and in the plurality of wordline trenches 203, respectively, by a deposition process. A planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processing. The wordline insulating layer 205, the wordline electrodes 207, and the wordline cap layers 209 collectively form the wordlines 201.

Fig. 14 is a schematic top view and fig. 15 is a schematic cross-sectional view taken along line E-E of fig. 14 illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 16 is a schematic top view, and fig. 17 and 18 are schematic diagrams of a semiconductor device in an embodiment of the disclosure, wherein fig. 17 is a cross-sectional view taken along F-F in fig. 16, and fig. 18 is a cross-sectional view taken along G-G in fig. 16, illustrating a partial flow of a method for manufacturing the semiconductor device in an embodiment of the disclosure. For simplicity, some elements of the semiconductor device are not shown in fig. 14 and 16.

Referring to fig. 4 and 14-18, in step S19, in the illustrated embodiment, a plurality of bit lines 213 are formed over the substrate 101. Referring to fig. 14 and 15, in the illustrated embodiment, a first insulating layer 601 is formed on the substrate 101. A photolithography process is performed to pattern the first insulating layer 601 to define locations where the bit line contact plugs 211 are to be formed. After the photolithography process, an etching process is performed to form a plurality of openings penetrating the first insulating layer 601 and exposing the plurality of first doped regions 109, wherein the etching process is anisotropic dry etching. A conductive material is deposited into the plurality of openings by a deposition process, the conductive material being doped polysilicon, metal nitride or metal silicide. After the deposition process, a planarization process, such as chemical mechanical polishing, is performed to remove the excess filler and provide a flat surface for the subsequent processes, and simultaneously form the bit line contact plugs 211.

Referring to fig. 16 to 18, in the illustrated embodiment, a second insulating layer 603 is formed on the first insulating layer 601. A photolithography process is performed to pattern the second insulating layer 603 to define locations where the plurality of bit lines 213 are to be formed. After the photolithography process, an etching process is performed to form a plurality of openings penetrating the second insulating layer 603 and exposing the plurality of bit line contact plugs 211, and the etching process is anisotropic dry etching. Depositing a conductive material in the plurality of openings by a deposition process, wherein the conductive material is tungsten, aluminum, copper, nickel or cobalt. After the deposition process, a planarization process, such as chemical mechanical polishing, is performed to remove the excess filler and provide a flat surface for the subsequent processes, and simultaneously form the plurality of bit lines 213. The plurality of bit lines 213 extend in a direction Y, and the plurality of bit lines 213 have a long stripe shape when viewed from above. The direction Y and the direction X are perpendicular to each other.

Fig. 19 is a schematic top view, fig. 20 and fig. 21 are schematic diagrams of a semiconductor device according to an embodiment of the disclosure, wherein fig. 20 is a schematic cross-sectional view taken along H-H in fig. 19, and fig. 18 is a schematic cross-sectional view taken along I-I in fig. 19, illustrating a partial flow of a method for manufacturing the semiconductor device according to an embodiment of the disclosure. . Fig. 22 is a schematic top view, fig. 23 and fig. 24 are schematic diagrams illustrating a semiconductor device according to an embodiment of the disclosure, wherein fig. 23 is a schematic cross-sectional view taken along J-J in fig. 22, and fig. 24 is a schematic cross-sectional view taken along K-K in fig. 22, illustrating a partial flow of a method for manufacturing the semiconductor device according to an embodiment of the disclosure. Fig. 25 is a schematic top view of a semiconductor device according to an embodiment of the disclosure, fig. 26 to 28 are schematic diagrams, in which fig. 27 is a schematic cross-sectional view taken along L-L in fig. 25, and fig. 28 is a schematic cross-sectional view taken along M-M in fig. 25, illustrating a partial flow of a method for manufacturing a semiconductor device according to another embodiment of the disclosure. . For simplicity, some elements of the semiconductor device are not shown in fig. 19, 22 and 25.

Referring to fig. 4 and 19-28, in step S21, in the illustrated embodiment, a plurality of support structures 301 are formed over the substrate 101. Referring to fig. 19-21, in the illustrated embodiment, a column deposition process is performed to deposit a bottom insulating layer 401, an intermediate insulating layer 403, and a top insulating layer 405. The bottom insulating layer 401 is formed on the second insulating layer 603. The middle insulating layer 403 is formed on the bottom insulating layer 401. The top insulating layer 405 is formed on the middle insulating layer 403. The bottom insulating layer 401 and the top insulating layer 405 are formed of a first material. The intermediate insulating layer 403 is formed of a second material. The density of the first material is greater than the density of the second material. More specifically, the first material comprises polysilicon and the second material comprises doped polysilicon. Alternatively, in another embodiment shown, the first material and the second material comprise oxidizable materials. Alternatively, in another embodiment shown, the first material comprises an undoped oxidizable material or a doped oxidizable material. The second material comprises a doped material or a doped oxidizable material. Alternatively, in another embodiment shown, the first material is an undoped oxide. The ratio of the thickness of the top insulating layer 405 to the thickness of the middle insulating layer 403 is between 5:1 and 1: 1.

Referring to fig. 22-24, in the illustrated embodiment, a masking layer 701 is formed on the top insulating layer 405. A photolithography process is performed to define the locations where trenches 407 are to be formed in a plurality of processes. After the photolithography process, an etching process is performed to form the plurality of in-process trenches 407 in the mask layer 701 and the top insulating layer 405, the etching process being anisotropic dry etching. A sacrificial layer 703 is deposited from above and covers the top surface of the mask layer 701, the side surfaces of the in-process trenches 407, and the bottom of the in-process trenches 407. The sacrificial layer 703 is formed of a material having an etch selectivity with respect to the top insulating layer 405. More specifically, the sacrificial layer 703 is formed of a doped oxide, which is borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, carbon-doped silicon oxide, or the like. The top insulating layer 405 is formed of undoped oxide. Alternatively, in another embodiment, the sacrificial layer 703 is formed of a thermally decomposable polymer or a thermally degradable polymer. When the thermally decomposed polymer or thermally degraded polymer is exposed to a temperature higher than its decomposition temperature or degradation temperature, the thermally decomposed polymer or thermally degraded polymer will decompose or degrade into a gaseous state.

Referring to fig. 26, an anisotropic dry etching process is performed to remove portions of the sacrificial layer 703 covering the top surface of the mask layer 701 and the bottoms of the trenches 407 in the plurality of processes. After the anisotropic dry etching process, the sacrificial layer 703 is transformed into a plurality of sacrificial pads 409. A wet etching process is then performed to etch a plurality of etched spaces 411 respectively corresponding to the lower portions of the plurality of in-process trenches 407. The etched spaces 411 respectively penetrate the lower portion of the top insulating layer 405, the portion of the middle insulating layer 403, and the upper portion of the bottom insulating layer 401. The wet etch process has a higher etch rate for the middle insulating layer 403 formed of the second material than the top insulating layer 405 or the bottom insulating layer 401. Thus, the middle insulating layer 403 is removed faster and more compared to the bottom insulating layer 401 and the top insulating layer 405. In other words, the volume of the plurality of etched spaces 411 in the middle insulating layer 403 will be larger than the volume of the plurality of etched spaces 411 in the bottom insulating layer 401 or the top insulating layer 405.

Referring to fig. 25 and 27 to 28, an oxidation process is performed to oxidize the plurality of etched spaces 411. The areas of the bottom insulating layer 401, the middle insulating layer 403, and the top insulating layer 405 exposed by the etched spaces 411 will be oxidized to form bottom support structures 307, middle support structures 305, and top support structures 303, respectively. The plurality of bottom support structures 307 are located in the bottom insulating layer 401 and respectively located above the plurality of second doped regions 111. The plurality of middle support structures 305 are located in the middle insulating layer 403 and above the plurality of bottom support structures 307. The plurality of top support structures 303 are located in the top insulating layer 405 and above the plurality of middle support structures 305.

Referring to fig. 25 and 27-28, the oxidation process has a higher oxidation rate for the middle insulating layer 403 formed from the second material than the bottom insulating layer 401 or the top insulating layer 405 formed from the first material; therefore, a larger portion of the intermediate insulating layer 403 is oxidized. More specifically, the regions of the intermediate insulating layer 403 along the direction X and adjacent to the etched spaces 411 will be oxidized into interconnected intermediate support structures 305 along the direction X; in contrast, after the oxidation process, the intermediate support structures 305 along the direction W or the direction Y are still spaced apart from each other. The plurality of top support structures 303, the plurality of middle support structures 305, and the plurality of bottom support structures 307 collectively comprise the plurality of support structures 301.

Fig. 29 is a schematic top view and fig. 30 is a schematic cross-sectional view taken along line N-N of fig. 29 illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 31 to 35 are schematic views illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in cross-section. For simplicity, some elements of the semiconductor device are not shown in fig. 30.

Referring to fig. 4 and 29-35, in step S23, in the illustrated embodiment, plugs 415 and air gaps 421 are formed over the substrate 101. Referring to fig. 29 and 30, the in-process trenches 407 and the etched spaces 411 are further dug deep to form a plurality of plug trenches 413, the plurality of plug trenches 413 penetrating the mask layer 701, the top insulating layer 405, the plurality of middle support structures 305, the bottom insulating layer 401, the second insulating layer 603 and the first insulating layer 601. The second doping regions 111 are correspondingly exposed through the plug trenches 413, respectively.

Referring to fig. 31, in the illustrated embodiment, the mask layer 701 is removed. Next, a spacer layer 417 is deposited to cover the top surface of the top insulating layer 405, the sidewalls of the plurality of plug trenches 413, and the bottoms of the plurality of plug trenches 413. The spacer layer 417 is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. More specifically, the spacer layer 417 is formed of silicon oxide. Referring to fig. 32, in the illustrated embodiment, an etching process is performed to remove the spacer layer 417 covering the top surface of the top insulating layer 405 and the bottom portions of the plug trenches 413, and simultaneously form a plurality of spacers 419 respectively attached to the sidewalls of the plug trenches 413. After the etch process, the sacrificial liners 409 are exposed.

Referring to fig. 33, in the illustrated embodiment, the plurality of plug trenches 413 is filled with a conductive material, such as doped polysilicon, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or aluminum alloy, by a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes, and simultaneously form the plugs 415.

Referring to fig. 34, in the illustrated embodiment, the sacrificial liners 409 are removed with a hf vapor and air gaps 421 are formed at the same location. The hydrogen fluoride vapor has a higher etch rate for the sacrificial pads 409 formed from the doped oxide due to the different densities between the sacrificial pads 409 formed from the doped oxide and the top insulating layer 405 and spacers 419 formed from the undoped oxide; thus, the sacrificial liners 409 formed of doped oxide are removed by the hf vapor, while the top insulating layer 405 and spacers 419 formed of undoped oxide remain. Alternatively, as shown in another embodiment, when the sacrificial pads 409 are formed of a thermally decomposable polymer or a thermally degradable polymer, a heating process is performed to remove the sacrificial pads 409. The temperature of the heating process is between about 300 degrees celsius and about 450 degrees celsius. Preferably, the temperature of the heating process is between about 350 degrees Celsius and about 420 degrees Celsius. Referring to fig. 35, in the illustrated embodiment, a sealing layer 605 is formed on the top insulating layer 405. The sealing layer 605 covers the plurality of air gaps 421, the plurality of spacers 419, and the plurality of spacers 419.

Fig. 36 to 38 are schematic views illustrating a partial flow of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure in cross-section.

Referring to fig. 1-4 and 36-38, in step S25, in the illustrated embodiment, a plurality of capacitor structures 501 are formed over the substrate 101. Referring to fig. 36, in the illustrated embodiment, a third insulating layer 607 is formed over the sealing layer 605. A photolithography process is performed to define the locations where the plurality of capacitive structures 501 are to be formed. After the photolithography process, an etching process is performed to form a plurality of capacitor trenches 503 penetrating the third insulating layer 607 and the sealing layer 605, and the etching process is anisotropic dry etching. The plugs 415 are correspondingly exposed through the capacitor trenches 503.

Referring to fig. 37, in the illustrated embodiment, an insulating layer is deposited to cover the top surface of the third insulating layer 607, the sidewalls of the plurality of capacitor trenches 503, and the bottoms of the plurality of capacitor trenches 503. A planarization process, such as chemical mechanical polishing, is performed to remove the portion of the insulating layer covering the top surface of the third insulating layer 607 and simultaneously form a plurality of capacitor bottom electrodes 505. Referring to fig. 38, in the illustrated embodiment, a capacitor insulating layer 507 is formed on the plurality of capacitor bottom electrodes 505 and in the plurality of capacitor bottom electrodes 505, the capacitor insulating layer 507 also covering the top surface of the third insulating layer 607. Referring back to fig. 1-3, in the illustrated embodiment, a capacitor top electrode 509 is formed on the capacitor insulating layer 507 and fills the plurality of capacitor trenches 503.

One aspect of the present disclosure provides a semiconductor device including a substrate, a plurality of plugs disposed over the substrate, a plurality of air gaps disposed adjacent to the plurality of plugs, and a plurality of capacitor structures disposed over the substrate.

A method for fabricating a semiconductor device includes providing a substrate, forming a plurality of plugs over the substrate, forming a plurality of air gaps adjacent to the plurality of plugs, and forming a plurality of capacitor structures over the substrate.

Due to the design of the semiconductor device of the present disclosure, the parasitic capacitance of the semiconductor device will be reduced, and thus the performance of the semiconductor device will be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are intended to be included within the scope of the present invention.