阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 鱼住宜弘 于 2020-09-09 设计创作，主要内容包括：实施方式涉及一种半导体装置及其制造方法。实施方式的半导体装置具备：贴合衬底,所述贴合衬底具备第1芯片构成部以及贴合于所述第1芯片构成部的第2芯片构成部,所述第1芯片构成部具有设置在半导体衬底的第1金属焊垫、以及连接于第1金属焊垫的第1电路,所述第2芯片构成部具有与第1金属焊垫接合的第2金属焊垫、以及连接于第2金属焊垫的第2电路；以及绝缘膜,填充在贴合衬底的外周部中的第1芯片构成部与第2芯片构成部的未贴合区域,且至少一部分包含选自由氮化硅及含氮碳化硅组成的群中的至少一种。(Embodiments relate to a semiconductor device and a method of manufacturing the same. The semiconductor device of the embodiment includes: a bonded substrate including a 1 st chip component and a 2 nd chip component bonded to the 1 st chip component, the 1 st chip component including a 1 st metal pad provided on a semiconductor substrate and a 1 st circuit connected to the 1 st metal pad, the 2 nd chip component including a 2 nd metal pad joined to the 1 st metal pad and a 2 nd circuit connected to the 2 nd metal pad; and an insulating film which fills a non-bonded region between the 1 st chip component and the 2 nd chip component in the outer periphery of the bonded substrate, and at least a part of which includes at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.)

1. A semiconductor device includes:

a bonded substrate including a 1 st chip component and a 2 nd chip component bonded to the 1 st chip component, the 1 st chip component including a 1 st metal pad provided on a semiconductor substrate and a 1 st circuit connected to at least a part of the 1 st metal pad, the 2 nd chip component including a 2 nd metal pad bonded to the 1 st metal pad and a 2 nd circuit connected to at least a part of the 2 nd metal pad; and

and an insulating film which fills a non-bonded region between the 1 st chip component and the 2 nd chip component in an outer peripheral portion of the bonded substrate, and at least a part of which includes at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

2. The semiconductor device according to claim 1, wherein the insulating film has: a 1 st insulating film filled in a 1 st portion of the non-bonded region along surfaces of the 1 st and 2 nd chip components exposed in the non-bonded region, the insulating film including at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide; and a 2 nd insulating film filling a 2 nd portion of the non-bonded region other than the 1 st portion and including at least one selected from the group consisting of silicon oxide and silicon oxynitride.

3. The semiconductor device according to claim 2, wherein the 2 nd insulating film comprises the silicon oxide doped with at least one selected from the group consisting of boron, phosphorus, fluorine, and carbon.

4. The semiconductor device according to claim 1, wherein the bonded substrate has a cutout portion provided so as to cut out a part of the non-bonded region in the outer peripheral portion,

the insulating film fills at least a remaining portion of the non-bonded region where a part thereof is cut out.

5. The semiconductor device according to claim 4, wherein the cutout portion has a step-difference shape,

the insulating film is further provided along the step shape of the cutout.

6. The semiconductor device according to claim 5, wherein the insulating film has: a 1 st insulating film provided along the step shape of the cutout and a surface of the cutout, the 1 st insulating film including at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide; and a 2 nd insulating film provided on the 1 st insulating film along a step shape of the step portion, and including at least one selected from the group consisting of silicon oxide and silicon oxynitride.

7. The semiconductor device according to claim 1, wherein the 2 nd chip component is a memory cell array chip having the 2 nd circuit, the 2 nd circuit includes a plurality of memory cells, and a 2 nd wiring layer connecting the plurality of memory cells to at least a part of the 2 nd metal pad,

the 1 st chip component is a control circuit chip having the 1 st circuit and controlling the memory cell array chip, and the 1 st circuit includes a plurality of transistors and a 1 st wiring layer connecting the plurality of transistors to at least a part of the 1 st metal pad.

8. A semiconductor device includes:

a bonding substrate including a 1 st chip component and a 2 nd chip component bonded to the 1 st chip component, the 1 st chip component including a 1 st metal pad provided on a semiconductor substrate and a 1 st circuit connected to at least a part of the 1 st metal pad, the 2 nd chip component including a 2 nd metal pad joined to the 1 st metal pad and a 2 nd circuit connected to at least a part of the 2 nd metal pad, the bonding substrate including a non-bonded region of the 1 st chip component and the 2 nd chip component in an outer peripheral portion thereof, and a notch portion provided to cut off at least a part of the non-bonded region of the 2 nd chip component; and

and an insulating film filling at least a part of the remaining portion of the non-bonded region.

9. The semiconductor device according to claim 8, wherein the insulating film is further provided so as to cover a surface of a remaining portion of the bonded substrate from which a part of the non-bonded region is cut.

10. The semiconductor device according to claim 8, wherein a part of a non-bonded region of the 1 st chip component is cut out of the bonded substrate so as to face the cutout portion provided in the 2 nd chip component.

11. The semiconductor device according to claim 8, wherein a part of a non-bonded region of the 1 st chip component is not cut away from the bonded substrate so as to face the cutout portion provided in the 2 nd chip component.

12. The semiconductor device according to claim 8, wherein the insulating film comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, nitrogen-containing silicon carbide, and aluminum oxide.

13. The semiconductor device according to claim 8, wherein the 2 nd chip component is a memory cell array chip having the 2 nd circuit, the 2 nd circuit includes a plurality of memory cells, and a 2 nd wiring layer connecting the plurality of memory cells to at least a part of the 2 nd metal pad,

the 1 st chip component is a control circuit chip having the 1 st circuit and controlling the memory cell array chip, and the 1 st circuit includes a plurality of transistors and a 1 st wiring layer connecting the plurality of transistors to at least a part of the 1 st metal pad.

14. A method for manufacturing a semiconductor device includes the steps of:

preparing a 1 st chip component and a 2 nd chip component, wherein the 1 st chip component comprises a 1 st semiconductor substrate, a 1 st metal pad arranged on the 1 st semiconductor substrate, and a 1 st circuit connected to at least a part of the 1 st metal pad, and the 2 nd chip component comprises a 2 nd semiconductor substrate, a 2 nd metal pad arranged on the 2 nd semiconductor substrate, and a 2 nd circuit connected to at least a part of the 2 nd metal pad;

bonding a 1 st chip component to a 2 nd chip component so as to connect the 1 st metal pad to the 2 nd metal pad, thereby manufacturing a bonded substrate having a non-bonded region of the 1 st chip component and the 2 nd chip component on an outer peripheral portion thereof; and

at least a part of the non-bonded region of the bonded substrate is filled with an insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the step of filling the insulating film comprises the steps of: filling a 1 st portion of the non-bonded region along the 1 st and 2 nd chip components exposed in the non-bonded region with a 1 st insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide; and filling a 2 nd insulating film containing at least one selected from the group consisting of silicon oxide and silicon oxynitride in a 2 nd portion of the non-bonded region other than the 1 st portion.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the step of filling the 2 nd insulating film comprises the steps of: forming a film of the silicon oxide doped with at least one selected from the group consisting of boron, phosphorus, fluorine, and carbon as the 2 nd insulating film; and reflowing the silicon oxide.

17. The method for manufacturing a semiconductor device according to claim 14, further comprising the steps of: forming a notch by cutting off a part of the non-bonded region of at least one of the 1 st chip component and the 2 nd chip component in the bonded substrate before filling the insulating film,

the insulating film fills at least a remaining portion of the non-bonded region where a part thereof is cut out.

18. The method for manufacturing a semiconductor device according to claim 14, further comprising the steps of: after the insulating film is filled, a cut-out portion is formed by cutting out a portion of the non-bonded region and a portion of the insulating film of at least one of the 1 st chip component and the 2 nd chip component.

19. The method for manufacturing a semiconductor device according to claim 14, wherein the step of preparing the 1 st chip component and the 2 nd chip component includes the steps of: forming a notch by cutting out an outer peripheral portion of at least one of the 1 st chip component and the 2 nd chip component,

in the step of producing the bonded substrate, at least the 1 st chip component having the notch portion is bonded to the 2 nd chip component.

20. The method for manufacturing a semiconductor device according to claim 14, further comprising the steps of: removing at least a portion of the 2 nd semiconductor substrate in the 2 nd chip component.

Technical Field

Embodiments disclosed herein relate to a semiconductor device and a method of manufacturing the same.

Background

In order to achieve higher density of a semiconductor device, effective use of a device area, and the like, for example, a bonding process is applied in which metal pads provided on respective semiconductor substrates are bonded to each other and bonded to a semiconductor substrate having a memory cell and a semiconductor substrate having a peripheral circuit such as a CMOS (complementary metal oxide semiconductor). In a semiconductor device to which a bonding process is applied and a method for manufacturing the same, it is required to suppress chipping, peeling, or the like of at least one semiconductor substrate at the time of thinning, and to improve the quality or manufacturing yield of the semiconductor device.

Disclosure of Invention

Embodiments provide a semiconductor device and a method for manufacturing the same, which can suppress a reduction in characteristics, quality, manufacturing yield, and the like due to a bonding process.

A semiconductor device according to an embodiment includes: a bonded substrate including a 1 st chip component and a 2 nd chip component bonded to the 1 st chip component, the 1 st chip component including a 1 st metal pad provided on a semiconductor substrate and a 1 st circuit connected to the 1 st metal pad, the 2 nd chip component including a 2 nd metal pad joined to the 1 st metal pad and a 2 nd circuit connected to the 2 nd metal pad; and an insulating film which fills a non-bonded region between the 1 st chip component and the 2 nd chip component in an outer peripheral portion of the bonded substrate, and at least a part of which includes at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Drawings

Fig. 1 is a cross-sectional view showing a semiconductor device according to embodiment 1.

Fig. 2 is a sectional view showing a final structure of the semiconductor device according to embodiment 1.

Fig. 3 is a cross-sectional view showing an example of a state of bonding between metal pads in the semiconductor device according to embodiment 1.

Fig. 4A to 4D are cross-sectional views showing a manufacturing process of a semiconductor device according to embodiment 1.

Fig. 5 is a cross-sectional view showing the semiconductor device according to embodiment 2.

Fig. 6A to 6D are cross-sectional views showing a manufacturing process of a semiconductor device according to embodiment 2.

Fig. 7 is a cross-sectional view showing a semiconductor device according to embodiment 3.

Fig. 8 is a cross-sectional view showing a semiconductor device according to embodiment 4.

Fig. 9 is a cross-sectional view showing a modification of the semiconductor device according to embodiment 4.

Fig. 10A to 10E are cross-sectional views showing a manufacturing process of a semiconductor device according to embodiment 5.

Fig. 11 is a cross-sectional view showing a 1 st modification of the manufacturing process of the semiconductor device according to embodiment 5.

Fig. 12A and 12B are cross-sectional views showing a 2 nd modification of the manufacturing process of the semiconductor device according to embodiment 5.

Fig. 13 is a cross-sectional view showing an example of a configuration of a semiconductor chip using the semiconductor device of the embodiment.

Detailed Description

Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment will be described with reference to the drawings. In each embodiment, substantially the same constituent elements are denoted by the same reference numerals, and a part of the description thereof may be omitted. The drawings are schematic drawings, and the relationship between the thickness and the plane size, the thickness ratio of each portion, and the like may be different from the actual ones. In the case where no particular description is given, the term indicating the vertical direction in the description may indicate that the direction of relativity in the case where the surface of the semiconductor substrate 1 described below on which the metal pad is formed is not the same as the actual direction with reference to the gravitational acceleration direction.

(embodiment 1)

Fig. 1 and 2 are cross-sectional views showing a part of a semiconductor device 1(1A) according to embodiment 1. Fig. 1 shows a semiconductor device 1A at a preceding stage in which one semiconductor substrate out of 2 semiconductor substrates constituting a bonded substrate is thinned by back grinding or chemical solution treatment, and fig. 2 shows a semiconductor device 1A at a subsequent stage in which one semiconductor substrate is thinned by back grinding or chemical solution treatment.

The semiconductor device 1A shown in fig. 1 includes a 1 st semiconductor substrate 2 and a 2 nd semiconductor substrate 3. The 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded to form a bonded substrate 4. That is, the semiconductor device 1A includes the bonded substrate 4. Symbol S denotes a bonding surface of the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3. The bonding surface S is shown for convenience, and since the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are integrated, a bonding interface which can be visually recognized may not exist. However, by analyzing the cross section of the bonded substrate 4, it can be determined that the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded.

The 1 st semiconductor substrate 2 has a plurality of 1 st metal pads 5. The 1 st wiring layer 6 is connected to the 1 st metal pad 5. The 1 st metal pad 5 and the 1 st wiring layer 6 are embedded in the 1 st insulating layer 7 as an interlayer insulating film. The 2 nd semiconductor substrate 3 has a plurality of 2 nd metal pads 8. The 2 nd wiring layer 9 is connected to the 2 nd metal pad 8. The 2 nd metal pad 8 and the 2 nd wiring layer 9 are embedded in the 2 nd insulating layer 10 as an interlayer insulating film. Here, although the 1 st and 2 nd wiring layers 6 and 9 are connected to the 1 st and 2 nd metal pads 5 and 8, a dummy pad in which a part of the 1 st and 2 nd metal pads 5 and 8 is not connected to the wiring layers may be used.

The 1 st semiconductor substrate 2 has a 1 st circuit region 12 in which a 1 st circuit (not shown) including, for example, peripheral circuits (not shown) such as transistors and passive elements of a CMOS or the like and a wiring layer connecting these peripheral circuits to at least a part of the 1 st metal pad 5 is provided on a substrate portion 11. The 2 nd semiconductor substrate 3 has a 2 nd circuit region 14 in which a 2 nd circuit (not shown) including, for example, a pixel array including a plurality of pixels of an image sensor or a memory cell array including a plurality of memory cells, a source line, a plurality of word lines, a plurality of bit lines, a wiring layer connected to at least a part of the 2 nd metal pad 8, and the like is provided under the substrate portion 13. Details of the 1 st and 2 nd circuit regions 12 and 14 will be described later. The 1 st semiconductor substrate 2 constitutes, for example, a control circuit chip, and the 2 nd semiconductor substrate 3 constitutes, for example, an array chip.

As shown in fig. 2, the 2 nd semiconductor substrate 3 is thinned by performing back grinding or chemical treatment on the bonded substrate 4 so that at least the 2 nd circuit region 14 remains. At this time, the substrate portion 13 of the 2 nd semiconductor substrate 3 may not remain, or may remain. In the semiconductor device 1A shown in fig. 2, the 1 st semiconductor substrate 2 having the 1 st metal pad 5 or the 1 st circuit region 12 serves as the 1 st chip component. In addition, the 2 nd semiconductor substrate 3 having the 2 nd metal pad 8 or the 2 nd circuit region 14 and the substrate portion 13 removed, in other words, the remaining portion of the 2 nd semiconductor substrate 3 from which the substrate portion 13 is removed becomes the 2 nd chip constituent part.

The 1 st metal pad 5 and the 2 nd metal pad 8 facilitate the attachment of the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3. In addition, the 1 st insulating layer 7 and the 2 nd insulating layer 10 also contribute to bonding of the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3. The 1 st and 2 nd metal pads 5 and 8 use copper, a copper alloy, or the like, but may include a conductive material such as a metal other than these. The 1 st and 2 nd insulating layers 7 and 10 are made of an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or nitrogen-containing silicon carbide (SiCN), but may be made of an insulating material other than these. The 1 st and 2 nd insulating layers 7 and 10 may be formed by laminating one or more materials.

The surface of the 1 st metal pad 5 exposed on the 1 st semiconductor substrate 2 and the surface of the 2 nd metal pad 8 exposed on the 2 nd semiconductor substrate 3 are directly bonded by intermetallic element diffusion, van der waals force, volume expansion, or recrystallization, and the like, and the surface of the 1 st insulating layer 7 exposed on the 1 st semiconductor substrate 2 and the surface of the 2 nd insulating layer 10 exposed on the 2 nd semiconductor substrate 3 are directly bonded by chemical reaction such as diffusion of elements between insulators, van der waals force, dehydration condensation, or polymerization, and the like, and the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded.

When the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded, the 1 st and 2 nd semiconductor substrates 2 and 3 are processed by, for example, Chemical Mechanical Polishing (CMP) in order to planarize the exposed surfaces of the 1 st and 2 nd metal pads 5 and 8. When the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 are processed by CMP, the corners of the outer peripheries may have a curvature. When the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded, the surface may be receded due to the curvature of the corner, and a non-bonded region 15 may be generated in the outer peripheral portion of the bonded substrate 4.

When the non-bonded region 15 exists in the outer peripheral portion of the bonded substrate 4, the metal material such as copper forming the 1 st and 2 nd metal pads 5 and 8 may diffuse to contaminate the semiconductor device 1A. Fig. 3 is a cross-sectional view showing an example of a bonding state between the 1 st and 2 nd metal pads 5 and 8 in the semiconductor device 1A. In fig. 3, reference numeral 16 denotes a barrier metal layer. As shown in fig. 3, if a position offset occurs between the 1 st metal pad 5 and the 2 nd metal pad 8, the surfaces of the metal pads 5 and 8 are exposed at the bonding surface S. Contamination may occur due to diffusion of a metal material such as copper from the exposed surface of such metal pads 5, 8. Further, when the non-bonded region reaches the metal pad portion, the metal surface is exposed, and contamination of the metal material may spread from this region to the substrate itself or the manufacturing apparatus. These circumstances may cause a reduction in the electrical characteristics of the semiconductor device 1A.

In the semiconductor device 1A according to embodiment 1, the non-bonded region 15 generated in the outer peripheral portion of the bonded substrate 4 is filled with the insulating film 17. The insulating film 17 suppresses an influence on the electrical characteristics of the 1 st and 2 nd circuit regions 12 and 14, and includes at least one selected from silicon nitride (SiN) and nitrogen-containing silicon carbide (SiCN) which can be formed at a low temperature (for example, 450 ℃. Since SiN or SiCN functions as a diffusion barrier for a metal material such as copper (Cu), it is possible to suppress a decrease in electrical characteristics or the like due to diffusion and contamination of the metal material such as copper from the exposed surfaces of the 1 st and 2 nd metal pads 5 and 8. The insulating film 17 is not limited to being formed of one material, and may be a mixed film or a laminated film of a plurality of materials. Further, SiN or SiCN may have poor filling properties into the non-bonded region 15 when formed at a particularly low temperature. In this case, it is effective to trim the non-bonded region 15 or a part of the insulating film 17 (embodiments 2, 3, and 5), or to use the insulating film 17 containing SiN or SiCN in combination with an insulating material having excellent filling properties (embodiment 4).

With respect to the bonded substrate 4 having the non-bonded region 15 in the outer peripheral portion, if so-called back grinding is performed to grind, for example, the back surface of the 2 nd semiconductor substrate 3, chipping and peeling may occur, and the quality and manufacturing yield of the semiconductor device 1A may be lowered. In this case, chipping and peeling at the time of back grinding can be suppressed by filling the non-bonded region 15 with the insulating film 17. When the non-bonded region 15 reaches the metal pad portion, the metal surface is exposed, and contamination of the metal material may spread from this region to the substrate itself or the manufacturing apparatus. On the other hand, by filling the non-bonded region 15 with the insulating film 17, it is possible to suppress contamination of the substrate or the manufacturing apparatus with the metal material during the back grinding or the chemical solution treatment and in the subsequent manufacturing process apparatuses. Therefore, the quality or manufacturing yield of the semiconductor device 1A can be improved. Further, it is considered that a defect such as back grinding is suppressed by trimming the outer peripheral portion of the bonded substrate 4 so as to remove the whole of the non-bonded region 15. However, since the trimming region completely removes the non-bonded region, there is a problem that the element forming region becomes small. In contrast, by filling the non-bonded region 15 with the insulating film 17, the trimming region can be reduced even when trimming is not necessary or is separately performed, and therefore the element formation region can be enlarged.

The semiconductor device 1A according to embodiment 1 is manufactured, for example, as follows. The manufacturing process of the semiconductor device 1A will be described with reference to fig. 4A to 4D. First, as shown in fig. 4A, the 1 st semiconductor substrate 2 in which the surfaces of the 1 st metal pad 5 and the 1 st insulating layer 7 are exposed, and the 2 nd semiconductor substrate 3 in which the surfaces of the 2 nd metal pad 8 and the 2 nd insulating layer 10 are exposed are prepared. The surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 are planarized by CMP. At this time, the corners of the 1 st and 2 nd insulating layers 7 and 10 of the 1 st and 2 nd semiconductor substrates 2 and 3 may have a curvature by CMP, and the surfaces of the outer peripheral portions of the 1 st and 2 nd semiconductor substrates 2 and 3 may recede.

Next, as shown in fig. 4B, the 1 st semiconductor substrate 2 in which the surfaces of the 1 st metal pad 5 and the 1 st insulating layer 7 are exposed and the 2 nd semiconductor substrate 3 in which the surfaces of the 2 nd metal pad 8 and the 2 nd insulating layer 10 are exposed are bonded to each other. The bonding process is performed under conventionally known conditions. For example, the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded by mechanical pressure. Thereby, the 1 st insulating layer 7 and the 2 nd insulating layer 10 are joined and integrated. Then, the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are annealed at a temperature of, for example, 400 ℃. Thereby, the 1 st metal pad 5 and the 2 nd metal pad 8 are joined, and these 1 st and 2 nd metal pads 5, 8 are electrically connected and integrated.

In this way, a bonded substrate 4 is produced by bonding the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3. At this time, since the surface recedes based on the curvature generated in the outer peripheral portions of the 1 st and 2 nd semiconductor substrates 2 and 3, a non-bonded region 15 where the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are not bonded is formed in the outer peripheral portion of the bonded substrate 4. As described above, the unbonded area 15 causes diffusion and contamination of a metal material such as copper from the exposed surface of the 1 st and 2 nd metal pads 5 and 8, and also causes chipping and peeling during back grinding. Therefore, as shown in fig. 4C, the non-bonded region 15 is filled with the insulating film 17.

The step of filling the non-bonded region 15 with the insulating film 17 is performed by forming an insulating material as described above by peripheral CVD (Chemical Vapor Deposition/Chemical Vapor Deposition). The insulating film 17 may be filled by forming a coating solution containing an insulating material by a coating method. Further, the non-bonded region 15 may be filled with an insulating material by outer periphery CVD, outer periphery coating, or the like, and the insulating material may be reflowed. In some cases, the filling property of the insulating film 17 into the non-bonded region 15 can be improved by filling the insulating material and reflowing the insulating material.

As described above, by filling the non-bonded region 15 generated in the outer peripheral portion of the bonded substrate 4 with the insulating film 17 containing SiN or SiCN, it is possible to suppress a decrease in electrical characteristics or the like caused by diffusion or contamination of a metal material such as copper from the exposed surfaces of the 1 st and 2 nd metal pads 5 and 8. Further, by filling the non-bonded region 15 generated in the outer peripheral portion of the bonded substrate 4 with the insulating film 17, chipping and peeling at the time of back grinding due to the non-bonded region 15 can be suppressed. Therefore, as shown in fig. 4D, the thickness of the 2 nd semiconductor substrate 3 can be reduced to a desired thickness by, for example, performing back grinding or chemical treatment on the back surface (the surface opposite to the surface on which the 2 nd metal pad 8 is formed) of the 2 nd semiconductor substrate 3 without trimming the outer peripheral portion of the bonded substrate 4. According to the semiconductor device 1A and the manufacturing method thereof, not only the manufacturing yield of the semiconductor device 1A can be improved, but also the characteristics, quality, reliability, and the like of the semiconductor device 1A can be improved. Further, since the area of the bonded substrate 4 is effectively used, the manufacturing cost of the semiconductor chip manufactured by the semiconductor device 1A can be reduced.

(embodiment 2)

Next, a semiconductor device 1B according to embodiment 2 will be described with reference to fig. 5. A semiconductor device 1B shown in fig. 5 includes a bonded substrate 4 produced by bonding a 1 st semiconductor substrate 2 and a 2 nd semiconductor substrate 3, as in embodiment 1. The specific configuration of the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 is also the same as that of embodiment 1. Bonded substrate 4 has unbonded area 15 located at the outer peripheral portion, as in embodiment 1.

The semiconductor device 1B according to embodiment 2 differs from the semiconductor device 1A according to embodiment 1 in that the outer peripheral portion of the bonded substrate 4 is trimmed so that at least a part of the 1 st semiconductor substrate 2 remains from the 2 nd semiconductor substrate 3 side or so that at least a part of the 2 nd semiconductor substrate 3 remains from the 1 st semiconductor substrate 2 side, and then the non-bonded region 15 is filled with the insulating film 17. The insulating film 17 is formed of the same insulating material as in embodiment 1. The insulating film 17 is not limited to being formed of one material, and may be a mixed film or a laminated film of a plurality of materials. The insulating film 17 containing SiN or SiCN can be formed at a low temperature, but may have poor filling properties into the non-bonded region 15. In this case, it is effective to trim the outer peripheral portion of bonded substrate 4 to reduce the volume of non-bonded region 15 filled with insulating film 17. The trimming is performed, for example, so as to reach a part of the 1 st semiconductor substrate 2 from the 2 nd semiconductor substrate 3 side, and a part of the non-bonded region 15 of the 1 st semiconductor substrate 2 is also cut away at a portion facing the notch 18 provided at the outer peripheral portion of the 2 nd semiconductor substrate 3.

That is, in the outer peripheral portion of bonded substrate 4, notch 18 is provided so as to cut off a part of non-bonded region 15 in the outer peripheral portion of 2 nd semiconductor substrate 3. The cut-out 18 is formed before filling the insulating film 17. The cutout 18 cuts out a part of the non-bonded region 15 and cuts out the outer peripheral portion of the 2 nd semiconductor substrate 3 so as to reach a part of the 1 st semiconductor substrate 2. Therefore, a notch 18 having a step shape is provided in the outer peripheral portion of the bonded substrate 4, and the notch 18 has a step surface for flattening a part of the side surface of the 2 nd semiconductor substrate 3 and the side surface of the 1 st semiconductor substrate 2, and a horizontal cross section formed by cutting out a part of the 1 st semiconductor substrate 2 flatly. A part of the non-bonded region 15 is removed by the cut-out portion 18. The insulating film 17 is formed and filled in the remaining portions of the cut-out portions 18 and the non-bonded regions 15.

By forming the cut-out portion 18 by trimming the outer peripheral portion of the bonded substrate 4, the filling property of the insulating film 17 into the non-bonded region 15 can be improved. In embodiment 2, the outer peripheral portion of bonded substrate 4 is trimmed, but it is not necessary to trim so as to remove all of non-bonded region 15. Trimming of the outer peripheral portion of bonded substrate 4 may be performed to such an extent that filling property of insulating film 17 can be improved. Therefore, the element formation area in bonded substrate 4 is not extremely reduced as compared with the case where non-bonded region 15 is entirely removed, and the element formation region in bonded substrate 4 can be effectively used. In addition, in the semiconductor device 1B according to embodiment 2, similarly to the semiconductor device 1A shown in fig. 2 of embodiment 1, the bonded substrate 4 is thinned by performing back grinding or chemical treatment so that at least the 2 nd circuit region 14 remains.

The effect of improving the filling property of the insulating film 17 by trimming the outer peripheral portion of the bonded substrate 4 is effective not only when the insulating film 17 containing SiN or SiCN is used but also when another insulating material is used. That is, in order to suppress chipping or peeling at the time of back grinding, various insulating materials can be applied. In such a case, trimming of the outer peripheral portion of bonded substrate 4 for removing a part of non-bonded region 15 is also effective. The same applies to the following embodiments 3 and 5. As the insulating film in such a case, an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), nitrogen-containing silicon carbide (SiCN), or aluminum oxide (AlO) can be used. Silicon oxide containing impurities such as boron (B), phosphorus (P), fluorine (F), and carbon (C), so-called doped glass, may be used for the insulating film. When a doped glass is used, reflow soldering at a low temperature (for example, 450 ℃ or lower) after film formation is also effective in improving the filling property.

The semiconductor device 1B according to embodiment 2 is manufactured, for example, as follows. The manufacturing process of the semiconductor device 1B will be described with reference to fig. 6A to 6D. As shown in fig. 6A, the 1 st semiconductor substrate 2 in which the surfaces of the 1 st metal pad 5 and the 1 st insulating layer 7 are exposed and the 2 nd semiconductor substrate 3 in which the surfaces of the 2 nd metal pad 8 and the 1 st insulating layer 10 are exposed are bonded to each other. The steps up to bonding are performed in the same manner as in embodiment 1. A non-bonded region 15 where the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are not bonded is formed in the outer peripheral portion of the bonded substrate 4.

Next, as shown in fig. 6B, the outer peripheral portion of bonded substrate 4 is trimmed so that at least a portion of 1 st semiconductor substrate 2 remains from 2 nd semiconductor substrate 3 side, thereby forming notch 18. The dressing step is performed by, for example, mechanical grinding using a rotary blade or the like. The cutout 18 is formed so as to remove only a part of the non-bonded region 15. Therefore, the element formation area in the bonded substrate 4 is not extremely reduced. Then, as shown in fig. 6C, the non-bonded region 15 is filled with an insulating material, and the side surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 or the horizontal cross section of the 1 st semiconductor substrate 2 in the cutout 18 are covered with the insulating material to form an insulating film 17. The steps of filling and forming the insulating material are performed in the same manner as the step of forming the insulating film 17 in embodiment 1. Then, as shown in fig. 6D, the back surface of the 2 nd semiconductor substrate 3 may be subjected to back grinding or chemical treatment, for example, to reduce the thickness of the 2 nd semiconductor substrate 3 to a desired thickness. The trimming may be performed so that at least a part of the 2 nd semiconductor substrate 3 remains from the 1 st semiconductor substrate 2 side.

As described above, by forming the cutout 18 in the outer peripheral portion of the bonded substrate 4 and then filling the insulating film 17 in the non-bonded region 15, the filling property of the insulating film 17 into the non-bonded region 15 can be improved. Therefore, it is possible to more effectively suppress the deterioration of the electrical characteristics due to the diffusion and contamination of the metal material such as copper from the exposed surface of the 1 st and 2 nd metal pads 5 and 8 due to the non-bonded region 15, and to more effectively suppress chipping and peeling at the time of back grinding. Since the trimming of the outer peripheral portion of bonded substrate 4 is performed to such an extent that the filling property of insulating film 17 can be improved, the element formation area in bonded substrate 4 is not extremely reduced. Therefore, the element forming region in the bonded substrate 4 can be effectively used. Further, according to the semiconductor device 1B and the method of manufacturing the same of embodiment 2, as in embodiment 1, the manufacturing yield of the semiconductor device 1B can be improved, and the electrical characteristics, quality, reliability, and the like of the semiconductor device 1B can be improved. Further, since the area of the bonded substrate 4 can be effectively used, the manufacturing cost of the semiconductor chip manufactured by the semiconductor device 1B can be reduced.

(embodiment 3)

Next, a semiconductor device 1C according to embodiment 3 will be described with reference to fig. 7. A semiconductor device 1C shown in fig. 7 has a notch 18 formed by trimming a part of the insulating film 17 filled in the non-bonded region 15 and the outer peripheral portion of the bonded substrate 4, as compared with the semiconductor device 1A of embodiment 1. The shape of the cutout portion 18 is substantially the same as that of embodiment 2. That is, the cutout portion 18 is a portion of the insulating film 17 cut out so as to reach a portion of the 1 st semiconductor substrate 2, and an outer peripheral portion of the 2 nd semiconductor substrate 3 is cut out. A notch 18 having a step shape is provided in the outer peripheral portion of the bonded substrate 4, and the notch 18 has a step surface for flattening a part of the side surface of the 2 nd semiconductor substrate 3, the insulating film 17 filled in the non-bonded region 15, and the side surface of the 1 st semiconductor substrate 2, and a horizontal cross section formed by flatly cutting out a part of the 1 st semiconductor substrate 2. The trimming may be performed so that at least a part of the 2 nd semiconductor substrate remains from the 1 st semiconductor substrate 2 side. The insulating film 17 is not limited to being formed of one material, and may be a mixed film or a laminated film of a plurality of materials.

In semiconductor device 1C according to embodiment 3, trimming of the outer peripheral portion of bonded substrate 4 and formation of cutout 18 by trimming are performed after insulating film 17 is filled in unbonded area 15. By performing trimming after filling the insulating film 17 in the non-bonded region 15, even when an unfilled portion of the insulating film 17 is formed in the non-bonded region 15, that is, an unfilled portion of the insulating film 17 is formed on the outer peripheral side of the non-bonded region 15, for example, when SiN or SiCN is formed as the insulating film 17 at a particularly low temperature, such an unfilled portion can be removed by trimming. Therefore, it is possible to more effectively suppress the deterioration of the electrical characteristics due to the diffusion and contamination of the metal material such as copper from the exposed surface of the 1 st and 2 nd metal pads 5 and 8 due to the non-bonded region 15, and to more effectively suppress chipping and peeling at the time of back grinding. In addition, in the semiconductor device 1C according to embodiment 3, similarly to the semiconductor device 1A shown in fig. 2 of embodiment 1, the bonded substrate 4 is thinned by performing back grinding or chemical treatment so that at least the 2 nd circuit region 14 remains.

(embodiment 4)

Next, a semiconductor device 1D according to embodiment 4 will be described with reference to fig. 8. A semiconductor device 1D shown in fig. 8 has the same configuration as the semiconductor device 1A of embodiment 1, except for the structure of the insulating film. The insulating film 17 in the semiconductor device 1D according to embodiment 4 includes: a 1 st insulating film 19 formed along and covering the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15 located in the outer peripheral portion of the bonded substrate 4; and a 2 nd insulating film 20 filled in the non-bonded region 15 which is the non-filled portion of the 1 st insulating film 19. The 1 st insulating film 19 contains at least one selected from SiN and SiCN.

That is, when SiN or SiCN is formed at a particularly low temperature, the filling property into the non-bonded region 15 may be poor. In the semiconductor device 1D according to embodiment 4, the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15 are covered with the 1 st insulating film 19 containing SiN or SiCN. The 1 st insulating film 19 is formed in a range capable of covering the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15. The non-bonded region 15 remaining after the formation of the 1 st insulating film 19 is filled with a 2 nd insulating film 20 containing silicon oxide (SiO) having excellent filling properties, silicon oxide (doped glass) containing an impurity such as B, P, F, C, silicon oxynitride (SiON), or the like. Thus, by using the 1 st insulating film 19 containing SiN or SiCN, the filling property of the insulating film 17 into the non-bonded region 15 can be improved. In particular, using doped glass as the 2 nd insulating film 20, performing low-temperature reflow during or after the film formation is very effective in improving the filling property of the insulating film 17 into the non-bonded region 15. The 1 st and 2 nd insulating films 19 and 20 are not limited to one type, and may be formed by mixing or laminating a plurality of materials.

As shown in fig. 9, in the semiconductor device 1D according to embodiment 4, after trimming the outer peripheral portion of the bonded substrate 4 to form the cutout 18, the non-bonded region 15 may be filled with the 2-layer insulating film 17. In this case, in the manufacturing process shown in embodiment 2, the same manufacturing process can be applied except that the 1 st insulating film 19 and the 2 nd insulating film 20 are sequentially formed as the insulating film 17. The 2 nd insulating film 20 is not limited to one type, and may be formed by mixing or laminating a plurality of materials. In the semiconductor device 1D according to embodiment 4, as in embodiment 3, after the 1 st and 2 nd insulating films 19 and 20 are formed, a part of the insulating film 17 filled in the non-bonded region 15 and the outer peripheral portion of the bonded substrate 4 may be trimmed.

(embodiment 5)

Next, the manufacturing process of the semiconductor device according to embodiment 5 will be described with reference to fig. 10A to 10E, fig. 11, and fig. 12A to 12B. The manufacturing process of embodiment 5 differs from the manufacturing processes of embodiments 1 to 4 in that after trimming the outer peripheral portion of at least one of the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3, the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are bonded. The steps of manufacturing the semiconductor device 1E according to embodiment 5 will be specifically described with reference to fig. 10A to 10E.

As shown in fig. 10A, a 2 nd semiconductor substrate 3 is prepared. The 2 nd semiconductor substrate 3 has the same configuration as that of embodiment 1. Although not shown in fig. 10A, the 1 st semiconductor substrate 2 similar to that of embodiment 1 is prepared. Then, as shown in fig. 10B, the outer peripheral portion of the 2 nd semiconductor substrate 3 is trimmed to form a notch portion 18. The outer peripheral portion of the 2 nd semiconductor substrate 3 is trimmed, for example, by removing a portion of the 2 nd insulating layer 10 and a portion of the 2 nd circuit region 14 of the 2 nd semiconductor substrate 3 on the outer peripheral side and removing a portion of the substrate portion 13 of the 2 nd semiconductor substrate 3 in the thickness direction and a portion in the surface direction. The dressing step is performed by, for example, mechanically grinding with a rotary blade or the like.

Next, as shown in fig. 10C, the 2 nd semiconductor substrate 3 having the cutout portion (trimmed portion) 18 in the outer peripheral portion is bonded to the 1 st semiconductor substrate 2. The bonding step of the semiconductor substrates 2 and 3 is performed in the same manner as in embodiment 1. That is, the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 having the notch 18 in the outer peripheral portion are bonded to each other by mechanical pressure. Thereby, the 1 st insulating layer 7 and the 2 nd insulating layer 10 are joined and integrated. Here, the non-bonded region 15 of the 1 st semiconductor substrate 2 does not have a cut-out portion in a portion opposed to the cut-out portion 18 provided in the outer peripheral portion of the 2 nd semiconductor substrate 3.

Then, the 1 st semiconductor substrate 2 and the 2 nd semiconductor substrate 3 are annealed at a temperature of, for example, 400 ℃. Thereby, the 1 st metal pad 5 and the 2 nd metal pad 8 are joined, and these 1 st and 2 nd metal pads 5 and 8 are electrically connected and integrated, so that the bonded substrate 4 is obtained. Since the 2 nd semiconductor substrate 3 has the cutout portion 18 provided in the outer peripheral portion, the gap between the 1 st semiconductor substrate 2 and the non-bonded region 15 of the 2 nd semiconductor substrate 3 in the outer peripheral portion of the bonded substrate 4 is enlarged.

That is, since the opening portion of the non-bonded region 15 is enlarged and the volume of the non-bonded region 15 is enlarged, the filling property of the insulating film 17 into the non-bonded region 15 is improved. As shown in fig. 10D, the non-bonded region 15 is filled with an insulating film 17. The insulating film 17 is formed of the same insulating material as in embodiments 1 to 4. The insulating film 17 is not limited to being formed of one material, and may be a mixed film or a laminated film of a plurality of materials. The insulating film 17 containing SiN or SiCN can be formed at a low temperature, but may have poor filling properties into the non-bonded region 15. In this case, the opening portion of the non-bonded region 15 in the outer peripheral portion of the bonded substrate 4 is enlarged, and the volume of the non-bonded region 15 is enlarged, thereby improving the filling property of the insulating film 17 into the non-bonded region 15.

The steps of filling and forming the insulating material are performed in the same manner as the step of forming the insulating film 17 in embodiments 1 to 4. The effect of improving the filling property of the insulating film 17 in the outer peripheral portion of the bonded substrate 4 is not limited to that when the insulating film 17 containing SiN or SiCN is used, and is also effective when another insulating material is used. That is, in order to suppress chipping or peeling at the time of back grinding, various insulating materials can be applied. In this case, trimming on the outer peripheral portion side of the 2 nd semiconductor substrate 3 before bonding is also effective. In such a case, an inorganic insulating material such as SiO, SiN, SiON, SiCN, or AlO can be used as the insulating film. Silicon oxide containing an impurity such as B, P, F, C, so-called doped glass, may be used for the insulating film. As shown in fig. 10E, the back surface of the 2 nd semiconductor substrate 3 is subjected to back grinding or chemical treatment, for example, to reduce the thickness of the 2 nd semiconductor substrate 3 to a desired thickness.

As described above, by bonding the 2 nd semiconductor substrate 3 with the outer peripheral portion trimmed in advance to the 1 st semiconductor substrate 2 to produce the bonded substrate 4, the filling property of the insulating film 17 into the non-bonded region 15 can be improved. Therefore, it is possible to more effectively suppress the deterioration of the electrical characteristics due to the diffusion and contamination of the metal material such as copper from the exposed surface of the 1 st and 2 nd metal pads 5 and 8 due to the non-bonded region 15, and to more effectively suppress chipping and peeling at the time of back grinding. Further, since the trimming of the outer peripheral portion of the 2 nd semiconductor substrate 3 is performed to such an extent that the filling property of the insulating film 17 can be improved, the element formation area in the bonded substrate 4 is not extremely reduced. Therefore, the element forming region in the bonded substrate 4 can be effectively used. Further, according to the manufacturing method of embodiment 5, as in embodiment 1, the manufacturing yield of the semiconductor device 1E can be improved, and the electrical characteristics, quality, reliability, and the like of the semiconductor device 1E can be improved. Further, since the area of the bonded substrate 4 can be effectively used, the manufacturing cost of the semiconductor chip manufactured by the semiconductor device 1E can be reduced.

In the manufacturing process of the semiconductor device 1E according to embodiment 5, trimming before the bonding process is not limited to trimming the 2 nd semiconductor substrate 3. As shown in fig. 11, both the outer peripheral portion of the 1 st semiconductor substrate 2 and the outer peripheral portion of the 2 nd semiconductor substrate 3 may be trimmed, and the cutout portions 18 may be formed. In this case, the 1 st semiconductor substrate 2 having the cutout portion 18 and the 2 nd semiconductor substrate having the cutout portion 18 are bonded. The bonding step is performed in the same manner as the above-described step. Further, the notch 18 may be formed by trimming only the outer peripheral portion of the 1 st semiconductor substrate 2.

In the manufacturing process of the semiconductor device 1E according to embodiment 5, the insulating film 17 filled in the non-bonded region 15 in the outer peripheral portion of the bonded substrate 4 is not limited to an insulating material containing SiN or SiCN. As shown in fig. 12A and 12B, the insulating film 17 may include, as in the semiconductor device 1D according to embodiment 4: a 1 st insulating film 19 formed along the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15; and a 2 nd insulating film 20 filled in an unfilled portion of the 1 st insulating film 19. Specifically, as shown in fig. 12A, the 1 st insulating film 19 is formed so as to cover the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15 of the bonded substrate 4. Then, the non-bonded region 15 which is the non-filled portion of the 1 st insulating film 19 is filled with the 2 nd insulating film 20. The 1 st and 2 nd insulating films 19 and 20 are formed in the same manner as in embodiment 4. Then, as shown in fig. 12B, the back surface of the 2 nd semiconductor substrate 3 is subjected to back grinding or chemical treatment, for example, to reduce the thickness of the 2 nd semiconductor substrate 3 to a desired thickness.

The 1 st insulating film 19 contains at least one selected from SiN and SiCN. By covering the surfaces of the 1 st and 2 nd semiconductor substrates 2 and 3 exposed in the non-bonded region 15 of the bonded substrate 4 with the 1 st insulating film 19 functioning as a diffusion barrier for a metal material such as copper (Cu), it is possible to suppress a decrease in electrical characteristics or the like caused by diffusion and contamination of the metal material such as copper from the exposed surfaces of the 1 st and 2 nd metal pads 5 and 8. However, SiN or SiCN may have poor filling properties into the non-bonded region 15 when formed at a particularly low temperature. In this case, for example, by filling the 2 nd insulating film 20 in the unfilled portion of the 1 st insulating film 19, the filling property of the insulating film 17 into the unbonded area 15 can be improved. The 2 nd insulating film 20 is preferably made of SiO (doped glass) having excellent filling properties, SiO containing an impurity such as B, P, F, C, SiON, or the like. In particular, using doped glass as the 2 nd insulating film 20 and performing low-temperature reflow during or after the film formation is very effective in improving the filling property of the insulating film 17 into the non-bonded region 15. The 1 st and 2 nd insulating films 19 and 20 are not limited to one type, and may be formed by mixing or laminating a plurality of materials.

(embodiment 6)

Next, an example of a semiconductor chip manufactured using the semiconductor devices 1(1A, 1B, 1C, 1D, 1E) of the above-described embodiments will be described with reference to fig. 13. The semiconductor chip 21 shown in fig. 13 includes: a control circuit chip 22 including a part of the 1 st semiconductor substrate 2 having the 1 st circuit region; and an array chip 23 including a portion of the 2 nd semiconductor substrate 3 having the 2 nd circuit region. Such a semiconductor chip 21 is produced by cutting and singulating the semiconductor device 1 according to each embodiment along each chip region. Therefore, the control circuit chip 22 is attached to the array chip 23.

The array chip 23 includes a memory cell array 24 including a plurality of memory cells, an insulating film 25 on the memory cell array 24, and an interlayer insulating film 26 under the memory cell array 24. The circuit chip 22 is disposed under the array chip 23. Symbol S denotes a bonding surface of the array chip 23 and the control circuit chip 22. The control circuit chip 22 includes an interlayer insulating film 27 and a substrate 28 under the interlayer insulating film 27. The substrate 28 is a semiconductor substrate such as a silicon substrate. The insulating films 25, 26, and 27 are, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like, and may have a structure in which one or more materials are mixed or laminated.

Fig. 13 shows the X direction and the Y direction parallel to and perpendicular to the surface of the substrate 28, and the Z direction perpendicular to the surface of the substrate 28. Here, the + Z direction is taken as the upward direction, and the-Z direction is taken as the downward direction. For example, the memory cell array 24 functioning as the 2 nd circuit region in the array chip 23 is located above the substrate 28, and the substrate 28 is located below the memory cell array 24. the-Z direction may or may not coincide with the direction of gravity.

The array chip 23 includes a plurality of word lines WL, source lines BG, bit lines BL, and selection gates, not shown, as electrode layers in the memory cell array 24. Fig. 13 includes a staircase structure portion of the memory cell array 24. One end of a columnar portion CL penetrating the word line WL is electrically connected to the source line BG, and the other end is electrically connected to the bit line BL, and a memory cell is formed at an intersection of the columnar portion CL and the word line WL.

The control circuit chip 22 includes a plurality of transistors 29. Each transistor 29 includes: a gate electrode 30 provided on the substrate 28 with a gate insulating film interposed therebetween; and a source diffusion layer and a drain diffusion layer, not shown, provided in the substrate 28. The control circuit chip 22 further includes: a plurality of plugs 31 provided on the source diffusion layers or the drain diffusion layers of the transistors 29; a wiring layer 32 provided on the plugs 31 and including a plurality of wirings; and a wiring layer 33 provided on the wiring layer 32 and including a plurality of wirings. The control circuit chip 22 further includes: a plurality of via plugs 34 provided on the wiring layer 33; and a plurality of metal pads 5 provided on the via plugs 34 in the insulating film 27. The control circuit chip 22 having the 1 st circuit region described above functions as a control circuit (logic circuit) for controlling the array chip 23.

The array chip 23 includes: a plurality of metal pads 8 provided on the metal pad 5 within the insulating film 26; a plurality of via plugs 35 provided on the metal pad 8; and a wiring layer 36 provided on the via plug 35 and including a plurality of wirings. Each word line WL or each bit line BL is electrically connected to a corresponding wiring in the wiring layer 36. The array chip 23 further includes: a via plug 37 provided in the insulating film 26 or the insulating film 25 and provided on the wiring layer 36; and a metal pad 38 provided on the insulating film 25 or on the via plug 37.

The metal pad 38 functions as an external connection pad of the semiconductor chip 21 shown in fig. 13, and can be connected to a mounting substrate or other devices via a bonding wire, a solder ball, a metal bump, or the like. The array chip 23 further includes a passivation film 39 formed on the insulating film 25 and the metal pad 38. The passivation film 39 has an opening P for exposing the upper surface of the metal pad 38, and the opening P is used for connecting a bonding wire to the metal pad 38, for example.

Further, the respective configurations of the above embodiments can be combined and applied, and some of them can be replaced. Several embodiments of the present invention have been described herein, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.