阅读说明：本技术 功率半导体器件和方法 (Power semiconductor device and method ) 是由 E·菲尔古特 P·S·科赫 S·平德尔 H-J·舒尔策 于 2020-08-27 设计创作，主要内容包括：功率半导体器件(1)包括：具有前侧表面(10-1)的半导体本体(10)、以及布置在前侧表面(10-1)上方的第一钝化层(15-1),其中,第一钝化层(15-1)是多晶金刚石层。(A power semiconductor device (1) comprises: a semiconductor body (10) having a front side surface (10-1), and a first passivation layer (15-1) arranged above the front side surface (10-1), wherein the first passivation layer (15-1) is a polycrystalline diamond layer.)

1. A power semiconductor device (1) comprising:

-a semiconductor body (10) having a front side surface (10-1); and

-a first passivation layer (15-1) arranged over the front side surface (10-1), wherein the first passivation layer (15-1) is a layer of polycrystalline diamond.

2. A power semiconductor device (1) according to claim 1, wherein the polycrystalline diamond layer (15-1) comprises crystals having a diameter of at least 10 nm.

3. Power semiconductor device (1) according to one of the preceding claims, wherein the thickness (t 1) of the first passivation layer (15-1) is in the range from 30 nm to 2000 nm.

4. Power semiconductor device (1) according to one of the preceding claims, wherein the polycrystalline diamond layer (15-1) has a thermal conductivity of at least 1200W/(K m).

5. Power semiconductor device (1) according to one of the preceding claims, wherein the polycrystalline diamond layer (15-1) has a specific heat capacity of at least 400J/(kg K).

6. Power semiconductor device (1) according to one of the preceding claims, wherein the polycrystalline diamond layer (15-1) has at least 10¹³Ohm cm resistivity.

7. Power semiconductor device (1) according to one of the preceding claims, wherein the polycrystalline diamond layer (15-1) has a dielectric strength of at least 1500 kV/mm.

8. Power semiconductor device (1) according to one of the preceding claims, wherein the first passivation layer (15-1) is arranged at least partially over the edge termination structure (13) of the power semiconductor device (1).

9. The power semiconductor device (1) according to claim 8, wherein the edge termination structure (13) comprises a doped crystalline semiconductor region (131, 132) in contact with at least a portion of the first passivation layer (15-1).

10. A power semiconductor device (1) according to claim 9, wherein the doped crystalline semiconductor region (131, 132) comprises at least one of a junction termination extension (131) and a guard ring (132).

11. Power semiconductor device (1) according to one of the preceding claims, wherein the first passivation layer (15-1) is at least partially arranged in the active region (16) of the power semiconductor device (1).

12. A power semiconductor device (1) according to claim 11, wherein the first passivation layer (15-1) is in contact with a front side metallization (11) of the power semiconductor device (1).

13. Power semiconductor device (1) according to one of the preceding claims, wherein the first passivation layer (15-1) extends only in the active region (16) of the power semiconductor device (1).

14. Power semiconductor device (1) according to one of the preceding claims, wherein a second passivation layer (15-2) is arranged between the first passivation layer (151) and the front side surface (10-1).

15. Power semiconductor device (1) according to claim 14, wherein the second passivation layer (15-2) comprises at least one of the following materials: oxide, amorphous carbon, amorphous silicon carbide, nitride.

16. Power semiconductor device (1) according to one of the preceding claims, wherein a portion of the first passivation layer (15-1) covers at least a portion of a lateral chip edge (10-3) of the semiconductor body (10).

17. Power semiconductor device (1) according to one of the preceding claims, wherein the power semiconductor device (1) is or comprises at least one of: diode, IGBT, reverse conducting IGBT, MOSFET, HEMT, thyristor.

18. A method of producing a power semiconductor device (1), comprising:

-providing a semiconductor body (10) having a front side surface (10-1); and

-forming a first passivation layer (15-1) over the front side surface (10-1), wherein the first passivation layer (15-1) is a polycrystalline diamond layer.

19. The method according to claim 18, wherein forming the first passivation layer (15-1) comprises deposition of a layer of polycrystalline diamond at a deposition temperature of at least 350 ℃.

Technical Field

The present description relates to embodiments of power semiconductor devices and to embodiments of methods of producing power semiconductor devices. In particular, the present description relates to aspects of power semiconductor devices having a passivation layer disposed over at least a portion of a frontside surface.

Background

Many functions of modern equipment in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to power supplies and switches in power converters, to name a few.

Power semiconductor devices typically include a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device.

In addition, in order to conduct the load current, the power semiconductor device may include: one or more power cells may be arranged in a so-called active area of the power semiconductor device. For example, in the case of a controllable power semiconductor device (e.g. a transistor), the load current path may be controlled by means of an insulated electrode (also commonly referred to as gate electrode). For example, the control electrode may set the power semiconductor device in one of the conducting state and the blocking state upon receiving a corresponding control signal from, for example, a driver unit. In some cases, the gate electrode may be included within a trench of the power semiconductor switch, wherein the trench may exhibit, for example, a stripe-shaped configuration or a needle-shaped configuration.

The power semiconductor device may be laterally bounded by an edge (such as a lateral chip edge), and between the edge and an active region comprising one or more power cells, an edge termination region may be arranged, which may comprise an edge termination structure. Such edge termination structures may be used for the purpose of influencing the course of the electric field within the semiconductor body, for example, in order to ensure a reliable blocking capability of the power semiconductor device. The edge termination structure may include one or more components disposed within the semiconductor body, and also one or more components disposed over a surface of the semiconductor body.

Typically, the power semiconductor device comprises one or more passivation layers arranged over at least a portion of the front side surface of the semiconductor body, for example over at least a portion of the edge termination region. For example, such a passivation layer may be configured to prevent contaminant ions from entering the edge termination structure.

There is a general trend to increase power density in power semiconductor devices. In this context, but also more generally, it is desirable to provide a novel passivation concept that is improved, for example, in its impact on device robustness and reliability and/or in the area consumption of the edge termination region.

Disclosure of Invention

Aspects described herein relate to a specific novel design of a front side passivation layer of a power semiconductor device, which may for example result in improved thermal robustness and higher mechanical stability compared to conventional passivation layers.

According to an embodiment, a power semiconductor device includes: a semiconductor body having a front side surface; and a first passivation layer disposed over the front side surface, wherein the first passivation layer is a polycrystalline diamond layer. For example, the first passivation layer may be structured in a horizontal plane, i.e. if viewed from above.

According to another embodiment, a method of producing a power semiconductor device is presented. The method comprises the following steps: providing a semiconductor body having a front side surface; and forming a first passivation layer over the front side surface, wherein the first passivation layer is a polycrystalline diamond layer.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

Drawings

The parts of the drawings are not necessarily to scale. Emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. In the drawings:

fig. 1A-C each schematically and exemplarily illustrate a portion of a vertical cross-section of a power semiconductor device in accordance with one or more embodiments;

2A-C each schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device in accordance with one or more embodiments;

3A-C each schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device in accordance with one or more embodiments;

4A-D each schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device in accordance with one or more embodiments;

fig. 5 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; and

fig. 6 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

In this regard, directional terminology, such as "top," "bottom," "below," "front," "back," "leading," "lagging," "above," etc., may be used with reference to the orientation of the figure(s) being described. Because various portions of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to the various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not meant as a limitation of the invention. For instance, features illustrated or described as part of one embodiment, can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. Examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, identical elements or manufacturing steps are indicated by identical reference numerals in different figures, if not stated otherwise.

The term "horizontal" as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, both the first and second lateral (or horizontal) directions X, Y mentioned below and/or shown in the drawings may be horizontal directions, wherein the first and second lateral directions X, Y may be perpendicular to each other.

The term "vertical" as used in this specification intends to describe an orientation arranged substantially perpendicular to a horizontal surface (i.e. parallel to the normal direction of the surface of the semiconductor wafer/chip/die). For example, the vertical direction Z mentioned below and/or shown in the drawings may be a direction perpendicular to both the first lateral direction X and the second lateral direction Y.

In this specification, n-doping is generally referred to as "first conductivity type", and p-doping is referred to as "second conductivity type". Alternatively, the opposite doping relationship may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low ohmic electrical connection or a low ohmic current path between two regions, sections, zones, portions or subsections of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a portion or subsection of a semiconductor device. In addition, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements that are contacting each other may not include additional intermediate elements, and so forth.

Furthermore, in the context of this specification, if not otherwise stated, the term "electrically isolated" is used in its generally well understood context and is therefore intended to describe two or more components positioned apart from one another and without an ohmic connection connecting the components. However, components that are electrically isolated from each other may still be coupled to each other, e.g. mechanically and/or capacitively and/or inductively. For example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, e.g., by means of an insulator (e.g., a dielectric).

The specific embodiments described in this specification relate to, but are not limited to, the following power semiconductor devices: the power semiconductor device exhibits a single cell, strip cell or honeycomb (also referred to as "pin" or "pillar") cell configuration, for example, a power semiconductor device that may be used within a power converter or power supply. Thus, in embodiments, such a device may be configured to carry a load current to be fed to a load and/or provided by a power supply, respectively. For example, the power semiconductor device may include: one or more active power semiconductor cells, such as monolithically integrated diode cells, derivatives of monolithically integrated diode cells (e.g. monolithically integrated cells of two diodes connected in anti-series), monolithically integrated transistor cells, e.g. monolithically integrated IGBT or MOSFET cells and/or derivatives thereof. Such a diode/transistor cell may be integrated in a power semiconductor module. A plurality of such cells may constitute a cell field of an active area in which the power semiconductor device is arranged.

The term "power semiconductor device" as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking capability and/or high current carrying capability. In other words, such power semiconductor devices are intended for high currents (typically in the ampere range, e.g. up to several tens or hundreds of amperes) and/or high voltages (typically above 15V, more typically above 100V and above, e.g. up to at least 400V or even higher, e.g. in the range from 1.2 kV to 2 kV, or up to at least 3 kV, or even up to 6 kV or higher).

For example, the power semiconductor devices described below may be a single semiconductor chip exhibiting a single cell configuration, a bar cell configuration, or a cellular cell configuration, and may be configured to be used as power components in low, medium, and/or high voltage applications.

For example, the term "power semiconductor device" as used in this specification does not relate to a logic semiconductor device that is used for, for example, storing data, computing data, and/or other types of semiconductor-based data processing.

Fig. 1A schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device 1 according to one or more embodiments. The power semiconductor device 1 comprises a semiconductor body 10 having a front side surface 10-1. For example, the semiconductor body 10 may comprise or consist of: a silicon-based substrate, a silicon carbide-based substrate, a gallium nitride-based substrate, or another wide band gap semiconductor substrate, for example.

In addition, an active area 16, which may also be referred to as an active cell area 16, is arranged below the front side 10-1. The active cell area 16 may comprise one or more power cells 160, which power cells 160 may be configured for conducting and/or controlling a load current, for example, between a first load terminal structure arranged at the front side of the semiconductor body 10 and a second load terminal structure arranged at the back side of the semiconductor body 10. Thus, according to some embodiments, the power semiconductor device 1 may be configured as a vertical power semiconductor device 1.

For example, the power semiconductor device 1 is or comprises at least one of: power diodes, IGBTs, reverse-conducting IGBTs (RC-IGBTs), MOSFETs, High Electron Mobility Transistors (HEMTs), such as gallium-based HEMTs, and thyristors (thyristors).

In case the power semiconductor device 1 is or comprises a power diode, the active area 16 may comprise for example one high power cell 160, as exemplarily illustrated in fig. 1A. For example, the power cell 160 may include a p-doped semiconductor region configured as an anode region and in contact with a frontside metallization forming part of a first load terminal structure (not shown in fig. 1A). For example, the anode region may form a pn junction with an n-doped drift region of the semiconductor body 10.

Alternatively, in the case of a transistor configuration (for example in the form of an IGBT or MOSFET), the active region 16 may comprise a plurality of transistor cells, which may for example in each case comprise a source region, a body region and a gate electrode (such as a trench gate electrode) configured for selectively switching the power semiconductor device 1 into one of a forward-conducting state and a forward-blocking state.

The design of the active cell region 16 of such a device is known per se to the person skilled in the art and will therefore not be explained in further detail here. An exemplary and schematic illustration of the active area 16 is shown in fig. 4A-D, and will be explained further below, the active area 16 comprising a plurality of transistor cells 161, e.g. an anode region 162 of a diode or an IGBT.

In addition to the active region 16, the power semiconductor device 1 further comprises an edge termination region 17, which edge termination region 17 extends between the active region 16 and the lateral chip edge 10-3. For example, the edge termination region 17 may laterally surround the active region 16, as schematically indicated in the cross-sectional view of fig. 1A.

As used herein, the terms "edge termination region" and "active region" are both associated with the respective technical meaning that a person skilled in the art is typically associated with in the context of power semiconductor devices. That is, the active region 16 is mainly configured for load current conduction and, in the case of a transistor configuration, for switching purposes, while the edge termination region 17 mainly fulfills a function with regard to reliable blocking capability, proper guidance of the electric field, and sometimes also a charge carrier draining function, and/or further functions with regard to protection and proper termination of the active region 16.

The edge termination region 17 may comprise an edge termination structure 13, which edge termination structure 13 may be arranged at the front side of the semiconductor body 10. Such edge termination structures 13 may also be referred to as junction termination structures or simply junction terminations. For example, the edge termination structure 13 may include one or more components disposed within the semiconductor body 10, and/or one or more components disposed over the frontside surface 10-1 of the semiconductor body 10.

Common examples of edge termination structures 13 are field rings (also referred to as guard rings), field plates, combinations of field rings and field plates, and Junction Termination Extension (JTE) edge termination structures such as lateral doping Variation (VLD) edge termination structures. The skilled person is very familiar with these kinds of edge termination structures per se. Therefore, it will not be explained in detail at this point. Fig. 4A-D show some exemplary and schematic representations of the edge termination structure 13 mentioned above. These will be explained in further detail below.

The power semiconductor device 1 further includes: a first passivation layer 15-1 disposed over the front side surface 10-1. For example, in the embodiment according to fig. 1A, the first passivation layer 15-1 may extend at least in a portion of the edge termination region 17. For example, the first passivation layer 15-1 may be arranged at least partially over the edge termination structure 13 of the power semiconductor device 1, as schematically shown in fig. 1A. Such a first passivation layer 15-1 extending over the edge termination structure 13 may also be referred to as a junction termination passivation layer. Optionally, the passivation layer 15-1 may extend into the active region 16.

The first passivation layer 15-1 is a polycrystalline diamond layer. Thus, the first passivation layer 15-1 has a polycrystalline structure, in contrast to an amorphous carbon passivation layer, which is also commonly referred to as a diamond-like carbon (DLC) passivation layer. As a result, for example, the first passivation layer 15-1 may have better electrical insulating properties (also at high temperatures) and increased thermal conductivity, for example, compared to a DLC passivation layer.

Regarding the polycrystalline structure of the first passivation layer 15-1, in an embodiment, the polycrystalline diamond layer 15-1 includes: crystals having a diameter of at least 10 nm, such as at least 20 nm, for example at least 50 nm. For example, the polycrystalline diamond layer 15-1 may comprise or consist of a so-called nanocrystalline diamond (NCD) material having crystals with a diameter of less than 100 nm. Additionally or alternatively, the polycrystalline diamond layer 15-1 may comprise or consist of a so-called microcrystalline diamond (MCD) material having crystals up to 5 μm in diameter.

In an embodiment, the polycrystalline diamond layer 15-1 has a thermal conductivity of at least 1200W/(K m) (such as at least 1500W/(K m), such as at least 1800W/(K m), for example at least 2000W/(K m). For example, the first passivation layer 15-1 may thus exhibit good heat dissipation properties, which may for example help to minimize self-heating effects occurring in the edge termination region 17, e.g. during turn-off in case of a transistor configuration (such as an IGBT configuration) of the power semiconductor device 1.

Additionally, in embodiments, the polycrystalline diamond layer 15-1 may be used as a heat sink and/or in thermal contact, for example in conjunction with thermoelectric cooling, such as by means of a peltier device.

Still referring to the thermal properties of the first passivation layer 15-1, in an embodiment, it may be provided that the polycrystalline diamond layer 15-1 has a specific heat capacity of at least 400J/(kg K), such as 427J/(kg K).

With respect to the electrical properties of the first passivation layer 15-1, the polycrystalline diamond layer 15-1 has at least 10 according to an embodiment¹³Ohm cm resistivity. Accordingly, the first passivation layer 15-1 may have very good electrical insulation properties.

Additionally, in an embodiment, the polycrystalline diamond layer 15-1 has a dielectric strength of at least 1500 kV/mm (such as at least 1800 kV/mm, for example at least 2000 kV/mm). As a result, the first passivation layer 15-1 may, for example, contribute to a relatively high breakdown voltage of the power semiconductor device 1.

In addition, the polycrystalline diamond layer 15-1 may prevent or at least reduce harmful atoms (such as sodium, potassium, OH) due to the low diffusion constant of such materials in diamond^-Li, etc.). If such atoms are close to the semiconductor surface 10-1, or for the case that they diffuse into the semiconductor body 10In this case, the electrical characteristics of the power semiconductor device 1 may deteriorate.

In accordance with one or more embodiments, the polycrystalline diamond layer 15-1 has a hardness of at least 5 (such as at least 7, such as, for example, 10) on the mohs scale with respect to the mechanical properties of the first passivation layer 15-1. As a result, the first passivation layer 15-1 may exhibit a very high mechanical stability, which may for example prevent scratching of sensitive underlying structures during front-end and/or back-end manufacturing.

With regard to the spatial dimensions of the first passivation layer 15-1, in an embodiment the thickness t1 (e.g. as measured along the vertical direction Z) of the first passivation layer 15-1 is in the range from 30 nm to 2000 nm, such as in the range from 50 nm to 800 nm, for example in the range from 100 nm to 400 nm. In embodiments, the thickness t1 may be in a range up to 20 μm or even up to 50 μm.

In an embodiment, the polycrystalline diamond layer 15-1 may cover substantially the entire edge termination region 17 or at least the entire edge termination structure 13. Alternatively, in the edge termination region 17, the polycrystalline diamond layer 15-1 may exhibit a patterned structure in the horizontal plane XY, i.e. if viewed from above.

Fig. 1B schematically and exemplarily illustrates another embodiment, which differs from the embodiment described above with reference to fig. 1A in that: although the first passivation layer 15-1 is still disposed over the front side surface 10-1, the second passivation layer 15-2 is additionally disposed between the first passivation layer 15-1 and the front side surface 10-1.

In an embodiment, the second passivation layer 15-2 comprises at least one of the following materials: oxides, amorphous carbon, amorphous silicon carbide, and nitrides.

In other words and more generally, the polycrystalline diamond-based passivation layer 15-1 may be used in combination with one or more other passivation layers, such as an oxide-based layer, an amorphous carbon layer, an amorphous silicon carbide layer, or a nitride-based layer. For example, as schematically illustrated in fig. 1B, the polycrystalline diamond layer 15-1 may form an upper layer of such a passivation stack.

In another variant embodiment, schematically and exemplarily illustrated in fig. 1C, a third passivation layer 15-3 (such as, for example, at least one of a polyimide layer, an oxide layer or a nitride layer) is arranged over the polycrystalline diamond passivation layer 15-1. For example, the third passivation layer 15-3 may be arranged and configured for further enhancing the breakdown voltage of the power semiconductor device 1. It should be noted that in another embodiment, the power semiconductor device 1 may comprise a first passivation layer 15-1 and a third passivation layer 15-3 arranged above the first passivation layer 15-1, wherein, contrary to the example of fig. 1C, the second passivation layer 15-2 is not necessarily present below the first passivation layer 15-1.

Optionally, adhesion of the first passivation layer 15-1 to the underlying and/or overlying layers 15-2, 15-3 may be improved by: the surface free energy is controlled by means of one or more additional adhesion layers (not shown) and/or adhesion treatments (such as silanes, plasma activated surfaces, rough surfaces), or by using other methods, which are known in principle to the person skilled in the art.

The cross-sectional views in fig. 2A, 2B and 2C show variant embodiments which differ from the embodiments explained above with reference to fig. 1A, 1B and 1C, respectively, in that: the first passivation layer 15-1 is partially arranged in the active region 16 of the power semiconductor device 1. For example, the polycrystalline diamond layer 15-1 may thus be used as a local heat sink layer in the active cell region 16 and/or in the junction termination region 17. For example, an overlap of the polycrystalline diamond layer 15-1 between the active region 16 (e.g., the front side metallization 11 disposed on the active region 16; not illustrated in FIGS. 2A-C, see, e.g., FIG. 3A) and the edge termination region 17 may be provided in order to allow for efficient dissipation of heat generated in the edge termination region 17. For example, the first passivation layer 15-1 may be arranged in contact with the front side metallization of the power semiconductor device 1.

Additionally, in an embodiment, the front side metallization may be divided into a plurality of contact pads, wherein the polycrystalline diamond layer 15-1 may extend at least partially (laterally) between the contact pads (not shown). This may also apply to further contact pads, such as may be provided for temperature sensing functions, current sensing functions, etc. For example, the contact pads may have a rectangular layout, such as a quadratic layout. Additionally or alternatively, a honeycomb arrangement or an arrangement based on another shape may be employed.

In addition, the portion of the polycrystalline diamond layer 15-1 extending in the active region 16 may be configured to provide flashover (flash) protection for the power semiconductor device 1, for example, due to its relatively high dielectric strength.

For example, in an embodiment, the first passivation layer 15-1 and/or possibly further passivation layers 15-2, 15-3 may only partially overlap the active region 16, as schematically illustrated in each of fig. 2A-C. That is to say that the passivation layers 15-1, 15-2, 15-3 can be structured in the horizontal plane XY, i.e. if viewed from above.

In a further variant embodiment, schematically and exemplarily illustrated in fig. 3A-C, one or more of the passivation layers 15-1, 15-2, 15-3 may extend in the active area 16 (e.g. over the front side metallization 11, such as in contact with the front side metallization 11, as illustrated), wherein an opening for allowing one or more bonding wires 2 to pass through the passivation stack is provided. Such an opening may be arranged, for example, above a contact pad (such as a gate pad) of the power semiconductor device 1. In the embodiment according to each of fig. 3A-C, one or more passivation layers 15-1, 15-2, 15-3 may cover the entire active area 16 except for such openings provided for the bond wires 2 or for other electrical contacts (such as clips, etc.). It should be noted that the passivation layer(s) 15-1, 15-2, 15-3 do not necessarily need to be in direct lateral contact with the bond wire 2, as it is illustrated schematically and schematically in fig. 3A-C. In contrast, in some embodiments (not shown), the pad opening provided in the passivation layer(s) 15-1, 15-2, 15-3 may be larger than the diameter of the bond wire 2, such that after the passivation layer(s) 15-1, 15-2, 15-3 are created, the end of the bond wire 2 may be easily placed in the opening. However, it would also be possible in principle to first connect the bonding wires 2 and only then produce one or more passivation layers 15-1, 15-2, 15-3. In that case a direct lateral contact between the bonding wire 2 and the passivation layer(s) 15-1, 15-2, 15-3 as illustrated in fig. 3A-C may be created.

In the following, several exemplary configurations of the power semiconductor device 1 will be described with reference to fig. 4A-D, including an exemplary configuration of one or more power cells 160, 161, 162 in the active area 16, and an exemplary configuration of the edge termination structures 13, 131, 132 in the edge termination region 17. Each of fig. 4A-D shows a part of a vertical cross section of the power semiconductor device 1, wherein the depicted part is in each case located close to the lateral chip edge 10-3 and also comprises a part of the active region 16, the edge termination region 17 comprising an edge termination structure 13 arranged between the active region 16 and the lateral chip edge 10-3.

In the embodiment schematically illustrated in fig. 4A, the power semiconductor device 1 is configured as a diode. Thus, in the active region 16, the semiconductor body 10 comprises: a back side doped region 107-3 of the first conductivity type (e.g., n-type, in which case the back side doped region 107-3 forms a cathode region); and a front-side doped region 162 of a second conductivity type complementary to the first conductivity type (e.g., p-type, in which case the front-side doped region forms an anode region). The front-side doped region 162 extends along the front-side surface 10-1 of the semiconductor body 10 inside the active region 16 and is in contact with a front-side metallization 11 forming part of the first load terminal structure. Similarly, the back side doped region 107-3 extends along the back side surface 10-2 of the semiconductor body 10 inside the active region 16 and is in contact with the back side metallization 12 forming part of the second load terminal structure.

Between the front side doped region 162 and the back side doped region 107-3, a drift region 100 is provided. For example, the drift region 100 may have dopants of the first conductivity type at a relatively low dopant concentration (such as an intrinsic dopant concentration of the semiconductor substrate). For example, the drift region 100 may include n^-And doping the region. At the back side, the drift region 100 may include a field stop region 100-1 (sometimes also referred to as a buffer region) thatThe field stop region has a dopant of the first conductivity type with a higher dopant concentration than in the remainder of the drift region 100. Thus, the field stop region may be, for example, an n-doped region, while the remainder of the drift region may be n^-And (4) doping. In this case, the back side doped region 107-3 may be, for example, n⁺A doped cathode region.

Turning now to the edge termination region 17, in the exemplary embodiment of fig. 4A, the edge termination structure 13 is provided in the form of a so-called Junction Termination Extension (JTE). That is, JTE region 131 having a dopant of the second conductivity type (e.g., at a lower dopant concentration than frontside doped region 162) extends along frontside surface 10-1 in edge termination region 17. For example, JTE region 131 may exhibit a VLD (variation in lateral doping) profile with a decreasing dopant concentration in the direction of lateral chip edge 10-3. The JTE region 131 may be a doped crystalline semiconductor region of the semiconductor body 10.

As schematically and exemplarily illustrated in fig. 4A, the first passivation layer 15-1 may be disposed directly on the front side surface 10-1 in the edge termination region 17. Thus, in this case, at least a portion of the polycrystalline diamond layer 15-1 may be placed in contact with the doped crystalline semiconductor region of the edge termination structure 13, i.e., with the JTE region 131. In other embodiments, additional layers, such as one or more oxide layers and/or one or more second passivation layers 15-2 as described above, may be disposed between the JTE region 131 and at least a portion of the first passivation layer 15-1.

Referring now to fig. 4B, in another exemplary embodiment, the power semiconductor device 1 may have an IGBT configuration. In this case, the active region 16 may include a plurality of transistor cells 161, each including: one or more source regions of the first conductivity type, which source regions are coupled to the first load terminal structure, for example by means of front-side metallization 11; a body region of the second conductivity type separating the source region from the drift region of the first conductivity type, wherein a transition from the body region to the drift region forms a pn-junction; and an insulated gate electrode configured to selectively induce a conductive channel in the body region, the conductive channel extending from the source region to the drift region. For example, each transistor cell 161 may have a vertical trench gate configuration, as schematically illustrated in fig. 4B. The skilled person is familiar with the design of such an IGBT transistor cell 161 and will therefore not be explained in more detail here. As is also well known to those skilled in the art, also in the case of an IGBT, the drift region 100 may include a field stop region 100-1, as described above with reference to fig. 4A.

In addition, in the active region 16, the semiconductor body 10 may comprise a back-side emitter region 107-1, which back-side emitter region 107-1 has dopants of the second conductivity type and extends along the back-side surface 10-2 of the semiconductor body 10 and is in contact with a back-side metallization 12 forming part of the second load terminal structure. In the edge termination region 17, a less strongly doped region 107-2 of the second conductivity type may be provided instead of the backside emitter region 107-1, so that the emitter efficiency at the backside may be reduced in a direction pointing from the active region 16 towards the lateral chip edge 10-3. Such a concept is sometimes referred to as HDR (high dynamic robustness) concept. The exemplary embodiment shown in fig. 4B provides such a weakly doped HDR region 107-2. In other embodiments, there may be no HDR function, and the backside emitter regions 107-1 may instead extend continuously, e.g., along the entire backside surface 10-2.

Regarding the design of the edge termination region 17, also in the exemplary embodiment of fig. 4B, JTE regions 131 may be provided, which JTE regions 131 may for example have a VLD profile, as explained above with reference to fig. 4A. For example, the JTE region may have dopants of the second conductivity type at a lower dopant concentration than the body region(s) of the IGBT-cell 161.

In addition, as has also been explained above, in an embodiment, at least a portion of the first passivation layer 15-1 may be arranged in direct contact with at least a portion of the JTE region 131.

Referring now to fig. 4C, in an embodiment, edge termination structure 13 may include one or more field rings 132 instead of (or in addition to) JTE region 131. Each field ring 132 may be configured as a doped semiconductor region of the second conductivity type which is comprised in the semiconductor body 10 and is in contact with the front side surface 10-1, and each field ring 132 may laterally surround the active region 16. For example, field ring 132 may be electrically floating.

In addition, in a modified embodiment schematically illustrated in fig. 4D, a combination of field rings 132 and field plates 133 may be provided as the edge termination structure 13. For example, the field plate 133 may be configured to provide effective shielding from external charges. The field plate 133 may comprise, for example, a metal, such as aluminum. Alternatively, such field plates 133 may be formed of polysilicon, for example. For example, in an edge termination structure 13 that combines field rings 132 with field plates 133, an electrical contact may be provided between each field plate 133 and the corresponding field ring 132, for example by means of a metal contact plug.

Also in such embodiments shown in fig. 4C-D, the polycrystalline diamond layer 15-1 forming the first passivation layer may be in direct contact with the doped crystalline semiconductor region, i.e. the one or more field rings 132, at the front side surface 10-1. However, in other variant embodiments, an additional layer (such as an oxide or a second passivation layer 15-2) may be arranged between the front side surface 10-1 and at least a portion of the first passivation layer 15-1.

It should also be noted that in another embodiment, which is not illustrated in the figures, the field plates 133 may be provided without the field rings 132, i.e. the edge termination structure 13 may be entirely based on one or more field plates 133.

The skilled person is generally familiar with various edge termination concepts such as JTE (e.g. with VLD profile), field plates, field rings and combinations of field plates and field rings.

In addition, it should be noted that the edge termination structure 13, which has been explained above with reference to the diode 1 in fig. 4C-D, may also be provided in the power semiconductor device 1 in the active region 16 with a different configuration, such as for example the transistor configuration explained above with reference to fig. 4B.

Referring now to fig. 5, in an embodiment, a portion of the first passivation layer 15-1 may cover at least a portion of the lateral chip edge 10-3 of the semiconductor body 10. For example, the structure as exemplarily and schematically illustrated in fig. 5 may be formed by creating trenches not only in the active area 16 (e.g., gate trenches of IGBTs or MOSFETs) but also in the edge termination region 17, and by carrying out chip segmentation (segmentation) in such a way that the resulting lateral chip edges 10-9 pass through such trenches. In other words, the trench may be sawn in half after wafer dicing, resulting in the shape of the lateral chip edge 10-3 as depicted in fig. 5. Then, the polycrystalline diamond layer 15-1 may be deposited such that the bottom and sidewalls of the trench are covered by the first passivation layer 151.

In addition, in the case where the second passivation layer 15-2 is disposed between the front side surface 10-1 and the first passivation layer 15-1, the first passivation layer 15-1 may be disposed such that it encapsulates the second passivation layer 15-2 (i.e., the first passivation layer 15-1 covers the second passivation layer 15-2 from above and from at least one lateral side).

In addition, in the embodiment illustrated schematically and exemplarily in fig. 6, it may be provided that the first passivation layer 15-1 extends only inside the active region 16 of the power semiconductor device 1. In other words, in this embodiment, the first passivation layer 15-1 does not extend inside the edge termination region 17. For example, in that case, the polycrystalline diamond layer 15-1 may be arranged and configured for the purpose of flashover protection and better heat dissipation in the active region 16.

According to another aspect, a method of producing a power semiconductor device 1 is presented. The method comprises the following steps: providing a semiconductor body 10 having a front side surface 10-1; and forming a first passivation layer 15-1 over the front side surface 10-1, wherein the first passivation layer 15-1 is a polycrystalline diamond layer.

Embodiments of the method correspond to the embodiments of the power semiconductor device 1 described above with reference to the drawings. Therefore, what has been stated above may be equally/similarly applied to the power semiconductor device 1, and the method of forming the power semiconductor device 1, for forming further embodiments. Therefore, the proposed method may further comprise: for example, one or more power cells 160, 161, 162 are formed in the active region 16 and/or the edge termination structures 13, 131, 132, 133 as described above in connection with various exemplary embodiments of the power semiconductor device 1.

In an embodiment of the method of producing the power semiconductor device 1, forming the first passivation layer 15-1 may comprise deposition of a layer of polycrystalline diamond 15-1. For example, the deposition may be carried out at a deposition temperature of at least 350 ℃ (such as at least 400 ℃) (such as, for example, at about 530 ℃).

For example, seeding of the non-diamond substrate may be performed prior to the deposition step. For example, this may involve one or more of the following: polishing by using diamond powder; carrying out ultrasonic treatment by using the diamond powder slurry; and coating with a diamond containing material.

The depositing step may include: for example, Chemical Vapor Deposition (CVD), such as Microwave Plasma Enhanced Chemical Vapor Deposition (MPECVD), hot wire CVD, or a combination of CVD and pulsed laser deposition processes.

In the above, embodiments are explained regarding a power semiconductor device and a corresponding processing method.

For example, these semiconductor devices are based on silicon (Si). Thus, a single-crystal semiconductor region or layer (e.g., semiconductor body 10 and regions/zones thereof, such as regions, etc.) may be a single-crystal Si region or layer. In other embodiments, polycrystalline or amorphous silicon may be employed.

It should be understood, however, that the semiconductor body 10 and its regions/zones may be made of any semiconductor material suitable for the manufacture of semiconductor devices. Examples of such materials include, without limitation: basic semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, without limitation: aluminum gallium nitride (AlGaN) -aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) -gallium nitride (GaN), aluminum gallium nitride (AlGaN) -gallium nitride (GaN), indium gallium nitride (InGaN) -aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC 1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switching applications, Si, SiC, GaAs and GaN materials are currently mainly used.

For ease of description, spatially relative terms such as "below," "above," "upper," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding device in addition to different orientations than those depicted in the figures. In addition, terms such as "first," "second," and the like, are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Throughout this description, like terms refer to like elements.

As used herein, the terms "having," "containing," "including," "exhibiting," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.