Multi-chip packaged semiconductor device and forming method thereof
阅读说明：本技术 多芯片封装的半导体器件及其形成方法 (Multi-chip packaged semiconductor device and forming method thereof ) 是由 刘峻 于 2020-08-31 设计创作，主要内容包括：本发明提供能减小封装面积、缩短信号传输路径、提高产品高频性能和数据传输性能的多芯片封装的半导体器件及其形成方法。多芯片封装的半导体器件包括：包括第一衬底、设在第一衬底的第一表面上的第一内插触点、及设在第一内插器的与第一表面相对的第二表面上的第二内插触点的第一内插器,第二内插触点通过第一衬底电连接至第一内插触点；通过第二内插触点附接到第一内插器的第二表面的、包括沿第一半导体结构的层叠方向层叠的多个NAND管芯的第一半导体结构；通过第二内插触点附接到第一内插器的第二表面的、包括沿第二半导体结构的层叠方向层叠的多个逻辑工艺兼容管芯的第二半导体结构；以及通过第一内插触点附接到第一内插器的电路板。(The invention provides a multi-chip packaged semiconductor device and a forming method thereof, which can reduce the packaging area, shorten the signal transmission path and improve the high-frequency performance and the data transmission performance of the product. A semiconductor device of a multi-chip package includes: a first interposer including a first substrate, a first interposer contact provided on a first surface of the first substrate, and a second interposer contact provided on a second surface of the first interposer opposite to the first surface, the second interposer contact being electrically connected to the first interposer contact through the first substrate; a first semiconductor structure including a plurality of NAND dies stacked in a stacking direction of the first semiconductor structure, attached to a second surface of the first interposer by second interposer contacts; a second semiconductor structure attached to the second surface of the first interposer by second interposer contacts and including a plurality of logic process compatible dies stacked in a stacking direction of the second semiconductor structure; and a circuit board attached to the first interposer by the first interposer contacts.)
1. A multi-chip packaged semiconductor device, comprising:
a first interposer including a first substrate, first interposer contacts disposed on a first surface of the first substrate, and second interposer contacts disposed on a second surface of the first interposer opposite the first surface, the second interposer contacts being electrically connected to the first interposer contacts through the first substrate;
a first semiconductor structure attached to the second surface of the first interposer by the second interposer contact, the first semiconductor structure comprising a plurality of NAND dies stacked along a stacking direction of the first semiconductor structure;
a second semiconductor structure attached to the second surface of the first interposer by the second interposer contact, the second semiconductor structure including a plurality of logic process compatible dies stacked along a stacking direction of the second semiconductor structure; and
a circuit board attached to the first interposer through the first interposer contacts.
2. The multi-chip packaged semiconductor device of claim 1,
in the first semiconductor structure,
a plurality of first bonding contacts are provided on sides of the plurality of NAND dies facing each other, respectively, the NAND dies facing each other are contacted by the first bonding contacts facing each other, thereby bonding the plurality of NAND dies to each other,
in the second semiconductor structure, the first semiconductor structure,
the logic process compatible dies are provided with a plurality of second bonding contacts on the opposite sides, and the logic process compatible dies opposite to each other are contacted through the second bonding contacts opposite to each other, so that the logic process compatible dies are bonded with each other.
3. The multi-chip packaged semiconductor device of claim 2,
the first bonding contact and the second bonding contact are comprised of copper or cobalt.
4. The multi-chip packaged semiconductor device of claim 1,
in the first semiconductor structure,
a plurality of the NAND dies are respectively provided with a first through silicon channel and first die contacts positioned at two ends of the first through silicon channel, the plurality of the NAND dies are electrically connected through the first through silicon channel and the first die contacts between the plurality of the NAND dies,
in the second semiconductor structure, the first semiconductor structure,
the plurality of logic process compatible dies are respectively provided with a second through silicon channel and second die contacts positioned at two ends of the second through silicon channel, and the plurality of logic process compatible dies are electrically connected through the second through silicon channel and the second die contacts among the plurality of logic process compatible dies.
5. The multi-chip packaged semiconductor device of claim 1,
in the first semiconductor structure,
a plurality of the NAND dies and a plurality of second interposers are alternately stacked in a stacking direction of the first semiconductor structure,
the second interposer includes a second substrate, third interposer contacts disposed on a third surface of the second substrate, and fourth interposer contacts disposed on a fourth surface of the second interposer opposite the third surface, the fourth interposer contacts being electrically connected to the third interposer contacts through the second substrate,
the NAND die is attached to a third surface of an adjacent second interposer by the third interposer contacts, to a fourth surface of an adjacent second interposer by the fourth interposer contacts,
in the second semiconductor structure, the first semiconductor structure,
a plurality of the logic process compatible dies and a plurality of third interposers are alternately stacked in a stacking direction of the second semiconductor structure,
the third interposer includes a third substrate, fifth interposer contacts disposed on a fifth surface of the third substrate, and sixth interposer contacts disposed on a sixth surface of the third interposer opposite the fifth surface, the sixth interposer contacts being electrically connected to the fifth interposer contacts through the third substrate,
the logic process compatible die is attached to the fifth surface of the adjacent third interposer by the fifth interposer contacts and to the sixth surface of the adjacent third interposer by the sixth interposer contacts.
6. The multi-chip packaged semiconductor device of claim 5,
the second interposer is formed integrally with the third interposer.
7. The multi-chip packaged semiconductor device of any one of claims 1 to 6,
the NAND die includes an array of NAND memory cells comprised of at least one of two-dimensional NAND memory cells and three-dimensional NAND memory cells.
8. The multi-chip packaged semiconductor device of any one of claims 1 to 6,
the logic process compatible die includes at least one of a controller, a random access memory array, and peripheral circuitry of the NAND die.
9. A method for forming a multi-chip packaged semiconductor device, comprising:
a first interposer forming step in which a first substrate is provided, first interposer contacts are provided on a first surface of the first substrate, second interposer contacts are provided on a second surface of the first interposer opposite to the first surface, the second interposer contacts being electrically connected to the first interposer contacts through the first substrate;
a first semiconductor structure forming step of attaching the first semiconductor structure to the second surface of the first interposer through the second interposer contact, the first semiconductor structure including a plurality of NAND dies stacked in a stacking direction of the first semiconductor structure;
a second semiconductor structure forming step of attaching the second semiconductor structure to the second surface of the first interposer through the second interposer contact, the second semiconductor structure including a plurality of logic process compatible dies stacked along a stacking direction of the second semiconductor structure; and
a circuit board forming step: in this circuit board forming step, a circuit board is formed, and the circuit board is attached to the first interposer through the first interposer contacts.
10. The method for forming a semiconductor device of a multi-chip package of claim 9,
in the first semiconductor structure forming step,
providing a plurality of first bonding contacts on sides of the plurality of NAND dies that are opposite to each other, respectively, and contacting the NAND dies that are opposite to each other through the first bonding contacts that are opposite to each other, thereby bonding the plurality of NAND dies to each other,
in the second semiconductor structure forming step,
and respectively arranging a plurality of second bonding contacts on the opposite sides of the logic process compatible dies, so that the logic process compatible dies opposite to each other are contacted through the second bonding contacts opposite to each other, thereby bonding the logic process compatible dies to each other.
11. The method for forming a multi-chip packaged semiconductor device of claim 10,
the first bonding contact and the second bonding contact are comprised of copper or cobalt.
12. The method for forming a semiconductor device of a multi-chip package of claim 9,
in the first semiconductor structure forming step,
providing a first through-silicon via and first die contacts at both ends of the first through-silicon via in the plurality of NAND dies, respectively, electrically connecting the plurality of NAND dies through the first through-silicon via and the first die contacts between the plurality of NAND dies,
in the second semiconductor structure forming step,
and respectively arranging a second through silicon channel and second die contacts positioned at two ends of the second through silicon channel in the plurality of logic process compatible dies, and electrically connecting the plurality of logic process compatible dies through the second through silicon channel and the second die contacts between the plurality of logic process compatible dies.
13. The method for forming a semiconductor device of a multi-chip package of claim 9,
in the first semiconductor structure forming step,
alternately stacking a plurality of the NAND dies with a plurality of second interposers in a stacking direction of the first semiconductor structure,
the second interposer includes a second substrate, third interposer contacts disposed on a third surface of the second substrate, and fourth interposer contacts disposed on a fourth surface of the second interposer opposite the third surface, the fourth interposer contacts being electrically connected to the third interposer contacts through the second substrate,
attaching the NAND die to a third surface of an adjacent second interposer through the third interposer contacts, to a fourth surface of an adjacent second interposer through the fourth interposer contacts,
in the second semiconductor structure forming step,
alternately stacking a plurality of the logic process compatible dies with a plurality of third interposers in a stacking direction of the second semiconductor structures,
the third interposer includes a third substrate, fifth interposer contacts disposed on a fifth surface of the third substrate, and sixth interposer contacts disposed on a sixth surface of the third interposer opposite the fifth surface, the sixth interposer contacts being electrically connected to the fifth interposer contacts through the third substrate,
attaching the logic process compatible die to a fifth surface of an adjacent third interposer through the fifth interposer contact and to a sixth surface of an adjacent third interposer through the sixth interposer contact.
14. The multi-chip packaged semiconductor device of claim 13,
the second interposer is formed integrally with the third interposer.
15. The method for forming a semiconductor device of a multi-chip package of any of claims 9 to 14,
the NAND die includes an array of NAND memory cells comprised of at least one of two-dimensional NAND memory cells and three-dimensional NAND memory cells.
16. The method for forming a semiconductor device of a multi-chip package of any of claims 9 to 14,
the logic process compatible die includes at least one of a controller, a random access memory array, and peripheral circuitry of the NAND die.
Technical Field
The present invention relates to a semiconductor device of a multi-chip package and a method of forming the same, and more particularly, to a semiconductor device of a multi-chip package for realizing 2.5D by an interposer structure and a method of forming the same.
Background
In the past, higher requirements have been put forward on packaging technology along with the application of integrated circuits in emerging fields such as smart phones, automotive electronics, artificial intelligence and the like. In order to reduce the circuit scale, reduce power consumption, and improve circuit performance, a multi-chip package technique is widely used in which a plurality of elements such as chips are arranged in the same package, and the functions of these elements are integrated by connection.
As a conventional multi-chip package technology, for example, a memory package mainly configured by a high-stack package connected by gold wires as shown in fig. 8 is given. As shown in fig. 8, a plurality of chips or films are stacked on a substrate, and after the leads of the chips are connected to the gold fingers on the substrate by the wire loop of the gold wire, the substrate, the gold wire, the chips, and the like are covered with a molding compound, and solder balls are formed on the surface of the substrate opposite to the molding surface, thereby forming a multi-chip package structure.
However, in such a conventional package structure, for example, when the memory package structure of fig. 8 is viewed from above, the external area after packaging increases by at least 30% as compared with the area of the internal chip due to the loop of the gold wire and the presence of the gold finger. The cost of the substrate in the package (i.e., the cost of removing the silicon chip) is a major portion of the overall package cost, and thus, the cost of the multi-chip packaged semiconductor device is greatly increased. Meanwhile, with the continuous upgrading of the performance of the semiconductor, the requirement on the substrate is higher and higher, and the structure of the substrate is more and more complicated and the design period is prolonged by adopting the existing packaging mode, so that the speed of the product to be put on the market is restricted. In addition, the substrate used in the conventional packaging method has a complicated structure and a long delivery time, and the existence of market fluctuation often causes great troubles to the preparation of the substrate.
In addition, the conventional gold Wire (WB) process has a long conductive path, which limits the high frequency performance of the chipset. Moreover, due to the restriction of wire bonding, the number of I/O terminals that can be led out from a single-layer chip is limited, and it is difficult to improve the data transmission performance of the product.
Disclosure of Invention
An object of the present invention is to provide a semiconductor device of a multi-chip package capable of reducing a package area, shortening a signal transmission path, and improving high frequency performance and data transmission performance of a product, and a method of forming the semiconductor device of the multi-chip package.
In order to solve the above problem, a semiconductor device of a multi-chip package according to a first aspect of the present invention includes:
a first interposer including a first substrate, first interposer contacts disposed on a first surface of the first substrate, and second interposer contacts disposed on a second surface of the first interposer opposite the first surface, the second interposer contacts being electrically connected to the first interposer contacts through the first substrate;
a first semiconductor structure attached to the second surface of the first interposer by the second interposer contact, the first semiconductor structure comprising a plurality of NAND dies stacked along a stacking direction of the first semiconductor structure;
a second semiconductor structure attached to the second surface of the first interposer by the second interposer contact, the second semiconductor structure including a plurality of logic process compatible dies stacked along a stacking direction of the second semiconductor structure; and
a circuit board attached to the first interposer through the first interposer contacts.
In addition, in order to solve the above problem, a method for forming a semiconductor device of a multi-chip package according to a second aspect of the present invention includes:
a first interposer forming step in which a first substrate is provided, first interposer contacts are provided on a first surface of the first substrate, second interposer contacts are provided on a second surface of the first interposer opposite to the first surface, the second interposer contacts being electrically connected to the first interposer contacts through the first substrate;
a first semiconductor structure forming step of attaching the first semiconductor structure to the second surface of the first interposer through the second interposer contact, the first semiconductor structure including a plurality of NAND dies stacked in a stacking direction of the first semiconductor structure;
a second semiconductor structure forming step of attaching the second semiconductor structure to the second surface of the first interposer through the second interposer contact, the second semiconductor structure including a plurality of logic process compatible dies stacked along a stacking direction of the second semiconductor structure; and
a circuit board forming step: in this circuit board forming step, a circuit board is formed, and the circuit board is attached to the first interposer through the first interposer contacts.
According to the semiconductor device of the multi-chip package and the forming method thereof, the packaging area can be reduced, the signal transmission path can be shortened, and the high-frequency performance and the data transmission performance of the product can be improved.
Drawings
Fig. 1 is a schematic diagram showing the structure of a semiconductor device of a multi-chip package of the present invention.
Fig. 2(a) to 2(D) are schematic cross-sectional views of main processes in forming a semiconductor device of a multi-chip package according to
Fig. 3 is a flowchart illustrating a method of forming a semiconductor device of the multi-chip package of
Fig. 4(a) to 4(D) are schematic cross-sectional views of main processes in forming a semiconductor device of a multi-chip package according to embodiment 2 of the present invention.
Fig. 5 is a flowchart illustrating a method of forming a semiconductor device of a multi-chip package of embodiment 2.
Fig. 6(a) to 6(D) are schematic cross-sectional views of main processes in forming a semiconductor device of a multi-chip package according to embodiment 3 of the present invention.
Fig. 7 is a flowchart illustrating a method of forming a semiconductor device of a multi-chip package of embodiment 3.
Fig. 8 is a schematic diagram showing the structure of a conventional memory package.
Description of the reference symbols
1 first interpolator
1a first substrate
1b second interposer contact
1c first inner contact
2 first semiconductor structure
2 a-2 d NAND die
21 first bonding contact
22 first through silicon channel
23 first die contact
24 second interposer
24a second substrate
24b fourth interposer contact
24c third interposer contact
3 second semiconductor structure
3 a-3 e logic process compatible tube core
31 second bonding contact
32 second through silicon via
33 second die contact
34 third interpolator
34a third substrate
34b sixth interposer contact
34c fifth inner interposer contact
4 Circuit board
100. 100A, 100B, 100C multi-chip packaged semiconductor device
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
Next, a basic structure of the semiconductor device of the multi-chip package of the present invention will be described with reference to fig. 1.
Fig. 1 is a schematic diagram showing the structure of a semiconductor device of a multi-chip package of the present application. As shown in fig. 1, a semiconductor device 100 of a multi-chip package includes a
The
As one of the methods of electrically connecting second interposer contact 1b and
The dashed box on the left side of fig. 1 represents the first semiconductor structure 2. As shown, the first semiconductor structure 2 is attached to the second surface of the
The dashed box on the right side of fig. 1 represents the second semiconductor structure 3. As shown, the second semiconductor structure 3 is attached to the second surface of the
In addition, as shown in the figure, the circuit board 4 is attached to the
According to the above-described basic structure of the present application, since the semiconductor device of the multi-chip package is formed in a manner of replacing the conventional gold wire with the interposer, the area waste caused by the arc of the gold wire can be saved, so that the entire area of the semiconductor device of the multi-chip package can be further reduced. In addition, since the first semiconductor construct 2 and the second semiconductor construct 3 are connected to the circuit board 4 through the second interposer contact 1b formed on the surface of the
Next, a preferred embodiment of the present application will be described with reference to fig. 2 to 7.
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