阅读说明：本技术 薄膜覆晶封装结构 (Thin film flip chip packaging structure ) 是由 陈崇龙 于 2019-06-13 设计创作，主要内容包括：本发明提供一种薄膜覆晶封装结构,包括可挠性基材、多个引脚、芯片以及多个凸块。可挠性基材具有芯片接合区。这些引脚设置于可挠性基材上并包括多个第一引脚与多个第二引脚。这些第一引脚与这些第二引脚沿着芯片接合区的第一侧边交错排列。芯片位于芯片接合区内。芯片的主动面面向可挠性基材。这些凸块设置于芯片的主动面上并包括邻近主动面的第一边缘的多个第一凸块与多个第二凸块。这些第一凸块接合于这些第一引脚,这些第二凸块接合于这些第二引脚,且接合于这些第一引脚的其一的第一凸块的宽度与相邻的第二引脚的宽度相等。(The invention provides a chip-on-film packaging structure, which comprises a flexible substrate, a plurality of pins, a chip and a plurality of bumps. The flexible substrate is provided with a chip joint area. The leads are arranged on the flexible substrate and comprise a plurality of first leads and a plurality of second leads. The first pins and the second pins are staggered along a first side edge of the chip bonding area. The chip is located within the chip bonding region. The active surface of the chip faces the flexible substrate. The bumps are arranged on the active surface of the chip and comprise a plurality of first bumps and a plurality of second bumps, wherein the first bumps and the second bumps are adjacent to the first edge of the active surface. The first bumps are connected with the first pins, the second bumps are connected with the second pins, and the width of the first bump connected with one of the first pins is equal to that of the adjacent second pin.)

1. A chip on film package structure, comprising:

the flexible substrate is provided with a chip joint area, and the chip joint area is provided with a first side edge and a second side edge which are opposite;

a plurality of leads disposed on the flexible substrate, wherein the plurality of leads include a plurality of first leads and a plurality of second leads, the plurality of first leads and the plurality of second leads are staggered along the first side and extend from the chip bonding area through the first side;

a chip disposed in the chip bonding area, the chip having an active surface, the active surface having a first edge and a second edge opposite to each other, the active surface facing the flexible substrate, wherein the first edge is adjacent to the first side of the chip bonding area, and the second edge is adjacent to the second side of the chip bonding area; and

the bumps are arranged on the active surface of the chip, the bumps comprise a plurality of first bumps and a plurality of second bumps, the first bumps are adjacent to the first edge, the first bumps are jointed with the first pins, the second bumps are jointed with the second pins, and the width of each first bump jointed with one of the first pins is equal to the width of the adjacent second pin.

2. The COF package structure of claim 1, wherein the second bumps and the first bumps are staggered in a direction parallel to the first edge, the second bumps are closer to the center of the chip than the first bumps, and the ends of the second pins are closer to the center of the chip bonding area than the ends of the first pins.

3. The COF package structure of claim 1, wherein the width of each second bump is greater than the width of the corresponding second lead.

4. The COF package structure of claim 1, wherein the width of the first bump equal to the width of the adjacent second leads is less than or equal to the width of the corresponding bonded first leads.

5. The COF package structure of claim 4, wherein a ratio of a width of the first bump equal to a width of the adjacent second lead to a width of the corresponding bonded first lead is between 0.8 and 1.

6. The COF package structure of claim 1, wherein one of the second leads is disposed between any two adjacent first leads or one of the first leads is disposed between any two adjacent second leads.

7. The COF package structure of claim 1, wherein a width direction of the first bump and a width direction of the second lead are parallel to the first edge of the chip.

8. The COF package structure of claim 1, wherein the plurality of leads includes a plurality of third leads arranged along the second side and extending from the chip bonding area through the second side, the plurality of bumps includes a plurality of third bumps adjacent to the second edge, and the plurality of third bumps are bonded to the plurality of third leads.

9. The COF package structure of claim 1, further comprising a solder mask layer on the flexible substrate and partially covering the leads, wherein the solder mask layer has an opening exposing the die bonding area.

10. The COF package structure of claim 1, further comprising an encapsulant at least filled between the chip and the flexible substrate.

Technical Field

The present invention relates to a package structure, and more particularly, to a chip-on-film package structure.

Background

A Chip On Film (COF) package structure is a common package type of a driving Chip of a liquid crystal display. With the increase of the number of bumps, the increase of the number of pins, and the reduction of the pitch of the pins on the chip, the layout of the bumps and the pins is increasingly limited.

With respect to the current size design of the bump and the lead, the width of the bump is designed to be larger than that of the lead, so as to ensure that a sufficient bonding area can be maintained when the bump and the lead are bonded with each other. With the trend of fine pitch (FinePitch), the spacing between adjacent bumps is reduced, and once a machine precision error or a pin offset occurs, the existing spacing between adjacent bumps may be difficult to provide a sufficient safety space or buffer space, so that the risk of the bumps overlapping the adjacent pins is greatly increased.

Disclosure of Invention

The invention provides a chip-on-film packaging structure which is beneficial to reducing the risk of overlapping adjacent pins by bumps.

The chip on film package structure of the invention comprises a flexible substrate, a plurality of pins, a chip and a plurality of bumps. The flexible substrate is provided with a chip joint area. The chip bonding area is provided with a first side edge and a second side edge which are opposite. The pins are arranged on the flexible substrate. The pins comprise a plurality of first pins and a plurality of second pins. The first leads and the second leads are staggered along the first side edge and extend from the chip bonding area through the first side edge. The chip is located within the chip bonding region. The chip is provided with an active surface, the active surface is provided with a first edge and a second edge which are opposite, and the active surface faces the flexible substrate. The first edge is adjacent to the first side of the die attach region and the second edge is adjacent to the second side of the die attach region. The bumps are arranged on the active surface of the chip. The bumps include a plurality of first bumps and a plurality of second bumps adjacent to the first edge. The first bumps are connected with the first pins, the second bumps are connected with the second pins, and the width of the first bump connected with one of the first pins is equal to that of the adjacent second pin.

In an embodiment of the invention, the second bumps and the first bumps are staggered in a direction parallel to the first edge of the chip-on-film package structure. The second bumps are closer to the center of the chip than the first bumps, and the ends of the second pins are closer to the center of the chip bonding area than the ends of the first pins.

In an embodiment of the invention, a width of each of the second bumps is greater than a width of the corresponding bonded second lead.

In an embodiment of the invention, the width of the first bump equal to the width of the adjacent second lead is less than or equal to the width of the corresponding bonded first lead.

In an embodiment of the invention, a ratio of the width of the first bump equal to the width of the adjacent second lead to the width of the corresponding bonded first lead is between 0.8 and 1.

In an embodiment of the invention, a second pin is disposed between any two adjacent first pins or a first pin is disposed between any two adjacent second pins.

In an embodiment of the invention, the width direction of the adjacent first bumps and the width direction of the second leads are parallel to the first edge of the chip.

In an embodiment of the invention, the leads include a plurality of third leads. The third pins are arranged along the second side edge and extend out from the chip bonding area through the second side edge. The bumps include third bumps adjacent to the second edge, and the third bumps are bonded to the third leads.

In an embodiment of the invention, the chip-on-film package structure further includes a solder mask layer. The solder mask layer is located on the flexible substrate and partially covers the leads. The solder mask layer has an opening to expose the chip bonding area.

In an embodiment of the invention, the above-mentioned chip-on-film package structure further includes an encapsulant. The packaging colloid is at least filled between the chip and the flexible substrate.

Based on the above, in the chip-on-film package structure of the present invention, the width of a part of the plurality of bumps is designed to be equal to the width of the adjacent pins, so that the distance between the bump and the adjacent pin is increased without affecting the pin distance. Once the machine precision error or pin deviation occurs, because the bump and the adjacent pin have enough space therebetween as a safety space or a buffer space, the risk of the bump overlapping the adjacent pin is reduced, thereby improving the manufacturing yield and the product reliability of the chip-on-film package structure.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention.

Fig. 1B is an enlarged schematic view of the region a of fig. 1A.

FIG. 1C is a schematic cross-sectional view taken along line B-B' of FIG. 1B.

Fig. 1D is a schematic top view of a portion of a chip-on-film package structure according to an embodiment of the invention.

Fig. 1E is a partial top view of a chip-on-film package structure in the prior art.

Fig. 2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention.

[ notation ] to show

100. 100 a: thin film flip chip packaging structure

110: flexible base material

112: chip bonding area

112 a: the first side edge

112 b: second side edge

120: pin

122: first pin

122a, 124 a: end part

122W: width of the first pin

124. 1241: second pin

124W: width of the second pin

126: third pin

130: chip and method for manufacturing the same

130 a: active surface

140: bump

142. 1421: first bump

142W, W1: width of the first bump

144. 1441: second bump

144W, W2: width of the second bump

146: third bump

150: welding-proof layer

152: opening of the container

160: packaging colloid

A: region(s)

C: center (C)

D: direction of rotation

E1: first edge

E2: second edge

S1, S2: spacer

Detailed Description

Fig. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. Fig. 1B is an enlarged schematic view of the region a of fig. 1A. FIG. 1C is a schematic cross-sectional view taken along line B-B' of FIG. 1B. For clarity of connection among the leads 120, the chip 130 and the bumps 140, the chip 130 and the solder mask 150 in fig. 1A are shown in a perspective drawing, and the encapsulant 160 is omitted.

Referring to fig. 1A to fig. 1C, in the present embodiment, the thin film flip chip package structure 100 includes a flexible substrate 110, a plurality of leads 120, a chip 130, and a plurality of bumps 140, wherein the flexible substrate 110 may be made of polyethylene terephthalate (PET), Polyimide (PI), Polyether (PES), Polycarbonate (PC), or other suitable flexible materials. On the other hand, the flexible substrate 110 is used for carrying the leads 120, wherein the flexible substrate 110 has a chip bonding area 112, and the chip bonding area 112 has a first side 112a and a second side 112b opposite to each other.

Specifically, the leads 120 are disposed on the flexible substrate 110, and the leads 120 include a plurality of first leads 122 and a plurality of second leads 124, wherein the first leads 122 and the second leads 124 are staggered along the first side 112a and extend from the chip bonding region 112 through the first side 112 a. That is, at least one second lead 124 is disposed between any two adjacent first leads 122, or at least one first lead 122 is disposed between any two adjacent second leads 124. In addition, the first leads 122 and the second leads 124 respectively have a section in the chip bonding region 112 and another section outside the chip bonding region 112.

On the other hand, the length of the section of each second lead 124 in the chip bonding region 112 is longer than the length of the section of each first lead 122 in the chip bonding region 112. That is, the end 124a of each second lead 124 is closer to the center C of the die attach region 112 than the end 122a of each first lead 122, or the end 124a of each second lead 124 is farther from the first side 112a of the die attach region 112 than the end 122a of each first lead 122. The chip 130 is located in the chip bonding region 112, the chip 130 has an active surface 130a, wherein the active surface 130a of the chip 130 faces the flexible substrate 110, and the bumps 140 disposed on the active surface 130a are bonded to the leads 120 located in the chip bonding region 112.

Further, the active surface 130a of the chip 130 has a first edge E1 and a second edge E2 opposite to each other, wherein the first edge E1 is adjacent to the first side 112a of the chip bonding region 112, and the second edge E2 is adjacent to the second side 112b of the chip bonding region 112. The first edge E1 and the second edge E2 may be long sides of the chip 130, wherein the bumps 140 include a plurality of first bumps 142 and a plurality of second bumps 144 adjacent to the first edge E1, the first bumps 142 are bonded to the first leads 122, and the second bumps 144 are bonded to the second leads 124. More specifically, in the direction D parallel to the first edge E1, the second bumps 144 and the first bumps 142 are staggered, and the second bumps 144 are closer to the center C of the chip 130 than the first bumps 142. For example, in the direction D parallel to the first edge E1, the second bumps 144 are aligned with each other, the first bumps 142 are aligned with each other, and any second bump 144 is offset from any first bump 142.

Based on the layout of the bumps 140 and the leads 120, the thin film flip chip package structure 100 can meet the design requirements of high pin count, high bump count and fine pitch.

In the present embodiment, the width 142W of the first bump 142 bonded to one of the first leads 122 is equal to the width 124W of the adjacent second lead 124, and the width direction of the adjacent first bump 142 and second lead 124 may be parallel to the first edge E1 of the chip 130. Therefore, a larger distance is reserved between the adjacent first bumps 142 and the second leads 124, and once a machine precision error or a lead offset occurs, since a sufficient distance is reserved between the adjacent first bumps 142 and the second leads 124 as a safety space or a buffer space, the risk that the adjacent second leads 124 are overlapped by the first bumps 142 is reduced, so as to improve the manufacturing yield and the product reliability of the thin film flip chip package structure 100.

For example, the width 142W of the first bump 142 and the width 124W of the second lead 124 may be 8 micrometers (μm), but the invention is not limited thereto. On the other hand, the width 144W of each second bump 144 may be larger than the width 124W of the corresponding bonded second lead 124, so as to provide a better bonding effect. For example, the width 144W of the second bump 144 may be 13 to 15 micrometers, but the present invention is not limited thereto. Because the width 144W of the second bumps 144 is designed to be larger than the width 124W of the second leads 124, if the leads are deviated when the chip 130 is bonded to the leads 120, a sufficient bonding area can be maintained between the second bumps 144 and the second leads 124, so that good bonding strength can be maintained between the bumps and the leads, and the deviation degree when the leads are abutted to the bumps can be further suppressed.

In the present embodiment, the width 142W of each first bump 142 and the width 122W of the corresponding bonded first lead 122 may be the same. In other words, the width 122W of each first lead 122 and the width 124W of the adjacent second lead 124 may be the same, for example, 8 μm, but the invention is not limited thereto.

In the present embodiment, the leads 122 may further include a plurality of third leads 126, and the bumps 140 include a plurality of third bumps 146 adjacent to the second edge E2. The third leads 126 may be arranged along the second side 112b and extend from the chip bonding region 112 through the second side 112b, wherein the third bumps 146 are bonded to the third leads 126. On the other hand, to protect the leads 120 and prevent the leads 120 from being damaged or contaminated by foreign matters to cause the bridging of the leads, the chip-on-film package 100 may further include a solder mask 150, wherein the solder mask 150 is disposed on the flexible substrate 110 and partially covers the leads 120. The solder mask layer 150 exposes the die attach region 112. further, the solder mask layer 150 has an opening 152, and the die attach region 112 is substantially defined by the opening 152 of the solder mask layer 150.

In addition, in order to protect the electrical contacts of the bumps 140 and the leads 120 from moisture and contamination, the chip-on-film package structure 100 may further include an encapsulant 160, wherein the encapsulant 160 is at least filled between the chip 130 and the flexible substrate 110 and further covers the periphery of the opening 152 of the solder mask 150 and the side surface of the chip 130.

Fig. 1D is a schematic top view of a portion of a chip-on-film package structure according to an embodiment of the invention. Fig. 1E is a partial top view of a chip-on-film package structure in the prior art. Specifically, the dashed pins in fig. 1D are used to indicate the positions of the second pins 124 after being offset, and the dashed pins in fig. 1E are used to indicate the positions of the second pins 1241 after being offset.

For example, if the width 142W of the first bump 142 is 8 microns, the width 144W of the second bump 144 is 13 microns, and the distance between the center of the first bump 142 and the center of the second bump 144 is 16 microns, the space S1 between the first bump 142 and the second bump 144 is 5.5 microns, as shown in fig. 1D. On the other hand, if the width W1 of the first bump 1421 and the width W2 of the second bump 1441 are both 13 microns, and the distance between the center of the first bump 1421 and the center of the second bump 1441 is 16 microns, the distance S2 between the first bump 1421 and the second bump 1441 is 3 microns, as shown in fig. 1E.

Continuing from the above, the spacing S1 (e.g. 5.5 microns) between the first bump 142 and the second bump 144 is much larger than the spacing S2 (e.g. 3 microns) between the first bump 1421 and the second bump 1441, and if the second lead 1241 is offset, the second lead 1241 is easily overlapped with the adjacent first bump 1421. In contrast, since the space S1 between the first bump 142 and the second bump 144 is larger in the embodiment, even if the second lead 124 is offset, a sufficient buffer space is still remained between the second lead 124 and the adjacent first bump 142, which is helpful for preventing the second lead 124 from overlapping with the adjacent first bump 142.

Fig. 2 is a schematic cross-sectional view of a chip-on-film package structure according to another embodiment of the invention. Referring to fig. 2, the chip-on-film package structure 100a of the present embodiment is similar to the chip-on-film package structure 100 of the previous embodiment, and the difference is: in the chip-on-film package structure 100a, the width 122W of each first lead 122 is greater than the width 142W of the corresponding bonded first bump 142. More specifically, the ratio of the width 142W of the first bump 142 to the width 122W of the corresponding bonded first lead 122 may be between 0.8 and 1, that is, when the width 142W of the first bump 142 is, for example, 8 micrometers, the width 122W of the first lead 122 is, for example, between 8 micrometers and 10 micrometers, but the invention is not limited thereto. Because the width 122W of the first leads 122 is designed to be larger than the width 144W of the first bumps 142, if a lead offset occurs when the chip 130 is bonded to the leads 120, a sufficient bonding area can be maintained between the first bumps 142 and the first leads 122, so that good bonding strength can be maintained between the bumps and the leads.

In summary, in the chip-on-film package structure of the invention, the width of the first bump is designed to be equal to the width of the adjacent second pin, and the distance between the first bump and the adjacent second pin is increased without affecting the pin distance. Once the machine precision error or the pin offset is generated, because the first bump and the adjacent second pin have enough space therebetween as the safety space or the buffer space, the risk that the first bump overlaps the adjacent second pin is reduced, so as to improve the manufacturing yield and the product reliability of the chip-on-film package structure.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.