阅读说明：本技术 用于接合结构的保护性元件 (Protective element for a joining structure ) 是由 J·A·德拉克鲁斯 B·哈巴 R·卡特卡尔 于 2020-04-10 设计创作，主要内容包括：公开了一种接合结构,接合结构可以包括具有源电路系统的半导体元件。接合结构可以包括保护性元件,该保护性元件沿着接合表面在没有粘合剂的情况下被直接接合到半导体元件。保护性元件可以包括设置在有源电路系统的至少一部分之上的阻碍性材料。阻碍性材料可以被配置为阻隔到有源电路系统的外部接入。接合结构可以包括中断结构,该中断结构被配置为一旦将保护性元件从半导体元件剥离,则中断有源电路系统的至少一部分的功能。(A bonding structure is disclosed, which may include a semiconductor element having source circuitry. The bonding structure may include a protective element that is bonded directly to the semiconductor element along the bonding surface without an adhesive. The protective element may include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material may be configured to block external access to the active circuitry. The bonding structure may include an interruption structure configured to interrupt a function of at least a portion of the active circuitry upon peeling the protective element from the semiconductor element.)

1. A joining structure comprising:

a semiconductor element including active circuitry;

an obstructive element bonded directly to the semiconductor element along a bonding interface without adhesive, the obstructive element comprising an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry; and

an interruption structure configured to interrupt a function of the at least a portion of the active circuitry once the blocking element is peeled off the semiconductor element.

2. The joining structure of claim 1, wherein the obstructive material is positioned at a distance of less than 10 microns from the joining interface.

3. The joining structure of claim 1, wherein the obstructive material is positioned at a distance of less than 5 microns from the joining interface.

4. The joining structure of claim 1, wherein said obstructive material comprises a destructive material having a hardness in the range of 20GPa to 150GPa on the vickers hardness scale.

5. The joining structure of claim 1, wherein said obstructive material comprises a destructive material having a hardness of at least 80GPa on the vickers hardness scale.

6. The bonding structure of claim 1, wherein the interruption structure comprises an etched path through a portion of the semiconductor element.

7. The bonded structure of claim 6, wherein the semiconductor element comprises a first bonding layer, and wherein the obstructive element comprises a second bonding layer directly bonded to the first bonding layer without an adhesive.

8. The bonded structure of claim 7, wherein the first bonding layer comprises a first material and the etch path also comprises the first material.

9. The bonded structure of claim 8, wherein the first material comprises silicon oxide.

10. The bonded structure of claim 9, wherein the first bonding layer further comprises one or more of fluorine and nitrogen.

11. The joining structure of claim 7, wherein the interrupting structure is configured to: interrupting a function of the at least a portion of the active circuitry upon selective etch lift-off from one or more of the first bonding layer and the second bonding layer.

12. The bonding structure of claim 7, wherein the first bonding layer and the second bonding layer comprise silicon oxide.

13. The bonded structure of claim 7, further comprising one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers including circuitry, the etch path extending through at least a portion of the one or more intermediate layers.

14. The bonded structure of claim 13, wherein the one or more intermediate layers comprise a barrier layer in which one or more openings are formed, the barrier extending through the one or more openings.

15. The bonded structure of claim 14, wherein one or more openings in the barrier layer comprise the material of the first bonding layer.

16. The bonded structure of claim 14, wherein the barrier layer comprises silicon nitride.

17. The bonded structure of claim 14, further comprising a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer.

18. The joining structure of claim 13, wherein said interrupting structure further comprises a cavity in said one or more intermediate layers.

19. The bonding structure of claim 7, further comprising a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads.

20. The bonded structure of claim 19, further comprising a first barrier layer in the first bonding layer and a layer of anchor material in the second bonding layer, the first barrier layer having one or more openings therethrough.

21. The bonding structure of claim 20, wherein the second plurality of contact pads are at least partially embedded in the layer of anchoring material.

22. The bonding structure of claim 19, wherein at least one contact pad is connected to a monitoring circuit to monitor connectivity of the first and second pluralities of contact pads that are directly bonded.

23. The bonding structure of claim 19, wherein at least two or more of the second plurality of contact pads are electrically connected.

24. The bonded structure of claim 19 further comprising a Back End (BEOL) layer comprising power circuitry in the obstructive elements.

25. The bonding structure of claim 1, wherein the interrupting structure further comprises a conductive trace configured to detect whether the obstructive element has been peeled away from the semiconductor element.

26. The bonding structure of claim 1, wherein the obstructive material is patterned to expose portions of the semiconductor element, the etch path extending through the exposed portions.

27. The bonding structure of claim 1, wherein a first hardness of the obstructive material is greater than a second hardness of the semiconductor element or a third hardness of the material at the bonding interface.

28. The joining structure of claim 1, wherein the obstructive material comprises an abrasive material.

29. The joining structure of claim 1, wherein the obstructive material comprises a light blocking material.

30. The joined structure of claim 29, wherein the light blocking material is configured to block light of Near Infrared (NIR) wavelengths.

31. The joining structure of claim 1, wherein said obstructive material comprises an optical or Infrared (IR) blocking or modifying material.

32. A joining structure comprising:

a semiconductor element including active circuitry;

an obstructive element bonded directly to the semiconductor element along a bonding interface without adhesive, the obstructive element comprising an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry; and

an etch path through a portion of the semiconductor element, the etch path configured to: interrupting a function of the at least a portion of the active circuitry while the obstructive element is peeled off the semiconductor element.

33. The bonded structure of claim 32, wherein the obstructive material is positioned at a distance of less than 10 microns from the bonding interface.

34. The bonded structure of claim 32 wherein said barrier material is positioned at a distance of less than 5 microns from said bonding interface.

35. The joined structure according to claim 32, wherein the obstructive material comprises a destructive material having a hardness in a range of 20GPa to 150 GPa.

36. The bonded structure of claim 32, wherein said obstructive material comprises a destructive material having a hardness of at least 80 GPa.

37. The bonded structure of claim 32, wherein the semiconductor element comprises a first bonding layer, and wherein the obstructive element comprises a second bonding layer directly bonded to the first bonding layer without an adhesive.

38. The bonded structure of claim 37, wherein the first bonding layer comprises a first material and the etch path also comprises the first material.

39. The bonded structure of claim 38, wherein the first material comprises silicon oxide.

40. The bonded structure of claim 39, wherein the first bonding layer further comprises one or more of fluorine and nitrogen.

41. The bonded structure of claim 37, further comprising one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers including circuitry, the etch path extending through at least a portion of the one or more intermediate layers.

42. The bonded structure of claim 41, wherein the one or more intermediate layers comprise a barrier layer, one or more openings are formed in the barrier layer, and the etch path extends through the one or more openings.

43. The bonded structure of claim 42, wherein the barrier layer comprises silicon nitride.

44. The bonded structure of claim 42, wherein one or more openings or partial openings in the barrier layer comprise the material of the bonding interface.

45. The bonded structure of claim 42, further comprising a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer.

46. The bonded structure of claim 32, further comprising a cavity in the one or more intermediate layers.

47. The bonding structure of claim 37, further comprising a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads.

48. The bonding structure of claim 47, wherein at least two or more of the second plurality of contact pads are electrically connected.

49. The bonded structure of claim 47 further comprising a first barrier layer in the first bonding layer and a layer of anchor material in the second bonding layer, the first barrier layer having one or more openings therethrough.

50. The bonding structure of claim 49, wherein the second plurality of contact pads are at least partially embedded in the layer of anchoring material.

51. The bonding structure of claim 47 wherein at least one contact pad is connected to a monitoring circuit to monitor connectivity of the first and second pluralities of contact pads that are directly bonded.

52. The bonding structure of claim 32, wherein the obstructive material is patterned to expose portions of the semiconductor element, the etch path extending through the exposed portions.

53. A joining structure comprising:

a semiconductor element including an active circuitry;

an obstructive element bonded directly to the semiconductor element without adhesive, the obstructive element comprising an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry; and

a conductor connected to one or both of the semiconductor element and the obstructive element, the conductor configured to detect whether the obstructive element has been peeled off the semiconductor element.

54. The bonded structure of claim 53, wherein the semiconductor element comprises a first bonding layer, and wherein the obstructive element comprises a second bonding layer directly bonded to the first bonding layer without an adhesive.

55. The bonded structure of claim 54, wherein the first bonding layer and the second bonding layer comprise silicon oxide.

56. The bonded structure of claim 54, further comprising one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers including circuitry, the etch path extending through at least a portion of the one or more intermediate layers.

57. The bonded structure of claim 56, wherein the one or more intermediate layers comprise a barrier layer in which one or more openings are formed, the etch path extending through the one or more openings.

58. The joining structure of claim 56, wherein the conductor is at least partially disposed in the one or more intermediate layers.

59. The bonding structure of claim 56, further comprising a monitoring circuit configured to monitor current through the conductor to determine whether the obstructive element has been peeled away from the semiconductor element.

60. The bonding structure of claim 59, wherein the monitoring circuit is configured to: indicating that the obstructive element has been peeled away from the semiconductor element if the electrical signal through the conductor is interrupted.

61. The bonded structure of claim 54, further comprising a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads without an adhesive.

62. The bonded structure of claim 61 further comprising a first barrier layer in the first bonding layer and a layer of anchor material in the second bonding layer, the first barrier layer having one or more openings therethrough.

63. The bonded structure of claim 62, wherein the second plurality of contact pads are at least partially embedded in the second barrier layer.

64. The bonding structure of claim 61, wherein at least one contact pad is connected to a monitoring circuit to monitor connectivity of the first and second pluralities of contact pads that are directly bonded.

65. The bonding structure of claim 53, wherein a first hardness of the obstructive material is greater than a second hardness of the semiconductor element.

66. The joining structure of claim 53, wherein said obstructive material comprises an abrasive material.

67. The joinder structure of claim 53, wherein the obstructive material comprises a light blocking material.

68. The joined structure of claim 67, wherein the light blocking material is configured to block light of Near Infrared (NIR) wavelengths.

69. A method of forming a bonded structure, the method comprising:

patterning an interrupting structure into at least one of a semiconductor element having active circuitry and an obstructive element comprising an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry;

bonding the obstructive element directly to the semiconductor element without an adhesive, the peel-interrupt structure configured to: once the obstructive element is peeled off from the semiconductor element, the function of the semiconductor element is interrupted.

70. The method of claim 69 further comprising depositing a first bonding layer on the semiconductor element and depositing a second bonding layer on the obstructive element, the method comprising directly bonding the first bonding layer and the second bonding layer without an adhesive.

71. The method of claim 70, further comprising forming a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising a same material as the first bonding layer.

72. The method of claim 70, further comprising directly bonding a first plurality of contact pads in the first bonding layer to a second plurality of contact pads in the second bonding layer.

73. The method of claim 72, further comprising forming a first barrier layer in the first bonding layer, the first barrier layer having one or more openings therethrough, and forming a layer of anchor material in the second bonding layer.

74. The method of claim 69, wherein patterning the interrupted structure comprises patterning an opening through one or more barrier layers within one or more intermediate layers.

75. The method of claim 69, further comprising patterning an opening in the obstructive material to expose a portion of the semiconductor element.

76. The method of claim 69, further comprising monitoring an electrical signal along a conductor at least partially disposed in one or both of the semiconductor element and the obstructive element to determine whether the obstructive element has peeled away from the semiconductor element.

Technical Field

The field relates to protective or blocking elements for bonded structures, and in particular to interrupting structures configured to interrupt the function of active circuitry upon subtractive or reverse engineering of the protective elements.

Background

A semiconductor chip (e.g., an integrated device die) may include active circuitry with security-sensitive components that include valuable and/or proprietary information, structures, or devices. Such security-sensitive components may include, for example, intellectual property of the entity, software or hardware security (e.g., encryption) features, private data, or any other component or data that the entity may wish to remain secure and hidden from third parties. For example, third party malicious personnel may utilize various techniques to attempt to access the security-sensitive components to gain economic and/or geopolitical advantages. Accordingly, there remains a continuing need to improve the security of semiconductor chips from third party access.

Drawings

Fig. 1 shows a schematic side cross-sectional view including a protective element bonded (e.g., directly bonded) to a semiconductor element, and a possible chemical attack path for peeling or damaging sensitive circuitry.

Fig. 2A shows a schematic side cross-sectional view of a protective element.

Fig. 2B shows a schematic side cross-sectional view of the bonding structure in fig. 1 without showing a chemical attack path.

Fig. 2C is a top view of the bonding structure of fig. 2B.

Fig. 3 is a schematic side view of a protective element and a semiconductor element prior to bonding according to various embodiments.

Fig. 4 is a schematic side view of a protective element and a semiconductor element before bonding according to another embodiment.

Fig. 5A-5B show schematic side cross-sectional views of a joining structure according to various embodiments.

Fig. 6A is a schematic side cross-sectional view of a bonding structure according to another embodiment.

Fig. 6B is an enlarged view of a portion of the bonding structure shown in fig. 6A.

Fig. 7 is a schematic side cross-sectional view of a protective element according to various embodiments.

Fig. 8 is a schematic diagram of an electronic system including one or more engagement structures, according to an embodiment.

Detailed Description

As described herein, a third party (e.g., a third party malicious person) may attempt to access a security-sensitive component on an element, such as an integrated device die. In some elements, security sensitive components may be protected by a net list as well as non-volatile memory (NVM) data. However, a third party may attempt to hack into the security-sensitive component through a combination of destructive and non-destructive techniques, for example, probing and/or de-layering the element to expose or otherwise gain access to the security-sensitive component. In some cases, a third party may attempt to hack into a security-sensitive component by: the method includes the steps of pulsing Electromagnetic (EM) waves onto active circuitry of the component, using fault implantation techniques, near-infrared triggered or Focused Ion Beam (FIB) modification using circuitry, chemical etching techniques, and other physical, chemical and/or electromagnetic hacking tools and even reverse engineering. These techniques may be used to physically access sensitive circuitry of a microdevice, such as an integrated circuit, to directly read encrypted information, to trigger a circuit from outside to release information that is otherwise encrypted, to learn about the manufacturing process, or even to extract enough information to ultimately be able to replicate a sensitive design. For example, in some cases, an intruder may attempt to access an encryption key, which may be stored in the circuit design, in memory, or a combination of both. Techniques may also be used to indirectly read sensitive information by: the resulting output is analyzed based on the fault injection input and the encryption key or data content is determined by recursive analysis. It is challenging to structurally protect security sensitive components on a component.

It is therefore important to provide improved security for components (e.g., semiconductor integrated dies) that include security-sensitive components.

One way to physically protect the chip from such unauthorized access is to: providing materials that are difficult to remove or penetrate by grinding, polishing, chemical etching or by other techniques. However, some such materials (e.g., abrasive materials) may have too high a processing temperature to be applicable to the manufactured semiconductor devices, which have a tight thermal budget after the devices are manufactured. The processing of some materials may not be chemically compatible with typical semiconductor processing foundries. The obstructive material may not typically be used or found in standard semiconductor processing foundries, and/or the obstructive material may use non-standard processing.

The various embodiments disclosed herein may utilize a chip or chiplet having a protective element 3 (also referred to herein as a blocking element) that includes, for example, a security or blocking material 4, the security or blocking material 4 protecting the sensitive circuit area (also referred to herein as sensitive circuitry) to which it is bonded. Fig. 1 is a schematic side cross-sectional view of a bonding structure 1 comprising a protective element 3 bonded (e.g. directly bonded) to a semiconductor element 2, and a possible chemical supply path P for peeling or damaging sensitive circuitry. Fig. 2A is a schematic side sectional view of the protective element 3. Fig. 2B is a schematic side sectional view of the bonding structure 1 of fig. 1, without showing a chemical supply path. Fig. 2C is a top view of the bonding structure 1 of fig. 2B.

In some embodiments, the obstructive material 4 may comprise a physically destructive material (e.g., an abrasive and/or hard material) configured to: physically damaging or destroying the tool attempting to access sensitive circuitry 6, physically damaging or destroying sensitive circuitry 6 itself, or otherwise preventing physical or mechanical access to sensitive circuitry 6. In some embodiments, the obstructive material 4 may include a light blocking material configured to block incident electromagnetic radiation (e.g., infrared radiation, such as near infrared light) from entering the sensitivity circuitry 6.

In some embodiments, the obstructive material 4 may include a light blocking material that is also a destructive material, such that the obstructive material may prevent physical and electromagnetic access to the sensitive circuitry 6. In some embodiments, the obstructive material 4 may include a light blocking material that is also not a destructive material. In other embodiments, the obstructive material 4 may comprise a destructive material that is also not a light blocking material. In some embodiments, the obstructive material 4 may include light scattering, light diffusing, or light filtering material.

In embodiments utilizing a destructive material for the obstructive material 4, the obstructive material 4 may include, for example, a diamond-based material such as synthetic diamond, diamond-like carbon, or industrial diamond, tungsten, synthetic fibers, carbides (e.g., silicon carbide, tungsten carbide, boron carbide), borides (e.g., tungsten boride, rhenium boride, boron aluminum boride, etc.), boron nitride, nitrogen carbide, sapphire, and certain types of ceramics and other suitable destructive materials or combinations of materials, may be disposed adjacent to the bonding interface 8. In some embodiments, particles of these destructive materials may be dispersed into the mixture to form the obstructive material 4. In various embodiments, the obstructive material 4 may be an unpatterned and/or blanket material layer as compared to a patterned layer. For example, the barrier layer 4 may comprise a covering over the entire protective element 3, or a covering over the sensitive area 6 of the circuitry to be protected. A bonding layer 5 (e.g., a semiconductor material or an inorganic dielectric) may be disposed over the capping layer of the obstructive material 4. As explained herein, the obstructive material 4 may be bonded directly to the semiconductor element 2 without an adhesive to form the bonded structure 1 in a different arrangement. As explained herein, the semiconductor elements 2 may include any suitable type of semiconductor element, such as an integrated device die, an interposer, a semiconductor wafer, a reconstituted wafer, or the like. The selected obstructive material 4 may have a high shear modulus, a high bulk modulus, and may not exhibit plastic deformation. For example, a material having a hardness of at least 80GPa (e.g., as measured on the vickers hardness scale) may be used for the destructive material. In various embodiments, the destructive material may have a hardness of at least 12GPa, at least 13GPa, at least 15GPa, at least 20GPa, at least 30GPa, or at least 50GPa, as measured on the vickers hardness scale. For example, the hardness of the destructive material may have a hardness in the range of 12.5Gpa to 150Gpa, in the range of 13Gpa to 150Gpa, in the range of 15Gpa to 150Gpa, in the range of 20Gpa to 150Gpa, in the range of 40Gpa to 150Gpa, or in the range of 80Gpa to 150Gpa, as measured on the vickers hardness scale. In another embodiment, the abrasive or destructive material may have a higher hardness than typical materials used in semiconductor chips. For example, the destructive material may have a hardness that is higher than the hardness of Si, SiO, SiN, SiON, SiCN, or the like. In some embodiments, the obstructive material 4 may comprise one or more materials or layers deposited on top of each other. Further, the barrier material 4 may comprise a continuous, non-continuous, or patterned layer, or the barrier material 4 may comprise some such continuous, non-continuous, or patterned layer. In some embodiments, there may not be any circuitry or wiring within the obstructive material 4. In other embodiments, the obstructive material 4 may include circuitry embedded in the material 4, or conductive vias that partially or completely penetrate the obstructive material 4.

The obstructive or protective elements 3 (e.g., chips or chiplets) can be bonded directly (e.g., using dielectric-to-dielectric bonding techniques, such as Xperi, san jose, caTechnology) to at least a sensitive area 6 (e.g., an area including security sensitive components) of an element 2, such as a semiconductor chip, which element 2 may benefit from a high degree of security protection against third party tampering. For example, the dielectric-to-dielectric connection may be formed without an adhesive using at least the direct bonding techniques disclosed in U.S. patent nos. 9,391,143 and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. After the protective element 3 is directly bonded or hybrid bonded to the element 2 (e.g., a semiconductor chip or an integrated device die), one or more layers of the obstructive material 4 (which may include a destructive or abrasive material, a light blocking material, a light scattering material, a light filtering material, or a light diffusing material, etc.) may be positioned proximate to the bonding interface 8, e.g., as close as possible to the bonding interface 8. In one embodiment, the obstructive material 4 may be located less than 50 microns from the bonding interface 8, less than 25 microns from the bonding interface 8, or less than 10 microns from the bonding interface 8, such as less than 5 microns from the bonding interface 8. In various embodiments, the obstructive material 4 may be located withinIn a range of about 1 micron to about 10 microns, or about 1 micron to about 5 microns from the bonding interface 8. In other embodiments, two or more obstructive or protective elements 3 are bonded directly to the element 2.

In various embodiments, the direct bond structure may be formed directly without the use of an intermediate bond. For example, the protective element 3 and the semiconductor element 2 may each have a bonding layer (e.g., bonding layer 5) associated with the dielectric bonding surfaces 9, 10. The respective dielectric joint surfaces 9, 10 in the protective element 3 and the semiconductor element 2 may be polished to a high degree of smoothness. The respective bonding surfaces 9, 10 may be cleaned and exposed to plasma and/or suitable chemicals (e.g. etchants) to activate the surfaces. In some embodiments, the surfaces 9, 10 may terminate in a substance after activation or during activation (e.g., during plasma and/or chemical processes). In various embodiments, the termination species may include nitrogen. Furthermore, in some embodiments, the joining surfaces 9, 10 may be exposed to fluorine. For example, one or more fluorine peaks may be present near the layer and/or the bonding interface 8. Thus, in the directly bonded structure 1 disclosed herein, the bonding interface 8 between the two dielectric materials may include a smooth interface with a high nitrogen content and/or a fluorine peak at the bonding interface 8.

In various embodiments, the direct bonding of the separately fabricated protective element 3 facilitates the use of separate processes that are difficult to apply directly to the fabricated integrated circuit or sensitive microelectronic element due to thermal budget, chemical compatibility constraints, or other technical reasons. For example, the obstructive material 4 may be formed on the individual protective elements 3 at a higher temperature than the direct bonding temperature. The direct bonding process itself consumes relatively little thermal budget, including room temperature initial covalent bonding between dielectric bonding layers and possible annealing to enhance bonding and/or facilitate metallic bonding in a hybrid bonding process.

In some embodiments, if a third party attempts to remove destructive materials (e.g., abrasive materials and/or hard materials), the removal tool may be damaged (by abrasive material obstructive materials) and/or the underlying active circuitry removed in an attempt to damage. The obstructive material 4 may be "destructive" to the removal tool or the protected circuit. Either result can introduce significant resistance to: complete reverse engineering, hacking, inspection, or other breach of a secure area, circuitry, or device.

In some embodiments, the obstructive material 4 may include an abrasive and/or destructive layer on the chiplet. Additionally or alternatively, the chiplets themselves can include abrasive and/or destructive materials, and/or hard materials. Multiple abrasive and/or destructive materials may be incorporated in multiple layers or patterns within a layer to enhance the destructive effect. As explained above, the destructive material (e.g., abrasive and/or hard material) may be in close proximity to the faying interface 8. For example, the destructive material may be located within 5 microns of the bonding interface 8. A third party may attempt to etch or grind away the protective chiplets. If the destructive material is in close proximity to the bonding interface 8 between the protective element (chiplet) and the semiconductor element 2, the process of removing or grinding away the chiplet can become very difficult.

In various embodiments, as described above, the obstructive material 4 may alternatively or additionally include a light blocking material configured to block light, and/or an electromagnetic absorbing or dissipating material configured to block electromagnetic waves. For example, the obstructive material 4 may be selected to block light having a wavelength in the range of 700nm to 1mm, in the range of 750nm to 2500nm, or in the range of 800nm to 2500 nm. The obstructing material 4 may alternatively or additionally be selected or shaped to scatter incident light. The obstructive material 4 may alternatively or additionally be electrically conductive and may effectively act as an electromagnetic shield. The obstructive material 4 may additionally or alternatively absorb electromagnetic waves. In various embodiments, the obstructive material 4 may be selected to block Near Infrared (NIR) and Focused Ion Beam (FIB) fault intrusion attempts. In another embodiment, the obstructive material 4 may include or may be deposited with one or more optical or infrared filter layers. Thin film optical filters can be used to filter out or modify the illuminated optical or IR light passing through them in either direction, e.g., light incident over or emitted from the circuitry to trigger a response.

In some embodiments, a portion of the secure structure or circuit to be protected may be shared between the protective element 3 (e.g., a chiplet having abrasive and/or destructive materials) and the element 2 to be protected (e.g., an integrated device die having a secure active area). For example, a hybrid joining structure may be used to provide conductor-to-conductor direct joining along a joining interface 8, the joining interface 8 comprising a dielectric-to-dielectric surface 9, 10 that is covalently direct joined. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and dielectric-to-dielectric bonds may be formed using direct bonding techniques disclosed in at least U.S. patents 9,716,033 and 9,852,988, each of which is incorporated herein by reference in its entirety and for all purposes.

For example, the direct-bonding surfaces 9, 10 may be prepared and may be directly bonded to each other without an adhesive. The conductive connection pads (which may be surrounded by non-conductive dielectric field areas) may also be directly bonded to each other without adhesive. For example, in some embodiments, the individual connection pads may be flush with the surface 9, 10 of the dielectric, or recessed below the dielectric field region, for example in the range of 1nm to 20nm, or in the range of 4nm to 10 nm. In some embodiments, the bonding surfaces 9, 10 of the dielectric field regions may be bonded directly to each other without adhesive at room temperature, and subsequently, the bonded structure 1 may be annealed. Upon annealing, the contact pads may expand and contact each other to form a metal-to-metal direct bond.

Additional details of the protective element 3 with the obstructive material 4 may be found throughout U.S. provisional patent application nos. 62/833,491 ("the 491 application") and 62/953,058 ("the 058 application"), which are incorporated herein by reference in their entirety and for all purposes. The embodiments disclosed herein may be used in conjunction with any of the embodiments disclosed in the 491 application and the 058 application.

As shown in fig. 1 and 2A-2C, the bonding structure 1 may include a protective element 3, the protective element 3 being bonded directly to the semiconductor element 2 without adhesive over the sensitive active circuitry 6 along the bonding interface 8. In fig. 1 and 2C, the semiconductor element 2 may be directly electrically connected to a carrier 32 (such as a package substrate) by one or more bond wires 34. In other embodiments, the semiconductor element 2 may be mounted to the carrier 32 by solder balls in a flip-chip arrangement. In the illustrated embodiment, the carrier 32 includes a package substrate, such as a printed circuit board, a lead substrate, a ceramic substrate, or the like. In other embodiments, carrier 32 may comprise an integrated circuit die, an interposer, a reconstituted wafer, or any other possible device.

In fig. 2A, the protective element 3 includes a semiconductor (e.g., silicon) base or substrate 7 (also referred to herein as a handle). In other embodiments, the substrate 7 for the security chiplet need not be a semiconductor because it serves primarily as a handle for the obstructive material 4 and the bonding layer 5, as described herein, and can be replaced with other materials, such as glass or quartz. However, the semiconductor substrate is provided in a form convenient for processing and handling using existing equipment, and also has sufficient flatness and smoothness to simplify subsequent polishing of the bonding layer 5.

The protective element 3 may include an obstructive material 4 (as a layer on the substrate or substrates) on a substrate 7, the obstructive material 4 including a destructive material (e.g., abrasive and/or hard materials), a light or electromagnetic wave blocking material, a conductive material, a light filtering or scattering material, etc., and may have more than one of the properties described herein. As described herein, the protective element 3 may prevent external access to the security sensitive circuitry 6. As described above, the obstructive material 4 may include abrasive and/or destructive materials (e.g., materials having a high mechanical hardness compared to materials typically used in semiconductor manufacturing, such as silicon, silicon dioxide, aluminum, and copper).

In various embodiments, the obstructive material 4 may additionally or alternatively be selected to block impinging electromagnetic radiation. The obstructive material 4 may comprise, for example, a ceramic material, a composite material, diamond, tungsten, a combination of tungsten and diamond, or any other suitable type of obstructive material that may prevent external access to active circuitry on the semiconductor element 2 to which the protective element 3 is bonded 2. In various embodiments, the obstructive material 4 may comprise a material for which a selective etchant may not be available to remove the blocking material 4 without removing inorganic dielectrics common to semiconductor manufacturing.

The obstructive material 4 may be manufactured and assembled to the handle or substrate 7 in the first facility at one or more process temperatures. For example, the barrier material 4 may be deposited on the handle or substrate 7 at a temperature of at least 400 ℃, or at least 800 ℃ (e.g., in the range of 400 ℃ to at least 1000 ℃). Such high processing temperatures may not be suitable for foundries, such as wafers or integrated device dies, used for manufacturing the semiconductor element 2 (which should not be exposed to temperatures above 300 c or 400 c for a long time after manufacture), since such high temperatures may damage the active circuitry 6 and other components of the semiconductor element 2. In some cases, the material used for the barrier layer may be incompatible with the semiconductor fabrication facility due to contamination considerations.

As shown in fig. 2A, a bonding layer 5 may be disposed on the obstructive material 4. Bonding layer 5 may comprise any suitable type of non-conductive or dielectric material, particularly inorganic dielectrics compatible with integrated circuit fabrication, such as silicon dioxide, nitrogen suicide, and the like. In some embodiments, the bonding layer 11 may also be provided on the semiconductor element 2. The bonding layer 5 (e.g., silicon oxide) may be thin such that the layer 5 is unable to sufficiently protect or shield the secure circuitry 6 from third parties accessing itself. As shown in fig. 2B, the protective element 3 may be bonded directly to the semiconductor element 2 along the bonding interface 8 without an adhesive. The respective bonding layers 5, 11 may be prepared for bonding as described herein. For example, the bonding layers 5, 11 may have bonding surfaces 9, 10, the bonding surfaces 9, 10 being planarized to a high surface smoothness and exposed to a termination process (e.g., a nitrogen termination process). The bonding layers 5, 11 of the protective element 3 and the semiconductor element 2 may be brought into contact with each other at room temperature, and no adhesive or voltage is applied. The bonding layers 5, 11 may form a strong covalent bond along the bonding interface 8. Strong covalent bonding may be sufficient for processing and even for post-bonding processing, such as grinding, polishing or otherwise thinning the substrate, singulation, etc.), but post-bonding annealing may further enhance the strength of the bond.

Although the protective element 3 may block external access to the sensitive circuitry 6, a third party may attempt to access the security sensitive active circuitry 6 by removing the protective element 3 from the semiconductor element 2 to expose the active circuitry 6. For example, as shown in fig. 1, a third party may attempt to peel the protective element 3 off the semiconductor element by supplying an etchant along the chemical attack path P. Various embodiments described herein relate to the following apparatus and methods: is configured to prevent or deter third parties from removing or otherwise disrupting the function of the protective element 3 and the sensitive circuitry below. The deterrence may take the form of a combination of configurations to destroy the functionality of the sensitive circuitry 6 upon removal of the protective element 3, thereby preventing meaningful access to the sensitive circuitry 6 by third parties.

Fig. 3 is a schematic side view of a protective element 3 and a semiconductor element 2 according to various embodiments before bonding. Semiconductor component 2 may include a bulk substrate region 22, one or more intermediate layers 21, and one or more upper layers that define or include sensitive circuitry 6, with sensitive circuitry 6 including, for example, power grid region 20. Sensitive circuitry 6 (e.g., power grid area 20) may be defined at or near the upper bonding layer 11 of semiconductor element 2. In various embodiments disclosed herein, the bonding structure 1 may be designed to match the dielectric material of the dielectric bonding layer 5 of the protective element 3 with an upper layer of the semiconductor element 2 (e.g., an integrated device die, such as a logic die), the bonding structure 1 including the upper bonding layer 11 of the semiconductor element 2 and a layer below the bonding layer 11 that includes portions of the sensitive circuitry 6. The matching dielectric bonding layers 5, 11 may be compromised with upper layers (e.g., upper logic layers or power grid areas 20) of the matching semiconductor element 2 (e.g., integrated device die) such that chemical etch attacks against the direct bonding interface 8 also attack and destroy the power grid areas 20 and/or logic circuits in the sensitive area 6 of the semiconductor element 2. For example, the semiconductor element 2 may have a silicon oxide-based only material surrounding the metal in the upper metallization layer. The barrier and/or etch stop material (e.g., SiN, SiC, SiOC, SiON, etc.) may be absent or may be replaced by other materials that are sensitive to etchants that may otherwise selectively remove oxides (such as differently doped silicon oxides) or other materials used to bond the layers 5, 11. Although various embodiments describe the bonding layers 5, 11 as comprising silicon oxide or silicon oxide based materials for the bonding surfaces 9, 10, any other suitable material (e.g. SiN) may be used for the bonding layers 5, 11.

In various embodiments, the power grid area 20 may be at least partially disposed on an adjacent protective element 3 such that if the protective element 3 is removed, the power grid area 20 (and/or other sensitive circuitry 6) may be non-functional. As shown in fig. 3, in some embodiments, the bonding layer 5 of the protective element 3 and the upper layer (e.g., power grid region 20) of the semiconductor element 2 may comprise the same material, e.g., silicon oxide in some embodiments. As described above, these layers 5, 11 may include features prepared for direct bonding, such as a significant spike in fluorine concentration at the oxide interface, and/or a nitrogen spike at the bonding interface 8. In this arrangement, if a third party attempts to remove the protective element 3 from the semiconductor element 2 by selectively etching the material of the bonding layers 5, 11, the etchant may also damage the upper metallization layer (power grid layer or region 20) of the semiconductor element 2, thereby damaging the sensitive region 6 and preventing external access thereto. Thus, the provision of sensitive circuitry 6 (e.g., power mesh region 20) at or near the upper bonding layer 11 of the semiconductor element 2 may be used as an interruption structure 30, which interruption structure 30 may be configured to interrupt the function of the circuitry 6 once the protective element 3 is peeled off from the semiconductor element 2. As explained herein, matching the materials of the dielectric bonding layers 5, 11 may provide an etch path that can interrupt the function of the circuitry 6 upon peeling or other interruption. The interrupt structure 30 described herein may interrupt sensitive active circuitry 6 that includes one or more active devices (e.g., transistors and other active circuitry), as well as local interconnects and wiring (e.g., back end wiring) connected to the active devices.

In some embodiments, conductive signal traces 23 may be provided through the sensitive circuit area 6 (e.g., power grid area 20). The conductive trace 23 may be configured to detect whether the protective element 3 has been peeled off from the semiconductor element 2. For example, the conductive traces 23 may be connected to other circuitry (e.g., monitoring circuitry 24) that may monitor the impedance to determine if the direct bond is compromised. If the protective element 3 is removed from the semiconductor element 2, the removal may trigger a signal along the trace 23 (e.g., detected by a change in impedance, current, voltage, etc.) indicating the removal. The monitoring circuit 24 may be formed in the protective element 3 or the semiconductor element 2, or may scan both the protective element 3 and the semiconductor element 2. In such embodiments, the monitoring circuitry 24 may be disposed in the bulk substrate region 22.

Fig. 4 is a schematic side view of the protective element 3 and the semiconductor element 2 before bonding according to another embodiment. Unless otherwise indicated, the components of fig. 4 may be the same or substantially similar to like-numbered components in fig. 1-3. In fig. 4, the semiconductor element 2 may include one or more intermediate layers 21, e.g., one or more interlayer dielectric materials (ILDs), under the upper bonding layer. The intermediate layer 21 may include one or more barrier layers 26 between dielectric wiring or circuit layers 27. The barrier layer 26 may, for example, act as an etch stop layer for a CMP stop layer and/or a barrier layer of the semiconductor element 2 to be protected. The layers of alternating dielectric barrier layers 26 (e.g., barrier layers) and wiring layers 27 may comprise silicon nitride in some arrangements. Other examples of barrier layers 26 include SiC, SiON, SiOC, and the like. These barrier layers may effectively act as barrier layers selected for the etchant used by the third party to remove the protective elements 3. As shown in fig. 4, one or more openings 25 may be provided in the intermediate layer 21 (e.g., through the barrier layer 26) to create an etch path 28 through the upper layer 11 and through at least a portion of the intermediate layer 21. The opening 25 in the barrier layer 26 may be used to damage the sensitive circuitry 6 of the semiconductor element 2 if a third party attempts to remove the protective element 3 by etching. The sensitive circuitry 6 may be arranged in one or more intermediate layers 21 and/or semiconductor regions 22.

Thus, in various embodiments, the interrupt structure 30 may be provided as: once the protective element 3 is peeled off from the semiconductor element 2, the function of at least a part of the sensitive active circuitry 6 (including the active devices and/or the interconnects or wiring structures connected to the active devices) is interrupted. In various arrangements, the interruption structure 30 may comprise an etch path 28 through a portion of the semiconductor element 2. Beneficially, if a third party attempts to strip the protective element 3 by etching, the etch path 28 may cause the chemical etchant to destroy or damage the circuitry 6 in the semiconductor element 2. In some arrangements, one or more barrier layers 26 (e.g., silicon nitride) may be present in the semiconductor element 2. These barrier layers 26 are typically present in integrated circuit metallization stacks and can be used, for example, as etch stops or CMP stops during processing of metallization or back end of line (BEOL) structures, and/or as diffusion barriers to prevent migration of metal into surrounding interlayer dielectrics (ILDs, typically in the form of silicon oxide). The barrier layer 26 may also incidentally protect the underlying interconnect pattern (e.g., power grid area 20) as well as the underlying circuitry 6 during the selective etching of the bonding layers 5, 11 that bond the protective element 3 to the sensitive circuitry 6. Thus, openings 25 may be selectively provided in the barrier layer 26 to create etch paths 28 in the lower or intermediate layer 21 of the semiconductor element 2 in the event of a chemical attack on the bonding layer 5, 11 (e.g. silicon oxide). Such an etching path 28 may destroy or disable the underlying circuitry 6 of the semiconductor element 2, for example the power grid area 20 of the semiconductor element 2. In such an embodiment, the semiconductor element 2 may be modified in combination with the addition of the protection element 3. The opening 25 in the barrier layer 26 may have a width in the range of 2 μm to 3 mm. For example, in various embodiments, the opening 25 may have a width in the following range: 1 μm to 100 μm, 100 μm to 1mm, or 1mm to 3 mm.

In various embodiments, a trench (not shown in fig. 4) may be provided along an edge of the semiconductor element 2 (e.g., die) to allow any etchant used to strip the protective element 3 to attack the underlying layers of the semiconductor element 2. Although trenches may be used in some arrangements, other patterns that create cavities or voids may also be suitable.

In some embodiments, as described above, the traces 23 may be disposed in the power grid area 20 of the semiconductor element 2. The trace 23 may be used to monitor the impedance or other electrical characteristic of the circuitry 6 by monitoring circuitry 24. The removal of the dielectric bonding layer 11 of the semiconductor element may cause a significant increase in the impedance, thereby indicating that a third party may tamper with the bonding structure 1. For example, traces 23 may comprise jumper traces in power grid area 20 that sag if dielectric bonding layer 11 of semiconductor element 2 is removed or separated from protective element 3.

In various embodiments, the monitoring circuit 24 may be provided on one or both of the protective element 3 and the semiconductor element 2. For example, in some embodiments, the monitoring circuit 24 may be provided on the semiconductor element 2. The joint structure 1 may also comprise a structure with a large number of conductive interconnections to the grid, which will be cut if the protective element 3 is removed. It is not practical to reconnect such a large number of interconnects to the grid with a post-peel attachment. The monitoring circuit 24 may be configured to electrically disable the sensitive circuitry 6 if any tamper indication is detected.

Fig. 5A-5B illustrate schematic side cross-sectional views of a joining structure 1 according to various embodiments, and unless otherwise indicated, the components of fig. 5A-5B may be the same or substantially similar to like-numbered components in fig. 1-4. In fig. 5A-5B, one or more cavities 29 may be provided in the upper dielectric layer of the semiconductor element. For example, as shown in fig. 5A to 5B, a cavity 29 may be formed in the bonding layer 11 and the one or more intermediate layers 21 of the semiconductor element 2. Similar to the openings 25 in fig. 4, one or more of the cavities 29 in fig. 5A-5B may similarly provide an interruption structure 30 comprising an etched path 28 to enable etchant to penetrate the intermediate and underlying layers of the semiconductor element 2 to interrupt the function of the security sensitive circuitry 6 (including the active devices and or wiring structures interconnecting or connecting to the active devices) once the protective element 3 is stripped from the semiconductor element 2. For example, in fig. 5A, a cavity 29 on the right side of the structure 1 may provide a vertical path 31 through the bonding layer 11 of the semiconductor element 2 to the intermediate layer 21. Lateral channels 32 may connect this vertical path 31 to other cavities 33 of the intermediate layer 21, providing a network of voids or cavities 29 to provide ready access to any lift-off etchant across the semiconductor element 2 and through the intermediate layer 21. Known methods can form the cavities 29 and possibly the microchannels interconnecting them. The cavity 29 may have dimensions in the range of 1 micron to 3 microns in length, width, and height. For example, in various embodiments, the cavity 29 may have dimensions with a length, width, and height in a range of 1 micron to 100 microns, in a range of 100 microns to 1mm, or in a range of 1mm to 3 mm.

Fig. 6A is a schematic side sectional view of a bonding structure 1 according to another embodiment. Fig. 6B is an enlarged view of a part of the bonding structure 1 shown in fig. 6A. Unless otherwise indicated, the components of fig. 6A-6B may be the same or substantially similar to like-numbered components in fig. 1-5B. In various embodiments, the direct bonding layer 5 and the conductive contact pads 40 of the protective element 3 may be directly bonded to the corresponding dielectric bonding layer 11 and the corresponding conductive contacts 42 of the semiconductor element 2 without an adhesive. With this arrangement, the directly bonded conductive contacts 40,42 can be used to monitor the connectivity between the protective element 3 and the semiconductor element 2 as an indicator of tampering or peel attempts. Multiple conductive contacts 40,42 may be used, but in some arrangements, only a portion of the contacts may complete the connection, while the other contacts create an electrical short.

In some embodiments utilizing a dielectric as well as a conductive direct bond (e.g., a direct bond interconnect, or DBI, connection), if the dielectric bonding layer 5 and/or 11 (e.g., oxide) is removed and the protective element 3 is detached from the semiconductor element 3, such removal will result in a defect (e.g., a short circuit at the power grid area 20). For example, the etch-resistant material will be embedded in a portion of the conductors (e.g., contact pads 40) in the protective element 3 such that the conductors remain connected to the protective element 3 even after the selective etching of the bonding layers 5 and/or 11. Non-limiting examples of etch-resistant materials include silicon nitride, which is resistant to selectively etching the silicon oxide bonding layer. Various embodiments may not utilize chain connections on the dummy die.

As shown in fig. 6A and 6B, in some embodiments, the dielectric bonding layers 5 and the conductive contact pads 40 of the protective element 3 may be bonded directly to the respective dielectric bonding layers 11 and the respective conductive contact pads 42 of the semiconductor element 2 without an adhesive, in a hybrid direct bonding process, such as direct bonding interconnection or commercially available from Xperi corporation of san joseAnd (5) processing. As described above, the dielectric bonding layer 5 and/or 11 can be selectively etched by a third party using an etchant that can remove the protective element 3 from the semiconductor element 2. However, removal of the protective element 3 can destroy the underlying sensitive circuitry 6 by debonding the conductive vias and traces from the semiconductor element 2.

As shown in fig. 6A-6B, in some embodiments, a barrier layer 41 (e.g., silicon nitride) may be used in the protective element 3 and the semiconductor element 2 as a barrier to prevent release of metal in the protective element 3 during lift-off attempts. Barrier layer 41 may be thicker than conventional etch stop layers (e.g., in the range of 250nm to 400 nm) and may be used as a layer of anchor material to anchor contact pads 40,42 to the underlying sensitive circuitry 6 (via other internal traces and connections 43). In some embodiments, a continuous barrier or anchoring layer 41 (which may comprise one or more layers) may be provided on the protective element 3 to complicate the peeling work. In other embodiments, barrier material 41 may be provided as a multi-layer dielectric ring to complicate peeling and die separation. Even if the bonding layers 5, 11 are selectively removed, the contact pads 40,42 (e.g. metal) of the protective element 3 and the semiconductor element 2 to be protected remain connected and intact, so that the separation of the elements 3, 2 will cause physical damage to the semiconductor element 2. For example, even if the dielectric bonding layers 5, 11 are etched away, the direct bonding connection between the contact pads 40,42 and protected by the barrier layer 41 may remain intact, which may result in tearing and destruction of circuitry connected to the contact pads 40,42 in the bottom layer 21 and the region 22. For example, connections 43 may be bonded directly to bond pads 40,42 to wiring and circuitry in layer 21 and/or to the sensitive circuitry itself. Furthermore, as in the embodiment disclosed above in connection with fig. 4, in the lower semiconductor element 2, openings in the anchor layer 41 and/or the barrier material 26 (e.g. the shown thick barrier layer protecting the metal of the semiconductor element 2, and/or an etch stop, CMP stop or barrier layer) may be provided around the sensitive region 6 of the semiconductor element 2. Such openings 25 may form an etching path to enable an etchant to reach the underlying layers of semiconductor element 2 and damage security sensitive circuitry 6 and/or wiring connected to sensitive circuitry 6.

Fig. 7 shows another example of the interruption structure 30. Unless otherwise indicated, the components of fig. 7 may be the same or substantially similar to like-numbered components in fig. 1-6B. In fig. 7, the barrier material 4 of the protective element 3 may be patterned to make delamination and peeling more difficult or uncontrollable. For example, vias or paths (e.g., openings) 45 through the insulative material may be provided to be filled with a dielectric material 46 (e.g., silicon oxide). Path 45 may include an over-etched via, an under-etched via, a through via, a partial via, a blind via, or the like, as shown in FIG. 7. Vias or paths 46 through the insulative material 4 can make stripping more challenging by complicating the stripping path without causing disabling damage to the semiconductor element 2 and its protected sensitive circuitry 6. For example, the openings 46 may allow an etchant or plasma to etch faster through the openings 46 (or portions of the openings), which may damage underlying circuitry, while the etchant or plasma is attempting to remove the other obstructive material 4.

Fig. 8 is a schematic diagram of an electronic system 80 including one or more joining structures 1, according to various embodiments. The system 80 may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet device, a laptop, etc.), a desktop computer, an automobile or component thereof, a stereo system, a relying device, a camera, or any other suitable type of system. In some embodiments, electronic system 80 may include a microprocessor, a graphics processor, an electronic recording device, or digital memory. The system 80 may include one or more device packages 82 mechanically and electrically connected to the system 80 (e.g., by way of one or more reticles). Each package 82 may include one or more bonding structures 1,. The package 82 may be similar or identical to the package 30 described herein. The system 80 shown in fig. 8 may include any of the engagement structures 1 and associated protective elements 3 shown and described herein.

In one embodiment, a joint structure is disclosed. The bonding structure may include a semiconductor element including active circuitry. The bonding structure may include an obstructive element bonded directly to the semiconductor element along the bonding interface without an adhesive, the obstructive element including at least a portion of an obstructive material disposed over the active circuitry, the obstructive material configured to block external access to the active circuitry. The bonding structure may include an interruption structure configured to interrupt a function of at least a portion of the active circuitry upon peeling the obstructive element from the semiconductor element.

In some embodiments, the obstructive material may be positioned at a distance of less than 10 microns from the engagement interface. The obstructive material may be positioned at a distance of less than 5 microns from the bonding interface. The obstructive material may comprise a destructive material having a hardness in the range of 20GPa to 150 GPa. The obstructive material may comprise a destructive material having a hardness of at least 80 GPa. The interruption structure may comprise an etched path through a portion of the semiconductor element. The semiconductor element may include a first bonding layer, and wherein the obstructive element includes a second bonding layer directly bonded to the first bonding layer without an adhesive. The first bonding layer may include a first material and the etch path also includes the first material. The first material may include silicon oxide. The first bonding layer may further include one or more of fluorine and nitrogen. The interrupt structure may be configured to: upon being stripped from the selective etching in one or more of the first bonding layer and the second bonding layer, the function of at least a portion of the active circuitry is interrupted. The first bonding layer and the second bonding layer may include silicon oxide. The bonding structure may include one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers including the circuitry, the etch path extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, with the one or more openings formed in the barrier layer, blocking extension through the one or more openings. The one or more openings in the barrier layer may include a material of the first bonding layer. The barrier layer may comprise silicon nitride. The bonding structure may include a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers including the same material as the first bonding layer. The interruption structure may comprise a cavity within one or more intermediate layers. The bonding structure may include a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads. The bonding structure may include a first barrier layer in the first bonding layer having one or more openings therethrough and an anchor material layer in the second bonding layer. The second plurality of contact pads may be at least partially embedded in the layer of anchoring material. At least one contact pad may be connected to a monitoring circuit to monitor connectivity of the directly bonded first and second pluralities of contact pads. At least two or more of the second plurality of contact pads may be electrically connected. The bonded structure may include a back end of line (BEOL) layer that includes power circuitry in the obstructive elements. The interrupting structure may include a conductive trace configured to detect whether the obstructive material has been peeled away from the semiconductor element. The obstructive material may be patterned to expose portions of the semiconductor element through which the etch path extends. The first hardness of the obstructive material may be greater than the second hardness of the semiconductor element or the third hardness of the material at the bonding interface. The obstructive material may comprise an abrasive material. The obstructive material may include a light blocking material. The light blocking material may be configured to block light of a Near Infrared (NIR) wavelength. The obstructive material may comprise an optical or Infrared (IR) blocking or modifying material.

In another embodiment, a joining structure is disclosed. The bonding structure may include a semiconductor element including active circuitry. The bonding structure may include an obstructive element bonded directly to the semiconductor element along the bonding interface without adhesive, the obstructive element including an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry. The bonding structure may include an etch path through a portion of the semiconductor element, the etch path configured to: when the obstructive element is peeled off from the semiconductor element, the function of at least a part of the active circuitry is interrupted.

In some embodiments, the obstructive material is positioned a distance of 10 microns away from the engagement interface. The obstructive material may be positioned at a distance of less than 5 microns from the bonding interface. The obstructive material may comprise a destructive material having a hardness in the range of 20GPa to 150 GPa. The obstructive material may comprise a destructive material having a hardness of at least 80 GPa. The semiconductor element may include a first bonding layer and the obstructive element may include a second bonding layer directly bonded to the first bonding layer without an adhesive. The first bonding layer may include a first material and the etch path also includes the first material. The first material may include silicon oxide. The first bonding layer may include one or more of fluorine and nitrogen. One or more intermediate layers may be between the first bonding layer and the active circuitry, the one or more intermediate layers including circuitry, the etch path extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, the one or more openings formed in the barrier layer, the etch path extending through the one or more openings. The barrier layer may comprise silicon nitride. One or more openings or portions of openings in the barrier layer may include a material of the bonding interface. The plurality of dielectric layers may be separated by a plurality of barrier layers comprising the same material as the first bonding layer. The cavities may be in one or more intermediate layers. The first and second plurality of contact pads in the first bonding layer may be in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads. At least two or more of the second plurality of contact pads may be electrically connected. The first barrier layer may be in the first tie layer and the layer of anchor material may be in the second tie layer, the first barrier layer having one or more openings therethrough. The second plurality of contact pads may be at least partially embedded in the layer of anchoring material. At least one contact pad may be connected to a monitoring circuit to monitor connectivity of the directly bonded first and second pluralities of contact pads. The obstructive material may be patterned to expose portions of the semiconductor element through which the etch path extends.

In another embodiment, a joining structure is disclosed. The bonding structure may include a semiconductor element including active circuitry. The bonding structure may include an obstructive element directly bonded to the semiconductor element without an adhesive, the obstructive element including an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry. The bonding structure may include a conductor connected to one or both of the semiconductor element and the obstructive element, the conductor being configured to detect whether the obstructive element has been peeled away from the semiconductor element.

In some embodiments, the semiconductor element may include a first bonding layer and the obstructive element may include a second bonding layer directly bonded to the first bonding layer without an adhesive. The first bonding layer and the second bonding layer may include silicon oxide. One or more intermediate layers may be between the first bonding layer and the active circuitry, the one or more intermediate layers including circuitry, the etch path extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, one or more openings formed in the barrier layer, the etch path extending through the one or more openings. The conductors may be at least partially disposed in one or more intermediate layers. The monitoring circuit may be configured to monitor current through the conductor to determine whether the obstructive element has been peeled away from the semiconductor element. The monitoring circuit may be configured to: in the event that the electrical signal through the conductor is interrupted, it indicates that the obstructive component has been peeled away from the semiconductor component. The first plurality of contact pads may be in the first bonding layer and the second plurality of contact pads may be in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads without an adhesive. The first barrier layer may be in the first tie layer and the layer of anchor material may be in the second tie layer, the first barrier layer having one or more openings therethrough. The second plurality of contact pads may be at least partially embedded in the second barrier layer. At least one contact pad may be connected to a monitoring circuit to monitor connectivity of the directly bonded first and second pluralities of contact pads. The first hardness of the obstructive material may be greater than the second hardness of the semiconductor element. The obstructive material may comprise an abrasive material. The obstructive material may include a light blocking material. The light blocking material may be configured to block light of a Near Infrared (NIR) wavelength.

In another embodiment, a method of forming a bonded structure is disclosed. The method may include patterning an interruption structure into at least one of a semiconductor element having active circuitry and an obstructive element comprising an obstructive material disposed over at least a portion of the active circuitry, the obstructive material configured to block external access to the active circuitry. The method may include directly bonding the obstructive element to the semiconductor element without an adhesive, the peel-interrupting structure being configured to interrupt a function of the semiconductor element upon peeling the obstructive element from the semiconductor element.

In some embodiments, the method may include depositing a first bonding layer on the semiconductor element and depositing a second bonding layer on the obstructive element, the method including directly bonding the first bonding layer and the second bonding layer without an adhesive. The method may include forming a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer. The method may include directly bonding a first plurality of contact pads in a first bonding layer to a second plurality of contact pads in a second bonding layer. The method may include forming a first barrier layer in the first bonding layer and forming a layer of anchor material in the second bonding layer, the first barrier layer having one or more openings therethrough. The patterned interruption structure may comprise openings patterned through one or more barrier layers within one or more intermediate layers. The method may include patterning an opening in the obstructive material to expose a portion of the semiconductor element. The method may include monitoring an electrical signal along a conductor at least partially disposed in one or both of the semiconductor element and the obstructive element to determine whether the obstructive element has been peeled away from the semiconductor element.

Although disclosed in the context of certain embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, unless otherwise indicated, components in a description may be the same or substantially similar to the same numbered components in one or more different descriptions. In addition, while several variations have been shown and described in detail, other modifications, which are within the scope of this disclosure, will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed inventions. Thus, the scope of the invention disclosed herein is not to be limited by the specific disclosed embodiments described above, but is to be determined only by a reasonable interpretation of the following aspects.