阅读说明：本技术 封装器件及其形成方法 (Packaged device and method of forming the same ) 是由 沈士雄 李冠贤 于 2021-05-10 设计创作，主要内容包括：实施例包括晶圆上晶圆接合,其中每个晶圆包括在晶圆中限定的管芯区域周围的密封环结构。实施例提供了跨越晶圆之间的界面的另一个密封环。实施例可以延伸晶圆的现有密封环,提供与晶圆的现有密封环分开的延伸的密封环结构,或其组合。本申请的实施例提供了封装器件及其形成方法。(Embodiments include wafer-on-wafer bonding, where each wafer includes a seal-ring structure around a die area defined in the wafer. Embodiments provide another seal ring across the interface between wafers. Embodiments may extend an existing seal ring of a wafer, provide an extended seal ring structure separate from the existing seal ring of the wafer, or a combination thereof. Embodiments of the present application provide packaged devices and methods of forming the same.)

1. A packaged device, comprising:

a first die comprising:

a first seal ring structure disposed in the first interconnect of the first die around a periphery of the first die;

a first dielectric layer over the first interconnect; and

a first seal ring extension disposed in the first dielectric layer, the first seal ring extension aligned with and physically connected to the first seal ring structure, the first seal ring extension extending continuously around the perimeter edge of the first die; and

a second die comprising:

a second dielectric layer disposed under the second interconnection; and

a second seal ring extension disposed in the second dielectric layer, the second seal ring extension aligned with and physically connected to the first seal ring extension.

2. The packaged device of claim 1, wherein the first seal ring extension and the second seal ring extension are physically connected by a direct metal-to-metal bond with no eutectic material formed therebetween.

3. The packaged device of claim 1, wherein an air gap between the first die and the second die is sealed by the connected first seal ring extension and the second seal ring extension.

4. The packaged device of claim 1, wherein the first seal ring extension and the second seal ring extension are offset by a lateral distance.

5. The packaged device of claim 1, further comprising: a third seal ring extension extending through the second die and into the first die, the third seal ring extension surrounding the first connector of the first die and the second connector of the second die.

6. The packaged device of claim 5, wherein the third seal ring extension contacts the first seal ring structure and the second seal ring structure.

7. The packaged device of claim 5, further comprising: one or more bond pads disposed at a top surface of the third seal ring extension.

8. A packaged device, comprising:

a first die comprising a first seal ring around a periphery of the first die;

a second die comprising a second seal ring around a periphery of the second die; and

a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring.

9. The packaged device of claim 8, wherein the third seal ring is aligned with and contacts the first and second seal rings.

10. A method of forming a packaged device, comprising:

bonding a first connector of a first wafer to a second connector of a second wafer, the first wafer including a first seal ring, the second wafer including a second seal ring;

forming a third seal ring around the first and second connectors, the third seal ring spanning an interface between the first and second wafers; and

singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer.

Technical Field

Embodiments of the present application relate to packaged devices and methods of forming the same.

Background

In wafer-to-wafer bonding techniques, various methods have been developed for bonding two package components (e.g., wafers) together. Useful bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In fusion bonding, the oxide surface of a wafer is bonded to the oxide surface or silicon surface of another wafer. In eutectic bonding, two eutectic materials are placed together and applied by high pressure and high temperature. Thus, the eutectic material is molten. When the molten eutectic material solidifies, the wafers are bonded together. In direct metal-to-metal bonding, two metal pads are pressed against each other at elevated temperatures, and interdiffusion of the metal pads causes bonding of the metal pads. In hybrid bonding, the metal pads of two wafers are bonded to each other by direct metal-to-metal bonding, and the oxide surface of one of the two wafers is bonded to the oxide surface or silicon surface of the other wafer.

Disclosure of Invention

An embodiment of the present application discloses a packaged device, including: a first die comprising: a first seal ring structure disposed in the first interconnect of the first die around a periphery of the first die; a first dielectric layer over the first interconnect; and a first seal ring extension disposed in the first dielectric layer, the first seal ring extension aligned with and physically connected to the first seal ring structure, the first seal ring extension extending continuously around the perimeter edge of the first die; and a second die comprising: a second dielectric layer disposed under the second interconnection; and a second seal ring extension disposed in the second dielectric layer, the second seal ring extension aligned with and physically connected to the first seal ring extension.

An embodiment of the present application provides a packaged device, including: a first die comprising a first seal ring around a periphery of the first die; a second die comprising a second seal ring around a periphery of the second die; and a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring.

Embodiments of the present application further provide a method, comprising: bonding a first connector of a first wafer to a second connector of a second wafer, the first wafer including a first seal ring, the second wafer including a second seal ring; forming a third seal ring around the first and second connectors, the third seal ring spanning an interface between the first and second wafers; and singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer.

Embodiments of the present application provide an extended seal ring structure on a wafer stack.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 shows a schematic top view of a wafer according to some embodiments;

2-7 illustrate various views of intermediate steps in forming a seal ring extension, according to some embodiments;

8-12 illustrate various views of intermediate steps of forming a seal ring extension including a seal ring extension through-hole, according to some embodiments;

fig. 13 shows a schematic top view of a wafer according to some embodiments;

FIG. 14 illustrates a cross-sectional view of a wafer according to some embodiments;

15-19 illustrate various views of intermediate steps in forming a seal ring extension through a wafer stack and a device package, according to some embodiments;

FIG. 20 illustrates a cross-sectional view of a wafer according to some embodiments;

21-25 illustrate various views of intermediate steps in forming a seal ring extension through a wafer stack and a device package, according to some embodiments;

fig. 26-34 illustrate various views of intermediate steps in forming a seal ring extension through a wafer stack and a device package, according to some embodiments;

fig. 35-40 illustrate various views of intermediate steps in forming a seal ring extension through a wafer stack and a device package, according to some embodiments;

41-47 illustrate various views through a wafer stack and a seal ring extension of a device package, according to some embodiments;

fig. 48 illustrates a device package incorporated in different device configurations, in accordance with some embodiments;

fig. 49 illustrates a device package incorporated in different device configurations according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) elements or components as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments of the present invention advantageously provide an extended seal ring structure for wafer level packaging. The seal ring structure is used to surround the die area to provide mechanical stress support and to provide a seal against moisture penetration. Debris can occur at the die interface when a wafer is bonded to another wafer in a wafer-on-wafer process and the die is singulated from the wafer. The debris may propagate along the interface and expose the bond pad, allowing moisture to penetrate. Moisture can cause an increase in ohmic resistance at the bonding interface and result in chip scrap and/or failure. To address this issue, embodiments of the present invention utilize an extended seal ring structure to pass the seal ring structure up through the bonding interface, thereby creating a seal ring bond between the two wafers and spanning the bonding interface between the two wafers. The extended seal ring provides better mechanical stress support to the bond interface and resists moisture penetration into the wafer level bond. The extended seal ring structure may be formed by a metal-to-metal bonding process, a solder bump process, or a through silicon via process, as described below.

Fig. 1 illustrates a schematic top view of a wafer 100 according to some embodiments. Wafer 100 includes die 112, and adjacent scribe lines or scribes 114 and 116, where scribe lines 114 and 116 separate die 112 from each other. Scribe line 114 has a length direction parallel to the X direction, and scribe line 116 has a length direction parallel to the Y direction, which is perpendicular to the X direction. Within each die 112, there may be one or more seal rings, where the outer boundaries of the seal rings define the outer boundaries of the die 112. Each scribe line 114 is located between and adjacent to two rows of dies 112 and each scribe line 116 is located between and adjacent to two columns of dies 112. It should be noted that wafer 100 is intended to be exemplary only, and that the dimensions of die 112, scribe lines 114, scribe lines 116, and so on may vary depending on the die design.

Die 112 may include logic devices, Complementary Metal Oxide Semiconductor (CMOS) devices, microelectromechanical systems (MEMS) devices, Integrated Passive Devices (IPDs), drivers, or memory devices such as memory cells including, but not limited to, Static Random Access Memory (SRAM) cells, Dynamic Random Access Memory (DRAM) cells, Magnetoresistive Random Access Memory (MRAM) cells, and the like. Die 112 may include other types of devices.

Fig. 2-12 show intermediate views of a process of forming an extended seal-ring structure for the die 112.

Fig. 2 shows a cross-sectional view of the die 112. The cross-section of fig. 2 is a portion of the cross-section taken along line a-a of fig. 4, but the details of the various views may be different for purposes of discussion. The die 112 includes a substrate 122, which may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbon substrate, a III-V compound semiconductor substrate, or the like. The device region 118 is formed at the surface or within the substrate 122. The device region 118 may include active devices or passive devices, such as transistors, resistors, capacitors, diodes, and the like. The example transistor device 108 is shown within the device region 118. In some embodiments, device region 118 may include an encapsulated die.

In some embodiments, the interconnect structure 126 may be used to redistribute connections between various active and passive devices. The interconnect structure 126 may include an insulating layer 128, such as an inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD), and conductive features (e.g., metal lines 127 and vias 129) formed in alternating layers over the substrate 122 using any suitable method. Interconnect structure 126 may connect various active and/or passive devices in device region 118 of substrate 122 to form a functional circuit. The insulating layer 128 may comprise a low-k dielectric material having a k value, for example, less than about 4.0 or even less than 2.8. The thickness of interconnect structure 126 may be between about 0.1 μm and about 6 μm, for example about 4 μm. Other thicknesses may be used.

More specifically, in some embodiments, interconnect structure 126 may be formed by first depositing an insulating layer 128 over substrate 122 and device region 118. In some embodiments, the insulating layer 128 may be formed by a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., which may be patterned using a photolithographic mask. In other embodiments, the insulating layer 128 is formed by: nitrides such as silicon nitride; oxides such as silicon oxide, Undoped Silicate Glass (USG), PSG, BSG, BPSG; spin coating carbon; and so on. The insulating layer 128 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof.

Then, the insulating layer 128 is patterned. The patterning may form openings to expose portions of the substrate 122 and the device region 118, including contacts (not shown) to the device. The patterning may be formed by an acceptable process, such as by exposing the insulating layer 128 to light when the insulating layer 128 is a photosensitive material, or by etching using, for example, anisotropic etching. If the insulating layer 128 is a photosensitive material, the insulating layer 128 can be developed after exposure.

To form the first layer of metal lines 127 and vias 129, a seed layer (not shown) may be formed over insulating layer 128 and in the openings through insulating layer 128. In some embodiments, the seed layer is a metal layer, which may be a single layer, or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pattern of the metal wire 127. The patterning may form an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process (e.g., using an oxygen plasma, etc.). Once the photoresist is removed, the exposed portions of the seed layer may be removed, for example, by using an acceptable etching process, such as by wet or dry etching. The seed layer and the remaining portion of the conductive material form the pattern of metal lines 127 and vias 129. A via 129 is formed in an opening through insulating layer 128 to, for example, substrate 122 or device region 118.

Insulating layer 128 may then be subsequently deposited over metal lines 127 and vias 129, and the process may be repeated as necessary to form interconnect structures 126, which form circuitry and provide input/output to substrate 122 and device region 118.

Seal-ring structure 132 may also be formed when each layer of interconnect structure 126 is formed. Two seal ring structures 132A and 132B are shown, but any number of seal ring structures 132 may be used. The seal ring structure 132 may be formed with a through-hole portion 134 and a metal ring portion 136. The via portion 134 of the seal ring structure 132 may be formed simultaneously and using the same processes and materials as the via 129 discussed above. Similarly, metal ring portion 136 may be formed at the same time and using the same processes and materials as metal wire 127 discussed above.

In some embodiments, via portions 134 may each include an elongated trench through insulating layer 128 that is filled with a conductive material (e.g., the conductive material of via 129) to form a vertical ring around die 112. In other embodiments, via portion 134 may be a circular or square protrusion through insulating layer 128 to interconnect different layers of metal ring portion 136. Metal ring portion 136 forms a solid horizontal ring around the periphery of die 112.

In fig. 3, a bonding dielectric layer 138 is deposited over the interconnect structure 126. The bond dielectric layer 138 may be formed by depositing an insulating material. In some embodiments, the bond dielectric layer 138 is formed by a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., which may be patterned using a photolithographic mask. In other embodiments, the bond dielectric layer 138 is formed by: nitrides such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; and so on. The bond dielectric layer 138 may be formed by spin coating, lamination, CVD, the like, or combinations thereof. The bond dielectric layer 138 may be between about 0.01 μm and 2 μm thick, for example about 0.9 μm thick. Other thicknesses may be used.

The bond dielectric layer 138 is patterned to form openings 139 and 151 therein, exposing top metal lines 127 of interconnect structure 126 and exposing top metal layers of metal ring portion 136 of seal ring structure 132, respectively. Patterning may be performed by an acceptable process, such as by exposing the bond dielectric layer 138 to light when the bond dielectric layer 138 is a photosensitive material, or by etching using, for example, anisotropic etching. If the bond dielectric layer 138 is a photosensitive material, the bond dielectric layer 138 may be developed after exposure.

Fig. 4 shows a top view of an enlarged portion of wafer 100 after openings 139 and 151 are formed. As shown in fig. 4, the top metal layer of metal ring portion 136 of seal ring structure 132 and the top metal layer of metal line 127 are exposed through bonding dielectric layer 138. Opening 139 is shown as a circle over metal lead 127 and opening 151 is shown as an annular opening over seal ring structure 132.

In fig. 5, a conductive material 140, such as copper, titanium nitride, aluminum, or the like, or combinations thereof, may be deposited in the openings 139 and 151 by a suitable deposition process, such as PVD, CVD, or plating process (e.g., electroless plating, electroplating, etc.). The deposition process may fill both openings 139 and 151 simultaneously. An optional conductive seed layer may first be deposited in the openings 139 and 151 by a suitable process such as PVD. An optional barrier layer may also be deposited in the openings 139 and 151 prior to the optional seed layer. The optional barrier layer may be deposited using any suitable process and serves to inhibit diffusion of the conductive material into the surrounding bond dielectric layer 138.

In fig. 6, excess material of conductive material 140 may be removed from over bond dielectric layer 138 to form bond pad 142 and seal ring extension 152. Any suitable process may be used to remove excess material of the conductive material 140, such as a planarization process, for example a CMP process. After the removal process, the upper surfaces of bond pad 142 and seal ring extension 152 may be flush with the upper surface of bond dielectric layer 138.

Fig. 7 shows a top view of an enlarged portion of wafer 100 after bond pads 142 and seal ring extensions 152 are formed. As shown in fig. 7, the bonding pads 142 are formed in a regular pattern, however, any distribution of the bonding pads 142 may be used. The seal ring extension 152 fills the opening 151 and is shown as an annular structure positioned above the seal ring structure 132 (shown in phantom).

Fig. 8-15 illustrate the formation of an optional bond pad via 146. Utilizing bond pad vias 146 may allow the use of integrated test pads, high density micro-capacitors, and other structures disposed within the dielectric layer 144 of the bond pad vias 146. Bond pads 142 may be electrically connected to metal lines 127 and vias 129 by a corresponding bond pad via 146 for each active bond pad 142. The bond pad vias 146 and their formation described below may be incorporated into any of the other embodiments described below, but are omitted from the figures for simplicity.

In fig. 8, a dielectric layer 144 may be formed over the interconnect structure 126. In some embodiments, the dielectric layer 144 is an oxide layer, which may include silicon oxide. In other embodiments, the dielectric layer 144 includes other silicon and/or oxygen containing materials such as SiON, SiN, etc., and may be formed by any suitable deposition technique. The dielectric layer 144 may be deposited to any suitable thickness, for example, between 0.01 μm and about 1000 μm.

In fig. 9, dielectric layer 144 is patterned to form openings 145 and 155 therein, exposing top metal lines 127 of interconnect structure 126 and exposing top metal layers of metal ring portion 136 of seal ring structure 132, respectively. Patterning may be performed by any acceptable process. In one embodiment, a photolithographic mask is deposited over dielectric layer 144, patterned using photolithographic techniques, and used as a mask to etch openings 145 and 155 using, for example, an anisotropic etch. In some embodiments, opening 155 may comprise a single separate through-hole exposing separate regions of metal ring portion 136; while in other embodiments, opening 155 may comprise a groove formed to expose a continuous region of metal ring portion 136 of seal ring structure 132.

In fig. 10, a metal via is formed by depositing a conductive material 147, such as copper, titanium nitride, aluminum, or the like, or combinations thereof, in opening 145 and opening 155 by performing a suitable deposition process, such as by PVD, CVD, or a plating process, such as electroless plating, electroplating, or the like, on an optional seed layer first deposited in the opening. The deposition process may fill both opening 145 and opening 155 simultaneously. An optional conductive seed layer may first be deposited in openings 145 and 155 by a suitable process such as PVD. An optional barrier layer may also be deposited in opening 145 and opening 155 prior to the optional seed layer.

In fig. 11, excess material of conductive material 147 may be removed from over dielectric layer 144 to form bond pad via 146 and seal ring extension via 156. Any suitable process may be used to remove excess material of conductive material 147, such as a planarization process, for example a CMP process. After the removal process, the upper surfaces of bond pad via 146 and seal ring extension via 156 may be flush with the upper surface of dielectric layer 144.

Fig. 12 shows bond pad 142 and seal ring extension 152 disposed over bond pad via 146 and seal ring extension via 156, respectively. The bond pads 142 and seal ring extensions 152 may be formed using the processes and materials described above with respect to fig. 3-6, where like reference numerals refer to like elements. As mentioned above, the inclusion of bond pad vias 146 and seal ring extension vias 156 may be added to other embodiments below, but are not shown for simplicity.

Fig. 13-14 illustrate a die 212 according to some embodiments. Similar features of die 212 are labeled with similar identifiers used above with respect to die 112, except modified to guide at the number 2. Although die 212 is not shown with bond pad vias such as bond pad via 146 of fig. 12, it should be understood that bond pad vias may be present in some embodiments. Fig. 13 shows a schematic top view of a wafer 200 according to some embodiments. Wafer 200 includes die 212 and adjacent scribe lines or scribes 214 and 216, where scribes 214 and 216 separate die 212 from each other. Scribe line 214 has a length direction parallel to the X direction, and scribe line 216 has a length direction parallel to the Y direction, which is perpendicular to the X direction. In each die 212, there may be one or more seal rings, where the outer boundaries of the seal rings define the outer boundaries of the die 212. Each scribe line 214 is located between and adjacent to two rows of dies 212, and each scribe line 216 is located between and adjacent to two columns of dies 212. It should be noted that wafer 200 is merely an example, and the dimensions of die 212, scribe lines 214 and 216, etc. may vary depending on the die design.

In some embodiments, die 212 may be a similar or identical device to die 112 and may have similar dimensions thereto, including the thickness of the layers, and so on. In some embodiments, die 212 may be different from die 112 and may include a logic device or a memory device such as memory cells including, but not limited to, Static Random Access Memory (SRAM) cells, Dynamic Random Access Memory (DRAM) cells, Magnetoresistive Random Access Memory (MRAM) cells, and the like. Die 212 may include other types of devices.

Fig. 14 shows a cross-sectional view of die 212. As mentioned above, similar features of die 212 as compared to die 112 are labeled with similar reference numerals. The processes and materials used to form die 212 may be the same as those used with respect to die 112.

Fig. 15 illustrates a process of bonding wafer 200 to wafer 100 to bond die 212 to die 112 to form wafer stack 290. Optional bond pad via 146 and the bond pad via for die 212 are omitted from the view for simplicity. Although wafer-to-wafer bonding is shown, it should be understood that the bonding may be wafer-to-wafer where two wafers are directly bonded together, chip-to-chip where two singulated chips (or dies) are directly bonded together, or chip-to-wafer where one or more chips (or dies) are directly bonded together, where the bonding dielectric layer 138 of one die is fusion bonded to the bonding dielectric layer 238 of the other die, the bonding pads 142 of the die 112 are bonded to the bonding pads 242 of the die 212, and the seal ring extensions 152 of the die 112 are bonded to the seal ring extensions 252 of the die 212, but without the use of any eutectic material, such as solder. For example, in wafer-to-wafer bonding, wafer 100 is bonded to wafer 200 by hybrid bonding, where die 112 is bonded to die 212 prior to singulation. In hybrid bonding of wafers 100 and 200, bonding dielectric layer 138 is bonded to bonding dielectric layer 238 by fusion bonding, the metal of bonding pad 142 is bonded to the metal of bonding pad 242 by metal-to-metal bonding, and the metal of seal ring extension 152 is bonded to the metal of seal ring extension 252 by metal-to-metal bonding. Chip-to-chip bonding or chip-to-wafer bonding is performed in a similar manner, except for the method used to align the chips or chips and the wafer.

The bonding process may include pre-bonding and annealing. During pre-bonding, a small pressure may be applied to press the wafers 100 and 200 against each other. The pre-bonding may be performed at room temperature (e.g., between about 21 ℃ to about 25 ℃), although higher temperatures may be used. After pre-bonding, the bonding dielectric layers 138 and 238 are bonded to each other. The bond strength is improved in a subsequent annealing step, wherein the bonded wafers 100 and 200 are annealed, for example, at a temperature between about 300 ℃ and about 400 ℃.

The annealing may be performed for a time period between about 1 hour and 2 hours. In an exemplary embodiment, as the temperature increases, the OH bonds in bond dielectric layer 138 and bond dielectric layer 238 break to form strong Si-O-Si bonds, and thus wafers 100 and 200 are bonded to each other by fusion bonding (and by van der waals forces). In addition, during annealing, the metal (e.g., copper) in bond pad 142 and bond pad 242, and the metal in seal ring extension 152 and seal ring extension 252 diffuse into each other, thereby also forming a metal-to-metal bond. Thus, the resulting bond between wafers 100 and 200 is a hybrid bond.

Fig. 16a and 16b are enlarged views of a portion of fig. 15, as indicated by the dashed boxes in fig. 15. In fig. 16a, bond pads 142 and 242 are shown bonded together in a one-to-one correspondence. Similarly, seal ring extension 152 and seal ring extension 252 are also bonded together to form a continuous seal ring through the bonding interface of each of wafers 100 and 200.

As shown in fig. 16a, bonding need not occur in perfect alignment, and embodiments advantageously allow for a lateral offset d1 between bond pads 142 and 242 and/or seal ring extensions 152 and 252. The lateral offset d1 is not greater than the minimum bond pad pitch to avoid interference with adjacent bond pads, and is also not greater than half the minimum bond pad size to ensure good connectivity between bond pads. For example, if the pitch of the bond pads is 2 μm and the size of the bond pads is 1 μm, the lateral offset d1 may be between 0 and 0.5 μm. If the bond pad pitch is 1 μm and the bond pad size is 2 μm, the lateral offset d1 may be between 0 and 1 μm. The lateral offset d1 also allows for other process variations and therefore does not require perfect alignment.

FIG. 16B is similar to the embodiment shown in FIG. 16a, except that seal ring extensions 252 extend from the same seal ring structure 232, while seal ring extensions 152 extend from different seal ring structures 132A and 132B. This illustrates that embodiments may use different configurations to flexibly extend the seal ring structures (e.g., seal ring structures 132 and 232). For example, in some embodiments, some seal ring structures may extend while other seal ring structures do not.

The embodiments discussed above may be implemented when the die sizes are the same such that the edges of the two dies 112 and 212 of the wafers 100 and 200, respectively, are aligned. A similar process may be used to provide bonding of two different sized dies, for example, aligning at least one seal-ring structure 232 of die 212 with seal-ring structure 132 of die 112.

In fig. 17, wafer stack 290 is singulated into packages 295. The packages 295 may be singulated using any suitable cutting technique 292. The dicing technique 292 may include dry etching, wet etching, anisotropic etching, or plasma etching using a suitable etchant. The dicing technique 292 may include multiple passes of a laser to laser dice the packages 295 from one another. The cutting technique 292 may include a mechanical process, such as a knife saw configured to cut to a desired depth. Combinations of the cutting techniques 292 discussed above may also be used. Singulation occurs through the non-encapsulated regions (outside the encapsulated region, see, e.g., scribe lines 114 and 116 of fig. 1 and scribe lines 214 and 216 of fig. 13). The processed wafer stack 290 is singulated, resulting in a package 295. Debris generated by singulation that may propagate to the bond interface or bond pads 142 and 242 is reduced or eliminated due to the seal ring extensions 152 and 252.

Fig. 18 shows a singulated package 295 with sealing ring extensions 152 and 252. Seal ring extensions 152 and 252 serve to reduce the propagation of debris and prevent moisture and contaminants from infiltrating along the bonding interface to affect the bonding of bond pads 142 and 242.

Fig. 19 illustrates a plan view of package 295. The various illustrated elements may not actually be visible in the final package, but are illustrated in this view for contextual purposes. Seal ring extension 152 surrounds bond pad 142 (and bond pad via 146, if used). The seal ring extension 152 and seal ring structures 132A and 132B extend around the periphery of the die 112. Similarly, seal ring extension 252 surrounds bond pad 242 (and corresponding bond pad via, if used). Seal ring extension 252 and seal ring structures 232A and 232B extend around the periphery of die 212. The shape shown is rectangular, but may comprise any suitable shape, and may have rounded corners, dog-ear corners, or the like.

Fig. 20-25 illustrate various views associated with a eutectic seal ring extension, in accordance with some embodiments. The wafer 300 of fig. 20 may be formed using processes and materials similar to those discussed above with respect to fig. 3, where like reference numerals refer to like elements except that the 1 guide is replaced with a 3 guide. Although not shown for purposes of simplicity, in this embodiment, the bond pad vias 146 shown above with respect to fig. 12 may also be formed using processes and materials similar to those discussed above.

After forming openings 139 and 151 (see fig. 3), a bump material, such as solder or a eutectic material, may be formed in openings 139 and 151 to form bumps 362 over interconnect 326 and seal ring extensions 364 over seal ring structure 336, as shown in fig. 20. In some embodiments, an under bump metallization layer or seed layer may be formed in openings 139 and 151 prior to forming bumps 362 and seal ring extensions 364. The underbump metallization layer or seed layer may be formed by: a photolithographic masking layer is formed over insulating layer 338, openings corresponding to openings 139 and 151 are formed in the photolithographic masking layer, and then an appropriate deposition process, such as ALD, PVD, or CVD, is used to form an under-bump metallization layer or seed layer in openings 139 and 151 and over the photolithographic masking layer. The photolithographic mask layer may then be removed, thereby removing unwanted portions of the under bump metallization layer or seed layer.

Next, the bump 362 and the seal ring extension 364 may be simultaneously formed using any suitable process. For example, the bump 362 and the seal ring extension 364 may be formed by solder printing techniques, plating techniques, board transfer techniques, or the like. The material for the bump 362 and the seal ring extension 364 may include any suitable eutectic material, such as solder, high lead bumps, lead-free bumps, tin-lead eutectic bumps, aluminum-germanium eutectic bumps, and the like, or combinations thereof. After deposition, the bump 362 and seal ring extension 364 can be reflowed to bond with a seed layer, an under bump metallization layer, or a metal wire 327 of the interconnect 326.

In fig. 21, wafer 400 may be bonded to wafer 300 to form wafer-on-wafer stack 490. According to some embodiments, wafer 400 may be prepared in a manner similar to wafer 300, wherein like reference numerals refer to like elements, except that the 3 guide is replaced with a 4 guide. In other embodiments, the wafer 200 may be used. Wafer 400 may be placed on wafer 300 with the eutectic material of bump 362 (and corresponding bump 462) reflowed to form a continuous connection of merged bump 466 (see fig. 22a) and the eutectic material of seal ring extension 364 (and corresponding seal ring extension 464) reflowed to form a continuous seal ring extension 468 (see fig. 22 a).

Fig. 22a and 22b are enlarged views of a portion of fig. 21, as indicated by the dashed box in fig. 21. In fig. 22a, the tabs 362 and 462 are shown joined together in a one-to-one correspondence to form a merged tab 466. Similarly, seal ring extension 364 and seal ring extension 464 are likewise joined together to form a continuous seal ring extension 468 through the joining interface of each of wafers 300 and 400.

Fig. 21, 22a, and 22b also show that in some embodiments, a gap between wafer 300 and wafer 400 may remain between the two wafers after bonding. The gap or void is sealed by the seal ring extension 468 to keep contaminants and moisture out of the gap, eliminating the need for an underfill. Wafers 300 and 400 may be laterally offset by a distance d2 to allow for slight misalignment or other process variations. The lateral offset d2 may be no greater than the minimum bond pad pitch so as not to interfere with adjacent bond pads, and may also be no greater than half the minimum bond pad size to ensure good connectivity between bond pads. For example, if the pitch of the pads is 2 μm and the size of the bond pads is 1 μm, the lateral offset d2 may be between 0 and 0.5 μm. If the bond pad pitch is 1 μm and the bond pad size is 2 μm, the lateral offset d2 may be between 0 and 1 μm.

Fig. 22b illustrates an enlarged view of the dashed portion of fig. 21 according to some embodiments. In fig. 22B, seal ring structures 332A and 332B are bonded to a single seal ring structure 432 of wafer 400. Embodiments advantageously provide the ability to flexibly bond a seal ring structure in one wafer to another wafer via a seal ring extension. Different combinations of configurations may be used to extend different seal ring structures to each other. Also, in some embodiments, some seal ring structures may not extend through the seal ring extension.

In fig. 23, the wafer stack 490 is singulated into packages 495. The packages 495 may be singulated using any suitable cutting technique 292 discussed above.

Fig. 24 shows a singulated enclosure 495 with a sealing ring extension 468. Seal ring extension 468 serves to reduce the propagation of debris and to prevent moisture and contaminants from infiltrating along the bonding interface and/or between the two wafers to affect the bonding of bumps 362 and 462. In some embodiments, an underfill material may be used between the wafer 300 and the wafer 400 after singulation to fill the gap to the first seal ring extension 468.

Fig. 25 shows a plan view of the package 495. The various illustrated elements may not actually be visible in the final package, but are illustrated in this view for contextual purposes. The merged seal ring extensions 468 surround the merged bumps 466 (and bond pad vias of each wafer, if used). The seal-ring extension 468 and the seal-ring structures 332A and 332B extend around the periphery of the die 312. Similarly, seal-ring extension 468 and seal-ring structures 432A and 432B extend around the periphery of die 412. The shape shown is rectangular, but may comprise any suitable shape, and may have rounded corners, dog-ear corners, or the like.

Fig. 26-33 illustrate intermediate views of a process of forming an extended seal ring structure 660 extending through a wafer stack, according to some embodiments. Fig. 26 shows wafer stack 690, which includes wafer 500, wafer 500 bonded to wafer 600. In some embodiments, wafers 500 and 600 are each similar to wafer 100, with like reference numerals referring to like elements except that the guidance at 1 is replaced with guidance at 5 and 6, respectively. However, the seal ring structures 532 and 632 do not include seal ring extensions. In such an embodiment, wafers 500 and 600 are bonded together using hybrid bonding, such as described above with respect to fig. 15, and dielectric layer 538 is fusion bonded to dielectric layer 638 and bond pads 542 are directly bonded to bond pads 642 by metal-to-metal bonding. In other embodiments, wafers 500 and 600 are each similar to wafer 300, and wafer stack 690 is bonded together using bumps (see fig. 32, discussed below), which are reflowed to effect bonding. However, in such embodiments, the seal ring extension (e.g., 364 of FIG. 20) is not included.

Although two wafers are depicted in wafer stack 690 of fig. 26, it should be understood that the following description may be applied to wafer stacks including additional wafers (including 3 to 8 or more wafers). The wafers in fig. 26 are shown in a face-to-face bonded configuration. It should also be understood that the following description may also apply to wafers bonded in a face-to-back bonding configuration. That is, the wafer 500 may be flipped over, vias (not shown) exposed through the substrate 522, and interconnects formed above it then bonded to the front side of the wafer 600.

A lateral offset may be observed between wafers 500 and 600 similar to that illustrated and discussed above with respect to fig. 16 a. The offset may allow for margins for bonding the wafers 500 and 600 together, and may allow for other process variations, such as variations in bond pad or bump patterns.

In fig. 27, the top wafer 600 is thinned to remove excess portions of the substrate 622. The thinning may be performed using any suitable planarization process (e.g., a grinding process, a chemical mechanical polishing process, an etching process, etc., or a combination thereof). In some embodiments, the thinning may expose vias formed in the substrate that connect to the interconnects 626. In other embodiments, vias may be formed through the substrate 622 to connect to the interconnects 626 after thinning. Such vias may be formed using any suitable process (e.g., such as the processes used to form the openings 655 and fill the openings 655, described below) to etch openings through the substrate 622 and deposit metal fillers in the openings.

After thinning the top wafer 600, openings 655 are etched through the wafer 600 and at least partially through the wafer 500, including through interconnects 526. If additional wafers are interposed between the top wafer 600 and the wafer 500, openings 655 are etched through each of the intermediate wafers. In some embodiments, the opening 655 may further extend partially or entirely through the substrate 522 (e.g., if connected to a carrier (not shown)). The openings 655 may be formed using any suitable patterning technique. In some embodiments, a mask is formed over substrate 622 and patterned to form openings therein corresponding to openings 655. The openings of the mask are then transferred to each layer of wafer stack 690 by a dry etching process, such as by reactive ion etching or plasma etching. The mask used may comprise multiple layers. By thinning the top wafer 600 before forming the opening 655, the aspect ratio of the opening 655 may be increased.

Opening 655 includes a trench that runs around the periphery of die 512 and die 612. As indicated in fig. 27, the openings 655 may be located outside of the sealing ring structures 532 and 632. In some embodiments, the opening 655 may be located between the sealing ring structures 532A and 532B and between the sealing ring structures 632A and 632B. In other embodiments, opening 655 may be located between seal-ring structure 532 and bond pad 542 and between seal-ring structure 632 and bond pad 642. In some embodiments, a combination of these arrangements may occur.

In fig. 28, an extended seal ring structure 660 is formed by depositing a fill material in the opening 655. In some embodiments, the fill material may be a conductive material, such as those discussed above with respect to bond pad vias 146. In other embodiments, the fill material may be an insulating material, such as a ceramic, nitride, or oxide. The selected material may exhibit resistance to mechanical stress and moisture. The extended seal ring structure 660 may be formed by a suitable deposition process, such as by PVD, CVD, or plating techniques. When the material of the extended seal ring structure 660 is a conductive material, seed layers and/or barrier layers may be used, such as discussed above with respect to the bond pad via 146. Upon deposition, the material of the extended seal-ring structure 660 may overfill the openings 655, after which a removal process may be performed to remove excess portions of the material of the extended seal-ring structure 660 and to bring the upper surface of the extended seal-ring structure 660 flush with the (underlying) upper surface of the substrate 622. The removal process may be any suitable process, such as a grinding process, a CMP process, an etch-back process, the like, or any combination thereof.

In fig. 29, an optional bond pad 670 may be added on top of the extended seal-ring structure 660. Optional bond pad 670 may be formed using processes and materials similar to those discussed above with respect to pad 142. The bond pads 670 may be used to electrically ground the extended seal-ring structure 660.

In fig. 30, wafer stack 690 is singulated into packages 695. The packages 695 may be singulated using any suitable cutting technique 292 described above.

Fig. 31 shows a singulated package 695 having an extended seal ring structure 660. Extended seal ring structure 660 serves to reduce the propagation of debris and to prevent moisture and contaminants from infiltrating along the bonding interface and/or between the two wafers to affect the bonding of bond pads 542 and 642.

Fig. 32 shows an alternative embodiment to that mentioned above, where wafer 500 and wafer 600 are similar to wafer 300, with bumps 562 and 662, respectively. In the singulated package 695 of fig. 33, bumps 562 and 662 are connected together to form a continuous connector from wafer 600 to wafer 500 (see fig. 30). In some embodiments, such as depicted in fig. 32, the air gap 696 may be surrounded by an extended seal ring structure 660. As seen on the left side view of the extended seal ring structure 660, in such embodiments, a portion of the extended seal ring structure 660 may extend laterally into the air gap 696 between the dielectric layers 538 and 638. In some embodiments, the extended extension portions 661 of the extended seal ring structure 660 may extend over the dielectric layer 538. In embodiments where the extended seal ring structure 660 is an insulating material, the extensions 661 can extend into the air gaps 696 and contact the bumps 562 and/or the bumps 662. In some embodiments, the extended seal ring structure 660 may not significantly laterally expand into the air gap 696. In some embodiments, an underfill material may be deposited between wafer 500 and wafer 600 when making opening 655 (see fig. 27). In the embodiment shown in fig. 32, an underfill may fill the gap and surround the connectors between wafers 500 and 600. In some embodiments, the underfill material may also serve as an extended seal ring structure 660. In other embodiments, the opening 655 may be modified or formed after application of the underfill material. The extended seal ring structure 660 serves to reduce debris propagation and prevent moisture and contaminants from infiltrating along the bonding interface and/or between the two wafers to affect the bonding of bumps 562 and 662.

Fig. 33 shows the embodiment mentioned above with respect to fig. 29, including bond pads 670 formed over extended seal-ring structures 660. The bond pads 670 may be used as ground points in subsequently formed packages or for other purposes.

Fig. 34 illustrates a plan view of the package 695. The various illustrated elements may not be visible in the final package, but are illustrated in this view for contextual purposes. An extended seal ring structure 660 surrounds the merged bond pads 542 and 642 (or bumps 562 and 662, if used). The extended seal-ring structure 660 and the seal-ring structures 532A and 532B extend around the perimeter of the die 512. Similarly, extended seal-ring structure 660 and seal-ring structures 632A and 632B extend around the periphery of die 612. The shape shown is rectangular, but may comprise any suitable shape, and may have rounded corners, dog-ear corners, or the like. As mentioned above, while the extended seal ring structure 660 is depicted as surrounding the seal ring structures 532 and 632, in some embodiments, part or all of the seal ring structure 532 may instead surround the extended seal ring structure 660.

Fig. 35-40 illustrate intermediate views of a process of forming an extended seal ring structure 660 (see fig. 36) extending through a wafer stack 690, according to some embodiments. Fig. 35 shows wafer stack 690 including wafer 500, wafer 500 bonded to wafer 600. One or more intermediate wafers may be interposed between wafer 500 and wafer 600. Wafer stack 690 may be similar to wafer stack 690 discussed above with respect to fig. 26-34, where like reference numerals refer to like elements.

In fig. 35, the substrate of wafer 600 is thinned using processes and materials similar to those discussed above with respect to fig. 27. Next, an opening 655 is formed through the wafer 600 and at least partially through the wafer 500. In fig. 35, the seal ring structures 532 and 632 are at least partially exposed in the formation of the opening 655. During the formation of the opening 655, the sealing ring structure 532 may remain and overhang the opening 655, or may be partially removed by the process used to create the opening 655.

In fig. 36, a fill material is deposited to form an extended seal ring structure 660. The fill material may be deposited using processes and materials similar to those discussed above with respect to fig. 28. When the fill material is formed in the opening 655, the fill material contacts the seal ring structures 532 and 632, e.g., 532A and 632A. When the fill material is a conductive material, the extended seal ring structure 660 is electrically connected to the seal ring structures 532 and 632. In some embodiments, these elements may be electrically grounded and may therefore serve as grounding points.

Fig. 36 also shows wafer stack 690 singulated into packages 695. Singulation may be performed by any suitable singulation process, such as the cutting technique 292 discussed above with respect to, for example, fig. 30.

In fig. 37, one embodiment of a package 695 includes bond pads 542 and 642 bonded directly to each other with metal-to-metal bonds, and dielectric layers 538 and 638 fusion bonded to each other. The extended seal ring structure 660 contacts the seal ring structures 532 and 632 and penetrates completely through the wafer 600 and at least partially through the wafer 500.

In fig. 38, one embodiment of a package 695 includes bumps 562 and 662 that merge together upon reflow. The resulting package 695 may have an air gap 696 between the two dies. The extended seal ring structure 660 seals the air gap 696 from unwanted moisture ingress, so that no underfill is required between the two dies. In some embodiments, a portion 661 of the extended seal ring structure 660 may extend laterally into the air gap 696, such as discussed above. In some embodiments, an underfill material may be deposited between wafers 500 and 600 when making opening 655 (see fig. 35). In the embodiment shown in fig. 38, an underfill may fill the gap and surround the connector between wafers 500 and 600. In some embodiments, the underfill material may also serve as an extended seal ring structure 660. In other embodiments, the opening 655 may be modified or formed after application of the underfill material.

In fig. 39, one embodiment of a package 695 includes an optional bond pad 670 formed over the extended seal ring structure 660. The bond pads 670 may be used as ground points in subsequently formed packages or for other purposes.

Fig. 40 illustrates a plan view of a package 695, according to some embodiments. The various illustrated elements may not be visible in the final package, but are illustrated in this view for contextual purposes. An extended seal ring structure 660 surrounds the merged bond pads 542 and 642 (or bumps 562 and 662, if used). The extended seal-ring structure 660 extends with the seal-ring structures 532A and 532B around the circumference of the die 512 and contacts one or more of the seal-ring structures 532A and 532B. Similarly, extended seal-ring structure 660 extends around the periphery of die 612 along with seal-ring structures 632A and 632B, and contacts one or more of seal-ring structures 632A and 632B. The shape shown is rectangular, but may comprise any suitable shape, and may have rounded corners, dog-ear corners, or the like. Although the extended seal ring structure 660 is depicted as surrounding the seal ring structures 532 and 632, in some embodiments, instead, some or all of the seal ring structure 532 may surround the extended seal ring structure 660.

Fig. 40 also shows a top view of an optional bond pad 670 formed on the extended seal-ring structure 660, according to embodiments utilizing any of the extended seal-ring structures 660 discussed above. As shown in fig. 40, the bonding pads 670 may be circular pads, rectangular pads, or the like. In some embodiments, the bond pads 670 may extend along the entire length of the extended seal-ring structure 660 and form a continuous ring.

Fig. 41-47 illustrate combinations of features of previously illustrated embodiments according to some embodiments. Fig. 41 shows a wafer stack 890 including a wafer 700, the wafer 700 being bonded to a wafer 800. In some embodiments, wafers 700 and 800 are each similar to wafer 100, with like reference numerals referring to like elements except that the guidance at 1 is replaced with guidance at 7 and 8, respectively. In addition to seal ring extensions 752 and 852, wafers 700 and 800 also include extended seal ring structures 860 (see extended seal ring structures 660 above). The various illustrated elements may be formed using the materials and processes discussed above with respect to their corresponding elements.

In fig. 42, optional bond pad 870 (see bond pad 670 above) is formed over extended seal-ring structure 860. In fig. 43, extended seal ring structure 860 is formed such that it contacts seal ring structures 732 and 832, respectively, in each of wafers 700 and 800. Optional bond pads 870 may also be included in this embodiment. Both extended seal ring structure 860 that contacts seal ring structure 832 and extended seal ring structure 860 that does not contact seal ring structure 832 may be included in one embodiment, including both being on the same side of enclosure 895, and may or may not be made of the same material.

In fig. 44, each of wafers 700 and 800 corresponds to wafer 300 discussed above, where like reference numerals refer to like elements except that the 3 guide is replaced with a 6 guide for wafer 600 and a 7 guide for wafer 700. Wafer stack 890 includes seal ring extensions 868 made from bumps 864 bonded to bumps 764. In addition, wafer stack 890 includes extended seal ring structures 860, which may be similar to those discussed above with respect to fig. 32 or 37. Optional bond pad 870 is included, but may be omitted. The left extending seal ring structure does not contact seal ring structures 732 and 832, such as discussed above with respect to fig. 32, but the right extending seal ring structure 860 is shown contacting seal ring structure 832, such as discussed above with respect to fig. 37. Both extended seal ring structure 860 that contacts seal ring structure 832 and extended seal ring structure 860 that does not contact seal ring structure 832 may be included in the same embodiment, including both being on the same side of enclosure 895, and may or may not be made of the same material. The embodiment shown in fig. 44 also includes a gap 896, which may have an underfill deposited therein, such as described above with respect to the gap 696 of fig. 32 or 38.

In fig. 45, wafer stack 890 of fig. 41 is singulated to form packages 895, as represented by wafer stack 890. Singulation process may use a dicing technique 292 to dice wafer stack 890 into packages 895. The cutting technique 292 may be any of the techniques previously discussed (see, e.g., fig. 17).

In FIG. 46, enclosure 895 includes an extended seal ring structure 860 in addition to seal ring extensions 752 and 852. The use of both extended seal ring structure 860 and one or more seal ring extensions 752 and 852 may provide enhanced protection against debris propagation, as well as humidity or environmental contamination of the bond between bond pads 742 and 842 (or bumps 762 and 862 of fig. 44).

Fig. 47 illustrates a plan view of a package 895 according to some embodiments. The various illustrated elements may not be visible in the final package, but are illustrated in this view for contextual purposes. An extended seal ring structure 860 surrounds bond pads 742 and 842 (or bumps 762 and 862, if used). The extended seal-ring structure 860 extends around the perimeter of the die 712, alongside the seal-ring structures 732A and 732B. The extended seal ring structure 860 may contact one or more of the seal ring structures 732A and 732B. Similarly, the extended seal-ring structure 860 extends around the perimeter of the die 812 alongside the seal-ring structures 832A and 832B, and may also contact one or more of the seal-ring structures 832A and 832B. The shape shown is rectangular, but may comprise any suitable shape, and may have rounded corners, dog-ear corners, or the like. Although the extended seal ring structure 860 is depicted as surrounding the seal ring structures 732 and 832, in some embodiments, part or all of the seal ring structure 732 may surround the extended seal ring structure 860, instead.

Seal ring extensions 752 and 852 surround bond pads 742 and 842, respectively, and are formed on seal ring structures 732 and 832 of each of wafer 700 and wafer 800.

Fig. 48 and 49 illustrate packaged devices that utilize a package 295/495/695/895 as disclosed herein to connect to another device or structure 905, such as a printed circuit board, a system on an integrated chip package, a chip on wafer on substrate configuration, or an integrated fan-out package. In fig. 48, package 295/495/695/895 may have front connectors 910 formed thereon that connect to one or more devices in package 295/495/695/895. Package 295/495/695/895 may then be flipped over and bonded to structure 905 by connector 910 to form packaged device 925. In some embodiments, front connector 910 may electrically connect extended seal ring structure 860 to structure 905.

In fig. 49, package 295/495/695/895 may have pads 970 formed on the top surface and connected to one or more devices within package 295/495/695/895. The package may then be adhered to structure 905. Wire bond 960 may be used to connect pad 970 to pad 965 formed in structure 905. In some embodiments, wire bonds 960 may be used to electrically connect extended seal ring structure 860 to structure 905.

The seal ring is used to provide structural and mechanical support against stresses from warping and peeling. Each seal ring is typically active separately when bonding one wafer to another. Some embodiments of the present disclosure advantageously extend the seal rings of the wafers to the bonding surface and bond the seal ring of one wafer to the seal ring of another wafer when the wafers are bonded together in a wafer-to-wafer bond. The extended seal ring has the advantage of providing a strong stress handling capability between the two wafers to resist wafer delamination due to warpage. The extended seal ring also has the advantage that the bonding interface between the two wafers in which the active connector is bonded together can be completely sealed. The risk of humidity and contaminant infiltration is greatly reduced, providing a stronger, more resilient device with less chance of failure. At the same time, the cost-effective wafer-to-wafer bonding process can still be used for mass production since the seal ring can withstand slight misalignment or misalignment without absolute precision. Some embodiments of the present disclosure advantageously form an extended seal ring structure after wafer-to-wafer bonding, which forms a trench through the upper wafer and through all bonding interfaces, and fills the trench with a seal ring material. The extended seal ring structure serves to prevent contaminants and moisture from penetrating the bonding interface and further enhances the mechanical stability of the wafer stack (and the resulting die stack after singulation) to resist stress from warpage. Since the extended seal ring structure is formed after wafer-to-wafer bonding, misalignment is not a problem for the extended seal ring structure. In some embodiments, the extended seal ring structure may be physically and electrically connected to the seal ring of each wafer. Embodiments may also include bond pads over the extended seal ring structure, which may be used for grounding.

One embodiment is a packaged device, comprising: a first die comprising: a first seal ring structure disposed in the first interconnect of the first die around the periphery of the first die; a first dielectric layer over the first interconnect; and a first seal ring extension disposed in the first dielectric layer. The first seal ring extension is aligned with and physically connected to the first seal ring structure, and the first seal ring extension extends continuously around a periphery of the first die. The packaged device further includes: a second die comprising: a second dielectric layer disposed below the second interconnect and a second seal ring extension disposed in the second dielectric layer. The second seal ring extension is aligned with and physically connected to the first seal ring extension. In one embodiment, the first seal ring extension and the second seal ring extension are physically connected by a direct metal-to-metal bond with no eutectic material formed therebetween. In one embodiment, an air gap between the first die and the second die is sealed by the connected first seal ring extension and second seal ring extension. In one embodiment, the first seal ring extension and the second seal ring extension are offset by a lateral distance. In one embodiment, the packaged device may include a third seal ring extension extending through the second die and into the first die, the third seal ring extension surrounding the first connector of the first die and the second connector of the second die. In one embodiment, the third seal ring extension contacts the first seal ring structure and the second seal ring structure. In one embodiment, the packaged device may include one or more bond pads disposed at a top surface of the third seal ring extension.

Another embodiment is a packaged device, comprising: a first die including a first seal ring around a periphery thereof. The packaged device further includes: a second die comprising a second seal ring around a periphery thereof. The packaged device further includes: a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring. In one embodiment, the third seal ring is aligned with and contacts the first seal ring and the second seal ring. In one embodiment, the third seal ring extends up through the second die, which is located above the first die. In one embodiment, the third seal ring surrounds the first seal ring and the second seal ring. In one embodiment, a packaged device may include: a fourth seal ring interposed between the first seal ring and the second seal ring, the fourth seal ring spanning an interface between the first die and the second die, the fourth seal ring having an upper surface in contact with a lower surface of the second seal ring, and a bottom surface in contact with the upper surface of the first seal ring.

Another embodiment is a method comprising: the first connectors of the first wafer are bonded to the second connectors of the second wafer. The first wafer may include a first seal ring; the second wafer may include a second seal ring. The method also includes forming a third seal ring around the first and second connectors, the third seal ring spanning an interface between the first and second wafers. The method also includes singulating the first wafer and the second wafer to singulate the first package therefrom. In one embodiment, forming the third seal ring may include: forming a first trench opening in the first dielectric layer over the first seal ring, the first trench opening exposing an upper surface of the first seal ring; and depositing a conductive material in the first trench opening to form a first seal ring extension; forming a second trench opening in the second dielectric layer over the second seal ring, the second trench opening exposing an upper surface of the second seal ring; depositing a conductive material in the second trench opening to form a second seal ring extension; the first seal ring extension is bonded to the second seal ring extension while the first connector of the first wafer is bonded to the second connector of the second wafer. In one embodiment, the first seal ring extension and the second seal ring extension may comprise a eutectic material. In one embodiment, the first seal ring extension and the second seal ring extension are joined together using a direct metal-to-metal bond. In one embodiment, forming the third seal ring may include: thinning the second wafer; and forming a trench through the second wafer, the trench penetrating the first wafer, the trench surrounding the first connector and the second connector; and filling the trench with a seal ring material. In one embodiment, the seal ring material is a conductive material. In one embodiment, the method may further comprise: a bond pad is formed over the third seal ring. In one embodiment, the trench exposes the first seal ring and the second seal ring, the seal ring material electrically and physically connecting the first seal ring and the second seal ring.

An embodiment of the present application discloses a packaged device, including: a first die comprising: a first seal ring structure disposed in the first interconnect of the first die around a periphery of the first die; a first dielectric layer over the first interconnect; and a first seal ring extension disposed in the first dielectric layer, the first seal ring extension aligned with and physically connected to the first seal ring structure, the first seal ring extension extending continuously around the perimeter edge of the first die; and a second die comprising: a second dielectric layer disposed under the second interconnection; and a second seal ring extension disposed in the second dielectric layer, the second seal ring extension aligned with and physically connected to the first seal ring extension. In some embodiments, the first seal ring extension and the second seal ring extension are physically connected by a direct metal-to-metal bond with no eutectic material formed therebetween. In some embodiments, the air gap between the first die and the second die is sealed by the connected first seal ring extension and the second seal ring extension. In some embodiments, the first seal ring extension and the second seal ring extension are offset by a lateral distance. In some embodiments, further comprising: a third seal ring extension extending through the second die and into the first die, the third seal ring extension surrounding the first connector of the first die and the second connector of the second die. In some embodiments, a third seal ring extension contacts the first seal ring structure and the second seal ring structure. In some embodiments, further comprising: one or more bond pads disposed at a top surface of the third seal ring extension.

An embodiment of the present application provides a packaged device, including: a first die comprising a first seal ring around a periphery of the first die; a second die comprising a second seal ring around a periphery of the second die; and a third seal ring spanning an interface between the first die and the second die, the third seal ring surrounding the interface and sealing the interface within the third seal ring. In some embodiments, a third seal ring is aligned with and contacts the first seal ring and the second seal ring. In some embodiments, a third seal ring extends up through the second die, the second die being located above the first die. In some embodiments, a third seal ring surrounds the first seal ring and the second seal ring. In some embodiments, further comprising: a fourth seal ring interposed between the first seal ring and the second seal ring, the fourth seal ring spanning the interface between the first die and the second die, the fourth seal ring having an upper surface in contact with a lower surface of the second seal ring, and a bottom surface in contact with an upper surface of the first seal ring.

Embodiments of the present application further provide a method, comprising: bonding a first connector of a first wafer to a second connector of a second wafer, the first wafer including a first seal ring, the second wafer including a second seal ring; forming a third seal ring around the first and second connectors, the third seal ring spanning an interface between the first and second wafers; and singulating the first wafer and the second wafer to singulate a first package from the first wafer and the second wafer. In some embodiments, forming the third seal ring comprises: forming a first trench opening in a first dielectric layer over the first seal ring, the first trench opening exposing an upper surface of the first seal ring; depositing a conductive material in the first trench opening to form a first seal ring extension; forming a second trench opening in a second dielectric layer over the second seal ring, the second trench opening exposing an upper surface of the second seal ring; depositing the conductive material in the second trench opening to form a second seal ring extension; and bonding the first seal ring extension to the second seal ring extension while bonding the first connector of the first wafer to the second connector of the second wafer. In some embodiments, the first seal ring extension and the second seal ring extension comprise a eutectic material. In some embodiments, the first seal ring extension and the second seal ring extension are joined together using a direct metal-to-metal bond. In some embodiments, forming the third seal ring comprises: thinning the second wafer; forming a trench through the second wafer, the trench penetrating the first wafer, the trench surrounding the first and second connectors; and filling the trench with a seal ring material. In some embodiments, the seal ring material is a conductive material. In some embodiments, further comprising: a bond pad is formed over the third seal ring. In some embodiments, the trench exposes the first and second seal rings, the seal ring material electrically and physically connecting the first and second seal rings.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.