阅读说明：本技术 一种存储器及其制造方法 (Memory and manufacturing method thereof ) 是由 陈赫 伍术 潘震 胡思平 赵祎 华子群 于 2021-02-02 设计创作，主要内容包括：本申请提供一种存储器包括：第一晶圆,具有内侧面和外侧面,在第一晶圆的内侧面设置有外围电路,第一晶圆的外侧面包括密封区域和芯片区域；下部功能层,设置在第一晶圆的外侧面；以及中部功能层,设置在下部功能层远离第一晶圆的一侧,其中,中部功能层在密封区域具有贯穿触点和缓冲部件,所述缓冲部件嵌入至所述中部功能层中的至少一部分中,嵌入的缓冲部件的材料与被嵌入的中部功能层的材料不同。(The present application provides a memory comprising: the semiconductor device comprises a first wafer, a second wafer and a third wafer, wherein the first wafer is provided with an inner side surface and an outer side surface, a peripheral circuit is arranged on the inner side surface of the first wafer, and the outer side surface of the first wafer comprises a sealing area and a chip area; the lower functional layer is arranged on the outer side surface of the first wafer; and the middle functional layer is arranged on one side, far away from the first wafer, of the lower functional layer, wherein the middle functional layer is provided with a through contact and a buffer component in a sealing area, the buffer component is embedded into at least one part of the middle functional layer, and the embedded buffer component is made of a material different from that of the embedded middle functional layer.)

1. A memory, comprising:

the semiconductor device comprises a first wafer, a second wafer and a third wafer, wherein the first wafer is provided with an inner side face and an outer side face, a peripheral circuit is arranged on the inner side face of the first wafer, and the outer side face of the first wafer comprises a sealing area and a chip area;

the lower functional layer is arranged on the outer side surface of the first wafer; and

a middle functional layer arranged on one side of the lower functional layer far away from the first wafer,

wherein the central functional layer has through contacts and a cushioning component in the sealing region, the cushioning component being embedded in at least a portion of the central functional layer, the material of the embedded cushioning component being different from the material of the embedded central functional layer.

2. The memory according to claim 1, wherein the buffer member comprises:

at least one of the buffer through contact and the backside isolation trench.

3. The memory of claim 2,

the buffer component is positioned on one side of the through contact close to the chip area and/or one side far away from the chip area.

4. The memory of claim 3,

the through contacts and the buffer through contacts are staggered with each other.

5. The memory of claim 4,

the buffer through contact is positioned on the perpendicular bisector of two adjacent through contacts.

6. The memory of claim 2,

the lower functional layer has a contact wall in the sealing area,

wherein the contact wall and the buffer through contact are aligned and connected to each other.

7. The memory of claim 6,

said lower functional layer having a sealing ring in said sealing area,

wherein the seal ring is aligned with the through contact and connected to each other.

8. The memory of claim 2,

the middle functional layer is of a multilayer structure, the penetrating contact and the buffering penetrating contact penetrate through the multilayer structure, and the back insulation groove at least penetrates through one layer of structure, close to the lower functional layer, in the multilayer structure.

9. The memory of claim 8,

the multilayer structure comprises at least: a semiconductor layer and an insulating layer.

10. The memory of claim 1, further comprising:

and the upper functional layer is arranged on one side of the middle functional layer, which is far away from the first wafer.

11. The memory according to any one of claims 1-10, further comprising:

a second wafer having an array of memory cells and interconnect structures on an inner side,

wherein an inner side of the first wafer and an inner side of the second wafer are bonded to each other.

12. A method of manufacturing a memory, comprising:

providing a first wafer with an inner side face and an outer side face, wherein a peripheral circuit is formed on the inner side face of the first wafer, and the outer side face of the first wafer comprises a sealing area and a chip area;

forming a lower functional layer on the outer side surface of the first wafer; and

forming a middle functional layer on the lower functional layer, wherein the middle functional layer has a through contact and a cushioning component in the sealing region, the cushioning component being embedded into at least a portion of the middle functional layer, the embedded cushioning component being of a different material than the embedded middle functional layer.

13. The memory manufacturing method according to claim 12, wherein the step of forming a middle functional layer on the lower functional layer includes:

depositing a first middle sub-functional layer and a second middle sub-functional layer on the lower functional layer in sequence;

patterning the first middle sub-functional layer and the second middle sub-functional layer to remove the first middle sub-functional layer and the second middle sub-functional layer located in a through-contact sub-area and a buffer component sub-area of the seal area to form a through-contact opening and a buffer component opening; and

the through contact is formed in the through contact opening, and the buffer member is formed in the buffer member opening.

14. The memory manufacturing method according to claim 13,

the buffer member opening includes at least one of a buffer through contact opening and a backside insulation trench opening.

15. The memory manufacturing method according to claim 14,

the buffer member opening is located at a side of the through contact opening close to the chip region and/or a side away from the chip region.

16. The memory manufacturing method according to claim 15,

the through contact openings and the buffer through contact openings are patterned to be staggered with respect to each other.

17. The memory manufacturing method according to claim 14,

the step of forming a lower functional layer on the outer side of the first wafer comprises:

depositing the lower functional layer on the outer side surface of the first wafer;

patterning the lower functional layer to remove the sealing ring sub-region located in the sealing region and the lower functional layer contacting the wall sub-region, and forming a sealing ring opening and a contacting wall opening; and

forming a sealing ring in the sealing ring opening and a contact wall in the contact wall opening,

the step of forming the through contact in the through contact opening and the buffer through contact in the buffer through contact opening includes:

depositing an insulating material to cover sidewalls and a bottom of the through contact opening and the buffer through contact opening;

removing at least part of the insulating material at the bottom of the through contact opening and the buffer through contact opening to expose the upper surfaces of the sealing ring and the contact wall, respectively; and

completely filling the through contact openings and the buffer through contact openings with a conductive material to form the through contacts and buffer through contacts.

18. The memory fabrication method of claim 14, wherein forming the through contact in the through contact opening and forming the back isolation trench in the back isolation trench opening comprises:

depositing an insulating material to completely fill the back insulating trench opening and cover sidewalls and bottom of the through contact opening;

removing at least a portion of the insulating material at the bottom of the through contact opening to expose an upper surface of the seal ring; and

completely filling the through contact openings with a conductive material to form the through contacts.

19. The memory manufacturing method according to claim 18,

the width of the through contact opening is greater than the width of the back insulation trench opening.

20. The memory manufacturing method according to claim 12, further comprising:

an upper functional layer is formed on the middle functional layer.

21. The memory manufacturing method of claim 12, further comprising, before forming a lower functional layer on the outer side of the first wafer:

providing a second wafer having an array of memory cells and an interconnect structure on an inner side; and

bonding an inner side of the first wafer and an inner side of the second wafer to each other.

Technical Field

The present application relates to a method of manufacturing a semiconductor device, and also relates to a memory and a method of manufacturing the same.

Background

The memory is a sequential logic circuit. Random Access Memory (RAM) is one type of Memory. With the development of semiconductor manufacturing processes, the memory density of the memory is higher and the size of the memory is smaller, and the structure of the memory is also developed from two dimensions to three dimensions.

The manufacturing method of the memory may include: forming various film layers with preset patterns on the wafer, cutting the wafer and the like. As a way of dicing the wafer, laser dicing may be employed. Specifically, when the wafer is cut by laser cutting, the carbon material in the film structure on the wafer is thermally expanded due to laser heating, so that stress caused by the thermal expansion is generated inside the wafer. Typically, most of the stress is absorbed by the material layer in the dicing street area. But a small portion of the stress may be conducted to other areas, such as the chip area, resulting in defects.

The same problem exists as another way of dicing wafers, mechanical dicing.

Disclosure of Invention

An objective of the present invention is to provide a memory and a method for manufacturing the same, so as to solve the problem of the prior art that a part of stress is conducted to a chip region through a scribe line region when a wafer is diced.

To achieve the object of the present application, there is provided a memory including: the semiconductor device comprises a first wafer, a second wafer and a third wafer, wherein the first wafer is provided with an inner side face and an outer side face, a peripheral circuit is arranged on the inner side face of the first wafer, and the outer side face of the first wafer comprises a sealing area and a chip area; the lower functional layer is arranged on the outer side surface of the first wafer; and the middle functional layer is arranged on one side, far away from the first wafer, of the lower functional layer, wherein the middle functional layer is provided with a through contact and a buffer component in the sealing area, the buffer component is embedded into at least one part of the middle functional layer, and the embedded buffer component is made of a material different from that of the embedded middle functional layer.

In an embodiment of the present application, the buffer member includes: at least one of the buffer through contact and the backside isolation trench.

In an embodiment of the application, the buffer component is located on a side of the through contact close to the chip region and/or a side of the through contact far from the chip region.

In an embodiment of the present application, the through contact and the buffering through contact are staggered from each other.

According to one embodiment of the application, the buffer through contact is located on a perpendicular bisector of two adjacent through contacts.

In an embodiment of the application, the lower functional layer has a contact wall in the sealing area, wherein the contact wall is aligned with the buffer through contact and connected to each other.

In an embodiment of the application, the lower functional layer has a sealing ring in the sealing region, wherein the sealing ring is aligned with the through contact and connected to each other.

In an embodiment of the present application, the middle functional layer is a multilayer structure, the through contact and the buffer through contact penetrate through the multilayer structure, and the back insulation trench penetrates through at least one layer of structure of the multilayer structure near the lower functional layer.

In an embodiment of the present application, the multi-layer structure at least includes: a semiconductor layer and an insulating layer.

In an embodiment of the present application, the memory further includes: and the upper functional layer is arranged on one side of the middle functional layer, which is far away from the first wafer.

In an embodiment of the present application, the memory further includes: and the second wafer is provided with a storage unit array and an interconnection structure on the inner side, wherein the inner side of the first wafer and the inner side of the second wafer are bonded with each other.

In order to achieve the object of the present application, there is also provided a memory manufacturing method including: providing a first wafer with an inner side face and an outer side face, wherein a peripheral circuit is formed on the inner side face of the first wafer, and the outer side face of the first wafer comprises a sealing area and a chip area; forming a lower functional layer on the outer side surface of the first wafer; and forming a middle functional layer on the lower functional layer, wherein the middle functional layer has a through contact and a buffer member in the sealing region, the buffer member being embedded in at least a part of the middle functional layer, the embedded buffer member being of a different material from the material of the embedded middle functional layer.

In an embodiment of the present application, the step of forming a middle functional layer on the lower functional layer includes: depositing a first middle sub-functional layer and a second middle sub-functional layer on the lower functional layer in sequence; patterning the first middle sub-functional layer and the second middle sub-functional layer to remove the first middle sub-functional layer and the second middle sub-functional layer located in a through-contact sub-area and a buffer component sub-area of the seal area to form a through-contact opening and a buffer component opening; and forming the through contact in the through contact opening, and forming the buffer member in the buffer member opening.

In an embodiment of the present application, the buffer member opening includes at least one of a buffer through contact opening and a back insulation trench opening.

In an embodiment of the application, the buffer member opening is located at a side of the through contact opening close to the chip region and/or a side of the through contact opening away from the chip region.

In one embodiment of the present application, the through contact openings and the buffer through contact openings are patterned to be staggered with respect to each other.

In an embodiment of the present application, the step of forming the lower functional layer on the outer side of the first wafer includes: depositing the lower functional layer on the outer side surface of the first wafer; patterning the lower functional layer to remove the sealing ring sub-region located in the sealing region and the lower functional layer contacting the wall sub-region, and forming a sealing ring opening and a contacting wall opening; and the step of forming a seal ring in the seal ring opening and a contact wall in the contact wall opening, forming the through contact in the through contact opening, and forming the buffer through contact in the buffer through contact opening includes: depositing an insulating material to cover sidewalls and a bottom of the through contact opening and the buffer through contact opening; removing at least part of the insulating material at the bottom of the through contact opening and the buffer through contact opening to expose the upper surfaces of the sealing ring and the contact wall, respectively; and completely filling the through contact openings and the buffer through contact openings with a conductive material to form the through contacts and buffer through contacts.

In an embodiment of the present application, the step of forming the through contact in the through contact opening and the back isolation trench in the back isolation trench opening includes: depositing an insulating material to completely fill the back insulating trench opening and cover sidewalls and bottom of the through contact opening; removing at least a portion of the insulating material at the bottom of the through contact opening to expose an upper surface of the seal ring; and completely filling the through contact openings with a conductive material to form the through contacts.

In an embodiment of the present application, a width of the through contact opening is greater than a width of the back insulation trench opening.

In an embodiment of the present application, the method for manufacturing a memory further includes: an upper functional layer is formed on the middle functional layer.

In an embodiment of the present application, before forming the lower functional layer on the outer side of the first wafer, the method for manufacturing a memory further includes: providing a second wafer having an array of memory cells and an interconnect structure on an inner side; and bonding the inner side of the first wafer and the inner side of the second wafer to each other.

According to the memory of one embodiment of the application, the through contact and the buffer component (such as the buffer through contact) are formed on the middle functional layer, so that most of the stress generated when the cutting is carried out in the cutting track area is firstly absorbed by the sealing ring structure and the through contact in the sealing area, and then a small part of the stress which is transmitted to the chip area through the gap between the through contacts and is not absorbed is absorbed by the buffer component, so that the defect that the stress generated in the cutting process is transmitted to the chip area is effectively reduced through two times of stress absorption, and the production yield of the memory is improved.

According to the memory manufacturing method, the through contact and the buffer component are formed on the middle functional layer, therefore, most of the stress generated when the cutting is carried out in the cutting channel area is firstly absorbed by the sealing ring structure and the through contact in the sealing area, and then the small part of the stress which is transmitted to the chip area through the gap between the through contacts and is not absorbed is absorbed by the buffer component, so that the defect that the stress generated in the cutting process is transmitted to the chip area is effectively reduced through two times of stress absorption, and the production yield of the memory is improved.

Drawings

Fig. 1A is a schematic cross-sectional view of a memory according to an embodiment of the present application. Fig. 1B is a schematic plan view of the sealing region II of fig. 1A.

FIG. 2A is a cross-sectional view of a memory according to another embodiment of the present application. Fig. 2B is a schematic plan view of the sealing region II of fig. 2A.

Fig. 3 is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present application.

Fig. 4 is a schematic flow chart illustrating a process of forming a middle functional layer in a memory manufacturing method according to an embodiment of the present application.

Fig. 5A-5F are schematic cross-sectional views illustrating different stages of forming a middle functional layer in a memory manufacturing method according to another embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1A is a schematic cross-sectional view of a memory according to an embodiment of the present application. Fig. 1B is a schematic plan view of the sealing region II of fig. 1A.

As shown in fig. 1A and 1B, the memory of an embodiment of the present application may include: a first wafer 100 and a second wafer 200.

The first wafer 100 has an inner side and an outer side. Peripheral circuits are disposed on the inner side of the first wafer 100. The outer side surface of the first wafer 100 includes a dicing street region I, a sealing region II, and a chip region III. The material of the first wafer 100 may be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide, or other iii-v compounds.

The lower functional layer 101 is disposed on an outer side surface of the first wafer. The material of the lower functional layer may be an oxide, such as silicon oxide.

The middle functional layer has a multi-layer structure and is disposed on a side of the lower functional layer 101 away from the first wafer 100. Wherein the sealing area II of the middle functional layer has through contacts 1021 and a damping means. The cushioning component is embedded in at least a portion of the central functional layer, the embedded cushioning component being of a different material than the embedded central functional layer.

In this embodiment, for convenience of description, the middle functional layer of the two-layer structure will be described as an example, but the embodiments of the present application are not limited to the two-layer structure. Wherein, middle part functional layer includes: a first sub-central functional layer 102a and a second sub-central functional layer 102 b. The first sub-middle functional layer 102a is made of silicon; the material of the second sub-middle functional layer 102b may be an oxide, such as silicon oxide, which is the same as the material of the lower functional layer.

In this embodiment, the buffer member may include: at least one of the buffer through contact and the backside isolation trench. As shown in fig. 1A and 1B, in the present embodiment, the buffer member is a buffer through contact 1022. Specifically, the through contact 1021 and the buffer through contact 1022 penetrate the multilayer structure, i.e., the first sub-middle functional layer 102a and the second sub-middle functional layer 102 b.

The second wafer 200 has an array of memory cell strings and interconnect structures on the inner side. The material of the second wafer 200 may be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide, or other iii-v compounds.

The inner side of the first wafer 100 and the inner side of the second wafer 200 are bonded to each other. The inner side surface of the first wafer 100 and the inner side surface of the second wafer 200 face each other through a Vertical Interconnection Access (VIA) and are electrically connected to each other.

According to the memory of one embodiment of the application, the through contact and the buffer component (such as the buffer through contact) are formed on the middle functional layer, so that most of the stress generated when the cutting is carried out in the cutting track area is firstly absorbed by the sealing ring structure and the through contact in the sealing area, and then a small part of the stress which is transmitted to the chip area through the gap between the through contacts and is not absorbed is absorbed by the buffer component, so that the defect that the stress generated in the cutting process is transmitted to the chip area is effectively reduced through two times of stress absorption, and the production yield of the memory is improved.

Although the memory according to the embodiment of the present application has been described as an embodiment in which two wafers are bonded to each other and then cut, the embodiment of the present application is also applicable to a structure of one wafer.

In the memory according to an embodiment of the present application, the buffer through contact 1022 is located on the side (inner side) of the through contact 1021 near the chip region III; however, the buffer through contact 1022 may be located on a side (outer side) of the through contact 1021 remote from the chip region III, or two buffer through contacts 1022 may be provided and located on a side of the through contact 1021 close to the chip region III and a side remote from the chip region III, respectively. That is, the buffer through contact 1022 may be located on a side of the through contact 1021 close to the chip region III and/or a side far from the chip region III.

According to the memory of an embodiment of the present application, when the buffer through contact 1022 is located on the side of the through contact 1021 away from the chip region III, the stress generated during cutting is firstly absorbed by the buffer through contact of the sealing region; the unabsorbed stress, which is then transferred to the chip region III via the gap between the buffer through-contacts, is then absorbed by the seal ring structure and the through-contacts, so that two stress absorptions are achieved.

According to the memory of an embodiment of the present application, when two buffer through contacts 1022 are provided and located on the side close to the chip region III and the side far from the chip region III of the through contact 1021, the stress generated during cutting is firstly absorbed by the buffer through contact located on the outer side of the sealing region; the unabsorbed stress, which is then transmitted to the chip region III via the gap between the buffer through-contacts, is absorbed by the seal ring structure and the through-contacts; finally, the stress which is continuously transmitted to the chip region through the gap between the through contacts and is not absorbed is absorbed by the buffer part positioned on the inner side, so that the stress absorption is realized for three times, the defect that the stress generated in the cutting process is transmitted to the chip region is further effectively reduced, and the production yield of the memory is further improved.

Similarly, a single buffer through contact or a plurality of buffer through contacts may be provided on one or both sides of the through contact. At this time, the stress absorption is performed a plurality of times according to the number of the buffer through contacts.

In the memory according to an embodiment of the present application, the through contact 1021 and the buffer through contact 1022 may be staggered.

According to the memory of one embodiment of the present application, when the through contacts and the buffer through contacts are displaced from each other, the unabsorbed stress transmitted to the chip region through the gap between the through contacts is absorbed by the buffer through contacts; or conversely, unabsorbed stresses transmitted to the chip region via the gap between the buffer through-contacts are absorbed by the through-contacts.

In the memory of an embodiment of the present application, the buffer through contact may be located on a perpendicular bisector of two adjacent through contacts.

According to the memory of an embodiment of the present application, when the buffer through-contact is located on the perpendicular bisector of two adjacent through-contacts, since stress is most likely to be transferred from the middle between the through-contacts to the chip region, the buffer through-contact located on the perpendicular bisector of the two adjacent through-contacts can absorb the unabsorbed stress at an optimal position.

In the memory according to an embodiment of the present application, the buffer through contact 1022 and the through contact 1021 are made of the same material. That is, the buffer through contact 1022 and the through contact 1021 are formed simultaneously.

According to the memory of an embodiment of the present application, since the through contact 1021 and the buffer through contact 1022 are formed at the same time, the problems of the prior art are effectively solved without increasing the manufacturing cost.

In the memory according to an embodiment of the present application, the lower functional layer 101 has a seal ring 1011 in the seal region II. Wherein the seal rings 1011 and the through contacts 1022 are aligned and connected to each other.

In the memory according to an embodiment of the present application, the lower functional layer 101 has a contact wall 1012 in the sealing region II. Wherein the contact walls 1012 and the buffer through contacts 1022 are aligned and connected to each other.

In the memory according to an embodiment of the present application, the upper functional layer 103 is disposed on a side of the middle functional layer away from the first wafer. Wherein the material of the upper functional layer 103 may be a metal, such as aluminum.

The upper functional layer 103 has different patterns in the dicing street area I, the sealing area II, and the chip area III. In the dicing street region I and the seal region II, the upper functional layer 103 has no pattern; the upper functional layer 103 has a predetermined pattern in the chip region III. And the upper functional layer 103 of the scribe line region I, the upper functional layer 103 of the seal region II, and the upper functional layer 103 of the chip region III are isolated from each other.

In the memory according to an embodiment of the present application, an outer protective film is provided on the upper functional layer 103. Wherein the material of the outer protective film may be a nitride, such as silicon nitride.

FIG. 2A is a cross-sectional view of a memory according to another embodiment of the present application. Fig. 2B is a schematic plan view of the sealing region II of fig. 2A. As shown in fig. 2A and 2B, the memory of another embodiment of the present application may include: a first wafer 100 and a second wafer 200.

The first wafer 100 has an inner side and an outer side. Peripheral circuits are disposed on the inner side of the first wafer 100. The outer side surface of the first wafer 100 includes a dicing street region I, a sealing region II, and a chip region III. The material of the first wafer 100 may be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide, or other iii-v compounds.

The lower functional layer 101 is disposed on an outer side surface of the first wafer. The material of the lower functional layer may be an oxide, such as silicon oxide.

The middle functional layer has a multi-layer structure and is disposed on a side of the lower functional layer 101 away from the first wafer 100. Wherein the sealing area II of the middle functional layer has through contacts 1021 and a damping means.

In this embodiment, for convenience of description, the middle functional layer of the two-layer structure will be described as an example, but the embodiments of the present application are not limited to the two-layer structure. Wherein, middle part functional layer includes: a first sub-central functional layer 102a and a second sub-central functional layer 102 b. The first sub-middle functional layer 102a is made of silicon; the material of the second sub-middle functional layer 102b may be an oxide, such as silicon oxide, which is the same as the material of the lower functional layer.

In this embodiment, the buffer member may include: at least one of the buffer through contact and the backside isolation trench. As shown in fig. 2A and 2B, in the present embodiment, the buffer member is a back insulation trench 1023. Specifically, the through contact 1021 penetrates the multilayer structure, i.e., the first sub-central functional layer 102a and the second sub-central functional layer 102 b; the backside insulation trench 1023 penetrates at least one layer of the multilayer structure adjacent to the lower functional layer 101, i.e., the second sub-middle functional layer 102 b.

The second wafer 200 has an array of memory cell strings and interconnect structures on the inner side. The material of the second wafer 200 may be monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide, or other iii-v compounds.

The inner side of the first wafer 100 and the inner side of the second wafer 200 are bonded to each other. The inner side surface of the first wafer 100 and the inner side surface of the second wafer 200 face each other through a Vertical Interconnection Access (VIA) and are electrically connected to each other.

According to the memory of another embodiment of the present application, the through contact and the buffer member (e.g., the back insulation trench) are formed on the middle functional layer, so that most of the stress generated when the dicing is performed in the dicing street region is first absorbed by the seal ring structure and the through contact in the seal region, and then a small part of the stress which is not absorbed and is transferred to the chip region through the gap between the through contacts is absorbed by the buffer member, thereby effectively reducing the defect that the stress generated during the dicing is transferred to the chip region through two times of stress absorption, and improving the yield of the memory.

Although the memory according to another embodiment of the present application has been described as an embodiment in which two wafers are bonded to each other and then cut, the memory according to another embodiment of the present application can be applied to a structure of one wafer.

In the memory according to another embodiment of the present application, the backside insulation trench 1023 is located at the side (outside) of the through contact 1021 away from the chip region III; however, back insulation groove 1023 may be located on the side (inner side) of through contact 1021 near chip region III, or two back insulation grooves 1023 may be provided and located on the side of through contact 1021 near chip region III and the side of through contact 1021 remote from chip region III, respectively. That is, the back insulation trench 1023 may be located at a side of the through contact 1021 close to the chip region III and/or a side far from the chip region III.

In the memory according to another embodiment of the present application, the backside insulation trench 1023 is formed in the process of forming the through contact 1021.

According to the memory of another embodiment of the present application, since the backside insulation trench 1023 is formed in the process of forming the through contact 1021, the problems of the prior art are effectively solved without causing an increase in manufacturing cost.

In the memory according to an embodiment of the present application, the upper functional layer 103 is disposed on a side of the middle functional layer away from the first wafer. Wherein the material of the upper functional layer 103 may be a metal, such as aluminum.

The upper functional layer 103 has different patterns in the dicing street area I, the sealing area II, and the chip area III. In the dicing street region I and the seal region II, the upper functional layer 103 has no pattern; the upper functional layer 103 has a predetermined pattern in the chip region III. And the upper functional layer 103 of the scribe line region I, the upper functional layer 103 of the seal region II, and the upper functional layer 103 of the chip region III are isolated from each other.

In the memory according to an embodiment of the present application, an outer protective film is provided on the upper functional layer 103. Wherein the material of the outer protective film may be a nitride, such as silicon nitride.

Although the case when the buffer member is the buffer through contact and the back insulation trench is described by the memory of an embodiment of the present application and the memory of another embodiment of the present application, respectively, the two embodiments may be organically combined. Specifically, when the number of the buffer parts is two and the buffer parts are respectively positioned at two sides of the through contact, the buffer part at the inner side of the through contact is a buffer through contact, and the buffer part at the outer side of the through contact is a back insulation groove; conversely, the buffer member inside the through contact is a back insulation groove, and the buffer member outside the through contact is a buffer through contact.

Fig. 3 is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present application. The memory manufacturing method of an embodiment of the present application may include:

step 301, providing a first wafer having an inner side and an outer side, wherein a peripheral circuit is formed on the inner side of the first wafer, and the outer side of the first wafer includes a scribe line region, a seal region and a chip region;

step 302, providing a second wafer having a memory cell array and an interconnect structure on an inner side;

step 303, bonding the inner side surface of the first wafer and the inner side surface of the second wafer to each other;

step 304, forming a lower functional layer on the outer side surface of the first wafer; and

step 305, forming a middle functional layer of a multilayer structure on the lower functional layer, wherein the middle functional layer has a through contact and a buffer component in the sealing area. The cushioning component is embedded in at least a portion of the central functional layer, the embedded cushioning component being of a different material than the embedded central functional layer.

According to the memory manufacturing method, the through contact and the buffer component are formed on the middle functional layer, therefore, most of the stress generated when the cutting is carried out in the cutting channel area is firstly absorbed by the sealing ring structure and the through contact in the sealing area, and then the small part of the stress which is transmitted to the chip area through the gap between the through contacts and is not absorbed is absorbed by the buffer component, so that the defect that the stress generated in the cutting process is transmitted to the chip area is effectively reduced through two times of stress absorption, and the production yield of the memory is improved.

Although the memory manufacturing method according to the embodiment of the present invention is described as an embodiment in which two wafers are bonded to each other and then cut, the embodiment of the present invention is also applicable to a structure of one wafer.

In the memory manufacturing method according to an embodiment of the present application, there is no strict order between step 301 and step 302, that is, as shown in an embodiment of the present application, step 301 may be executed first, and then step 302 may be executed; step 302 may be performed first, and then step 301 may be performed.

In the method for manufacturing a memory according to an embodiment of the present application, when the first wafer having the inner side and the outer side is provided (step 301), the material of the first wafer may be a iii-v compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide.

In the memory manufacturing method according to an embodiment of the present application, when the second wafer having the memory cell string composed of the gate stack structure on the inner side is provided (step 302), the material of the second wafer may be a iii-v compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), Silicon On Insulator (SOI), Germanium On Insulator (GOI), or gallium arsenide.

In the method for manufacturing a memory according to an embodiment of the present application, when the inner side of the first wafer and the inner side of the second wafer are bonded to each other (step 303), the inner sides of the first wafer and the second wafer are bonded to each other through Vertical Interconnection Access (VIA), so that the inner sides of the first wafer and the second wafer face each other and are electrically connected to each other.

In the memory manufacturing method according to an embodiment of the present application, when the lower functional layer is formed on the outer side of the first wafer (step 304), a material of the lower functional layer may be an oxide, such as silicon oxide.

Fig. 4 is a schematic flow chart illustrating a process of forming a middle functional layer in a memory manufacturing method according to an embodiment of the present application. As shown in fig. 4, in the memory manufacturing method according to an embodiment of the present application, the step of forming a middle functional layer of a multi-layer structure on the lower functional layer (i.e., step 305) may include:

3051, depositing a first middle sub-functional layer and a second middle sub-functional layer on the lower functional layer in sequence;

step 3052, patterning said first middle sub-functional layer and said second middle sub-functional layer to remove said first middle sub-functional layer and said second middle sub-functional layer of said seal region through contact sub-regions and buffer component sub-regions to form through contact openings and buffer component openings;

step 3053, forming the through contact in the through contact opening and forming the buffer member in the buffer member opening.

In this embodiment, for convenience of description, the middle functional layer of the two-layer structure will be described as an example, but the embodiments of the present application are not limited to the two-layer structure. In step 3051, the material of the first sub-middle functional layer 102a is silicon. The material of the second sub-middle functional layer 102b may be an oxide, such as silicon oxide, which is the same as the material of the lower functional layer.

In the memory manufacturing method according to an embodiment of the present application, when the first and second middle sub-functional layers are patterned to remove the through-contact sub-region of the seal region and the first and second middle sub-functional layers of the buffer member sub-region (step 3052), the buffer member sub-region may be located at a side (inner side) of the through-contact sub-region close to the chip region and/or a side (outer side) far from the chip region.

In the memory manufacturing method according to an embodiment of the present application, when patterning the first and second middle sub-functional layers to remove the first and second middle sub-functional layers of the seal region through-contact sub-region and the buffer member sub-region (step 3052), the buffer member sub-region may include: at least one of the buffered through contact sub-region and the backside insulated trench sub-region.

In the memory manufacturing method of an embodiment of the present application, when the buffer member is a buffer through contact, the forming the through contact in the through contact opening, and the forming the buffer member in the buffer member opening may include:

depositing an insulating material to cover sidewalls and a bottom of the through contact opening and the buffer through contact opening;

removing at least part of the insulating material at the bottom of the through contact opening and the buffer through contact opening to expose the upper surfaces of the sealing ring and the contact wall, respectively; and

completely filling the through contact openings and the buffer through contact openings with a conductive material to form the through contacts and buffer through contacts.

In the memory manufacturing method of an embodiment of the present application, when the buffer member is a back insulation trench, the forming the through contact in the through contact opening and the forming the buffer member in the buffer member opening may include:

depositing an insulating material to completely fill the back insulating trench opening and cover sidewalls and bottom of the through contact opening;

removing at least a portion of the insulating material at the bottom of the through contact opening to expose an upper surface of the seal ring; and

completely filling the through contact openings with a conductive material to form the through contacts.

In the memory manufacturing method according to an embodiment of the present application, the insulating material is the same as the material of the second middle sub-functional layer

According to the memory manufacturing method of the embodiment of the application, when the buffer component sub-region is the buffer through contact sub-region and is positioned at the outer side of the through contact sub-region, a buffer through contact positioned at the outer side of the through contact is formed, and the stress generated during cutting is firstly absorbed by the buffer through contact of the sealing region; the unabsorbed stress, which is then transferred to the chip region III via the gap between the buffer through-contacts, is then absorbed by the seal ring structure and the through-contacts, so that two stress absorptions are achieved.

According to the memory manufacturing method of the embodiment of the application, when the buffer component sub-region is the buffer through contact sub-region and is positioned at the inner side and the outer side of the through contact sub-region, two buffer through contacts positioned at the inner side and the outer side of the through contact are formed, and the stress generated during cutting is firstly absorbed by the buffer through contact positioned at the outer side of the sealing region; the unabsorbed stress transmitted to the chip region through the gap between the buffer through-contacts is then absorbed by the seal ring structure and the through-contacts; finally, the stress which is continuously transmitted to the chip region through the gap between the through contacts and is not absorbed is absorbed by the buffer part positioned on the inner side, so that the stress absorption is realized for three times, the defect that the stress generated in the cutting process is transmitted to the chip region is further effectively reduced, and the production yield of the memory is further improved.

Likewise, one or more buffer member sub-regions may be formed on one or both sides of the through contact sub-region. At this time, the stress absorption is performed a plurality of times according to the number of the buffer member sub-regions provided.

In the memory manufacturing method according to an embodiment of the present application, when the buffer member opening includes a buffer through contact opening, the step of patterning the first middle sub-functional layer and the second middle sub-functional layer (step 3052) may be: patterning the first middle sub-functional layer and the second middle sub-functional layer to remove the first middle sub-functional layer and the second middle sub-functional layer of the through contact sub-region and the buffer component sub-region of the sealing region, and form a through contact opening and a buffer through contact opening, so that the through contact opening and the buffer through contact opening are staggered with each other.

According to the memory manufacturing method of one embodiment of the present application, when the through contact opening and the buffer through contact opening are displaced from each other, the formed through contact and the buffer through contact are also displaced from each other, and at this time, the stress that is transmitted to the chip region through the gap between the through contacts and that is not absorbed is absorbed by the buffer through contact; or conversely, unabsorbed stresses transmitted to the chip region via the gap between the buffer through-contacts are absorbed by the through-contacts.

In the memory manufacturing method according to an embodiment of the present application, when the through contact openings and the buffer through contact openings are staggered from each other, the patterning of the first middle sub-functional layer and the second middle sub-functional layer (step 3052) may be: and patterning the first middle sub-functional layer and the second middle sub-functional layer to remove the first middle sub-functional layer and the second middle sub-functional layer of the through contact sub-area and the buffer component sub-area of the sealing area, and form a through contact opening and a buffer through contact opening, so that the buffer through contact opening is positioned on a perpendicular bisector between two adjacent through contact openings.

According to the memory manufacturing method of the embodiment of the present application, when the buffer through contact opening is located on the perpendicular bisector of two adjacent through contact openings, the formed buffer through contact is also located on the perpendicular bisector of two adjacent through contacts, and at this time, since the stress is most likely to be transmitted from the middle between the through contacts to the chip region, the buffer through contact located on the perpendicular bisector of two adjacent through contacts can absorb the stress which is not absorbed at the optimal position.

In the memory manufacturing method according to an embodiment of the present application, when the buffer member opening is a buffer through contact opening, the step of forming a lower functional layer on the outer side surface of the first wafer (step 304) may include:

depositing the lower functional layer on the outer side surface of the first wafer;

patterning the lower functional layer to remove the sealing ring sub-region located in the sealing region and the lower functional layer contacting the wall sub-region, and forming a sealing ring opening and a contacting wall opening; and

a sealing ring is formed in the sealing ring opening and a contact wall is formed in the contact wall opening.

According to the memory manufacturing method of the embodiment of the application, when the buffer through contact is formed on the contact wall, the transmitted stress can be absorbed through the combined structure of the buffer through contact and the contact wall, so that the absorption effect is improved.

In the memory manufacturing method according to an embodiment of the present application, after forming the middle functional layer of the multi-layer structure on the lower functional layer (step 305), the method may further include: an upper functional layer is formed on the middle functional layer. Wherein the material of the upper functional layer 103 may be a metal, such as aluminum. The upper functional layer has different patterns in the dicing street region, the sealing region, and the chip region. In the cutting path area and the sealing area, the upper functional layer has no pattern; the functional layer has a predetermined pattern on the upper portion of the chip region. And the upper functional layer of the dicing street region, the upper functional layer of the sealing region and the upper functional layer of the chip region are isolated from each other.

In the memory manufacturing method according to an embodiment of the present application, after forming the upper functional layer on the middle functional layer, the method may further include: an outer protective film is formed on the upper functional layer. Wherein the material of the outer protective film may be a nitride, such as silicon nitride.

Fig. 5A-5F are schematic cross-sectional views illustrating different stages of forming a middle functional layer in a memory manufacturing method according to another embodiment of the present application. In the memory manufacturing method according to another embodiment of the present application, the buffer through contact and the back insulation trench are simultaneously formed for convenience of description, but the embodiment of the present application is not limited thereto.

As shown in fig. 5A, in a memory manufacturing method according to another embodiment of the present application, a lower functional layer 101 is formed on an outer side surface of a first wafer. A sealing ring 1011 and a contact wall 1012 are formed in the sealing area of the lower functional layer 101, respectively. After the lower functional layer 101 is formed, a first sub-middle functional layer 102a and a second sub-middle functional layer 102b are sequentially deposited. Wherein the material of the first sub-middle functional layer 102a may be silicon. The material of the second sub-middle functional layer 102b may be an insulating material. In the memory manufacturing method according to another embodiment of the present application, the material of the second sub-middle functional layer 102b is an oxide, such as silicon oxide.

In the memory manufacturing method according to another embodiment of the present disclosure, the Deposition method may be Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like.

After the first sub-middle functional layer 102a and the second sub-middle functional layer 102b are sequentially deposited, a photoresist 109 is coated, and then the photoresist 109 is exposed and developed to expose predetermined regions, i.e., a buffer through contact sub-region for forming a buffer through contact and a back insulation trench sub-region for forming a back insulation trench. At this time, the width of the back insulation trench sub-region is smaller than the width of the through contact sub-region, and the width of the back insulation trench sub-region is smaller than the width of the buffer through contact sub-region.

As shown in fig. 5B, the first sub-middle functional layer 102a and the second sub-middle functional layer 102B are sequentially removed by an etching method, thereby exposing the structure of the lower functional layer 101. Specifically, the contact wall 1012 is exposed in the buffer through contact region to form a buffer through contact opening, and the lower functional layer 101 is exposed in the back insulation trench region to form a back insulation trench opening.

In the memory manufacturing method according to another embodiment of the present application, the etching method may be an anisotropic etching method, such as dry etching, for example, ion milling etching, plasma etching, reactive ion etching, laser etching, and the like.

As shown in fig. 5C, an insulating material is deposited by a deposition method in the through contact sub-region, the buffer through contact sub-region and the backside insulating trench sub-region. The insulating material may be the same as the material of the second sub-middle functional layer 102b, and is, for example, silicon oxide.

Since the width of the back insulation trench sub-region is smaller than the width of the through contact sub-region, and the width of the back insulation trench sub-region is smaller than the width of the buffer through contact sub-region, the width of the formed back insulation trench opening is smaller than the width of the through contact opening and the width of the buffer through contact opening respectively. The back insulation trench opening is filled with silicon oxide, and a silicon oxide layer is formed in the through contact opening and the buffer through contact opening. At this time, a back insulation trench is formed in the back insulation trench opening sub-region.

After the formation of the silicon oxide layer, the silicon oxide layer formed at the bottom of the through contact opening and the buffer through contact opening is etched, exposing the sealing rings 1011 of the through contact opening and the contact walls 1012 of the buffer through contact opening, as shown in fig. 5D. The etching may be dry etching.

After exposing the sealing rings 1011 of the through contact openings and the contact walls 1012 of the buffer through contact openings, a metallic material, for example tungsten, is deposited in the through contact openings and the buffer through contact openings, as shown in fig. 5E. In this case, tungsten hexafluoride may be used as a tungsten source, and silane or diborane may be used as a reducing substance.

As shown in fig. 5F, after depositing the metal material through the contact openings and the buffer through contact openings, the metal material (e.g., tungsten) above the middle functional layer is removed, leaving only the metal material of the through contact openings and the metal material of the buffer through contact openings, thereby forming through contacts and buffer through contacts.

The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.