阅读说明：本技术 埋入式磁阻式存储器结构及其制作方法 (Embedded magnetic resistance type memory structure and manufacturing method thereof ) 是由 李国兴 薛胜元 黄鼎翔 于 2019-11-08 设计创作，主要内容包括：本发明公开一种埋入式磁阻式存储器结构及其制作方法,其中该埋入式磁阻式存储器结构包含一基底划分为一存储器区和一逻辑元件区,一主动区域设置于基底的存储器区,一字符线设置于基底上并且与主动区域交错,一源极插塞设置于主动区域内并且位于字符线的一侧,一漏极插塞设置于主动区域并且位于字符线的另一侧,其中由垂直基底的上表面的方向观看,字符线为对称轴,源极插塞为漏极插塞的镜像。(The invention discloses an embedded magnetic resistance type memory structure and a manufacturing method thereof, wherein the embedded magnetic resistance type memory structure comprises a substrate divided into a memory area and a logic element area, an active area is arranged in the memory area of the substrate, a character line is arranged on the substrate and is staggered with the active area, a source plug is arranged in the active area and is positioned at one side of the character line, a drain plug is arranged in the active area and is positioned at the other side of the character line, wherein the character line is a symmetrical shaft when viewed from the direction vertical to the upper surface of the substrate, and the source plug is a mirror image of the drain plug.)

1. A buried magnetoresistive memory structure, comprising:

a substrate divided into a memory area and a logic element area;

an active region disposed in the memory region of the substrate;

a first word line disposed on the substrate and crossing the active region;

a source plug contacting the active region and located at one side of the first word line;

a drain plug contacting the active region and located at the other side of the first word line, wherein the source plug is a mirror image of the drain plug when viewed from a direction perpendicular to the upper surface of the substrate, taking the first word line as a symmetry axis;

a first source metal layer contacting the source plug and a first drain metal layer contacting the drain plug;

a first source through hole plug contacts the first source metal layer, and a first drain through hole plug contacts the first drain metal layer;

a source line contacting the first source via plug and a second drain metal layer contacting the first drain via plug, wherein an upper surface of the source line and an upper surface of the second drain metal layer are aligned;

a tungsten plug contacting the second drain metal layer;

a magnetic resistance type memory unit contacting the tungsten plug;

a third drain via plug contacting the magnetoresistive memory cell; and

and a bit line contacting the third drain via plug.

2. The structure of claim 1, wherein the source plug and the drain plug are elongated.

3. The structure of claim 1, further comprising a plurality of source plugs disposed in the active region and a plurality of drain plugs disposed in the active region.

4. The structure of claim 1, further comprising a logic device and a metal interconnect commonly disposed in the logic device region, wherein the logic device comprises: a second word line disposed on the substrate, a doped region disposed in the substrate and on a side of the second word line, a plug contacting the doped region, the metal interconnect comprising: the first metal layer contacts the plug, the first via plug contacts the first metal layer, the second metal layer contacts the first via plug, the second via plug contacts the second metal layer, the third metal layer contacts the second via plug, the third via plug contacts the third metal layer, and the fourth metal layer contacts the third via plug, wherein the upper surface of the second metal layer is flush with the upper surface of the source line, the upper surface of the second via plug is flush with the upper surface of the tungsten plug, the upper surface of the third metal layer is flush with the upper surface of the mram, and the upper surface of the fourth metal layer is flush with the upper surface of the bit line.

5. The structure of claim 1, wherein the drain plug, the first drain metal layer, the first drain via plug, the second drain metal layer, the tungsten plug, the mram cell, the third drain via plug and the bit line are sequentially stacked from bottom to top.

6. The structure of claim 1, wherein the source plug, the first source metal layer, the first source via plug and the source line are sequentially stacked from bottom to top.

7. The structure of claim 1, wherein the first drain metal layer, the first drain via plug, the second drain metal layer, the third drain via plug, the bit line, the first source metal layer, the first source via plug, and the source line comprise copper.

8. A method for fabricating a buried magnetoresistive memory structure, comprising:

providing a substrate divided into a memory area and a logic element area, wherein an active area is arranged in the memory area of the substrate, and first character lines are arranged on the substrate and are staggered with the active area;

forming a source plug and a drain plug, wherein the source plug contacts the active region and is located at one side of the first word line, the drain plug contacts the active region and is located at the other side of the first word line, and the source plug is a mirror image of the drain plug when viewed from a direction perpendicular to the upper surface of the substrate, with the first word line as an axis of symmetry;

simultaneously forming a first source metal layer contacting the source plug and a first drain metal layer contacting the drain plug;

simultaneously forming a first source via plug in contact with the first source metal layer and a first drain via plug in contact with the first drain metal layer;

simultaneously forming a source line contacting the first source via plug and a second drain metal layer contacting the first drain via plug, wherein an upper surface of the source line and an upper surface of the second drain metal layer are aligned;

forming a tungsten plug to contact the second drain metal layer;

forming a magnetic resistance type memory unit to contact the tungsten plug;

forming a third drain via plug to contact the magnetoresistive memory cell; and

forming a bit line contacting the third drain via plug.

9. The method as claimed in claim 8, further comprising a logic device disposed in the logic device region, the logic device comprising a second word line disposed on the substrate, and a doped region disposed in the substrate and located at one side of the second word line.

10. The method of claim 9, further comprising forming metal interconnects in the logic device region, wherein the forming of the metal interconnects comprises:

forming a first metal layer contact plug in the logic element region while forming the first drain metal layer, wherein the plug contacts the doped region;

forming a first via plug in the logic device region to contact the first metal layer while forming the first drain via plug;

forming a second metal layer in the logic element region to contact the first via plug when the second drain metal layer is formed;

forming a second via plug in the logic device region to contact the second metal layer;

forming a third metal layer in the logic device region to contact the second via plug;

forming a third via plug in the logic device region to contact the third metal layer while forming the third drain via plug; and

and forming a fourth metal layer in the logic element region to contact the third via plug, wherein the upper surface of the fourth metal layer is aligned with the upper surface of the bit line.

Technical Field

The present invention relates to a buried magnetoresistive memory structure and a method for fabricating the same, and more particularly, to a memory structure having a source line and a second metal layer aligned with each other and a method for fabricating the same.

Background

Many modern electronic devices have electronic memory. The electronic memory may be a volatile memory or a non-volatile memory. Non-volatile memories can retain stored data even in the absence of power, while volatile memories lose their stored data when power is removed. Magnetoresistive Random Access Memory (MRAM) is expected to have great potential for further generations of non-volatile memory technology due to its superior characteristics over current electronic memories.

Magnetoresistive random access memories do not store bit information with conventional charges, but rather store data with magnetic resistance effects. Structurally, an mram includes a data layer (data layer) and a reference layer (reference layer), wherein the data layer is made of a magnetic material and is switchable between two opposite magnetic states by an applied magnetic field during a write operation for storing bit information. The reference layer is usually made of a magnetic material with a fixed magnetic state and is difficult to be changed by an external magnetic field.

However, there are still many drawbacks in the conventional mram fabrication process that require further improvement. For example, the integration of a standard type magnetoresistive random access memory is improved. Therefore, there is still a need in the art for an improved method of manufacturing a mram device to solve the aforementioned problems.

Disclosure of Invention

The present invention provides a magnetoresistive memory structure in which the source line is disposed at the same level as the second metal layer of the logic device region.

According to a preferred embodiment of the present invention, an embedded magnetoresistive memory structure comprises a substrate divided into a memory region and a logic device region, an active (active) region disposed in the memory region of the substrate, a word line disposed on the substrate and interleaved with the active region, a source plug contacting the active region and located at one side of the word line, a drain plug contacting the active region and located at the other side of the word line, wherein the word line is a symmetry axis viewed from a direction perpendicular to the upper surface of the substrate, the source plug is a mirror image of the drain plug, a first source metal layer contacting the source plug, a first drain metal layer contacting the drain plug, a first source via plug contacting the first source metal layer, a first drain via plug contacting the first drain metal layer, a source line contacting the first source via plug, a second drain metal layer contacting the first drain via plug, the upper surface of the source line is flush with the upper surface of the second drain metal layer, a tungsten plug contacts the second drain metal layer, a magnetoresistive memory unit contacts the tungsten plug, a third drain through-hole plug contacts the magnetoresistive memory unit, and a bit line contacts the third drain through-hole plug.

According to another preferred embodiment of the present invention, a method for fabricating an embedded magnetoresistive memory structure includes providing a substrate divided into a memory region and a logic device region, an active region disposed in the memory region of the substrate, a first word line disposed on the substrate and interleaved with the active region, forming a source plug and a drain plug, the source plug contacting the active region and located at one side of the first word line, the drain plug contacting the active region and located at the other side of the first word line, wherein viewed from a direction perpendicular to the upper surface of the substrate, the first word line is a symmetry axis, the source plug is a mirror image of the drain plug, simultaneously forming a first source metal layer contacting the source plug and a first drain metal layer contacting the drain plug, and then simultaneously forming a first source via plug contacting the first source metal layer and a first drain via plug contacting the first drain metal layer, and then simultaneously forming a source line contacting the first source through hole plug and a second drain metal layer contacting the first drain through hole plug, wherein the upper surface of the source line and the upper surface of the second drain metal layer are aligned, then forming a tungsten plug contacting the second drain metal layer, forming a magnetoresistive memory unit contacting the tungsten plug, forming a third drain through hole plug contacting the magnetoresistive memory unit, and finally forming a bit line contacting the third drain through hole plug.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Drawings

Fig. 1 to 8 are schematic views illustrating a method for fabricating a buried magnetoresistive memory structure according to a preferred embodiment of the invention, wherein:

FIG. 2 is a schematic side view of FIG. 1 taken along cut lines AA 'and BB';

FIG. 3 is a schematic diagram of the subsequent steps of the fabrication process of FIG. 1;

FIG. 4 is a schematic side view of FIG. 3 taken along tangent lines CC 'and DD';

FIG. 5 is a schematic diagram of the manufacturing process steps following FIG. 3;

FIG. 6 is a schematic side view of FIG. 5 taken along tangent line EE 'and tangent line FF';

FIG. 7 is a schematic diagram of the manufacturing process steps following FIG. 5;

FIG. 8 is a schematic side view of the FIG. 7 view taken along tangent lines GG 'and HH';

fig. 9 is a schematic diagram illustrating a layout of source plugs and drain plugs according to another preferred embodiment of the present invention;

fig. 10 is a schematic diagram illustrating a layout of source plugs and drain plugs according to still another preferred embodiment of the invention.

Description of the main elements

10 upper surface of substrate 11

12 active region 14 insulating layer

16 doped region 18 doped region

20 source plug 22 drain plug

24 plug 50 embedded magnetoresistive memory

60 logic device 70 metal interconnect

100 buried magnetoresistive memory BL bit line

Structure of the product

L logic element area M memory area

M1 first Metal layer M1d first Drain Metal layer

M1S first Source Metal layer M2 second Metal layer

M2d second drain Metal layer M3 third Metal layer

M4 fourth metal layer MTJ magnetic resistance type memory unit

V1 first via plug V1d first drain via plug

V1S first source via plug V2 second via plug

V3 third via plug V3d third drain via plug

SL source line W tungsten plug

WL1 word line WL2 word line

WL3 virtual character line X region

Y region Z region

Detailed Description

Fig. 1 to 8 are schematic views illustrating a method for fabricating a buried magnetoresistive memory structure according to a preferred embodiment of the invention. Fig. 2 is a schematic side view of fig. 1 taken along the cut lines AA 'and BB'.

As shown in fig. 1, a substrate 10 is first divided into a memory region M and a logic device region L, a plurality of active (active) regions 12 are disposed on the substrate 10, insulator layers 14 are disposed between the active regions 12 to isolate adjacent active regions 12, a plurality of word lines WL1/WL2 are disposed on the substrate 10, and each word line WL1/WL2 crosses the active region 12, dummy (dummy) word lines WL3 may be disposed between the word lines WL1/WL2 depending on the design of the circuit layout. P-type or N-type dopants are then implanted on both sides of the word lines WL1/WL2 and dummy (dummy) word lines WL3 to form a plurality of doped regions 16/18, each doped region 16/18 being located in the active region 12. The plurality of word lines WL1/WL2, the plurality of active regions 12, and the plurality of doped regions 16/18 will form a plurality of buried magnetoresistive memories and a plurality of logic elements in the following, which will be described in the following with reference to the fabrication of a single buried magnetoresistive memory and a single logic element.

Referring to fig. 1 and 2, the region X in fig. 1 indicates the range where a single embedded mram will be disposed, and the region Y indicates the range where a single logic device will be disposed, where two source plugs 20 and two drain plugs 22 are formed at the same time, and two plugs 24 are also formed at the same time. The source plug 20 is disposed in the active region 12 of the memory region M, contacts the doped region 16 and is located at one side of the word line WL1, the drain plug 22 is disposed in the active region 12 of the memory region M, contacts the doped region 16 and is located at the other side of the word line WL1, and the plug 24 is disposed in the logic region L, contacts the doped region 18 and is located at both sides of the word line WL 2. The number of the source plugs 20 may be more than two, and the number of the drain plugs 22 may be more than two. Referring to fig. 1 and 2, it is noted that, when viewed from a direction perpendicular to the upper surface 11 of the substrate 10 and taking the word line WL1 as a symmetry axis, the source plugs 20 are mirror images of the drain plugs 22, that is, when viewed from a direction perpendicular to the upper surface 11 of the substrate 10, the positions of the source plugs 20 and the positions of the drain plugs 22 are symmetrically arranged and taken by taking the word line WL1 as a symmetry axis.

Fig. 9 is a layout of source plugs and drain plugs according to another preferred embodiment of the present invention. Fig. 10 is a layout of source plugs and drain plugs according to still another preferred embodiment of the present invention. Elements having the same function and the same position in fig. 9 and 10 will be referred to by the reference numerals of the elements in fig. 1, and the description of the related elements refers to the description of fig. 1. Fig. 9 and 10 are changed from fig. 1 only in the shape and number of source and drain plugs.

The difference between fig. 9 and fig. 1 is that the source plug 20 and the drain plug 22 in fig. 9 are elongated, and the area occupied by the elongated source plug 20 is larger than that occupied by the single source plug 20 in fig. 1, and the area occupied by the elongated drain plug 22 is larger than that occupied by the single drain plug 22 in fig. 1. The difference between fig. 10 and fig. 1 is that the number of the source plugs 20 and the drain plugs 22 of fig. 10 are both single, however, the source plugs 20 of fig. 1 and the source plugs 20 of fig. 10 are the same size, and the drain plugs 22 of fig. 1 and the drain plugs 22 of fig. 10 are the same size. Similar to the embodiment shown in fig. 1, fig. 9 and 10 are viewed from a direction perpendicular to the upper surface 11 of the substrate 10 (see fig. 2 for the position of the upper surface 11), with the word line WL1 as the axis of symmetry, and the source plug 20 as the mirror image of the drain plug 22.

Fig. 3 is a schematic side view of the manufacturing process of fig. 1, and fig. 4 is a schematic side view of the manufacturing process of fig. 3 along a cut line CC 'and a cut line DD'. Referring to fig. 3 and 4, a first source metal layer M1S is formed in the memory region M to contact the source plug 20 and a first drain metal layer M1d is formed to contact the drain plug 22, and a first metal layer M1 is formed in the logic device region L to contact the drain plug 24, in other words, the first source metal layer M1S, the first drain metal layer M1d and the first metal layer M1 are formed in the same metal deposition step, for example, by a copper damascene process, and the upper surfaces of the first source metal layer M1S, the first drain metal layer M1d and the first metal layer M1 are all aligned with each other. Then, a first source via plug V1S is formed in the memory region M to contact the first source metal layer M1S and a first drain via plug V1d is formed in the memory region M to contact the first drain metal layer M1d, and a first via plug V1 is formed in the logic device region L to contact the plug 24. The first source via plug V1S, the first drain via plug V1d, and the first via plug V1 are formed by the same metal deposition process, such as a copper damascene process. As shown in fig. 3, the positions of the first source via plug V1S and the first drain via plug V1d are viewed from a direction perpendicular to the upper surface 11 of the substrate 10 (see fig. 2 for the position of the upper surface 11), and the first source via plug V1S and the first drain via plug V1d are asymmetrically arranged with the word line WL1 as a symmetry axis.

Fig. 5 is a schematic side view of fig. 5 taken along cutting line EE 'and cutting line FF', continuing from the manufacturing process steps of fig. 3. As shown in fig. 5 and 6, a source line SL and a second drain metal layer M2d are formed in the memory region M at the same time, the source line SL contacts the first source via plug V1S, the second drain metal layer M2d contacts the first drain via plug V1d, a second metal layer M2 contacts the first via plug V1 is formed in the logic device region L at the same time, the upper surfaces of the source line SL, the second drain metal layer M2d and the second metal layer M2 are cut to be uniform, and the source line SL, the second drain metal layer M2d and the second metal layer M2 are formed by the same metal deposition process, for example, by a copper damascene process. Referring to fig. 5, the source lines SL electrically connect a plurality of magnetoresistive memories at the same time, for example, the source lines SL electrically connect the magnetoresistive memories to be disposed in the region X and the magnetoresistive memories to be disposed in the region Z. In detail, since the structures of the respective buried magnetoresistive memories are the same, all the magnetoresistive memories have the same structure as the magnetoresistive memory in the region X, and therefore the source line SL directly contacts the first source via plug V1S in different magnetoresistive memories in the same row (row).

Fig. 7 is a schematic side view of the process steps of fig. 5, and fig. 8 is a schematic side view of the process steps taken along the cut lines GG 'and HH' in fig. 7. As shown in fig. 7 and 8, a tungsten plug W is formed in the memory region M to contact the second drain metal layer M2d, a second via plug V2 is formed in the logic element region L to contact the second metal layer M2, wherein the upper surface of the tungsten plug W is aligned with the upper surface of the second via plug V2, then a magnetoresistive memory cell MTJ is formed in the memory region M to contact the tungsten plug W, and a third metal layer M3 is formed in the logic element region L to contact the second via plug V2. Then, a third drain via plug V3d and a third via plug V3 are formed at the same time, the third drain via plug V3d contacts the mram cell MTJ, the third via plug V3 contacts the third metal layer M3, and the third drain via plug V3d and the third via plug V3 are formed by the same metal deposition step, for example, by a copper damascene process, so that the upper surface of the third drain via plug V3d and the upper surface of the third via plug V3 are cut to be flush.

Then, a bit line BL is formed in the memory region M and a fourth metal layer M4 is formed in the logic element region L at the same time, the bit line BL contacts the third drain via plug V3d, the fourth metal layer M4 contacts the third via plug V3, and the upper surface of the fourth metal layer M4 is aligned with the upper surface of the bit line BL. Thus, the buried magnetoresistive memory structure 100 of the present invention has been completed.

Fig. 7 shows a buried magnetoresistive memory structure according to a preferred embodiment of the present invention. FIG. 8 is a schematic side view of the circuit shown in FIG. 7 along tangent lines GG 'and HH'. Fig. 1 is a top view of the locations of the active region, word line, source plug and drain plug of the buried magnetoresistive memory structure of the present invention.

Fig. 7 shows an embedded magnetoresistive memory structure 100, which includes a substrate 10, the substrate 10 is divided into a memory region M and a logic device region L, a plurality of active regions 12 are disposed in the memory region M and the logic device region L of the substrate 10 (please refer to fig. 1 for the location of the active regions 12), and a plurality of word lines WL1/WL2 are disposed on the substrate 10 and are interlaced with the active regions 12. As shown in fig. 7, a plurality of buried magnetoresistive memories 50 and logic elements 60 shown in fig. 8 are disposed on a substrate 10, wherein the buried magnetoresistive memory 50 shown in fig. 8 is disposed in a region X in fig. 7, and the logic element 60 shown in fig. 8 is disposed in a region Y in fig. 8. A single buried magnetoresistive memory and a single logic element will be described below. Referring to the region X of fig. 1 and fig. 8, at least one source plug 20 contacts the active region 12 and is located on one side of the word line WL1, and at least one drain plug 22 contacts the active region 12 and is located on the other side of the word line WL2, wherein the source plug 20 is a mirror image of the drain plug 22 when viewed from a direction perpendicular to the upper surface 11 of the substrate 10 and the word line WL1 is taken as a symmetry axis, and the number of the source plugs 20 and the number of the drain plugs 22 are two in fig. 1. In addition, the shapes of the source plugs 20 and the drain plugs 22 may be changed to be long strips according to product requirements, such as the source plugs 20 and the drain plugs 22 in fig. 9, and the number of the source plugs 20 and the number of the drain plugs 22 may be 1, respectively, as shown in fig. 10.

Referring again to fig. 8, the embedded mram 50 further includes a first source metal layer M1S contacting the source plug 20, a first drain metal layer M1d contacting the drain plug 22, a first source via plug V1S contacting the first source metal layer M1S, a first drain via plug V1d contacting the first drain metal layer M1d, a source line SL contacting the first source via plug V1S, a second drain metal layer M2d contacting the first drain via plug V1d, wherein the top surface of the source line SL is aligned with the top surface of the second drain metal layer M2d, a tungsten plug W contacting the second drain metal layer M2d, a magnetoresistive memory cell MTJ contacting the tungsten plug W, a third drain via plug V3d contacting the magnetoresistive memory cell MTJ, and a bit line BL contacting the third drain via plug V3 d. In detail, the drain plug 22, the first drain metal layer M1d, the first drain via plug V1d, the second drain metal layer M2d, the tungsten plug W, the magnetoresistive memory cell MTJ, the third drain via plug V3d, and the bit line BL are sequentially stacked from bottom to top, and the source plug 20, the first source metal layer M1S, the first source via plug V1S, and the source line SL are sequentially stacked from bottom to top, the first drain metal layer M1d, the first drain via plug V1d, the second drain metal layer M2d, the third drain via plug V3d, and the bit line BL, the first source metal layer M1S, the first source via plug V1S, and the source line SL include copper, and the drain plug 22 and the source plug 20 include aluminum.

As shown in fig. 7 and 8, the embedded mram structure 100 further includes a plurality of logic devices and a plurality of metal interconnects commonly disposed in the logic device region L, and the logic device 60 and the metal interconnects 70 in the region Y are described below as follows, the logic device 60 includes a word line WL2 disposed on the substrate 10, a doped region 18 disposed in the substrate 10 and located on one side of the word line WL2, a plug 24 contacting the doped region 18, the metal interconnects 70 include a first metal layer M1 contacting the plug 24, a first via plug V1 contacting a first metal layer M1, a second metal layer M2 contacting a first via plug V1, a second via plug V2 contacting a second metal layer M2, a third metal layer M3 contacting a second via plug V2, a third via plug V3 contacting a third metal layer M3, a fourth metal layer M4 contacting a third via plug V3, wherein an upper surface of the second metal layer M2 and an upper surface of the source line SL are aligned, the upper surface of the second via plug V2 is flush with the upper surface of the tungsten plug W, the upper surface of the third metal layer M3 is flush with the upper surface of the magnetoresistive memory cell MTJ, and the upper surface of the fourth metal layer M4 is flush with the upper surface of the bit line BL. The first metal layer M1, the first via plug V1, the second metal layer M2, the second via plug V2, the third metal layer M3, the third via plug V3, and the fourth metal layer M4 include copper, and the plug 24 includes aluminum.

The source line is arranged at the same height with the second metal layer in the logic element area, so that the source plug and the drain plug of the embedded type magnetic resistance memory can adopt a symmetrical layout.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.