阅读说明：本技术 衬底结构及其制造方法 (Substrate structure and manufacturing method thereof ) 是由 吕文隆 于 2019-12-30 设计创作，主要内容包括：本申请揭示了一种衬底结构及其制造方法。所述衬底结构包含衬底、第一重布结构、第一粘性层和第一连接组件。所述衬底包含在其第一表面上的第一导体。所述第一重布结构安置在所述衬底之上。所述第一粘性层安置在所述衬底和所述第一重布结构之间。所述第一连接组件与所述第一导体电连接,通过所述第一粘性层穿透到所述第一重布结构中,并将所述衬底电连接到所述第一重布结构。(A substrate structure and a method of fabricating the same are disclosed. The substrate structure includes a substrate, a first redistribution structure, a first adhesive layer, and a first connection component. The substrate includes a first conductor on a first surface thereof. The first redistribution structure is disposed over the substrate. The first adhesive layer is disposed between the substrate and the first redistribution structure. The first connection assembly is electrically connected to the first conductor, penetrates into the first redistribution structure through the first adhesive layer, and electrically connects the substrate to the first redistribution structure.)

1. A substrate structure, comprising:

a substrate including a first conductor on a first surface of the substrate;

a first redistribution structure disposed over the substrate;

a first adhesive layer between the substrate and the first redistribution structure; and

a first connection assembly electrically connected to the first conductor, penetrating into the first redistribution structure through the first adhesive layer, and electrically connecting the substrate to the first redistribution structure.

2. The substrate structure of claim 1, wherein the first connection component includes a base portion disposed on the first conductor and a tip portion extending in a tapered manner from the base portion toward the first redistribution structure.

3. The substrate structure of claim 1, wherein the first redistribution structure comprises a first dielectric layer and a first conductive layer in the first dielectric layer, the first conductive layer comprising a first conductor, wherein the first connection component physically contacts the first conductor of the first conductive layer and electrically connects the substrate to the first conductive layer.

4. The substrate structure of claim 3, wherein the first redistribution structure comprises a second dielectric layer between the substrate and the first dielectric layer, and comprises a second conductive layer in the second dielectric layer, the second conductive layer comprising a second conductor, wherein the first connection component passes through the second conductor of the second conductive layer.

5. The substrate structure of claim 4, wherein the second conductor of the second conductive layer includes a raised portion surrounding the first connection component.

6. The substrate structure of claim 5, wherein the raised portion extends into the first dielectric layer.

7. The substrate structure of claim 3, wherein the first conductor of the first conductive layer comprises a first seed layer and a first barrier layer on the first seed layer.

8. The substrate structure of claim 7, wherein the first conductor of the first conductive layer comprises a first solder layer, and the first barrier layer is disposed between the first seed layer and the first solder layer.

9. The substrate structure of claim 1, further comprising a second redistribution structure below a second surface of the substrate, the second surface opposite the first surface, and the substrate structure comprising a second adhesive layer between the substrate and the second redistribution layer.

10. The substrate structure of claim 9, wherein the substrate includes a second conductor on the second surface, the substrate structure further comprising a second connection component electrically connected with the second conductor, penetrating into the second redistribution structure through the second adhesive layer, and electrically connecting the substrate to the second redistribution structure.

11. The substrate structure of claim 1, wherein the first redistribution structure includes a first conductor overlaying the first adhesive layer, the substrate structure further comprising a pillar connected between the first conductor of the first redistribution structure and the first conductor of the substrate.

12. The substrate structure of claim 11, wherein the first redistribution structure includes a second conductor overlaying the first adhesive layer, the substrate structure further comprising a device electrically connected between the first and second conductors of the first redistribution structure.

13. A method of fabricating a substrate structure, the method comprising:

providing a substrate table having a first surface;

forming a first conductor on the first surface;

forming a first connection component on the first conductor, the first connection component including a tip portion;

providing a first redistribution structure; and

combining the substrate and the first redistribution structure by pushing the first connection component at the tip portion into the first redistribution structure.

14. The method of claim 13, wherein the first connection component comprises a stud bump, and wherein forming a first connection component on the first conductor comprises:

stud bumps are formed on the first conductor by a wire bonding process.

15. The method of claim 13, wherein the first connection component comprises a conductive pillar, and wherein forming a first connection component on the first conductor comprises:

providing a vector;

forming a patterned first photoresist layer on the carrier, the patterned first photoresist layer defining a tip portion of the first connection element;

forming a patterned second layer of photoresist over the patterned first layer of photoresist, exposing the defined tip portion, the patterned second layer of photoresist defining a base portion of the first connection element; and

forming a conductive layer conformally in the patterned first photoresist layer using the patterned second photoresist layer as a mask.

16. The method of claim 13, wherein combining the substrate and the first redistribution structure comprises:

attaching a first adhesive layer on the first redistribution structure; and

electrically connecting the substrate and the first redistribution structure in a lamination process such that the first connection component penetrates into the first redistribution structure through the first adhesive layer.

17. The method of claim 13, wherein the first redistribution structure comprises a first conductive layer comprising a first conductor, wherein combining the substrate and the first redistribution structure comprises pushing the first connection component into the first conductor of the first conductive layer.

18. The method of claim 17, wherein the first redistribution structure includes a second conductive layer between the first conductive layer and the substrate, the second conductive layer including a second conductor, wherein combining the substrate and the first redistribution structure includes pushing the first connection component into the second conductor of the second conductive layer.

19. The method of claim 13, wherein after forming a first conductor on the first surface, the method further comprises:

forming a second conductor on the first surface;

forming a second connection assembly on the second conductor; and

in combining the substrate and the first redistribution structure, the second connection component is pushed into a different conductive layer in the first redistribution structure than the first connection component.

20. The method of claim 13, further comprising:

forming a second conductor on a second surface of the substrate, the second surface being opposite the first surface;

forming a second connection component on the second conductor, the second connection component including a tip portion;

providing a second redistribution structure; and

combining the substrate and the second redistribution structure by pushing the second connection assembly at the tip portion into the second redistribution structure.

Technical Field

The present disclosure relates generally to a substrate structure, and more particularly, to a substrate structure including a substrate and a redistribution structure, and a method of manufacturing the substrate structure.

Background

A semiconductor device package may include a substrate and a redistribution structure attached to the substrate. The redistribution structure comprises a dielectric layer and one or more conductive layers in the dielectric layer and may be used for fan-out purposes. The substrate includes a conductive pad for electrically connecting with the conductive layer in the redistribution layer. The conductive pads or traces associated with the substrate are larger in line width and line spacing (L/S) than the conductive pads or traces associated with the redistribution structure.

Disclosure of Invention

Embodiments of the present disclosure provide a substrate structure, comprising: a substrate including a first conductor on a first surface of the substrate; a first redistribution structure disposed over the substrate; a first adhesive layer between the substrate and the first redistribution structure; and a first connection assembly electrically connected to the first conductor, penetrating into the first redistribution structure through the first adhesive layer, and electrically connecting the substrate to the first redistribution structure.

Some embodiments of the present disclosure provide a method of fabricating a substrate structure. The method comprises the following steps: providing a substrate table having a first surface; forming a first conductor on the first surface; forming a first connection component on the first conductor, wherein the first connection component includes a tip portion; providing a first redistribution structure; and combining the substrate and the first redistribution structure by pushing the first connection assembly at the tip portion into the first redistribution structure.

Drawings

Aspects of some embodiments of the disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that the various structures may not be drawn to scale and that the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a substrate structure according to an embodiment of the present disclosure.

Fig. 2A and 2B are cross-sectional views of substrate structures according to some embodiments of the present disclosure.

Fig. 3 is a cross-sectional view of a substrate structure according to another embodiment of the present disclosure.

Fig. 4 is a cross-sectional view of a substrate structure according to yet another embodiment of the present disclosure.

Fig. 5A, 5B, and 5C are cross-sectional views of substrate structures according to some embodiments of the present disclosure.

Fig. 6A and 6B are cross-sectional views of substrate structures according to some embodiments of the present disclosure.

Fig. 7A and 7B are cross-sectional views of substrate structures according to some embodiments of the present disclosure.

Fig. 8A and 8B are cross-sectional views of substrate structures according to some embodiments of the present disclosure.

Fig. 9A-9I illustrate one or more stages of a method of fabricating the substrate shown in fig. 1, in accordance with an embodiment of the present disclosure.

Fig. 9J illustrates one or more stages of a method of forming the connection assembly shown in fig. 1, in accordance with an embodiment of the present disclosure.

Fig. 10A-10I illustrate one or more stages of a method of forming a connection assembly according to another embodiment of the present disclosure.

Fig. 11A-11K illustrate one or more stages of a method of fabricating a redistribution structure as shown in fig. 1 in accordance with an embodiment of the present disclosure.

Fig. 12A-12C illustrate one or more stages of a method of fabricating the substrate structure shown in fig. 1, in accordance with an embodiment of the present disclosure.

Fig. 13 shows a schematic perspective view of a carrier according to an embodiment of the present disclosure.

Fig. 14 shows a schematic perspective view of a carrier according to another embodiment of the present disclosure.

Detailed Description

The same reference numbers will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are integrated with more and more electronic components to achieve better electrical performance and more functions. With the trend toward miniaturization and multi-functionalization of electronic devices, shrinking design rules and increasing the number of layers are aspects that characterize advances in semiconductor devices. Thus, the semiconductor chip has more input/output (I/O) connections. Redistribution structures for fan-out purposes have thus become popular. The redistribution structure may be formed by a more advanced manufacturing process than the substrate. As a result, the redistribution structure has a relatively fine line width and pitch, while the substrate has a relatively coarse line width and pitch. Furthermore, the surface uniformity (U%) of the redistribution structures may be significantly different from the surface uniformity of the substrate. In particular, the redistribution structure has relatively small thickness variation between the electrodes and relatively low U% in the dielectric layer. By comparison, the substrate has a relatively large thickness variation between the electrodes and a relatively high U% in the dielectric layer. Therefore, when the redistribution structure is formed on the substrate, the interconnection between the electrode of the redistribution structure and the substrate is likely to be broken. Therefore, it may be desirable to provide a substrate structure to address the open interconnect problem.

Fig. 1 is a cross-sectional view of a substrate structure 100 according to an embodiment of the present disclosure.

Referring to fig. 1, the substrate structure 100 includes a substrate 101, a redistribution structure 201, an adhesive layer 80 between the substrate 101 and the redistribution structure 201, and one or more connection components 30 electrically connecting the substrate 101 and the redistribution structure 201.

The substrate 101 includes a substrate board 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a, and a via hole 10v extending between the first surface 10a and the second surface 10 b. Further, the substrate 101 includes a first conductive pad 10p1 and a first conductive trace 10t1 disposed on the first surface 10a of the substrate board 10, and a second conductive pad 10p2 and a second conductive trace 10t2 disposed on the second surface 10b of the substrate board 10. The conductive pads or traces are referred to as conductors in this disclosure.

The substrate board 10 comprises a dielectric layer and a wiring structure in the dielectric layer for electrical communication between contact pads or traces on the first surface 10a and the second surface 10 b. The dielectric layer in the substrate board 10 may comprise an organic material selected from Polyamide (PA), Polyimide (PI), Polybenzoxazole (PBO), FR-4 or epoxy based materials. In other embodiments, the dielectric layer in the substrate sheet 10 may comprise an inorganic material selected from silicon (Si), glass, ceramic, or an oxidized or nitrided material such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). The substrate sheet 10 may have a thickness in a range of about twenty (20) micrometers (μm) to about one hundred (100) μm.

Each of the first conductive pad 10p1 or the first conductive trace 10t1 includes a patterned first metal foil 21 and a patterned first conductive layer 281 stacked thereon. The patterned first metal foil 21 may comprise titanium (Ti), tungsten (W) or an alloy thereof. In an embodiment, the patterned first metal foil 21 has a thickness in the range of about 1 μm to about 5 μm. In addition, the patterned first conductive layer 281 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the patterned first conductive layer 281 has a thickness in a range of about 5 μm to about 25 μm. The line width and spacing (L/S) of the first conductive pad 10p1 or the first conductive trace 10t1 are not less than about 7 μm and 7 μm, respectively.

Each of the second conductive pad 10p2 or the second conductive trace 10t2 includes a patterned second metal foil 22 and a patterned second conductive layer 282 stacked thereon. The patterned second metal foil 22 may comprise titanium (Ti), tungsten (W), or alloys thereof. In an embodiment, the patterned second metal foil 22 has a thickness in the range of about 1 μm to about 5 μm. In addition, the patterned second conductive layer 282 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the patterned second conductive layer 282 has a thickness in a range of about 5 μm to about 25 μm. The line width and pitch (L/S) of the second conductive pad 10p2 or the second conductive trace 10t2 are not less than about 7 μm and 7 μm, respectively.

The via 10v includes an insulating portion 27 and a via liner 15 substantially surrounding the insulating portion 27. The via liner 15 electrically connects the patterned first metal foil 21 and the patterned second metal foil 22 of a pair of conductive pads 10p1, 10p2 corresponding in position to the via liner 15. Suitable materials for the via liner 15 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof. In an embodiment, the via 10v has a diameter in a range of about 60 μm to about 150 μm.

The redistribution structure 201 includes a first dielectric layer p71, a second dielectric layer p72, a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. Thus, the redistribution structure 201 has a "2P 3M" configuration, which is merely exemplary and not limiting. The second dielectric layer p72 is disposed between the first dielectric layer p71 and the adhesive layer 80. Each of the first and second dielectric layers p71 and p72 may include an organic material selected from Polyamide (PA), Polyimide (PI), Polybenzoxazole (PBO), FR-4, or an epoxy-based material, or an inorganic material selected from silicon (Si), glass, ceramic, or an oxidized or nitrided material such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). In an embodiment, each of the first and second dielectric layers p71 and p72 has a thickness in a range of about 2 μm to about 10 μm.

The first conductive layer M1 is disposed in the first dielectric layer p 71. The first conductive layer M1 includes a first conductive pad M1p, a first conductive trace M1t, and a first via M1 v. Each of the first conductive pad m1p and the first conductive trace m1t further includes a first seed layer p51, a first barrier layer 511, and a first solder layer 512 arranged in a stack in that order. Suitable materials for the first seed layer p51 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), palladium (Pd), or an alloy thereof. In an embodiment, the first seed layer 51 has a thickness in a range of about 1 μm to about 5 μm. In addition, suitable materials for the first barrier layer 511 may include Ti and W. In an embodiment, the first barrier layer 511 has a thickness in a range of about 0.1 μm to about 0.5 μm. In addition, suitable materials for the first soldering layer 512 may include solder, Anisotropic Conductive Film (ACF), or Anisotropic Conductive Paste (ACP). In addition, the first solder layer 512 has a thickness in a range of about 5 μm to about 20 μm.

The second conductive layer M2 is disposed in the second dielectric layer p 72. The second conductive layer M2 includes a second conductive pad M2p, a second conductive trace M2t, and a second via M2 v. Each of the second conductive pad m2p and the second conductive trace m2t further includes a second seed layer p52, a second barrier layer 521, and a second solder layer 522 arranged in a stack in that order. Suitable materials and dimensions for the second seed layer p52, the second barrier layer 521 and the second solder layer 522 are similar or identical to suitable materials and dimensions for the first seed layer p51, the first barrier layer 511 and the first solder layer 512, respectively.

The third conductive layer M3 is disposed on the second dielectric layer P72 and covered in the adhesive layer 80. The third conductive layer M3 includes a third conductive pad M3p and a third conductive trace M3 t. Each of the third conductive pad m3p and the third conductive trace m3t further includes a third seed layer p53 and a third barrier layer 531 arranged in sequence as a stack. Suitable materials and dimensions for the third seed layer p53 and the third barrier layer 531 are similar or identical to suitable materials and dimensions for the first seed layer p51 and the first barrier layer 511, respectively.

In addition, the first via M1v in the first conductive layer M1 includes a second barrier layer 521 and a second seed layer p52 disposed in the first dielectric layer p 71. Further, the second via M2v in the second conductive layer M2 includes a third barrier layer 531 and a third seed layer p53 disposed in the second dielectric layer p 72.

The line widths and spacings (L/S) of the first, second, and third conductive layers M1, M2, and M3 are smaller than the line widths and spacings (L/S) of the first conductive pad 10p1 or the first and second conductive traces 10t1, 10p2, and 10t 2. In an embodiment, the line width and pitch (L/S) of the first conductive pad M1p and the first conductive trace M1t in the first conductive layer M1 are not greater than about 2 μ M and 2 μ M, respectively. Likewise, the line width and spacing (L/S) of second conductive pad M2p and second conductive trace M2t in second conductive layer M2 and the line width and spacing (L/S) of third conductive pad M3p and third conductive trace M3t in third conductive layer M3 are not greater than about 2 μ M and 2 μ M, respectively.

Adhesive layer 80 is disposed between substrate 101 and redistribution structure 201. The adhesive layer 80 serves to attach the redistribution structure 201 to the substrate 101 and serves as a buffer against the pushing force from the connection assembly 30. Suitable materials for adhesive layer 80 include ACP, ACF, non-conductive paste (NCP), non-conductive film (NCF), PI, epoxy, or resin. In an embodiment, adhesive layer 80 has a thickness in a range of about 20 μm to about 100 μm.

The connection assembly 30 includes a base portion 30b and a tip portion 30 t. The base portion 30b is disposed on the conductive pads 10p1 or the conductive traces 10t1 on the first surface 10a of the substrate board 10, while the tip portion 30t extends from the base portion 30b in a generally conical manner. The tip portion 30t has a tapered or relatively pointed end that facilitates pushing through the adhesive layer 80 into the redistribution structure 201. In the present embodiment, the connection assembly 30 includes stud bumps that may be formed by the method described and illustrated with reference to fig. 9J. In another embodiment, the connection assembly includes a post that may be formed by the method described and illustrated with reference to fig. 10A-10I. Suitable materials for the stud bump type connection assembly 30 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the connection assembly 30 has a thickness and a diameter that are each in a range of about 20 μm to about 50 μm.

When pushed into the redistribution structure 201, the connection member 30 penetrates the second dielectric layer p72 and then penetrates the first dielectric layer p71 to reach the first conductive layer M1 in the redistribution structure 201. As a result, the substrate 101 and the redistribution structure 201 are electrically connected to each other. In the first conductive pad M1p or the first conductive trace M1t in the first conductive layer M1 electrically connected to the connection component 30, the first solder layer 512 and the first barrier layer 511 are pierced, and the first seed layer p51 may not be pierced. In addition, the connection component 30 may penetrate one or more conductive layers in the redistribution structure 201 toward the first conductive layer M1. For example, in the present embodiment, the connection assembly 30 penetrates the second conductive trace m2t and the second conductive pad m2p, thereby obtaining a deformed second conductive trace dm2t and a deformed second conductive pad dm2p, respectively. Thus, the connection assembly 30 may electrically connect the substrate 101 to a desired conductive layer in the redistribution structure 201, and vice versa. The deformed conductive pad or trace includes a raised portion surrounding the tip portion 30t of the connection assembly 30.

In some prior approaches, a redistribution structure may be built on a substrate, which may easily break the interconnect due to significant differences in L/S and U% between the redistribution structure and the substrate. In the present disclosure, the substrate 101 and the redistribution structure 201 are combined with each other by pushing the connection component 30 into the redistribution structure 201. The connection assembly 30 may pierce the conductive layer and create a raised portion. However, the raised portion of the pierced conductive layer remains electrically connected to the connection assembly 30. As a result, although the substrate 101 and the redistribution structure 201 are manufactured in separate processes and may have significant differences in L/S and U% of the conductive and dielectric layers, respectively, the pushing-in of the connection assembly 30 ensures that the tip portion 30t of the connection assembly 30 reaches a desired or predetermined location in the redistribution structure 201, and thus ensures a reliable electrical connection between the substrate 101 and the redistribution structure 201. Thereby alleviating or solving the otherwise occurring broken interconnect problem in the prior art methods.

Fig. 2A and 2B are cross-sectional views of substrate structures 211 and 212, respectively, according to some embodiments of the present disclosure.

Referring to fig. 2A, the substrate structure 211 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, the redistribution structure 251 has a "1P 2M" configuration that is different from the "2P 3M" configuration of the redistribution structure 201. Specifically, the redistribution structure 251 includes a first dielectric layer p71, a first conductive layer M1 in the first dielectric layer p71, and a second conductive layer M2 disposed on the first dielectric layer p71 and covering the adhesive layer 80. In addition, the substrate structure 211 includes connection members 35, the connection members 35 having tip portions 35t shorter than the tip portions 30t of the connection members 30.

Referring to fig. 2B, substrate structure 212 is similar to substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, redistribution structure 271 has a "3P 4M" configuration that is different from the "2P 3M" configuration of redistribution structure 201. Specifically, the redistribution structure 271 includes the third dielectric layer p73 except for the first and second dielectric layers p71 and p72, and the fourth conductive layer M4 except for the first, second, and third conductive layers M1, M2, and M3. The third dielectric layer p73 is disposed between the second dielectric layer p72 and the adhesive layer 80. Suitable materials and dimensions for the third dielectric layer p73 are similar or identical to suitable materials and dimensions for the first dielectric layer p 71. In addition, a fourth conductive layer M4 is disposed on the third dielectric layer p73 and covered in the adhesive layer 80. Suitable materials and dimensions for the fourth conductive layer M4 are similar or identical to suitable materials and dimensions for the first conductive layer M1. In addition, the substrate structure 212 includes the connection members 38, and the connection members 38 have tip portions 37t longer than the tip portions 30t of the connection members 30.

Fig. 3 is a cross-sectional view of a substrate structure 300 according to another embodiment of the present disclosure.

Referring to fig. 3, a substrate structure 300 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except, for example, that additional wiring layers are included. Specifically, the substrate structure 300 includes a first wiring structure 361 disposed on the first surface 10a of the substrate board 10 between the substrate 101 and the adhesive layer 80. The first wiring structure 361 electrically connects the substrate 101 to the connection member 30. The substrate structure 300 may further include a second wiring structure 362 disposed on the second surface 10b of the substrate board 10. Each of the first and second wiring structures 361 and 362 may include one or more dielectric layers and a wiring structure routed through the one or more dielectric layers toward the redistribution structure 201.

Fig. 4 is a cross-sectional view of a substrate structure 400 according to yet another embodiment of the present disclosure.

Referring to fig. 4, a substrate structure 400 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, a second redistribution structure 202 is included in addition to the redistribution structure 201 (in this case, the first redistribution structure 201). The second redistribution structure 202 disposed below the second surface 10b of the substrate board 10 is attached to the substrate 101 by a second adhesive layer 480. The second adhesive layer 480 disposed on the second surface 10b of the substrate sheet 10 between the substrate 101 and the second redistribution structure 202 comprises substantially the same material as the first adhesive layer 80. In the present embodiment, the second redistribution structure 202 includes substantially the same configuration as the first redistribution structure 201, i.e., a 2P3M configuration. However, in other embodiments, the second redistribution structure 202 may comprise a different configuration, such as the 1P2M configuration shown in fig. 2A, or the 3P4M configuration shown in fig. 2B. The substrate structure 400 further comprises a second connection assembly 430, the second connection assembly 430 electrically connecting the substrate 101 and the second redistribution structure 202. The second connecting member 430 includes a tip portion 430 t. In the present embodiment, the tip portion 430t is substantially equal in length to the tip portion 30t of the first connection member 30. However, in other embodiments, the tip portion 430t may be shorter or longer than the tip portion 30t of the connection assembly 30 (in this case, the first connection assembly 30), as in the embodiments shown in fig. 2A and 2B, respectively.

In the present embodiment, the deformed second conductive gasket dm2p in the first redistribution structure 201 includes a convex portion r2p extending in the direction in which the first connection member 30 is pushed in. The convex portion r2p surrounds the tip portion 30t of the first connection member 30. Similarly, the deformed second conductive pad dm2p 'in the second redistribution structure 202 includes a convex portion r2p' extending in the direction in which the second connection member 430 is pushed in. The convex portion r2p' surrounds the tip portion 430t of the second connection assembly 430.

Fig. 5A, 5B, and 5C are cross-sectional views of substrate structures 501, 502, and 503, respectively, according to some embodiments of the present disclosure.

Referring to fig. 5A, substrate structure 501 is similar to substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, the conductive pads or traces are electrically connected by bond wires. Specifically, in the present embodiment, the first conductive pad 10p1 or the first conductive trace 10t1 is electrically connected to another first conductive pad 10p1 or another first conductive trace 10t1 by the bonding wire 51 w. Further, the third conductive pad m3p or the third conductive trace m3t is electrically connected to another third conductive pad m3p or another third conductive trace m3t by a bonding wire 52 w. Bond wires 51w and 52w facilitate electrical connection between conductive pads or traces disposed on the same conductive layer.

Referring to fig. 5B, a substrate structure 502 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except, for example, further including the pillars 57. In the present embodiment, the pillar 57 is connected between the first conductive pad 10p1 and the third conductive pad m3p, and the first conductive pad 10p1 and the third conductive pad m3p correspond in position to each other. The support posts 57 serve to mechanically reinforce the substrate structure 502 and may not provide electrical connections between conductive pads or traces connected to the support posts 57.

Referring to fig. 5C, substrate structure 503 is similar to substrate structure 100 described and illustrated with reference to fig. 1, except, for example, further including apparatus 58. In this embodiment, the device 58 is electrically connected between the third electrically conductive pads m3 p. Device 58 may include a chip or passive components.

Fig. 6A and 6B are cross-sectional views of substrate structures 601 and 602, respectively, according to some embodiments of the present disclosure.

Referring to fig. 6A, a substrate structure 601 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except for, for example, including connection components having different lengths than the connection components 30. Specifically, in the present embodiment, the first connecting member 61 includes the tip portion 61t shorter than the tip portion 30t of the connecting member 30. The first connection assembly 61 pierces the third conductive pad m3p such that the raised portion r3p of the third conductive pad m3p extends into the second dielectric layer p 72. In addition, the second connection member 62 includes a tip portion 62t shorter than the tip portion 30t of the connection member 30 and longer than the tip portion 61t of the first connection member 61. The second connection assembly 62 pierces the second conductive pad m2p such that the raised portion r2p of the second conductive pad m2p extends into the first dielectric layer p 71. Thus, these connection members 30, 61, and 62 electrically connect the substrate 101 to the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3, and vice versa.

Referring to fig. 6B, the substrate structure 602 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except, for example, that it includes vias that electrically connect to the connection components. Specifically, in the present embodiment, the via M2v in the second conductive layer M2 electrically connects the second conductive pad M2p and the third conductive pad M3 p. The third connecting assembly 63, which corresponds in position to the via m2v, includes a tip portion 63t in physical contact with a third conductive pad m3 p. As a result, the third connection member 63 electrically connects the substrate 101 to the third conductive layer M3 via the third conductive pad M3p, and additionally electrically connects the substrate 101 to the second conductive layer M2 via the via M2v and the second conductive pad M2 p.

Further, the via M1v in the first conductive layer M1 electrically connects the first conductive pad M1p and the second conductive pad M2 p. The fourth connection assembly 64, which corresponds in position to the via m1v, includes a tip portion 64t in physical contact with the second conductive pad m2 p. As a result, the fourth connection member 64 electrically connects the substrate 101 to the second conductive layer M2 via the second conductive pad M2p, and additionally electrically connects the substrate 101 to the first conductive layer M1 via the via M1v and the first conductive pad M1 p. Thus, by means of the vias 63 and 64, the connection members 63 and 64 electrically connect the substrate 101 to the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3, and vice versa.

Fig. 7A and 7B are cross-sectional views of substrate structures 701 and 702, respectively, according to some embodiments of the present disclosure.

Referring to fig. 7A, a substrate structure 701 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, the conductive pads or traces may be free of a solder layer. Specifically, in the present embodiment, although the first conductive pad m1p includes the first solder layer 512 except the first seed layer p51 and the first buffer layer 511, another first conductive pad m1p' includes only the first seed layer p51 and the first buffer layer 511 and does not have the first solder layer 512. Likewise, although the second conductive pad m2p includes the second soldering layer 522 in addition to the second seed layer p52 and the second buffer layer 521, another second conductive pad m2p' includes only the second seed layer p52 and the second buffer layer 521 and does not have the second soldering layer 522.

Referring to fig. 7B, the substrate structure 702 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except that, for example, the first, second, and third conductive layers M1, M2, M3 are devoid of any solder layer.

Fig. 8A and 8B are cross-sectional views of substrate structures 801 and 802, respectively, according to some embodiments of the present disclosure.

Referring to fig. 8A, a substrate structure 801 is similar to the substrate structure 100 described and illustrated with reference to fig. 1, except for the filler 88, for example, further included in the adhesive layer 80. The filler 88 serves to mechanically reinforce the substrate structure 801. Suitable materials for the filler 88 may include silica particles or glass fibers.

Referring to fig. 8B, substrate structure 802 is similar to substrate structure 801 described and illustrated with reference to fig. 8A, except that, for example, filler 88 is disposed in substrate plate 10 instead of adhesive layer 80. In other embodiments, the filler 88 may be disposed in the substrate board 10 and the adhesive layer 80.

Fig. 9A-9I illustrate one or more stages of a method of fabricating the substrate 101 shown in fig. 1, in accordance with an embodiment of the present disclosure.

Referring to fig. 9A, a substrate board 10 is provided. The substrate sheet 10 has a first surface 10a and a second surface 10b opposite to the first surface 10 a. The substrate board 10 is provided with a first metal foil 11 and a second metal foil 12 on the first surface 10a and the second surface 10b, respectively. The first metal foil 11 and the second metal foil 12 may each include titanium (Ti), tungsten (W), or an alloy thereof. In addition, the first and second metal foils 11 and 12 may each have a thickness in a range of about one (1) micrometer (μm) to about five (5) μm. The substrate board 10 may comprise a dielectric layer and a wiring structure in the dielectric layer for electrical communication between contact pads on the first surface 10a and the second surface 10 b. The dielectric layer may be formed by using, for example, a lamination, printing, potting, or coating process. In some embodiments, the dielectric layer in the substrate board 10 may comprise an organic material selected from Polyamide (PA), Polyimide (PI), Polybenzoxazole (PBO), FR-4 or epoxy based materials. In other embodiments, the dielectric layer in the substrate sheet 10 may comprise an inorganic material selected from silicon (Si), glass, ceramic, or an oxidized or nitrided material such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). The substrate sheet 10 may have a thickness in the range of about 20 μm to about 100 μm.

Referring to fig. 9B, a through-hole 10H penetrating the substrate board 10 is formed in a drilling process using, for example, a mechanical drill 200. Each through-hole 10H exposes a wall 10w in the substrate board 10 that defines the remaining portion of each through-hole 10H. The through-hole 10H may be vertical or tapered. In an embodiment, the via 10H has a diameter in a range of about 60 μm to about 150 μm.

Next, referring to fig. 9C, via liner 15 is conformally formed along the walls of the remaining portion of substrate plate 10 defining via 10H using, for example, electrolytic plating, electroless plating, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or other suitable metal deposition process. The via liner 15 electrically connects the first metal foil 11 and the second metal foil 12. Suitable materials for the via liner 15 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof.

Referring to fig. 9D, an electrically insulating layer 17 is formed by using, for example, a lamination, printing, potting, or coating process. The insulating layer 17 covers the first metal foil 11 and the second metal foil 12, and fills the through hole 10H. Suitable materials for the insulating layer 17 may be similar or identical to suitable materials for the dielectric layers in the substrate board 10, as discussed with reference to fig. 9A.

Referring to fig. 9E, the insulating layer 17 on the first and second metal foils 11 and 12 is removed by using, for example, a brush coating process, thereby exposing the remaining portion 27 of the insulating layer 17 filled in the via hole 10H. Each insulating portion 27 is substantially flush with the first metal foil 11 and the second metal foil 12.

Thereafter, referring to fig. 9F, a first conductive layer 181 and a second conductive layer 182 are formed on the first metal foil 11 and the second metal foil 12, respectively, by using, for example, sputtering, electrolytic plating, electroless plating, printing, laminating, or potting processes. Suitable materials for the first conductive layer 181 and the second conductive layer 182 may each include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the first conductive layer 181 and the second conductive layer 182 may each have a thickness in a range of about 5 μm to about 25 μm.

Referring to fig. 9G, in a coating process, a first photoresist layer 191 and a second photoresist layer 192 are formed on the first conductive layer 181 and the second conductive layer 182, respectively. Next, referring to fig. 9H, a patterned first photoresist layer 291 and a patterned second photoresist layer 292 are formed on the first conductive layer 181 and the second conductive layer 182, respectively, by patterning the first photoresist layer 191 and the second photoresist layer 192 in a photolithography process. The patterned first photoresist layer 291 and the patterned second photoresist layer 292 define conductive pads or traces to be subsequently formed on the first surface 10a and the second surface 10b, respectively, of the substrate board 10.

Subsequently, the first conductive layer 181 and the second conductive layer 182 are patterned in an etching process using the patterned first photoresist layer 291 and the patterned second photoresist layer 292 as masks, thereby obtaining a patterned first conductive layer 281 and a patterned second conductive layer 282, respectively, as shown in fig. 9I. Further, the first metal foil 11 and the second metal foil 12 shown in fig. 9H are patterned in an etching process using the patterned first conductive layer 181 and the patterned second conductive layer 182 as masks, resulting in the patterned first metal foil 21 and the patterned second metal foil 22, respectively, as shown in fig. 9I. The patterned first photoresist layer 291 and the patterned second photoresist layer 292 are then removed, resulting in the substrate structure 101 as described and illustrated with reference to fig. 1. The patterned first metal foil 21 and the patterned first conductive layer 281 thereon constitute the conductive pads 10p1 or the conductive traces 10t1 on the first surface 10a of the substrate board 10. In addition, the patterned second metal foil 22 and the patterned second conductive layer 282 thereon constitute a conductive pad 10p2 or a conductive trace 10t2 on the second surface 10b of the substrate board 10. Further, the pair of conductive pads 10p1, 10p2, and the conductive liner 15 and the corresponding insulating portion 27 corresponding in position to the pair of conductive pads 10p1, 10p2 together constitute a via 10v, as shown in fig. 9I. The line widths and spacings (L/S) of the conductive pads 10p1, 10p2 and the conductive traces 10t1, 10t2 are not less than about 7 μm and 7 μm, respectively.

Fig. 9J illustrates one or more stages of a method of forming the connection assembly 30 shown in fig. 1, in accordance with an embodiment of the present disclosure.

Referring to fig. 9J, the connection member 30 for interconnection is formed on the conductive pad 10p1 or the conductive trace 10t1 on the first surface 10a of the substrate board 10. The connection assembly 30 may be formed by a suitable process that creates a tapered or relatively pointed tip to facilitate pushing into the redistribution structure. In the present embodiment, the connection assembly 30 includes a stud bump, which in turn includes a base portion 30b and a tip portion 30 t. The base portion 30b is disposed on the conductive pad 10p1 or the conductive trace 10t1, and the tip portion 30t extends from the base portion 30b in a generally conical manner. The connection assembly 30 is formed by a wire bonding process using, for example, a capillary 280. The size of the joining assembly 30, particularly the length of the tip portion 30t, can be predetermined by controlling the force and ultrasonic energy applied from the capillary 280 to the bonding wire 280w over time. Suitable materials for the stud bump used as the connection member 30 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the connection assembly 30 has a thickness and a diameter that are each in a range of about 20 μm to about 50 μm.

A connection assembly suitable for interconnection as connection assembly 30 may be formed by another method other than wire bonding. Fig. 10A-10I illustrate one or more stages of a method of forming a connection assembly 83 in accordance with an embodiment of the present disclosure.

Referring to fig. 10A, a carrier 81 is provided. Then, a first photoresist layer 91 is formed on the support 81 in, for example, a lamination process.

Referring to fig. 10B, the first photoresist layer 91 is patterned in a photolithography process, resulting in a patterned first photoresist layer p 91. The patterned first photoresist layer p91 comprises recesses 91H, each recess 91H defining a tip portion of the connection component 83 to be formed later on. Specifically, the recess 91H is tapered from the first surface p91a toward the opposite second surface p91b of the patterned first photoresist layer p 91. Subsequently, a barrier layer 82 is conformally formed on the patterned first photoresist layer p91 in, for example, a Physical Vapor Deposition (PVD) process. Suitable materials for barrier layer 82 may include titanium (Ti) and tungsten (W). In an embodiment, the barrier layer 82 has a thickness in a range of about 0.1 μm to about 0.5 μm.

Next, referring to fig. 10C, a patterned second photoresist layer p92 is formed on the barrier layer 82 in a photolithography process, exposing portions of the barrier layer 82, particularly portions of the barrier layer 82 formed in the recess 91H, through the opening 92H. The patterned second photoresist layer p92 defines the base portion of the connection member 83.

Referring to fig. 10D, a first conductive layer 831 is formed on the exposed portion of the barrier layer 82 by, for example, an electroplating process, thereby filling the recess 91H. The first conductive layer 831 functions as a base portion and a tip portion of the connection member 83. Suitable materials for the first conductive layer 831 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof.

Then, a second conductive layer 832 is formed over the first conductive layer 831 by, for example, an electroplating process. The second conductive layer 832 serves as a barrier layer for connecting the components 83. Suitable materials for second conductive layer 832 may include titanium (Ti) and tungsten (W). In an embodiment, the second conductive layer 832 has a thickness in a range of about 0.1 μm to about 0.5 μm.

Thereafter, a third conductive layer 833 is formed over the second conductive layer 832 by, for example, an electroplating process. The third conductive layer 833 serves as a solder layer for connecting the components 83. Suitable materials for the third conductive layer 833 may include solder, an Anisotropic Conductive Film (ACF), or an Anisotropic Conductive Paste (ACP). In an embodiment, the third conductive layer 833 has a thickness in a range of about 5 μm to about 20 μm. The patterned second photoresist layer p92 is then removed, exposing portions of the barrier layer 82 that are not masked by the third conductive layer 833.

Next, referring to fig. 10E, the exposed portion of the barrier layer 82 is removed by an etching process, resulting in a patterned barrier layer p 82. A portion of the patterned barrier layer p82 disposed on the surface p91a of the patterned first photoresist layer p91 and a stack of the first, second, and third conductive layers 831, 832, 833 on the portion of the patterned barrier layer p82 constitute the base portion 83b of the connection component 83. In addition, the remaining portion of the patterned barrier layer p82 and the first conductive layer 831 in the patterned first photoresist layer p91 constitute a tip portion 83t of the connection member 83.

Referring to fig. 10F, a substrate structure 101 is provided, which may be prepared according to the method described and illustrated with reference to fig. 9A to 9I. A second conductive layer 852 serving as a barrier layer and a third conductive layer 853 serving as a solder layer are sequentially formed on the conductive pad 10p1 (or the conductive trace 10t 1). A portion of the third conductive layer 853 may correspond in position to the third conductive layer 833 of the connection member 83. Suitable processes and materials for second conductive layer 852 and third conductive layer 853 formed on conductive pad 10p1 are similar or identical to suitable processes and materials for second conductive layer 832 and third conductive layer 833, respectively, of connection component 83, as described and illustrated with reference to fig. 10D.

Then, referring to fig. 10G, the connection member 83 is connected to the corresponding conductive pad 10t1 by coupling the connection member 83 and the respective third conductive layers 833 and 853 of the corresponding conductive pad 10t1 in, for example, a reflow process, thereby obtaining a pillar-like connection member having the joint 85 between the second conductive layers 832 and 852. The carrier 81 and the patterned first photoresist layer p91 are subsequently removed.

Referring to fig. 10H, a fourth conductive layer 834 is formed on the third conductive layer 833 of the connection member 83 by using, for example, an electroless plating process in an aqueous solution. The fourth conductive layer 834 functions as a solder layer. Suitable materials for the fourth conductive layer 834 may include titanium (Ti) and tungsten (W). The connection assembly 83 is shown in fig. 10I with a fourth conductive layer 834. In an embodiment, the connection assembly 83 has a thickness and a diameter that are each in a range of about 20 μm to about 50 μm.

The connection member 30 in the form of stud bumps as shown in fig. 9J and the connection member 83 in the form of posts as shown in fig. 10I are exemplary connection members for combining the substrate board 10 and the redistribution structure 201 as shown in fig. 1. Fig. 11A-11K illustrate one or more stages of a method of fabricating the redistribution structure 201 shown in fig. 1, in accordance with embodiments of the present disclosure.

Referring to fig. 11A, a first carrier 41 is provided. The first carrier 41 is used to support a semiconductor component, device or structure to be subsequently formed or mounted thereon. The first carrier 41 may comprise one of a metal carrier, a ceramic carrier, a glass carrier, a substrate, or a semiconductor wafer. In addition, the first carrier 41 may have a rectangular or square shape, as shown in fig. 13. Alternatively, the first carrier 10 may have a circular or elliptical shape, as shown in fig. 14. Depending on the application, the thickness of the first carrier 41 may range from about 100 μm to about 500 μm, from about 200 μm to about 800 μm, or from about 500 μm to about 1500 μm.

A first release film 41r is then formed on the first carrier 41. The first release film 41r is used to facilitate detachment of the first carrier 41 from the semiconductor structure temporarily held by the first carrier 41. In an embodiment, the first release film 202 includes a polymer and has a thickness of about 0.5 μm.

Thereafter, a first seed layer 51 is formed on the first release film 41r by using, for example, sputtering, electrolytic plating, electroless plating, printing, laminating, or potting process. Suitable materials for the first seed layer 51 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), palladium (Pd), or an alloy thereof. In an embodiment, the first seed layer 51 has a thickness in a range of about 1 μm to about 5 μm.

Referring to fig. 11B, a patterned first photoresist layer 61 is formed on the first seed layer 51, exposing portions of the first seed layer 51 through the openings 61H. The patterned first photoresist layer 61 may be formed by forming a photoresist layer on the first seed layer 51 in a coating process, followed by a photolithography process including exposure and development.

Referring to fig. 11C, a first barrier layer 511 and a first solder layer 512 are sequentially formed on the exposed portion of the first seed layer 51 by using, for example, sputtering, electrolytic plating, electroless plating, printing, laminating, or potting processes. Suitable materials for the first barrier layer 511 may include Ti and W. Suitable materials for the first solder layer 512 may include solder, ACF, or ACP. In an embodiment, the first barrier layer 511 has a thickness in a range of about 0.1 μm to about 0.5 μm. In addition, the first solder layer 512 has a thickness in a range of about 5 μm to about 20 μm. The patterned first photoresist layer 61 is thereafter removed, exposing portions of the first seed layer 51 not masked by the first barrier layer 511 and the first solder layer 512.

Next, referring to fig. 11D, the exposed portion of the first seed layer 51 is patterned in an etching process, resulting in a patterned first seed layer p 51. The patterned first seed layer p51, the first barrier layer 511 and the first solder layer 512 formed as a stack constitute a first conductive pad m1p or a first conductive trace m1t of the first conductive layer in the redistribution structure under construction. The line width and spacing (L/S) of the first conductive pad m1p and the first conductive trace m1t are no greater than approximately 2 μm and 2 μm, respectively.

Subsequently, a first dielectric layer 71 is formed on the first release film 41 in, for example, a printing, laminating, potting, or coating process so as to cover the first conductive pad m1p and the first conductive trace m1 t. Suitable materials for the first dielectric layer 71 may include organic materials selected from Polyamide (PA), Polyimide (PI), Polybenzoxazole (PBO), FR-4, or epoxy-based materials, or inorganic materials selected from silicon (Si), glass, ceramics, or oxidized or nitrided materials such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). In an embodiment, the first dielectric layer 71 has a thickness in a range of about 2 μm to about 10 μm.

Referring to fig. 11E, the first dielectric layer 71 is patterned in a photolithography process, resulting in a patterned first dielectric layer p 71. The patterned first dielectric layer p71 exposes portions of the first conductive pad m1p or the first conductive trace m1t through the opening p 71H.

Then, referring to fig. 11F, a second seed layer 52 is conformally formed on the patterned first dielectric layer p 71. Suitable processes, materials, and dimensions for forming the second seed layer 52 are similar or identical to suitable processes, materials, and dimensions for forming the first seed layer 51, as described and illustrated with reference to fig. 11A. Thereafter, a patterned second photoresist layer 62 is formed on the second seed layer 52, exposing portions of the second seed layer 52. Specifically, the patterned second photoresist layer 62 exposes the second seed layer 52 disposed in the opening p 71H. Suitable processes for forming patterned second photoresist layer 62 are similar or identical to suitable processes for forming patterned first photoresist layer 61, as described and illustrated with reference to fig. 11B.

Referring to fig. 11G, a second barrier layer 521 and a second solder layer 522 are sequentially formed on the exposed portion of the second seed layer 52. The second barrier layer 521 fills the exposed portion of the second seed layer 52 disposed in the opening p 71H. Suitable processes, materials, and dimensions for forming second barrier layer 521 and second bonding layer 522 are similar or identical to suitable processes, materials, and dimensions for forming first barrier layer 511 and first bonding layer 512, respectively, as described and illustrated with reference to fig. 11C. The patterned second photoresist layer 62 is thereafter removed, exposing portions of the second seed layer 52 not masked by the second barrier layer 521 and the second solder layer 522.

Next, referring to fig. 11H, the exposed portion of the second seed layer 52 is patterned in an etching process, resulting in a patterned second seed layer p 52. The second patterned second seed layer p52, the second barrier layer 521 and the second solder layer 522 formed as a stack constitute a second conductive pad m2p or a second conductive trace m2t of the second conductive layer in the redistribution structure under construction. The line width and spacing (L/S) of the second conductive pad m2p and the second conductive trace m2t are no greater than about 2 μm and 2 μm, respectively. In addition, the second barrier layer 521 filled in the opening p71H and the patterned second seed layer p52 associated with the opening p71H constitute the via hole M1v of the first conductive layer M1 in the redistribution structure under construction. Specifically, referring also to fig. 11D, the first conductive layer M1 includes a first conductive pad M1p, a first conductive trace M1t, and a first via M1 v.

Subsequently, referring to fig. 11I, a patterned second dielectric layer p72 is formed on the patterned first dielectric layer p71, exposing portions of the second conductive pad m2p or the second conductive trace m2t through the opening p 72H. Suitable processes, materials, and dimensions for forming the patterned second dielectric layer p72 are similar or identical to suitable processes, materials, and dimensions for forming the patterned first dielectric layer p71, as described and illustrated with reference to fig. 11D.

Referring to fig. 11J, a third seed layer 53 is formed conformally on the patterned second dielectric layer p 72. Suitable processes, materials, and dimensions for forming third seed layer 53 are similar or identical to suitable processes, materials, and dimensions for forming first seed layer 51, as described and illustrated with reference to fig. 11A. Thereafter, a patterned third photoresist layer 63 is formed on third seed layer 53, exposing portions of third seed layer 53. Specifically, the patterned third photoresist layer 63 exposes the third seed layer 53 disposed in the opening p 72H. Suitable processes for forming the patterned third photoresist layer 63 are similar or identical to suitable processes for forming the patterned first photoresist layer 61, as described and illustrated with reference to fig. 11B.

Subsequently, a third barrier layer 531 is formed on the exposed portion of the third seed layer 53. The third barrier layer 531 fills the exposed portion of the third seed layer 53 disposed in the opening p 72H. Suitable processes, materials, and dimensions for forming the third barrier layer 531 are similar or identical to suitable processes, materials, and dimensions for forming the first barrier layer 511, as described and illustrated with reference to fig. 11C. The patterned third photoresist layer 63 is thereafter removed, exposing portions of the third seed layer 53 not masked by the third barrier layer 531.

Further, referring to fig. 11K, the exposed portion of the third seed layer 53 is patterned in an etching process, resulting in a patterned third seed layer p 53. The patterned third seed layer p53 and the third barrier layer 531 formed as a stack constitute the third conductive pad M3p or the third conductive trace M3t of the third conductive layer M3 in the redistribution structure under construction. The line width and spacing (L/S) of the third conductive pad m3p and the third conductive trace m3t are no greater than about 2 μm and 2 μm, respectively. In addition, the third barrier layer 531 filled in the opening p72H and the patterned third seed layer p53 associated with the opening p72H constitute the via M2v of the second conductive layer M2 in the redistribution structure under construction. Specifically, referring back also to fig. 11J, the second conductive layer M2 includes a second conductive pad M2p, a second conductive trace M2t, and a second via M2 v.

As a result, the redistribution structure 201 having the 2P3M configuration is realized including the patterned first and second dielectric layers P71 and P72 as 2P, and the first, second, and third conductive layers M1, M2, and M3 as 3M. The 2P3M redistribution structure 201 is exemplary only and not limiting. Redistribution structures having different configurations may be prepared according to the methods described and illustrated with reference to fig. 11A through 11K without departing from the intended scope of the present disclosure.

Fig. 12A-12C illustrate one or more stages of a method of fabricating the substrate structure shown in fig. 1, in accordance with an embodiment of the present disclosure.

Referring to fig. 12A, an adhesive layer 80 is formed on the redistribution structure 201 by using, for example, a printing, laminating, potting, or coating process, covering the third conductive layer M3 and the patterned second dielectric layer p 72. The adhesive layer 80 facilitates attachment of the redistribution structure 201 to the substrate 101 and acts as a buffer against the pushing force from the connection assembly. The adhesive layer 80 has a surface 80s facing away from the first carrier 41. Suitable materials for adhesive layer 80 include ACP, ACF, non-conductive paste (NCP), non-conductive film (NCF), PI, epoxy, or resin. In an embodiment, adhesive layer 80 has a thickness in a range of about 20 μm to about 100 μm.

Referring to fig. 12B, a substrate 101 is provided having one or more connection components 30 formed thereon. In addition, a redistribution structure 201 is provided with an adhesive layer 80 attached. The tip portion 30t of the joining assembly 30 is oriented toward the surface 80s of the adhesive layer 80. A force f is then applied, for example from a laminator, to combine the substrate 101 and the redistribution structure 201 (movement is shown by the arrow). Thus, the connection assembly 30 is pushed into the redistribution structure 201 by the adhesive layer 80. Specifically, referring to fig. 12C, the connection member 30 penetrates the patterned second dielectric layer p72 in addition to the adhesive layer 80, and then penetrates the patterned first dielectric layer p71 to reach the first conductive layer M1 in the redistribution structure 201, thereby electrically connecting the substrate 101 and the redistribution structure 201. In addition, the connection assembly 30 may be pushed all the way through one or more conductive layers toward the first conductive layer M1. In the present example, the connection assembly 30 penetrates the second conductive trace m2t and the second conductive pad m2p, resulting in a deformed second conductive trace dm2t and a deformed second conductive pad dm2p, respectively. Thus, the connection assembly 30 may electrically connect the substrate 101 to a desired conductive layer in the redistribution structure 201.

The first release film 41r or the first carrier 41 or both serve as a buffer against the pushing-in of the connection member 30 for the first conductive layer M1, and the first conductive layer M1 is disposed most adjacent to the first release film 41r or the first carrier 41. As a result, in the first conductive pad M1p or the first conductive trace M1t of the first conductive layer M1 electrically connected to the connection component 30, the first solder layer 512 and the first barrier layer 511 are pierced, and the patterned first seed layer p51 may not be pierced. Therefore, no significant deformation may occur at the first conductive pad m1p or the first conductive trace m1 t. The first carrier 41 and the first release film 41r are then removed, thereby obtaining the substrate structure 100 as shown in fig. 1.

Referring back to fig. 12B, instead of the stud-bump type connection assembly 30, a strut type connection assembly 83 described and illustrated with reference to fig. 10I is employed. Thus, a substrate 101 is provided on which one or more connection components 83 are formed. In addition, a redistribution structure 201 is provided with an adhesive layer 80 attached. The tip portion 83t of the connecting member 83 is oriented toward the surface 80s of the adhesive layer 80. The substrate 101 and the redistribution structure 201 are then electrically connected to each other in a similar manner as described and illustrated with reference to fig. 12B and 12C.

Spatial descriptions such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "over," "under," are directed relative to the orientation shown in the figures unless otherwise specified. It is to be understood that the spatial description used herein is for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure do not depart from such arrangements.

As used herein, the terms "about," "approximately," and "approximately" are used to describe and illustrate minor variations. When used in conjunction with an event or context, the terms may refer to instances in which the event or context occurs precisely as well as instances in which the event or context occurs in close approximation. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are "substantially" identical or equal if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values, e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise.

As used herein, the terms "conductive" and "conductivity" refer to the ability to transmit electrical current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electrical current. One measure of conductivity is siemens per meter (S/m). Typically, the conductivity of the conductive material is greater than about 104S/m, such as at least 105S/m or at least 106S/m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

Additionally, quantities, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and should be interpreted flexibly to include numerical values explicitly recited as the limits of the range, and also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The figures are not necessarily to scale. Due to manufacturing processes and tolerances, there may be a distinction between process reproductions of the present disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically shown. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.