阅读说明：本技术 具有静电放电保护机制的集成电路 (Integrated circuit with electrostatic discharge protection mechanism ) 是由 赵传珍 白景尧 于 2020-10-29 设计创作，主要内容包括：集成电路包括信号焊垫,用以在正常模式接收输入信号,及用以在静电放电模式接收静电放电信号；内部电路,用以在正常模式处理输入信号；可变阻抗电路,具有第一端耦接信号焊垫,第二端耦接内部电路,可变阻抗电路用以在正常模式及静电放电模式于信号焊垫与内部电路之间分别提供低阻抗路径及高阻抗路径；以及开关电路,具有第一端耦接可变阻抗电路的控制端,第二端耦接参考电压端,以及控制端用以接收节点电压,开关电路用以在正常模式使可变阻抗电路的控制端具有第一特定电压,以及用以在静电放电模式使可变阻抗电路的控制端为电性浮接。(The integrated circuit comprises a signal welding pad, a signal receiving module and a signal processing module, wherein the signal welding pad is used for receiving an input signal in a normal mode and receiving an electrostatic discharge signal in an electrostatic discharge mode; an internal circuit for processing an input signal in a normal mode; a variable impedance circuit having a first end coupled to the signal pad and a second end coupled to the internal circuit, the variable impedance circuit being configured to provide a low impedance path and a high impedance path between the signal pad and the internal circuit in the normal mode and the electrostatic discharge mode, respectively; and a switch circuit having a first terminal coupled to the control terminal of the variable impedance circuit, a second terminal coupled to the reference voltage terminal, and a control terminal for receiving the node voltage, the switch circuit being configured to enable the control terminal of the variable impedance circuit to have a first specific voltage in a normal mode, and to enable the control terminal of the variable impedance circuit to be electrically floating in an electrostatic discharge mode.)

1. An integrated circuit having an electrostatic discharge (ESD) protection mechanism, comprising:

a signal pad for receiving an input signal in a normal mode and for receiving an electrostatic discharge signal in an electrostatic discharge mode;

an internal circuit for processing the input signal in the normal mode;

a variable impedance circuit having a first terminal coupled to the signal pad, a second terminal coupled to the internal circuit, and a control terminal, the variable impedance circuit being configured to provide a low impedance path between the signal pad and the internal circuit in the normal mode, and to provide a high impedance path between the signal pad and the internal circuit in the electrostatic discharge mode; and

a switch circuit having a first terminal coupled to the control terminal of the variable impedance circuit, a second terminal coupled to a reference voltage terminal, and a control terminal for receiving a node voltage, the switch circuit being configured to enable the control terminal of the variable impedance circuit to have a first specific voltage in the normal mode, and to enable the control terminal of the variable impedance circuit to be electrically floating in the esd mode.

2. The integrated circuit of claim 1, wherein in the normal mode, an absolute value of a voltage difference between the node voltage and a voltage at the first terminal or a voltage at the second terminal of the switch circuit is greater than an absolute value of a threshold voltage of the switch circuit, so that the switch circuit is turned on.

3. The integrated circuit of claim 2, wherein the control terminal of the variable impedance circuit is electrically coupled to the reference voltage terminal to have the first specific voltage.

4. The integrated circuit of claim 1, wherein in the ESD mode, an absolute value of a voltage difference between the node voltage and a voltage at the first terminal or a voltage at the second terminal of the switch circuit is smaller than an absolute value of a threshold voltage of the switch circuit, such that the switch circuit is turned off.

5. An integrated circuit according to claim 4, wherein the node voltage has a floating voltage.

6. The integrated circuit of claim 1, wherein the control terminal of the switch circuit is coupled to the internal circuit, and the node voltage is related to a power on/off state of the internal circuit.

7. An integrated circuit according to claim 6, wherein

In the normal mode, the internal circuit is in a power-on state, so that the node voltage has a second specific voltage; and

in the ESD mode, the internal circuit is in a power-off state, so that the node voltage has a floating voltage.

8. The integrated circuit of claim 1, further comprising:

a first ESD detection circuit for generating the node voltage according to the input signal or the ESD signal.

9. The integrated circuit of claim 8, wherein the first ESD detection circuit has a first terminal coupled between the signal pad and the first terminal of the variable impedance circuit, a second terminal coupled to the reference voltage terminal, and an output terminal coupled to the control terminal of the switch circuit for outputting the node voltage.

10. The integrated circuit of claim 9, wherein the switch circuit comprises a PMOS transistor, the first esd detection circuit comprising:

at least one first diode having a first end coupled to the first end of the first ESD detection circuit and a second end coupled to the output end of the first ESD detection circuit; and

a first impedance element having a first end coupled to the second end of the at least one first diode and a second end coupled to the second end of the first ESD detection circuit.

11. The integrated circuit of claim 9, wherein the switch circuit comprises an NMOS transistor, and the first esd detection circuit comprises:

a first resistor having a first end coupled to the first end of the first ESD detection circuit and a second end coupled to the output end of the first ESD detection circuit; and

a first capacitor having a first end coupled to the second end of the first resistor and a second end coupled to the second end of the first ESD detection circuit.

12. The integrated circuit of claim 11 wherein a time constant of the first resistor and the first capacitor is greater than a pulse width of the esd signal and less than a switching time of the input signal.

13. The integrated circuit of claim 1, wherein the variable impedance circuit comprises at least one switch, a first switch of the at least one switch having a first terminal coupled to the first terminal of the variable impedance circuit, a second terminal coupled to the second terminal of the variable impedance circuit, and a control terminal coupled to the control terminal of the variable impedance circuit.

14. An integrated circuit as claimed in claim 13, wherein a second switch of the at least one switch has a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the second terminal of the variable impedance circuit, and a control terminal coupled to the control terminal of the variable impedance circuit.

15. An integrated circuit according to claim 13, wherein the first switch comprises a PMOS transistor, a PFET or a pHEMT.

16. The integrated circuit of claim 15, wherein the switch circuit comprises a PMOS transistor or an NMOS transistor.

17. The integrated circuit of claim 16, further comprising:

a second ESD detection circuit having a first terminal coupled to the signal pad and the first terminal of the variable impedance circuit, a second terminal coupled to the reference voltage terminal, and an output terminal coupled to the control terminal of the switch circuit for outputting the node voltage.

18. The integrated circuit of claim 17, wherein the switch circuit comprises the PMOS transistor, and the second esd detection circuit comprises:

at least one second diode having a first end coupled to the first end of the second ESD detection circuit and a second end coupled to the output end of the second ESD detection circuit; and

a second impedance element having a first end coupled to the second end of the at least one second diode and a second end coupled to the second end of the second ESD detection circuit.

19. The integrated circuit of claim 17, wherein the switch circuit comprises the NMOS transistor, and the second esd detection circuit comprises:

a second resistor having a first end coupled to the first end of the second ESD detection circuit and a second end coupled to the output end of the second ESD detection circuit; and

a second capacitor having a first end coupled to the second end of the second resistor and a second end coupled to the second end of the second ESD detection circuit.

20. An integrated circuit according to claim 17, wherein the integrated circuit further comprises:

an ESD protection device having a first terminal coupled between the signal pad and the first terminal of the second ESD detection circuit and a second terminal coupled to the reference voltage terminal, the ESD protection device providing an ESD signal discharge path in the ESD mode.

Technical Field

The present invention relates to an Integrated Circuit (IC) having an electrostatic discharge (ESD) protection mechanism, and more particularly, to an IC having an ESD protection mechanism and a smaller circuit area and parasitic capacitance.

Background

An electrostatic discharge (ESD) protection capability test is used to evaluate reliability of an Integrated Circuit (IC). In order to prevent damage caused by an excessive electrostatic discharge signal (ESD signal) entering an internal circuit of an IC, an electrostatic discharge protection device (ESD protection device) is usually provided in the IC to provide a discharge path for the ESD signal. However, the on-resistance of the ESD protection device and the voltage generated by the ESD signal may exceed the maximum voltage that can be borne by the internal circuit, thereby damaging the internal circuit. Therefore, the prior art generally increases the circuit size of the ESD protection device (e.g. by 3 times of the original circuit size) to reduce the on-resistance of the ESD protection device and improve the ESD signal discharge capability of the ESD protection device.

However, increasing the circuit size of the ESD protection device not only occupies more circuit area of the IC, but also requires higher production cost. In addition, the ESD protection device with larger circuit size has relatively larger parasitic capacitance, resulting in a reduction of the switching speed of the internal circuit. In view of the above, there is a need for improvement in the prior art.

Disclosure of Invention

Therefore, it is a primary objective of the claimed invention to provide an integrated circuit with esd protection mechanism and smaller circuit area and parasitic capacitance.

The invention provides an integrated circuit with an electrostatic discharge protection mechanism, which comprises a signal welding pad, a signal receiving module and a signal processing module, wherein the signal welding pad is used for receiving an input signal in a normal mode and receiving an electrostatic discharge signal in an electrostatic discharge mode; an internal circuit for processing the input signal in the normal mode; a variable impedance circuit having a first terminal coupled to the signal pad, a second terminal coupled to the internal circuit, and a control terminal, the variable impedance circuit being configured to provide a low impedance path between the signal pad and the internal circuit in the normal mode, and to provide a high impedance path between the signal pad and the internal circuit in the electrostatic discharge mode; and a switch circuit having a first terminal coupled to the control terminal of the variable impedance circuit, a second terminal coupled to a reference voltage terminal, and a control terminal for receiving a node voltage, the switch circuit being configured to enable the control terminal of the variable impedance circuit to have a first specific voltage in the normal mode, and to enable the control terminal of the variable impedance circuit to be electrically floating in the esd mode.

Drawings

FIG. 1 is a diagram of an integrated circuit according to an embodiment of the invention.

FIG. 2 is a diagram of another integrated circuit according to an embodiment of the present invention.

FIG. 3 is a diagram of another integrated circuit according to an embodiment of the present invention.

FIG. 4 is a diagram of another integrated circuit according to an embodiment of the present invention.

FIG. 5 is a diagram of another integrated circuit according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of the integrated circuit shown in FIG. 5 according to an embodiment of the invention.

Fig. 7 to 10 show a variation of the esd protection device shown in fig. 6 according to the embodiment of the invention.

[ notation ] to show

10,20,30,40,50: integrated circuit with a plurality of transistors

100: signal welding pad

102: internal circuit

104: variable impedance circuit

106: switching circuit

300,400,500: electrostatic discharge detection circuit

502: electrostatic discharge protection device

A, B: node point

Cap: capacitor with a capacitor element

D1-Dm diode

Mn: NMOS transistor

And Mp: PMOS transistor

Res: resistance (RC)

SW 1-SWn: switch with a switch body

And Vn: node voltage

Vref, Vdd: reference voltage

Z: impedance assembly

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of an Integrated Circuit (IC) 10 according to an embodiment of the invention. IC 10 has an electrostatic discharge (ESD) protection mechanism, and IC 10 includes a signal pad 100, an internal circuit 102, a variable impedance circuit 104, and a switch circuit 106. The signal pad 100 may be configured to receive an input signal in a normal mode (normal mode) and may be configured to receive an electrostatic discharge signal (ESD signal) in an electrostatic discharge mode (ESD mode). The input signal may be a dc voltage or an ac voltage, and the ESD signal may be an ESD current or an ESD voltage. The internal circuitry 102 may be used to process the input signal in the normal mode. The variable impedance circuit 104 has a first terminal coupled to the signal pad 100, a second terminal coupled to the internal circuit 102, and a control terminal. The variable impedance circuit 104 may be configured to provide a low impedance path between the signal pad 100 and the internal circuit 102 in the normal mode and may be configured to provide a high impedance path between the signal pad 100 and the internal circuit 102 in the ESD mode. The switch circuit 106 has a first terminal coupled to the control terminal of the variable impedance circuit 104, a second terminal coupled to the reference voltage terminal, and a control terminal for receiving the node voltage Vn. The switch circuit 106 is configured to enable the control terminal of the variable impedance circuit 104 to have a first specific voltage in the normal mode, and is configured to enable the control terminal of the variable impedance circuit 106 to be electrically floating (electrically floating) in the ESD mode. In addition, the reference voltage Vref may be applied to a reference voltage terminal, and the reference voltage Vref may be a ground voltage (e.g., 0 v) or other fixed voltage with a low voltage level.

Node a may be formed between the signal pad 100 and the first end of the variable impedance circuit 104. The node B may be formed between the second end of the variable impedance circuit 104 and the internal circuit 102. In other words, in the normal mode, the low impedance path provided by the variable impedance circuit 104 between the node a and the node B is equivalent to providing a transmission path from the signal pad 100 to the internal circuit 102 for the input signal, so that the internal circuit 102 can normally receive and process the input signal. On the other hand, in the ESD mode, the high impedance path provided by the variable impedance circuit 104 between the node a and the node B is equivalent to increase the difficulty of the ESD signal transmitting from the signal pad 100 to the internal circuit 102 (for example, the high impedance path is equivalent to provide the internal circuit 102 with an extra capability of bearing the ESD signal, so as to block the ESD signal from entering the internal circuit 102), so that the ESD signal is greatly reduced between the node a and the node B, and therefore the ESD signal is not easy to directly enter the internal circuit 102, thereby preventing the internal circuit 102 from being damaged. Therefore, the present invention can properly design the circuit to not affect the operation of the internal circuit 102 in the normal mode, and reduce the effect of the ESD signal on the internal circuit 102 in the ESD mode. In addition, the present invention can also have a smaller circuit area (e.g., the proportion of the variable impedance circuit 104 in the whole circuit area of the IC 10 is less than 0.5%) and a smaller parasitic capacitance by properly designing the circuit size of the variable impedance circuit 104. The smaller parasitic capacitance is beneficial to maintain the integrity of the input signal in the normal mode and may improve the impact on the switching speed of the internal circuit 102.

Specifically, in the normal mode, the absolute value of the voltage difference between the node voltage Vn and the voltage at the first terminal or the voltage at the second terminal of the switch circuit 106 is larger than the absolute value of the threshold voltage (threshold voltage) of the switch circuit 106, and the switch circuit 106 is turned on. The turned-on switch circuit 106 may electrically couple the control terminal of the variable impedance circuit 104 to the reference voltage terminal to have a first specific voltage (e.g., close to the reference voltage Vref on the reference voltage terminal), and the variable impedance circuit 104 thereby provides a low impedance path. In the ESD mode, on the other hand, the absolute value of the voltage difference between the node voltage Vn and the voltage at the first terminal or the voltage at the second terminal of the switch circuit 106 is smaller than the absolute value of the threshold voltage of the switch circuit 106, and the switch circuit 106 is turned off. The off switch circuit 106 may electrically float the control terminal of the variable impedance circuit 104, and the variable impedance circuit 104 may thereby provide a high impedance path. It is noted that the node voltage Vn may be related to the power on/off state of the internal circuit 102 or may be provided by other circuits. It is not limited thereto but may be modified or changed by those skilled in the art.

Specifically, referring to fig. 2, fig. 2 is a schematic diagram of another IC 20 according to an embodiment of the invention. The variable impedance circuit 104 may include at least one switch. Notably, the number of switches is related to the ESD protection capability of IC 20. That is, the variable impedance circuit 104 has flexibility in design. Further, the relationship between the number of switches and the ESD protection capability of the IC 20 may be designed to be positive. The embodiment of fig. 2 is described by way of example in which the variable impedance circuit 104 includes n switches SW 1-SWn. The n switches SW 1-SWn may form a stack (stack) structure. In detail, the switch SWi has a first terminal coupled to the first terminal of the variable impedance circuit 104, a second terminal coupled to the second terminal of the variable impedance circuit 104, and a control terminal coupled to the control terminal of the variable impedance circuit 104. The switch SW1 has a first terminal coupled to the first terminal of the variable impedance circuit 104, a second terminal coupled to the first terminal of the switch SWi, and a control terminal coupled to the control terminal of the variable impedance circuit 104. The switch SWn has a first terminal coupled to the second terminal of the switch SWi, a second terminal coupled to the second terminal of the variable impedance circuit 104, and a control terminal coupled to the control terminal of the variable impedance circuit 104. The variables n and i are positive integers, 1< i < n. Each of switches SW 1-SWn may include a P-channel metal oxide semiconductor (PMOS) transistor, a P-channel field effect transistor (PFET) or a pseudomorphic high electron mobility transistor (pHEMT). In addition, the present invention can select smaller size PMOS transistor, PFET or pHEMT to make the variable impedance circuit 104 have smaller circuit area and parasitic capacitance. The embodiment of fig. 2 is illustrated with switches SW 1-SWn each including a PMOS transistor. The first terminals of the switches SW 1-SWn may be one of the drain and source of the PMOS transistors, the second terminals may be the other of the drain and source of the PMOS transistors, and the control terminals may be the gates of the PMOS transistors.

As shown in fig. 2, the control terminal of the switch circuit 106 is coupled to the internal circuit 102, and the node voltage Vn is related to the power on/off state of the internal circuit 102. The switch circuit 106 may include a PMOS transistor or an N-channel metal oxide semiconductor (NMOS) transistor. The embodiment of fig. 2 is illustrated by taking the example that the switch circuit 106 includes the NMOS transistor Mn. The first terminal of the switch circuit 106 may be a drain of the NMOS transistor Mn, the second terminal may be a source of the NMOS transistor Mn, and the control terminal may be a gate of the NMOS transistor Mn.

In the normal mode, the internal circuit 102 is in a power-on state, so that the node voltage Vn has a second specific voltage. That is, the reference voltage Vdd is applied to the high level reference voltage terminal of the internal circuit 102, and the reference voltage Vref is applied to the low level reference voltage terminal of the internal circuit 102, so as to power the internal circuit 102, such that the internal circuit 102 can operate normally (e.g., process the input signal). The node voltage Vn associated with the power-on state of the internal circuit 102 has a second specific voltage due to the operation of the internal circuit 102, so that the absolute value of the voltage difference between the node voltage Vn and the voltage at the source of the NMOS transistor Mn (or the gate-source voltage difference of the NMOS transistor Mn) is greater than the absolute value of the threshold voltage of the NMOS transistor Mn, thereby making the NMOS transistor Mn in the on state. Thus, the control terminals of the switches SW 1-SWn are electrically coupled to the reference voltage terminal having the reference voltage Vref and have a lower voltage level, and the switches SW 1-SWn are turned on, so that the variable impedance circuit 104 can provide a low impedance path between the signal pad 100 and the internal circuit 102.

On the other hand, in the ESD mode, the internal circuit 102 is in a power-off state so that the node voltage Vn has a floating voltage. That is, the reference voltage Vdd is not applied to the high level reference voltage terminal of the internal circuit 102, and the reference voltage Vref is not applied to the low level reference voltage terminal of the internal circuit 102, the high level reference voltage terminal and the low level reference voltage terminal of the internal circuit 102 are electrically floating, and thus the internal circuit 102 is not powered. The node voltage Vn associated with the power-off state of the internal circuit 102 has a floating voltage due to the internal circuit 102 not being supplied with power, so that the absolute value of the voltage difference between the node voltage Vn and the voltage of the source of the NMOS transistor Mn (or alternatively, the gate-source voltage difference of the NMOS transistor Mn) is smaller than the absolute value of the threshold voltage of the NMOS transistor Mn, thereby putting the NMOS transistor Mn in the off state. Thus, the control terminals of the switches SW 1-SWn are electrically floating, and the switches SW 1-SWn are turned off, so that the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102. Wherein the floating voltage may have an unspecified voltage.

It is noted that, in other embodiments, when the switch circuit 106 includes a PMOS transistor, the first terminal of the switch circuit 106 may be a source of the PMOS transistor, the second terminal may be a drain of the PMOS transistor, and the control terminal may be a gate of the PMOS transistor. In the normal mode, the node voltage Vn also has a second specific voltage due to the operation of the internal circuit 102, such that the absolute value of the voltage difference between the node voltage Vn and the voltage of the source of the PMOS transistor (or the source gate voltage difference of the PMOS transistor) is greater than the absolute value of the threshold voltage of the PMOS transistor, thereby turning on the PMOS transistor. Thus, the control terminals of the switches SW 1-SWn are electrically coupled to the reference voltage terminal having the reference voltage Vref and have a lower voltage level, and the switches SW 1-SWn are turned on, so that the variable impedance circuit 104 can provide a low impedance path between the signal pad 100 and the internal circuit 102. In addition, in the ESD mode, the node voltage Vn also has a floating voltage due to the internal circuit 102 not being powered, so that the absolute value of the voltage difference between the node voltage Vn and the voltage of the source of the PMOS transistor (or the source-gate voltage difference of the PMOS transistor) is smaller than the absolute value of the threshold voltage of the PMOS transistor, thereby turning off the PMOS transistor. Thus, the control terminals of the switches SW 1-SWn are electrically floating, and the switches SW1 ℃

SWn is thus off, the variable impedance circuit 104 provides a high impedance path between the signal pad 100 and the internal circuit 102.

Specifically, referring to fig. 3, fig. 3 is a schematic diagram of another IC 30 according to an embodiment of the invention. The IC 30 is substantially similar to the IC 20 shown in fig. 2, and therefore components with similar structures and functions are denoted by the same symbols, the main difference between the IC 30 and the IC 20 is that the IC 30 further includes an electrostatic discharge detection circuit (ESD detection circuit)300 for generating a node voltage Vn according to an input signal or an ESD signal. In detail, the ESD detection circuit 300 has a first terminal coupled between the signal pad 100 and the first terminal of the variable impedance circuit 104, a second terminal coupled to the reference voltage terminal, and an output terminal coupled to the control terminal of the switch circuit 106 for outputting the node voltage Vn. The embodiment of fig. 3 is illustrated by taking the case where the switch circuit 106 includes the NMOS transistor Mn. In this case, the ESD detection circuit 300 may include a resistor Res and a capacitor Cap. The resistor Res has a first terminal coupled to the first terminal of the ESD detection circuit 300, and a second terminal coupled to the output terminal of the ESD detection circuit 300. The capacitor Cap has a first terminal coupled to the second terminal of the resistor Res, and a second terminal coupled to the second terminal of the ESD detection circuit 300. The time constant (time constant) between the resistor Res and the capacitor Cap can be designed to be greater than the pulse width (pulse width) of the ESD signal and smaller than the switching time of the input signal (for example, the time constant between the resistor Res and the capacitor Cap can be designed to be greater than 100ns and smaller than 300 ns). In other embodiments, in the case where the internal circuit 102 itself has a resistor and a capacitor connected in series between the node a and the reference voltage terminal, it can be used as an ESD detection circuit, i.e., the control terminal of the switch circuit 106 is coupled to the internal circuit 102 and shares the resistor and the capacitor with other components in the internal circuit 102, without additionally providing a resistor Res and a capacitor Cap outside the internal circuit 102.

In the normal mode, the input signal passes through the node a from the signal pad 100, and since the time constant between the resistor Res and the capacitor Cap is smaller than the switching time of the input signal, the capacitor Cap is equivalent to an open circuit (open circuit) for the input signal, so that the node voltage Vn is pulled up to a voltage close to the node a, and the absolute value of the voltage difference between the node voltage Vn and the voltage at the source of the NMOS transistor Mn (or the gate-source voltage difference of the NMOS transistor Mn) is larger than the absolute value of the threshold voltage of the NMOS transistor Mn, thereby making the NMOS transistor Mn in the on state. Thus, the control terminals of the switches SW 1-SWn are electrically coupled to the reference voltage terminal having the reference voltage Vref and have a lower voltage level, and the switches SW 1-SWn are turned on, so that the variable impedance circuit 104 can provide a low impedance path between the signal pad 100 and the internal circuit 102. In the ESD mode, the ESD signal passes through the node a from the signal pad 100, and the capacitor Cap is equivalent to a short circuit (short circuit) for the high frequency ESD signal, so that the node voltage Vn is pulled down to be close to the reference voltage Vref on the reference voltage terminal, or the node voltage Vn is pulled down to be close to the reference voltage Vref on the reference voltage terminal within the pulse width time of the ESD signal because the time constant of the resistor Res and the capacitor Cap is designed to be larger than the pulse width of the ESD signal. Therefore, the absolute value of the voltage difference between the node voltage Vn and the voltage at the source of the NMOS transistor Mn (or the gate-source voltage difference of the NMOS transistor Mn) is smaller than the absolute value of the threshold voltage of the NMOS transistor Mn, so that the NMOS transistor Mn is in the off state. Thus, the control terminals of the switches SW 1-SWn are electrically floating, and the switches SW 1-SWn are turned off, so that the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102.

On the other hand, please refer to fig. 4, in which fig. 4 is a schematic diagram of another IC 40 according to an embodiment of the present invention. IC 40 is substantially similar to IC 30 shown in fig. 3, and therefore components having similar structures and functions are denoted by the same symbols, the main difference between IC 40 and IC 30 is that the embodiment shown in fig. 4 is illustrated with switch circuit 106 comprising PMOS transistor Mp. IC 40 includes ESD detection circuit 400 externally connected in a manner similar to ESD detection circuit 300, but includes different components. In the case where the switch circuit 106 includes a PMOS transistor Mp, the ESD detection circuit 400 may include at least one diode and an impedance component Z. It is noted that the number of diodes is related to the operating voltage of the input signal. Further, the overall turn-on voltage of the at least one diode may be designed to be greater than the operating voltage of the input signal in the normal mode. The impedance component Z may comprise an inductance and/or a resistance. That is, the ESD detection circuit 400 has flexibility in design. The embodiment of FIG. 4 is illustrated with the ESD detection circuit 400 including m diodes D1-Dm and the impedance component Z including a resistor. The m diodes D1-Dm may form a stack structure. In detail, the diode Dj has a first terminal coupled to the first terminal of the ESD detection circuit 400, and a second terminal coupled to the output terminal of the ESD detection circuit 400. The diode D1 has a first terminal coupled to the first terminal of the ESD detection circuit 400, and a second terminal coupled to the first terminal of the diode Dj. The diode Dm has a first terminal coupled to the second terminal of the diode Dj, and a second terminal coupled to the output terminal of the ESD detection circuit 400. The impedance device Z has a first terminal coupled to the second terminal of the diode Dm, and a second terminal coupled to the second terminal of the ESD detection circuit 400. Wherein, variables m and j are positive integers, 1< j < m. However, when the ESD detection circuit 400 only includes the diode Dj and the impedance device Z, the first terminal of the impedance device Z is coupled to the second terminal of the diode Dj. The first terminal of the diodes D1-Dm may be an anode and the second terminal may be a cathode. In other embodiments, at least one diode connected (diode connected) transistor may be used to replace at least one of the diodes D1-Dm in the ESD detection circuit 400. In addition, in other embodiments, in the case where the internal circuit 102 itself has at least one diode and impedance element connected in series between the node a and the reference voltage terminal, it can be used as the ESD detection circuit, i.e. the control terminal of the switch circuit 106 is coupled to the internal circuit 102 and shares at least one diode and impedance element with other elements in the internal circuit 102, without additionally providing at least one diode D1-Dm and impedance element Z outside the internal circuit 102.

In the normal mode, the input signal passes through the node a from the signal pad 100, and since the overall on-voltage of the diodes D1-Dm is designed to be greater than the operating voltage of the input signal in the normal mode, that is, the voltage at the node a is smaller than the overall on-voltage of the diodes D1-Dm, the diodes D1-Dm are turned off, so that the node voltage Vn is close to the reference voltage Vref at the reference voltage end, and the absolute value of the voltage difference between the node voltage Vn and the voltage at the source of the PMOS transistor Mp (or the source-gate voltage difference of the PMOS transistor Mp) is greater than the absolute value of the threshold voltage of the PMOS transistor Mp, so that the PMOS transistor Mp is turned on. Thus, the control terminals of the switches SW 1-SWn are electrically coupled to the reference voltage terminal having the reference voltage Vref and have a lower voltage level, and the switches SW 1-SWn are turned on, so that the variable impedance circuit 104 can provide a low impedance path between the signal pad 100 and the internal circuit 102. In the ESD mode, the ESD signal passes through the node a from the signal pad 100, the voltage at the node a is greater than the overall on-voltage of the diodes D1-Dm, and thus the diodes D1-Dm are turned on, so that the node voltage Vn is considered as the voltage at the node a minus the overall on-voltage of the diodes D1-Dm, and the absolute value of the voltage difference between the node voltage Vn and the voltage at the source of the PMOS transistor (or the source-gate voltage difference of the PMOS transistor Mp) is smaller than the absolute value of the threshold voltage of the PMOS transistor, thereby turning off the PMOS transistor Mp. Thus, the control terminals of the switches SW 1-SWn are electrically floating, and the switches SW 1-SWn are turned off, so that the variable impedance circuit 104 can provide a high impedance path between the signal pad 100 and the internal circuit 102.

Referring to fig. 5, fig. 5 is a diagram of another IC50 according to an embodiment of the invention. The IC50 is substantially similar to the IC 10 shown in fig. 1, and therefore components with similar structures and functions are denoted by the same symbols, and the main difference between the IC50 and the IC 10 is that the IC50 further includes an ESD detection circuit 500 and an electrostatic discharge protection device (ESD protection device) 502. The ESD detection circuit 500 can be implemented by the ESD detection circuit 300 shown in fig. 3 or the ESD detection circuit 400 shown in fig. 4, which is not described herein for brevity. The ESD protection device 502 has a first terminal coupled to the signal pad 100 (e.g., the first terminal of the ESD protection device 502 is coupled between the signal pad 100 and the first terminal of the ESD detection circuit 500, or the first terminal of the ESD protection device 502 is coupled to the node a), and a second terminal coupled to the reference voltage terminal. The ESD protection device 502 is used to provide an ESD signal discharge path in the ESD mode. Further, the ESD signal discharge path is used to shunt (shunt) the ESD signal to the reference voltage terminal to reduce the strength of the ESD signal. In other words, in the ESD mode, the structure of the IC50 not only can shunt the ESD signal to the reference voltage terminal through the ESD protection device 502, but also can make the ESD signal less likely to directly enter the internal circuit 102 through the high impedance path provided by the variable impedance circuit 104 (e.g., the high impedance path is equivalent to providing the internal circuit 102 with an additional capability of bearing the on-resistance of the ESD protection device 502 and the voltage generated by the ESD signal, thereby blocking the ESD signal from entering the internal circuit 102). That is, the ESD protection device 502 and the variable impedance circuit 104 may be used to provide a dual-layer ESD protection mechanism for the internal circuit 102, which is beneficial to improve the ESD protection capability of the IC 50. It is noted that in the above embodiments, the ESD signal is reduced to enter the internal circuit 102 through the high impedance path provided by the variable impedance circuit 104, without increasing the circuit size of the ESD protection device 502. Therefore, compared to the prior art by increasing the circuit size of the ESD protection device (e.g., by 3 times the original circuit size), the variable impedance circuit 104 (e.g., the circuit size is 0.3 times the size of the ESD protection device 502) and the ESD protection device 502 can have a smaller overall circuit area (e.g., the circuit size is 1.3 times the size of the ESD protection device 502), and have a smaller parasitic capacitance. In other embodiments, the ESD detection circuit 500 may not be additionally disposed, and the control terminal of the switch circuit 106 is coupled to the internal circuit 102, so that the node voltage Vn is related to the power on/off state of the internal circuit 102, or the node voltage Vn may be provided by the components in the internal circuit 102. In addition, the node voltage Vn can be provided by other circuits.

In detail, referring to fig. 6, fig. 6 is a circuit diagram of the IC50 shown in fig. 5 according to an embodiment of the invention. IC50 is substantially similar to IC 30 of fig. 3, and therefore components having similar structures and functions are denoted by the same symbols, the main difference between IC50 and IC 30 is that IC50 further includes ESD protection device 502, and ESD protection device 502 is implemented by resistor, capacitor, inverter, and NMOS transistor structures. In the ESD mode, the resistor, the capacitor and the inverter are used for controlling the NMOS transistor to be in a conducting state so as to provide an ESD signal discharge path. The circuit operation of the ESD protection device 502 shown in fig. 6 is well known to those skilled in the art, and will not be described herein for brevity. In addition, referring to fig. 7 to 10, fig. 7 to 10 are modified embodiments of the ESD protection device 502 shown in fig. 6 according to the embodiment of the present invention. As shown in fig. 7 to 10, the circuit structure of the ESD protection device 502 can be implemented by a Silicon-Controlled Rectifier (SCR) structure, a MOS transistor structure, a diode structure, and an inductor, respectively, to provide an ESD signal discharge path in the ESD mode. The operation of the circuits of fig. 7 to 10 is well known to those skilled in the art, and will not be described herein for brevity.

In summary, the present invention can properly design the circuit to form a low impedance path resistance in the normal mode, so that the internal circuit can normally receive and process the input signal without affecting the operation of the internal circuit. And a high impedance path can be formed in the ESD mode to reduce the influence of ESD signals on internal circuits. In addition, the present invention can have a smaller circuit area and parasitic capacitance by properly designing the circuit size of the variable impedance circuit (for example, designing the number of switches included in the variable impedance circuit and selecting the switches with proper size), which is not only simpler in design, but also more flexible and has a lower production cost.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the protection scope of the present invention.