阅读说明：本技术 半导体装置及半导体元件的制造方法 (Semiconductor device and method for manufacturing semiconductor element ) 是由 野村典嗣 于 2020-09-21 设计创作，主要内容包括：本发明涉及半导体装置及半导体元件的制造方法。抑制了在为了进行在半导体基板形成的半导体元件的电气特性的评价等对半导体元件施加了电压的情况下在半导体元件与元件间部之间发生局部放电,对异物附着于半导体基板、在半导体基板形成部件痕迹等进行抑制。半导体装置具有半导体基板以及放电抑制材料。半导体基板具有元件间部以及多个半导体元件。多个半导体元件在半导体基板的扩展方向排列。元件间部位于多个半导体元件所包含的相邻的半导体元件之间。放电抑制材料附着于元件间部的表面,但没有附着于多个半导体元件所包含的各半导体元件的中央部的表面。放电抑制材料由绝缘体构成。(The present invention relates to a semiconductor device and a method for manufacturing a semiconductor element. The occurrence of partial discharge between a semiconductor element and an inter-element portion when a voltage is applied to the semiconductor element for the purpose of evaluating the electrical characteristics of the semiconductor element formed on a semiconductor substrate or the like is suppressed, and the adhesion of foreign matter to the semiconductor substrate, the formation of component traces on the semiconductor substrate, and the like are suppressed. The semiconductor device includes a semiconductor substrate and a discharge suppressing material. The semiconductor substrate has an inter-element portion and a plurality of semiconductor elements. The plurality of semiconductor elements are arranged in the direction of expansion of the semiconductor substrate. The inter-element portion is located between adjacent semiconductor elements included in the plurality of semiconductor elements. The discharge suppressing material adheres to the surface of the inter-element portion, but does not adhere to the surface of the central portion of each of the plurality of semiconductor elements. The discharge suppressing material is composed of an insulator.)

1. A semiconductor device, comprising:

a semiconductor substrate having an inter-element portion and a plurality of semiconductor elements, the plurality of semiconductor elements being arranged in an expansion direction of the semiconductor substrate, the inter-element portion being located between adjacent semiconductor elements included in the plurality of semiconductor elements; and

and a discharge suppressing material that is attached to a surface of the inter-element portion and is not attached to a surface of a central portion of each of the semiconductor elements included in the plurality of semiconductor elements, the discharge suppressing material being composed of an insulator.

2. The semiconductor device according to claim 1,

the discharge suppressing material is also attached to a surface of an outer peripheral portion of each of the semiconductor elements.

3. The semiconductor device according to claim 1 or 2,

each of the semiconductor elements has an active portion and a terminal portion surrounding the active portion,

the discharge suppressing material is attached to a part of a surface of the active portion and a surface of the terminal portion.

4. The semiconductor device according to any one of claims 1 to 3,

the discharge suppressing material can be peeled from the semiconductor substrate without damaging the plurality of semiconductor elements.

5. The semiconductor device according to any one of claims 1 to 4,

the discharge suppressing material is composed of latex.

6. The semiconductor device according to any one of claims 1 to 4,

the discharge suppressing material is composed of a dry film.

7. The semiconductor device according to any one of claims 1 to 4,

the discharge suppressing material is formed of a rubber seal.

8. A method for manufacturing a semiconductor device includes the steps of:

a step a) of preparing a semiconductor substrate having a plurality of semiconductor elements arranged in an extending direction of the semiconductor substrate and a scribe line between adjacent semiconductor elements included in the plurality of semiconductor elements;

a step b) of attaching a discharge suppressing material to the semiconductor substrate, the discharge suppressing material being attached to the surface of the dicing line but not to the surface of the central portion of each of the semiconductor elements included in the plurality of semiconductor elements, the discharge suppressing material being made of an insulator;

a step c) of applying a voltage to each of the semiconductor elements after the step b);

a step d) of peeling the discharge suppressing material from the semiconductor substrate after the step c); and

and e) cutting the semiconductor substrate along the dicing line after the step d).

9. The method for manufacturing a semiconductor element according to claim 8, wherein,

the step b) comprises the following steps:

a step b-1) of applying a fluid before curing of the discharge suppressing material to the semiconductor substrate to form a coating film; and

and a step b-2) of curing the coating film to change the coating film into the discharge suppressing material.

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor element.

Background

In many cases, a chip-like semiconductor element is manufactured by forming a plurality of semiconductor elements on a semiconductor substrate and singulating the plurality of formed semiconductor elements.

When the electrical characteristics of a semiconductor element are evaluated in the production of a chip-like semiconductor element, the electrical characteristics of the singulated semiconductor element may be evaluated, and the electrical characteristics of a semiconductor element formed on a semiconductor substrate that is not singulated may be evaluated.

When the electrical characteristics of the singulated semiconductor element are evaluated, the mounting surface of the semiconductor element to be evaluated is brought into contact with the surface of the chuck table of the evaluation apparatus by vacuum suction or the like, and fixed to the surface. The probe of the evaluation apparatus is in contact with an electrode provided on a non-mounting surface of the semiconductor element to be evaluated, and inputs and outputs an electric signal to and from the semiconductor element to be evaluated. When the semiconductor element to be evaluated has a vertical structure in which a large current flows in its longitudinal direction, i.e., in its out-of-plane direction, the chuck table functions as an electrode.

When the electrical characteristics of the singulated semiconductor elements are evaluated and the evaluated semiconductor elements have a vertical structure, partial discharge may occur in the evaluated semiconductor elements. The partial discharge is generated, for example, by a potential difference between a potential of an electrode provided on a part of the non-mounting surface of the semiconductor element and a potential of a region having the same potential as that of the chuck table. In addition, the partial discharge may cause a failure of the semiconductor device such as a local damage of the semiconductor device. When partial discharge generated in a process of evaluating electrical characteristics of a semiconductor device is ignored and a semiconductor device having a defective condition is directly transferred to a subsequent process as a non-defective product, it is difficult to extract the semiconductor device having the defective condition in the subsequent process. Therefore, it has been studied to provide an evaluation device with a component for suppressing the occurrence of partial discharge in a semiconductor element and the occurrence of defects in the semiconductor element.

For example, in the technique described in patent document 1, an evaluation jig is used for evaluating a high-voltage semiconductor chip. The evaluation jig is constituted by a probe holding table and the like. A mounting portion is formed on the probe holding stage. The silicone rubber is attached to the attachment portion. The silicone rubber is pressed against the terminal portion of the high withstand voltage semiconductor chip. Thus, the ignition path from the side surface portion of the high-voltage semiconductor chip to the emitter electrode or the gate electrode of the high-voltage semiconductor chip can be cut off by the silicone rubber (paragraph 0030-0045).

When evaluating the electrical characteristics of a semiconductor element formed on a semiconductor substrate, which is not singulated, a probe of an evaluation device is brought into contact with an electrode provided on a non-mounting surface of the semiconductor element to be evaluated, and an electrical signal is input to and output from the semiconductor element to be evaluated.

When electrical characteristics of a semiconductor element formed on a semiconductor substrate and not singulated are evaluated, partial discharge may occur in the evaluated semiconductor element in the same manner. In addition, the partial discharge may cause a failure of the semiconductor device such as a local damage of the semiconductor device. When partial discharge generated in a process of evaluating electrical characteristics of a semiconductor device is ignored and a semiconductor device having a defective condition is directly transferred to a subsequent process as a non-defective product, it is difficult to extract the semiconductor device having the defective condition in the subsequent process. Therefore, it has been studied to provide an evaluation device with a component for suppressing the occurrence of partial discharge in a semiconductor element and the occurrence of defects in the semiconductor element.

For example, in the technique described in patent document 2, a semiconductor wafer measuring apparatus tests a semiconductor device formed on a wafer. In a semiconductor wafer measuring apparatus, an insulating member is brought into contact with a wafer between tips of a pair of probes which are brought into contact with the wafer. Thus, the interface discharge on the chip can be effectively suppressed. Thus, dielectric breakdown due to discharge between the probes can be prevented (paragraph 0023-0026).

Patent document 1: japanese patent laid-open No. 2001-51011

Patent document 2: japanese laid-open patent application No. 2010-10306

In the technique described in patent document 1, a silicone rubber is pressed against a high-voltage semiconductor chip. Therefore, foreign matter sandwiched between the silicone rubber and the high-voltage semiconductor chip adheres to the high-voltage semiconductor chip. Further, silicone rubber traces were formed on the high-voltage semiconductor chip. The adhered foreign matter and the formed silicone rubber trace may cause a trouble in the high-voltage semiconductor chip in the subsequent process.

In the technique described in patent document 1, the silicone rubber is repeatedly pressed against the plurality of high-voltage semiconductor chips. Therefore, when a foreign substance is sandwiched between the silicone rubber and the high voltage semiconductor chips, the sandwiched foreign substance adheres to the plurality of high voltage semiconductor chips which are then pressed by the silicone rubber, and contamination by the sandwiched foreign substance spreads to the plurality of high voltage semiconductor chips. Therefore, when foreign matter is interposed between the silicone rubber and the high-voltage semiconductor chips, a plurality of high-voltage semiconductor chips which are then transferred to the subsequent process may have a problem. Therefore, it is necessary to manage foreign substances adhering to the silicone rubber. However, this management is complicated and difficult.

In the technique described in patent document 2, an insulating member is brought into contact with a wafer. Therefore, as in the technique described in patent document 1, foreign matter interposed between the insulating member and the wafer adheres to the wafer. In addition, an insulating member trace is formed on the wafer. The adhered foreign matter and the formed insulating member trace may cause a trouble in the wafer and the high-voltage semiconductor element in the subsequent process.

In the technique described in patent document 2, an insulating member is repeatedly brought into contact with a plurality of wafers. Therefore, when a foreign substance is sandwiched between the insulating member and the wafers, the foreign substance sandwiched therebetween adheres to a plurality of wafers which are then in contact with the insulating member, and contamination caused by the foreign substance sandwiched therebetween spreads to the plurality of wafers. Therefore, when foreign matter is interposed between the insulating member and the wafer, a plurality of wafers and a plurality of high-voltage semiconductor devices, which are transferred to a subsequent process, may be in a defective state. Therefore, it is necessary to manage foreign matters adhering to the insulating member. However, this management is complicated and difficult.

In addition, the technique described in patent document 2 cannot suppress a partial discharge that actually becomes a problem and is generated between a high-voltage semiconductor element formed on a wafer and an inter-element portion located between adjacent high-voltage semiconductor elements formed on the wafer.

On the other hand, in recent years, when the electrical characteristics of a semiconductor element formed on a semiconductor substrate are evaluated, a high power test can be performed. In addition, by directly assembling the product from the semiconductor substrate, the assembly efficiency of the product can be improved. Therefore, the electrical characteristics of the semiconductor element formed on the semiconductor substrate, which is not singulated, are often evaluated without evaluating the electrical characteristics of the semiconductor element after singulation. However, the above-described problems occur when the electrical characteristics of a semiconductor element formed on a semiconductor substrate and not singulated are evaluated.

Disclosure of Invention

The present invention has been made in view of the above problems. An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor element, which can suppress generation of partial discharge between a semiconductor element and an inter-element portion, and can suppress adhesion of foreign matter to a semiconductor substrate, formation of a component mark on the semiconductor substrate, and the like, when a voltage is applied to the semiconductor element for evaluation of electrical characteristics of the semiconductor element formed on the semiconductor substrate, and the like.

The 1 st aspect of the present invention relates to a semiconductor device.

The semiconductor device includes a semiconductor substrate and a discharge suppressing material.

The semiconductor substrate has an inter-element portion and a plurality of semiconductor elements. The plurality of semiconductor elements are arranged in the direction of expansion of the semiconductor substrate. The inter-element portion is located between adjacent semiconductor elements included in the plurality of semiconductor elements.

The discharge suppressing material adheres to the surface of the inter-element portion, but does not adhere to the surface of the central portion of each of the plurality of semiconductor elements. The discharge suppressing material is composed of an insulator.

The 2 nd aspect of the present invention relates to a method for manufacturing a semiconductor device.

In a method for manufacturing a semiconductor device, a semiconductor substrate is prepared. The prepared semiconductor substrate has a dicing line and a plurality of semiconductor elements. The plurality of semiconductor elements are arranged in the direction of expansion of the semiconductor substrate. The dicing lines are located between adjacent semiconductor elements included in the plurality of semiconductor elements.

In addition, the discharge suppressing material adheres to the semiconductor substrate. The discharge suppressing material adheres to the surface of the dicing line, but does not adhere to the surface of the central portion of each of the plurality of semiconductor elements. The discharge suppressing material is composed of an insulator.

After the discharge suppressing material is attached to the semiconductor substrate, a voltage is applied to each semiconductor element.

After a voltage is applied to each semiconductor element, the discharge suppressing material is peeled off from the semiconductor substrate.

After the discharge suppressing material is peeled off from the semiconductor substrate, the semiconductor substrate is cut along the cutting lines.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, the surface of the inter-element portion which is the starting portion of the partial discharge is covered with the discharge suppressing material made of an insulator. Therefore, the creepage distance between each semiconductor element and the inter-element portion becomes long, and when a voltage is applied to each semiconductor element for evaluation of each semiconductor element or the like, it is possible to suppress occurrence of partial discharge between each semiconductor element and the inter-element portion.

Further, according to the present invention, even when the member for suppressing the occurrence of partial discharge is not pressed against the semiconductor substrate, the creeping distance between each semiconductor element and the inter-element portion can be secured. Therefore, it is not necessary to press a member for suppressing the generation of the partial discharge against the semiconductor substrate. This can suppress the adhesion of foreign matter to the semiconductor substrate, the formation of component traces on the semiconductor substrate, and the like.

The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Drawings

Fig. 1 is a plan view schematically illustrating a semiconductor substrate included in a semiconductor device according to embodiment 1.

Fig. 2 is an enlarged plan view schematically illustrating a part of a semiconductor substrate included in the semiconductor device of embodiment 1.

Fig. 3 is a cross-sectional view schematically illustrating a semiconductor substrate included in the semiconductor device of embodiment 1.

Fig. 4 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 1.

Fig. 5 is a cross-sectional view schematically illustrating a state in which the discharge suppressing material is peeled off from the semiconductor substrate in the semiconductor device according to embodiment 1.

Fig. 6 is a cross-sectional view schematically illustrating a semiconductor substrate included in a semiconductor device according to modification 1 of embodiment 1.

Fig. 7 is a cross-sectional view schematically illustrating a semiconductor device according to modification 1 of embodiment 1.

Fig. 8 is a cross-sectional view schematically illustrating a semiconductor substrate included in a semiconductor device according to modification 2 of embodiment 1.

Fig. 9 is a cross-sectional view schematically illustrating a semiconductor device according to modification 2 of embodiment 1.

Fig. 10 is a diagram illustrating a relationship between a firing voltage, which is a voltage at which a partial discharge is generated between an upper surface electrode belonging to each semiconductor element and an inter-element portion, and a creeping distance, which is a creeping distance between the upper surface electrode belonging to each semiconductor element and the inter-element portion, calculated according to paschen's law, with respect to a semiconductor substrate included in the semiconductor device according to embodiment 1.

Fig. 11 is a flowchart illustrating a method for manufacturing a semiconductor device according to embodiment 2.

Description of the reference numerals

1.2, 3 semiconductor devices, 101, 201, 301 semiconductor substrates, 102 discharge suppressing materials, 110 semiconductor elements, 111 inter-element portions, 121 active portions, 122 terminal portions, 191 central portions, and 192 peripheral portions.

Detailed Description

1 embodiment mode 1

1.1 planar construction of semiconductor substrates

Fig. 1 is a plan view schematically illustrating a semiconductor substrate included in a semiconductor device according to embodiment 1. Fig. 2 is an enlarged plan view schematically illustrating a part of a semiconductor substrate included in the semiconductor device of embodiment 1. Fig. 2 is an enlarged view of a portion a depicted in fig. 1.

The semiconductor substrate 101 shown in fig. 1 and 2 includes a plurality of semiconductor elements 110 and an inter-element portion 111.

The plurality of semiconductor elements 110 are arranged in the extending direction of the semiconductor substrate 101. In the semiconductor substrate 101 shown in fig. 1 and 2, a plurality of semiconductor elements 110 are arranged in a matrix. The plurality of semiconductor elements 110 are formed by forming a p-type diffusion layer, an n-type diffusion layer, and the like on a semiconductor wafer, and disposing electrodes, insulating layers, and the like on the semiconductor wafer.

The inter-element portion 111 is located between the adjacent semiconductor elements 110A and 110B included in the plurality of semiconductor elements 110.

A chip-shaped semiconductor element is manufactured from the semiconductor substrate 101. At this time, the semiconductor substrate 101 is cut along the inter-element portions 111, and the plurality of semiconductor elements 110 are separated from each other. Therefore, the inter-element portion 111 is a dicing line along which the semiconductor substrate 101 is diced.

As shown in fig. 2, each semiconductor element 110N included in the plurality of semiconductor elements 110 includes an active portion 121 and a terminal portion 122. The terminal portion 122 surrounds the active portion 121. When each semiconductor element 110N is energized, a main current flows through the active portion 121. The terminal portion 122 is an electric field relaxation region in which an electric field relaxation structure is formed. By the electric field relaxation structure, the concentration of the electric field is relaxed on the surface 122S of the terminal portion 122, and the withstand voltage of each semiconductor element 110N is improved.

1.2 Cross-sectional Structure of semiconductor substrate

Fig. 3 is a cross-sectional view schematically illustrating a semiconductor substrate included in the semiconductor device of embodiment 1. Fig. 3 illustrates a cross-section at the location of the cutting line B-B depicted in fig. 2. Fig. 3 illustrates semiconductor elements adjacent to each other and an inter-element portion disposed therebetween.

As shown in fig. 3, the semiconductor substrate 101 includes a semiconductor wafer 131, an electrode 132, and an insulating layer 133. The electrode 132 and the insulating layer 133 are disposed on the semiconductor wafer 131. The semiconductor wafer 131 has a p-type diffusion layer 141 and an n-type diffusion layer 142. Thus, each semiconductor element 110N is formed on the semiconductor substrate 101.

In the semiconductor substrate 101 shown in fig. 3, each semiconductor element 110N is a diode. Each semiconductor element 110N may be a semiconductor element other than a diode. For example, each semiconductor element 110N may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like.

The p-type diffusion layer 141 has a p-type region 151. p-type region 151 is formed along upper surface 131U of semiconductor wafer 131. The p-type region 151 is formed over the entire active portion 121 in the active portion 121, and is formed discretely in the terminal portion 122.

n-type diffusion layer 142 includes n-type relaxation region 161 and n-type region 162. n-type relaxation region 161 and n-type region 162 are formed along lower surface 131L of semiconductor wafer 131. n-type relaxation region 161 and n-type region 162 are formed over the entire surface of semiconductor wafer 131.

The electrode 132 includes an upper surface electrode 171 and a lower surface electrode 172. The upper surface electrode 171 is disposed on the upper surface 131U of the semiconductor wafer 131. The upper surface electrodes 171 are disposed over the entire active portion 121 in the active portion 121, and are disposed discretely in the terminal portions 122. Upper surface electrode 171 is in contact with p-type region 151 and serves as an anode. The bottom surface electrode 172 is disposed on the bottom surface 131L of the semiconductor wafer 131. The lower surface electrode 172 is disposed over the entire surface of the semiconductor wafer 131. Lower surface electrode 172 is in contact with n-type region 162 and serves as a cathode.

The insulating layer 133 has a 1 st insulating layer 181, a 2 nd insulating layer 182, and a 3 rd insulating layer 183. The 1 st insulating layer 181, the 2 nd insulating layer 182, and the 3 rd insulating layer 183 are disposed on the upper surface 131U of the semiconductor wafer 131. The 1 st insulating layer 181, the 2 nd insulating layer 182, and the 3 rd insulating layer 183 are disposed at the terminal portion 122. The 1 st insulating layer 181 is disposed directly on the upper surface 131U of the semiconductor wafer 131. The 2 nd insulating layer 182 is disposed on the upper surface 131U of the semiconductor wafer 131 so as to overlap with the upper surface electrode 171 and the 1 st insulating layer 181. The 3 rd insulating layer 183 is disposed on the upper surface 131U of the semiconductor wafer 131 so as to overlap with the upper electrode 171, the 1 st insulating layer 181, and the 2 nd insulating layer 182. The 2 nd insulating layer 182 is made of an insulating material containing nitrogen. The 3 rd insulating layer 183 is made of an organic insulating material.

The surface 111S of the inter-element portion 111 is exposed. Therefore, when a voltage is applied to each semiconductor element 110N for evaluation of each semiconductor element 110N or the like, a partial discharge may occur between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111. For example, when a specific potential such as a potential of 600V or more is applied to the upper surface electrode 171 belonging to each semiconductor element 110N, a partial discharge occurs between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111.

1.3 attachment of discharge suppressing Material

Fig. 4 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 1. Fig. 5 is a cross-sectional view schematically illustrating a state in which the discharge suppressing material is peeled off from the semiconductor substrate in the semiconductor device according to embodiment 1. Fig. 4 and 5 illustrate cross sections at the location of the cutting line B-B depicted in fig. 2.

The semiconductor device 1 of embodiment 1 shown in fig. 4 and 5 includes a semiconductor substrate 101 and a discharge suppressing material 102.

The discharge suppressing material 102 adheres to the surfaces 111S of the inter-element portions 111, and covers the surfaces 111S of the inter-element portions 111. The discharge suppressing material 102 is made of an insulator. Thus, the surface 111S of the inter-element portion 111, which is the starting portion of the partial discharge, is covered with the discharge suppressing material 102 made of an insulator. Therefore, the creepage distance between each semiconductor element 110N and the inter-element portion 111 can be secured, and when a voltage is applied to each semiconductor element 110N for evaluation of each semiconductor element 110N or the like, generation of partial discharge between each semiconductor element 110N and the inter-element portion 111 can be suppressed.

The discharge suppressing material 102 is not attached to the surface 191S of the central portion 191 of each semiconductor element 110N. This can suppress a large amount of heat emitted from the surface 191S of the central portion 191 of each semiconductor element 110N from being transferred to the discharge suppressing material 102. Therefore, the discharge suppressing material 102 can be suppressed from being deteriorated, shrunk, or the like due to the heat.

The discharge suppressing material 102 adheres to the surface 192S of the outer peripheral portion 192 of each semiconductor element 110N, and covers the surface 192S of the outer peripheral portion 192 of each semiconductor element 110N. Thereby, the discharge suppressing material 102 adheres to a part of the surface 121S of the active portion 121 and the surface 122S of the terminal portion 122, and covers the part of the surface 121S of the active portion 121 and the surface 122S of the terminal portion 122. This further increases the creepage distance between each semiconductor element 110N and the inter-element portion 111, and can further suppress the occurrence of partial discharge between each semiconductor element 110N and the inter-element portion 111.

The discharge suppressing material 102 is made of latex, a dry film, a rubber seal, or the like.

When the discharge suppressing material 102 is made of latex, the semiconductor substrate 101 is coated with a fluid before curing of the latex to form a coating film, and the formed coating film is cured to form the discharge suppressing material 102.

The fluid before curing is applied to the semiconductor substrate 101 by ejecting the fluid before curing to the semiconductor substrate 101 using an application device such as an ink jet device. In the case where the fluid before curing is sprayed to the semiconductor substrate 101 by an inkjet device to apply the fluid before curing to the semiconductor substrate 101, a mask for patterning is not required. Therefore, the process of forming the discharge suppressing material 102 can be simplified. As shown in fig. 5, the discharge suppressing material 102 can be peeled off from the semiconductor substrate 101 without damaging the plurality of semiconductor elements 110.

After a voltage is applied to each semiconductor element 110N for evaluation of each semiconductor element 110N and the like, the discharge suppressing material 102 is peeled off from the semiconductor substrate 101. This can prevent foreign matter such as dust from adhering to the surface covered with the discharge suppressing material 102 during storage of the semiconductor device 1.

The discharge suppressing material 102 has an opening having an area necessary for evaluation of each semiconductor element 110N, and exposes the upper surface electrode 171 belonging to each semiconductor element 110N. Thus, each semiconductor element 110N can be evaluated in a state where the discharge suppressing material 102 is attached to the semiconductor substrate 101. In addition, the active portion 121 can be effectively used. The discharge suppressing material 102 can be peeled off from the semiconductor substrate 101 when wire bonding is performed on the semiconductor substrate 101. Therefore, the discharge suppressing material 102 does not hinder the assembly of the product. For example, narrowing of the region where wire bonding is performed can be suppressed. Thereby, the discharge suppressing material 102 can suppress partial discharge and does not hinder the assembly of the product. Further, the discharge suppressing material 102 can suppress contamination of the semiconductor substrate 101 with external dust or the like before the start of assembly of the product, and can suppress an increase in the fraction defective due to the dust.

Preferably, the pre-cure fluid of the latex is applied at ambient temperature. In addition, the fluid before curing of the latex is preferably cured at a temperature of 30 ℃ or higher and 100 ℃ or lower, more preferably at a temperature of 90 ℃ or higher and 100 ℃ or lower. This can suppress deterioration of the latex and further suppress partial discharge. In the case where the fluid before curing of the latex is cured at a temperature higher than these ranges, there is a tendency that it is difficult to suppress deterioration of the latex. Further, the higher the temperature, the faster the deterioration rate of the latex, and becomes about 2 times in the case where the temperature becomes higher by 10 ℃.

The fluid before curing of the latex has a property of coagulating in contact with air, acetic acid, or the like.

The preferable range of the preservation temperature of the fluid before curing of the latex is 0 ℃ or more and 30 ℃ or less. Therefore, the fluid before curing of the latex can be preserved at normal temperature.

As described above, the discharge suppressing material 102 is not attached to the surface 191S of the central portion 191 of each semiconductor element 110N. Thus, even when the discharge suppressing material 102 is made of latex, it is possible to suppress the latex whose deterioration speed increases as the temperature increases, from transmitting a large amount of heat generated from the surface 191S of the central portion 191 of each semiconductor element 110N when a voltage is applied to each semiconductor element 110N for the purpose of evaluation of each semiconductor element 110N or the like. Therefore, the discharge suppressing material 102 can be suppressed from deteriorating.

The latex constituting the discharge suppressing material 102 is synthetic latex or the like. Preferably, the synthetic latex has a low glass transition temperature, more preferably a glass transition temperature of less than or equal to-20 ℃. The reason why the synthetic latex has a low glass transition temperature is preferred is that the synthetic latex becomes soft in the case where the synthetic latex has a low glass transition temperature, and the plurality of semiconductor elements 110 can be prevented from being damaged when the discharge suppressing material 102 is peeled from the semiconductor substrate 101. Thus, the preferred synthetic latex is a butadiene-containing synthetic latex.

According to the discharge suppressing material 102, even when a member for suppressing the occurrence of partial discharge such as silicone rubber is not pressed against the semiconductor substrate 101, the creeping distance between each semiconductor element 110N and the inter-element portion 111 can be secured. Therefore, it is not necessary to press a member for suppressing the occurrence of partial discharge such as silicone rubber against the semiconductor substrate 101. This can suppress the adhesion of foreign matter to the semiconductor substrate 101, the formation of component traces on the semiconductor substrate 101, and the like.

1.4 modification of semiconductor substrate Structure

Fig. 6 is a cross-sectional view schematically illustrating a semiconductor substrate included in a semiconductor device according to modification 1 of embodiment 1. Fig. 7 is a cross-sectional view schematically illustrating a semiconductor device according to modification 1 of embodiment 1. Fig. 8 is a cross-sectional view schematically illustrating a semiconductor substrate included in a semiconductor device according to modification 2 of embodiment 1. Fig. 9 is a cross-sectional view schematically illustrating a semiconductor device according to modification 2 of embodiment 1.

The semiconductor substrate 201 included in the semiconductor device 2 according to the 1 st modification of embodiment 1 shown in fig. 6 and 7 is different from the semiconductor substrate 101 included in the semiconductor device 1 according to embodiment 1 shown in fig. 3 and 4 in that: the 2 nd insulating layer 182 and the 3 rd insulating layer 183 are not provided.

The semiconductor substrate 301 included in the semiconductor device 3 according to the 2 nd modification of embodiment 1 shown in fig. 8 and 9 is different from the semiconductor substrate 101 included in the semiconductor device 1 according to embodiment 1 shown in fig. 3 and 4 in that: the 3 rd insulating layer 183 is not provided.

1.5 Width of discharge suppressing Material

When the semiconductor device 1 does not include the discharge suppressing material 102, when a voltage is applied to each semiconductor element 110N for evaluation of each semiconductor element 110N or the like, a partial discharge may occur between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111. The partial discharge produced is a spark discharge phenomenon. Therefore, the relationship between the firing voltage, which is the voltage at which the partial discharge is generated, and the creeping distance, which is the creeping distance between the upper surface electrode 171 and the inter-element portion 111 of each semiconductor element 110N, can be calculated according to paschen's law.

Fig. 10 is a graph illustrating a relationship between a firing voltage, which is a voltage at which a partial discharge occurs between an upper surface electrode belonging to each semiconductor element and an inter-element portion, and a creeping distance, which is a creeping distance between the upper surface electrode belonging to each semiconductor element and the inter-element portion, of a semiconductor substrate included in the semiconductor device according to embodiment 1, which is calculated according to paschen's law. FIG. 10 is a graph showing the relationship between the strike voltage and the creeping distance at each of the temperatures of 25 deg.C, 75 deg.C, 125 deg.C, 150 deg.C and 175 deg.C.

When determining the width of the discharge suppressing material 102, first, a voltage applied between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111 is determined in order to evaluate each semiconductor element 110N and the like. Further, referring to the relationship between the firing voltage and the creeping distance calculated according to paschen's law shown in fig. 10, the creeping distance to which the firing voltage that matches the determined voltage is given is determined. The width of the discharge suppressing material 102 is determined so that the creepage distance between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111 is longer than the determined creepage distance. This can suppress the occurrence of partial discharge between the upper surface electrode 171 belonging to each semiconductor element 110N and the inter-element portion 111.

Next, theoretical derivation of the relationship between the ignition voltage and the creeping distance given to the ignition voltage will be described.

Based on paschen's law, a voltage at which spark discharge occurs between electrodes parallel to each other, i.e., a firing voltage V is represented by formula (1).

V＝A(pd)/(ln(pd)+B)…(1)

Wherein p is the pressure [ torr ] of the peripheral gas, d is the distance [ μm ] between the electrodes, and A and B are constants determined by the peripheral gas.

In the case where the ambient gas is atmospheric, the ignition voltage V is experimentally represented by the formula [2 ].

V＝126(pd)(log₁₀(pd)/0.22)…(2)

The relative air density ρ is expressed by equation (3).

ρ＝0.386p/(273+t)…(3)

Where t is the temperature [ ° c ].

2 embodiment 2

Fig. 11 is a flowchart illustrating a method for manufacturing a semiconductor element according to embodiment 2.

The method of manufacturing a semiconductor element of embodiment 2 has steps S1 to S6 shown in fig. 11.

In step S1, the semiconductor substrate 101 is prepared.

When the semiconductor substrate 101 is prepared, a semiconductor wafer is prepared.

In addition, impurities are implanted into the prepared semiconductor wafer, and the prepared semiconductor wafer is heated. Thus, p-type diffusion layer 141 and n-type diffusion layer 142 are formed on the semiconductor wafer, and semiconductor wafer 131 shown in fig. 3 is obtained.

Further, an electrode 132 and an insulating layer 133 are formed over the obtained semiconductor wafer 131. Thereby, the semiconductor substrate 101 shown in fig. 3 is obtained.

The obtained semiconductor substrate 101 has a plurality of semiconductor elements 110 and inter-element portions 111 as dicing lines. The plurality of semiconductor elements 110 are separated by the dicing lines 111. Each semiconductor element 110N has an active portion 121 and a terminal portion 122.

In steps S2 and S3 subsequent to step S1, the discharge suppressing material 102 shown in fig. 4 is attached to the semiconductor substrate 101.

In step S2, the pre-curing fluid of the discharge suppressing material 102 is applied to the prepared semiconductor substrate 101, thereby forming a coating film. The pre-curing fluid is applied along cutting line 111. Preferably, the pre-curing fluid is applied by an ink jet device. Thus, a mask for patterning is not required. Therefore, the process of forming the discharge suppressing material 102 can be simplified.

In step S3 after step S2, the formed coating film is cured to change the coating film into the discharge suppressing material 102 shown in fig. 4. When curing the coating film, the coating film is heated.

In step S4 after step S3, a voltage is applied to each semiconductor element 110N. Further, the electrical characteristics of each semiconductor element 110N were evaluated using the applied voltage.

In step S5 after step S4, the discharge suppressing material 102 is peeled off from the semiconductor substrate 101.

In step S6 after step S5, the semiconductor substrate 101 is cut along the dicing line 111. When the semiconductor substrate 101 is cut, the rotating blade cuts the semiconductor substrate 101 along the dicing line 111. Thereby, the plurality of semiconductor elements 110 are separated from each other, and a plurality of chip-shaped semiconductor elements are obtained.

According to steps S2 and S3, the pre-curing fluid of the discharge suppressing material 102 is applied along the cutting line 111 and then heated to be cured. This stabilizes the shape of the discharge suppressing material 102, and suppresses variation in the effect of suppressing partial discharge of the discharge suppressing material 102.

In addition, according to steps S2 and S3, the discharge suppressing material 102 is attached to the semiconductor substrate 101 before the electrical characteristics of each semiconductor element 110N are evaluated in step S4. This can prevent foreign matter such as dust from adhering to the electric field relaxation structure formed at the terminal portion 122, the dicing line 111, and the like during storage of the semiconductor substrate 101. Further, even when a member for suppressing the occurrence of partial discharge such as silicone rubber is not pressed against the semiconductor substrate 101, the creeping distance between each semiconductor element 110N and the inter-element portion 111 can be secured. Therefore, in step S4, it is not necessary to press a member for suppressing the occurrence of partial discharge, such as silicone rubber, against the semiconductor substrate 101. In this way, in step S4, it is possible to suppress adhesion of foreign matter to the semiconductor substrate 101, formation of component traces on the semiconductor substrate 101, and the like.

In addition, the present invention can freely combine the respective embodiments, or appropriately modify or omit the respective embodiments within the scope of the invention.

Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that numerous modifications not illustrated can be devised without departing from the scope of the invention.