阅读说明：本技术 隔离保护环、半导体结构及其制备方法 (Isolation guard ring, semiconductor structure and preparation method thereof ) 是由 何家兰 于 2020-03-13 设计创作，主要内容包括：本发明提供一种隔离保护环、半导体结构及其制备方法,隔离保护环的制备方法包括如下步骤：1)提供基底；2)于所述基底的上表面形成介质层；3)于所述介质层内形成环形凹槽,所述环形凹槽贯穿所述介质层；及4)于所述环形凹槽的侧壁及底部形成金属层,位于所述环形凹槽侧壁的所述金属层内侧具有间隙；并于所述间隙内形成填充介质层。本发明的隔离保护环的制备方法在不增加工艺流程及成本的基础上具有更大的工艺窗口,在凹槽内形成的金属层内不会有孔洞,避免缺陷的产生,具有更好的防水汽、防氧气、防机械损伤及防静电损伤的效果,性能更加可靠。(The invention provides an isolation guard ring, a semiconductor structure and a preparation method thereof, wherein the preparation method of the isolation guard ring comprises the following steps: 1) providing a substrate; 2) forming a dielectric layer on the upper surface of the substrate; 3) forming an annular groove in the dielectric layer, wherein the annular groove penetrates through the dielectric layer; and 4) forming metal layers on the side wall and the bottom of the annular groove, wherein a gap is formed inside the metal layers on the side wall of the annular groove; and forming a filling dielectric layer in the gap. The preparation method of the isolation protection ring has a larger process window on the basis of not increasing the process flow and the cost, and the metal layer formed in the groove does not have holes, so that the defects are avoided, the preparation method has better effects of preventing water vapor, oxygen and mechanical damage and electrostatic damage, and has more reliable performance.)

1. A preparation method of an isolation protection ring is characterized by comprising the following steps:

1) providing a substrate;

2) forming a dielectric layer on the upper surface of the substrate;

3) forming an annular groove in the dielectric layer, wherein the annular groove penetrates through the dielectric layer; and

4) forming metal layers on the side wall and the bottom of the annular groove, wherein a gap is formed inside the metal layers on the side wall of the annular groove; and forming a filling dielectric layer in the gap.

2. The method of claim 1, wherein the step of forming the isolation guard ring comprises: the following steps are also included after the step 4):

5) forming an interconnection structure on the upper surface of the filling dielectric layer formed in the previous step, wherein the upper surface of the interconnection structure is flush with the upper surface of the dielectric layer;

6) forming another dielectric layer on the upper surface of the dielectric layer formed in the step of forming the previous dielectric layer, the upper surface of the metal layer formed in the step of forming the previous metal layer and located on the side wall of the annular groove, and the upper surface of the interconnection structure formed in the step of forming the previous interconnection structure;

7) forming another annular groove in the dielectric layer formed in the previous step, wherein the annular groove in the previous step penetrates through the dielectric layer formed in the previous step and exposes the interconnection structure formed in the previous interconnection structure forming step; and

8) forming another metal layer on the side wall and the bottom of the annular groove formed in the previous step, wherein another gap is formed inside the metal layer on the side wall of the annular groove in the previous step; and forming another filling dielectric layer in the gap formed in the step.

3. The method of claim 2, wherein the step of forming the isolation guard ring comprises: the step 5) comprises the following steps:

5-1) back-etching the filling dielectric layer formed in the previous step and the dielectric layer formed in the previous step to enable the upper surfaces of the remained filling dielectric layer and the remained dielectric layer to be lower than the upper surface of the metal layer formed in the previous step of forming the metal layer and positioned on the side wall of the annular groove;

5-2) forming an interconnection material layer on the upper surface of the metal layer positioned on the side wall of the annular groove formed in the steps of forming the reserved upper surface of the filling dielectric layer, the reserved upper surface of the dielectric layer and the last metal layer; and

5-3) removing the interconnection material layer which is formed on the upper surface of the metal layer on the side wall of the annular groove in the step of forming the reserved dielectric layer and the previous metal layer, and removing a part of the metal layer on the side wall of the annular groove and a part of the interconnection material layer on the upper surface of the reserved filled dielectric layer in the step of forming the previous metal layer to form the interconnection structure; and the upper surface of the interconnection structure, the reserved upper surface of the dielectric layer and the reserved upper surface of the metal layer positioned on the side wall of the annular groove are flush.

4. The method of claim 2 or 3, further comprising, after step 8), the steps of: repeating the steps 5) to 8) at least once.

5. The method of claim 4, wherein the step of forming the top dielectric layer, the top fill dielectric layer, and the top metal layer on the top layer further comprises the steps of: and forming a bonding pad on the upper surface of the top metal layer on the side wall of the annular groove in the top dielectric layer.

6. The method of claim 4, wherein the step of forming the top dielectric layer, the top fill dielectric layer, and the top metal layer on the top layer further comprises the steps of: and forming a bonding pad on the upper surface of the top metal layer and the upper surface of the top filling dielectric layer on the side wall of the annular groove in the top dielectric layer.

7. The method of claim 5 or 6, further comprising the steps of, after forming the pad: and forming a covering dielectric layer on the upper surface of the top dielectric layer, the upper surface of the top filling dielectric layer and the surface of the bonding pad.

8. The method of claim 1, wherein the step of forming the isolation guard ring comprises: the following steps are also included after the step 4):

5) forming an interconnection structure on the upper surface of the filling dielectric layer formed in the previous step and the upper surface of the metal layer on the side wall of the annular groove formed in the previous metal layer forming step;

6) forming another dielectric layer on the upper surface of the dielectric layer formed in the forming step of the previous dielectric layer and the upper surface of the interconnection structure formed in the forming step of the previous interconnection structure;

7) forming another annular groove in the dielectric layer formed in the previous step, wherein the annular groove in the previous step penetrates through the dielectric layer formed in the previous step and exposes the interconnection structure formed in the previous interconnection structure forming step; and

8) forming another metal layer on the side wall and the bottom of the annular groove formed in the previous step, wherein another gap is formed inside the metal layer on the side wall of the annular groove in the previous step; and forming another filling dielectric layer in the gap formed in the step.

9. The method of claim 8, wherein: the step 5) comprises the following steps:

5-1) forming an interconnection material layer on the upper surface of the filling dielectric layer formed in the previous step, the upper surface of the dielectric layer formed in the formation step of the previous dielectric layer and the upper surface of the metal layer located on the side wall of the annular groove formed in the formation step of the previous metal layer;

5-2) forming a hard mask layer on the upper surface of the interconnection material layer formed in the previous step;

5-3) patterning the hard mask layer to obtain a hard mask pattern, wherein the shape and the position of the interconnection structure are defined by the hard mask pattern;

5-4) etching the interconnect material layer based on the hard mask pattern to form the interconnect structure; and

5-5) removing the hard mask pattern.

10. The method of claim 8, further comprising, after step 8), the steps of: repeating the steps 5) to 8) at least once.

11. The method of claim 10, wherein the step of forming a top dielectric layer, a top fill dielectric layer, and a top metal layer on the top layer further comprises the steps of: and forming a bonding pad on the upper surface of the top metal layer on the side wall of the annular groove in the top dielectric layer.

12. The method of claim 10, wherein the step of forming a top dielectric layer, a top fill dielectric layer, and a top metal layer on the top layer further comprises the steps of: and forming a bonding pad on the upper surface of the top metal layer and the upper surface of the top filling dielectric layer on the side wall of the annular groove in the top dielectric layer.

13. The method of claim 11 or 12, further comprising the steps of, after forming the pad: and forming a covering dielectric layer on the upper surface of the top dielectric layer, the upper surface of the top filling dielectric layer and the surface of the bonding pad.

14. An isolation guard ring, comprising:

the metal layer is positioned on the side wall and the bottom of the annular groove in the medium layer; a gap is formed on the inner side of the metal layer on the side wall of the groove; and

and the filling dielectric layer is positioned in the gap.

15. The isolation guard ring of claim 14, wherein the metal layer comprises:

the first metal ring penetrates through the dielectric layer along the thickness direction;

the second metal ring is positioned at the periphery of the first metal ring and has a distance with the first metal ring; the second metal ring penetrates through the dielectric layer along the thickness direction; and

and the bottom annular metal connecting layer is positioned at the bottoms of the first metal ring and the second metal ring and connects the first metal ring with the second metal ring.

16. The isolation guard ring of claim 14 or 15, wherein the isolation guard ring comprises a plurality of the metal layers, wherein the plurality of metal layers are stacked one on top of the other and electrically connected adjacent to each other.

17. The isolation guard ring of claim 16, further comprising an interconnect structure positioned between adjacent ones of the metal layers to electrically connect the adjacent metal layers.

18. The isolation guard ring of claim 17, wherein the interconnect structure is located on an upper surface of the fill dielectric layer, and wherein the upper surface of the interconnect structure is flush with an upper surface of the metal layer located on the sidewall of the annular recess.

19. The isolation guard ring of claim 17, wherein the interconnect structure is located on an upper surface of the fill dielectric layer and on an upper surface of the metal layer at a sidewall of the annular recess.

20. The isolation guard ring of claim 16, further comprising a pad disposed on an upper surface of the metal layer at a top layer.

21. The isolation guard ring of claim 16, further comprising a pad disposed on an upper surface of the top metal layer and on an upper surface of the top dielectric fill layer.

22. A method for manufacturing a semiconductor structure, comprising the steps of:

providing a substrate, wherein the substrate comprises a cutting channel and a plurality of chip areas which are separated by the cutting channel and are arranged at intervals; and

preparing a plurality of the isolation guard rings by using the method of preparing the isolation guard ring according to any one of claims 1 to 13, wherein the isolation guard ring is located between the scribe line and each of the chip regions, and the isolation guard ring surrounds each of the chip regions.

23. A semiconductor structure, comprising:

the chip comprises a substrate, a plurality of chip areas and a plurality of chip areas, wherein the substrate comprises a cutting channel and a plurality of chip areas which are separated by the cutting channel and are arranged at intervals; and

a plurality of the isolation guard rings of any of claims 14-21, the isolation guard ring positioned between the dicing street and each of the chip regions, and the isolation guard ring surrounding each of the chip regions.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an isolation guard ring, a semiconductor structure and a preparation method thereof.

Background

The sealing ring (Seal ring) is mainly used for packaging, can provide air-tight sealing, is positioned at the periphery of the chip and between the cutting channel and the chip, can protect the chip from mechanical damage when the chip is cut, and can prevent water vapor and oxygen from entering the chip. Guard rings (Guard rings) are mainly used for electrostatic protection with grounding, and can protect the sensing device and/or the main chip from electronic and/or electrostatic damage (ESD). Also, some electrical test keys and/or monitor pads may be placed within the guard ring.

Then, only the periphery of the chip is provided with a sealing ring which comprises a dielectric layer and an interconnection structure positioned in the dielectric layer, the left and right sides of the sealing protection of the chip are limited, the chip still suffers mechanical damage during cutting, water vapor and oxygen still enter the chip, and the chip suffers electronic and/or electrostatic damage; the protection ring is provided with a sealing ring with a dielectric layer and a single metal groove positioned in the dielectric layer, so that although the conventional structure can prevent the chip from mechanical damage and electronic and/or electrostatic damage, water vapor and oxygen can still enter the chip; and because the trench is deep, a hole is easily formed in the filled metal when the trench is filled with the metal, and when the hole is exposed after CMP (chemical mechanical polishing), particles fall into the hole in the subsequent process, and the particles falling into the hole overflow from the hole in the subsequent annealing and other process treatment processes to cause defects, thereby affecting the sealing protection performance of the sealing ring.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide an isolation guard ring, a semiconductor structure and a method for fabricating the same, which are used to solve the above-mentioned problems in the prior art.

To achieve the above and other related objects, the present invention provides a method for preparing a spacer ring, comprising the steps of:

1) providing a substrate;

2) forming a dielectric layer on the upper surface of the substrate;

3) forming an annular groove in the dielectric layer, wherein the annular groove penetrates through the dielectric layer; and

4) forming metal layers on the side wall and the bottom of the annular groove, wherein a gap is formed inside the metal layers on the side wall of the annular groove; and forming a filling dielectric layer in the gap.

The preparation method of the isolation protection ring has a larger process window on the basis of not increasing the process flow and the cost, and the metal layer formed in the groove does not have holes, so that the defects are avoided, the preparation method has better effects of preventing water vapor, oxygen and mechanical damage and electrostatic damage, and has more reliable performance.

Optionally, the following step is further included after step 4):

5) forming an interconnection structure on the upper surface of the filling dielectric layer formed in the previous step, wherein the upper surface of the interconnection structure is flush with the upper surface of the dielectric layer;

6) forming another dielectric layer on the upper surface of the dielectric layer formed in the step of forming the previous dielectric layer, the upper surface of the metal layer formed in the step of forming the previous metal layer and located on the side wall of the annular groove, and the upper surface of the interconnection structure formed in the step of forming the previous interconnection structure;

7) forming another annular groove in the dielectric layer formed in the previous step, wherein the annular groove in the previous step penetrates through the dielectric layer formed in the previous step and exposes the interconnection structure formed in the previous interconnection structure forming step; and

8) forming another metal layer on the side wall and the bottom of the annular groove formed in the previous step, wherein another gap is formed inside the metal layer on the side wall of the annular groove in the previous step; and forming another filling dielectric layer in the gap formed in the step.

Optionally, step 5) comprises the steps of:

5-1) back-etching the filling dielectric layer formed in the previous step and the dielectric layer formed in the previous step to enable the upper surfaces of the remained filling dielectric layer and the remained dielectric layer to be lower than the upper surface of the metal layer formed in the previous step of forming the metal layer and positioned on the side wall of the annular groove;

5-2) forming an interconnection material layer on the upper surface of the metal layer positioned on the side wall of the annular groove formed in the steps of forming the reserved upper surface of the filling dielectric layer, the reserved upper surface of the dielectric layer and the last metal layer; and

5-3) removing the interconnection material layer which is formed on the upper surface of the metal layer on the side wall of the annular groove in the step of forming the reserved dielectric layer and the previous metal layer, and removing a part of the metal layer on the side wall of the annular groove and a part of the interconnection material layer on the upper surface of the reserved filled dielectric layer in the step of forming the previous metal layer to form the interconnection structure; and the upper surface of the interconnection structure, the reserved upper surface of the dielectric layer and the reserved upper surface of the metal layer positioned on the side wall of the annular groove are flush.

Optionally, step 8) comprises the steps of: repeating the steps 5) to 8) at least once.

Optionally, after forming the top dielectric layer, the top filling dielectric layer, and the top metal layer on the top layer, the method further includes the following steps: and forming a bonding pad on the upper surface of the top metal layer on the side wall of the annular groove in the top dielectric layer.

Optionally, after forming the top dielectric layer, the top filling dielectric layer, and the top metal layer on the top layer, the method further includes the following steps: and forming a bonding pad on the upper surface of the top metal layer and the upper surface of the top filling dielectric layer on the side wall of the annular groove in the top dielectric layer.

Optionally, the method further includes the following steps after forming the pad: and forming a covering dielectric layer on the upper surface of the top dielectric layer, the upper surface of the top filling dielectric layer and the surface of the bonding pad.

Optionally, the following step is further included after step 4):

5) forming an interconnection structure on the upper surface of the filling dielectric layer formed in the previous step and the upper surface of the metal layer on the side wall of the annular groove formed in the previous metal layer forming step;

6) forming another dielectric layer on the upper surface of the dielectric layer formed in the forming step of the previous dielectric layer and the upper surface of the interconnection structure formed in the forming step of the previous interconnection structure;

7) forming another annular groove in the dielectric layer formed in the previous step, wherein the annular groove in the previous step penetrates through the dielectric layer formed in the previous step and exposes the interconnection structure formed in the previous interconnection structure forming step; and

8) forming another metal layer on the side wall and the bottom of the annular groove formed in the previous step, wherein another gap is formed inside the metal layer on the side wall of the annular groove in the previous step; and forming another filling dielectric layer in the gap formed in the step.

Optionally, step 5) comprises the steps of:

5-1) forming an interconnection material layer on the upper surface of the filling dielectric layer formed in the previous step, the upper surface of the dielectric layer formed in the formation step of the previous dielectric layer and the upper surface of the metal layer located on the side wall of the annular groove formed in the formation step of the previous metal layer;

5-2) forming a hard mask layer on the upper surface of the interconnection material layer formed in the previous step;

5-3) patterning the hard mask layer to obtain a hard mask pattern, wherein the shape and the position of the interconnection structure are defined by the hard mask pattern;

5-4) etching the interconnect material layer based on the hard mask pattern to form the interconnect structure; and

5-5) removing the hard mask pattern.

Optionally, step 8) further comprises the steps of: repeating the steps 5) to 8) at least once.

Optionally, after forming the top dielectric layer, the top filling dielectric layer, and the top metal layer on the top layer, the method further includes the following steps: and forming a bonding pad on the upper surface of the top metal layer on the side wall of the annular groove in the top dielectric layer.

Optionally, after forming the top dielectric layer, the top filling dielectric layer, and the top metal layer on the top layer, the method further includes the following steps: and forming a bonding pad on the upper surface of the top metal layer and the upper surface of the top filling dielectric layer on the side wall of the annular groove in the top dielectric layer.

Optionally, the method further includes the following steps after forming the pad: and forming a covering dielectric layer on the upper surface of the top dielectric layer, the upper surface of the top filling dielectric layer and the surface of the bonding pad.

The present invention also provides an isolation guard ring, comprising:

the metal layer is positioned on the side wall and the bottom of the annular groove in the medium layer; a gap is formed on the inner side of the metal layer on the side wall of the groove; and

and the filling dielectric layer is positioned in the gap.

The isolation protection ring has a larger process window on the basis of not increasing the process flow and the cost, and no hole is formed in the metal layer formed in the groove, so that the defects are avoided, the effects of better water vapor resistance, oxygen resistance, mechanical damage resistance and electrostatic damage resistance are achieved, and the performance is more reliable.

Optionally, the metal layer comprises:

the first metal ring penetrates through the dielectric layer along the thickness direction;

the second metal ring is positioned at the periphery of the first metal ring and has a distance with the first metal ring; the second metal ring penetrates through the dielectric layer along the thickness direction; and

and the bottom annular metal connecting layer is positioned at the bottoms of the first metal ring and the second metal ring and connects the first metal ring with the second metal ring.

Optionally, the isolation guard ring includes a plurality of metal layers, the metal layers are stacked in sequence, and adjacent metal layers are electrically connected.

Optionally, the isolation guard ring further comprises an interconnect structure located between adjacent metal layers to electrically connect adjacent metal layers.

Optionally, the interconnection structure is located on the upper surface of the filling dielectric layer, and the upper surface of the interconnection structure is flush with the upper surface of the metal layer located on the sidewall of the annular groove.

Optionally, the interconnection structure is located on the upper surface of the filling dielectric layer and on the upper surface of the metal layer on the sidewall of the annular groove.

Optionally, the isolation guard ring further includes a pad disposed on an upper surface of the metal layer at the top layer.

Optionally, the isolation guard ring further includes a pad, and the pad is disposed on the upper surface of the metal layer on the top layer and on the upper surface of the filling dielectric layer on the top layer.

The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:

providing a substrate, wherein the substrate comprises a cutting channel and a plurality of chip areas which are separated by the cutting channel and are arranged at intervals; and

the method for manufacturing the isolation protection ring according to any one of the above schemes is adopted to manufacture a plurality of isolation protection rings, the isolation protection rings are located between the cutting channel and each chip area, and the isolation protection rings surround each chip area.

The present invention also provides a semiconductor structure comprising:

the chip comprises a substrate, a plurality of chip areas and a plurality of chip areas, wherein the substrate comprises a cutting channel and a plurality of chip areas which are separated by the cutting channel and are arranged at intervals; and

a plurality of isolation guard rings as described in any of the above aspects, said isolation guard rings being located between said scribe line and each of said chip regions, and said isolation guard rings surrounding each of said chip regions.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a film isolation guard ring according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional structure diagram of the structure obtained in step S11 in the method for manufacturing an isolation guard ring according to the first embodiment of the present invention.

Fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step S12 in the method for manufacturing an isolation guard ring according to the first embodiment of the present invention.

Fig. 4 is a schematic cross-sectional structure diagram of the structure obtained in step S13 in the method for manufacturing an isolation guard ring according to the first embodiment of the present invention.

Fig. 5 to fig. 7 are schematic cross-sectional structures of the structures obtained in step S14 in the method for manufacturing the isolation guard ring according to the first embodiment of the present invention.

Fig. 8 to 10 are schematic cross-sectional structures of the structures obtained in step S15 in the method for manufacturing the isolation guard ring according to the first embodiment of the present invention.

Fig. 11 to 13 are schematic cross-sectional structures of structures obtained in step S15 in another example of the method for manufacturing the isolation guard ring according to the first embodiment of the present invention.

Fig. 14 to 15 are schematic cross-sectional structures of structures obtained in step S16 according to different examples of the method for manufacturing a isolation guard ring according to a first embodiment of the present invention.

Fig. 16 to 17 are schematic cross-sectional structures of structures obtained in step S17 according to different examples of the method for manufacturing a isolation guard ring according to the first embodiment of the present invention.

Fig. 18 to 21 are schematic cross-sectional structures of structures obtained in step S18 according to different examples of the method for manufacturing a isolation guard ring according to the first embodiment of the present invention.

Fig. 22 to fig. 25 are schematic cross-sectional structures of structures obtained after forming a pad in different examples of the method for manufacturing an isolation guard ring according to the first embodiment of the present invention.

Fig. 26 is a schematic top view illustrating a structure obtained after a capping dielectric layer is formed in a method for fabricating an isolation guard ring according to an embodiment of the invention; fig. 26 is a schematic top view of the semiconductor structure according to the second embodiment of the present invention.

Fig. 27 to 30 are schematic sectional structures along AA in fig. 26 in different examples.

Description of the element reference numerals

10 base

11. 16 dielectric layer

12. 17 annular groove

13. 18 metal layer

131. 181 metallic material layer

14. 19 filling dielectric layer

141. 191 a layer of filling dielectric material

15 interconnect structure

151 layer of interconnect material

20 bonding pad

21 first bonding pad

22 second bonding pad

23 cover the dielectric layer

24 hard mask layer

241 carbon layer

242 silicon oxynitride layer

25 patterned hard mask layer

26 patterned photoresist layer

30 chip area

31 cutting path

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.