阅读说明：本技术 一种数据处理装置及方法 (Data processing device and method ) 是由 檀珠峰 李宗岩 于 2020-02-28 设计创作，主要内容包括：本申请实施例公开了一种数据处理装置及相关方法,其中,一种数据处理装置,可包括堆叠封装的第一芯片和第二芯片；所述第一芯片包括通用处理器、总线和至少一个第一专用处理单元DPU,所述通用处理器和所述至少一个第一专用处理单元连接至所述总线,所述通用处理器用于产生数据处理任务；所述第二芯片包括第二专用处理单元,所述至少一个第一专用处理单元中的一个或多个第一专用处理单元和所述第二专用处理单元中的至少一个能够基于所述计算功能处理所述数据处理任务的至少一部分；其中,所述第一芯片和所述第二芯片通过芯片间互连线相互连接。该数据处理装置可以在不增加产品体积的情况下,满足用户越来越高的功耗和运算需求。(The embodiment of the application discloses a data processing device and a related method, wherein the data processing device can comprise a first chip and a second chip which are packaged in a stacked mode; the first chip comprises a general-purpose processor, a bus and at least one first special-purpose processing unit (DPU), wherein the general-purpose processor and the at least one first DPU are connected to the bus, and the general-purpose processor is used for generating data processing tasks; the second chip comprises second dedicated processing units, at least one of the second dedicated processing units and one or more of the at least one first dedicated processing units being capable of processing at least a portion of the data processing tasks based on the computational functionality; wherein the first chip and the second chip are connected to each other by an inter-chip interconnect. The data processing device can meet the higher and higher power consumption and operation requirements of users under the condition of not increasing the product volume.)

A data processing apparatus includes a first chip and a second chip which are stacked and packaged;

the first chip comprises a general-purpose processor, a bus and at least one first special-purpose processing unit (DPU), wherein the general-purpose processor and the at least one first DPU are connected to the bus, and the general-purpose processor is used for generating data processing tasks;

the second chip comprises a second dedicated processing unit having at least partially the same computational functionality as one or more of the at least one first dedicated processing unit, at least one of the one or more first dedicated processing units and the second dedicated processing unit being capable of processing at least a portion of the data processing task based on the computational functionality;

wherein the first chip and the second chip are connected to each other by an inter-chip interconnect.

The apparatus of claim 1, wherein the second specialized processing unit has the same computational functionality as one or more of the at least one first specialized processing unit.

The apparatus of claim 1 or 2, wherein the general purpose processor comprises a Central Processing Unit (CPU).

The apparatus of any of claims 1-3, wherein each of the one or more first dedicated processing units and the second dedicated processing unit comprises at least one of a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a Digital Signal Processor (DSP), or a neural Network Processing Unit (NPU).

The apparatus of any of claims 1-4, wherein the inter-chip interconnects comprise at least one of through-silicon-via (TSV) interconnects, or wire-bond interconnects.

The apparatus of any one of claims 1-5, further comprising a third chip stacked with the first chip and the second chip in a package, the third chip connected with at least one of the first chip or the second chip by the inter-chip interconnect;

the third chip comprises at least one of a memory, a power transmission circuit module, an input-output circuit module or an analog module.

The apparatus of any of claims 1-6, wherein the inter-chip interconnect connects between the one or more first dedicated processing units and the second dedicated processing unit; the second specialized processing unit is to obtain at least a portion of the data processing tasks from the one or more first specialized processing units.

An apparatus according to any one of claims 1-6, wherein said inter-chip interconnect is connected between said second dedicated processing unit and said bus, said second dedicated processing unit being adapted to fetch at least a part of said data processing tasks from said general purpose processor via said bus.

The apparatus of any of claims 1-8, wherein the general purpose processor is configured to send activation information to the second specialized processing unit via the inter-chip interconnect;

the second dedicated processing unit is configured to transition from a wait state to an active state in response to the activation information and process at least a portion of the data processing task based on the computing functionality.

The apparatus of claim 9, wherein the general purpose processor is to send an activation message to the second specialized processing unit via the inter-chip interconnect line when the computational power of the one or more first specialized processing units does not meet a requirement.

The apparatus of any of claims 1-8, wherein the one or more first specialized processing units are to send activation information to the second specialized processing unit via the inter-chip interconnect;

the second dedicated processing unit is configured to transition from a wait state to an active state in response to the activation information and process at least a portion of the data processing task based on the computing functionality.

The apparatus of claim 11, wherein the one or more first specialized processing units are to send activation information to the second specialized processing unit via the inter-chip interconnect line when the computational power of the one or more first specialized processing units does not meet a requirement.

A data processing method, comprising:

generating data processing tasks by a general purpose processor in a first chip, the first chip comprising the general purpose processor, a bus and at least one first dedicated processing unit, DPU, the general purpose processor and the at least one first dedicated processing unit being connected to the bus;

processing at least a portion of the data processing task by at least one of one or more of the at least one first specialized processing unit and a second specialized processing unit of a second chip package, the second specialized processing unit having at least partially the same computational functionality as one or more of the at least one first specialized processing unit, the first chip and the second chip stacked in a package and interconnected by inter-chip interconnects.