阅读说明：本技术 形成并联电容器的方法及并联电容器 (Method for forming parallel capacitor and parallel capacitor ) 是由 邹永金 于 2019-09-09 设计创作，主要内容包括：本发明提供了一种形成并联电容器的方法及并联电容器,形成并联电容器的方法包括：提供一衬底,所述衬底上形成有第一导电层、第一介质层及第二导电层,所述第一导电层、第一介质层及第二导电层构成第一电容器；在所述第二导电层上形成第二介质层及隔离层,并研磨去除所述第二介质层上的隔离层；在所述第二介质层上形成互连层,所述互连层、所述第二介质层及所述第二导电层构成第二电容器,所述第一电容器和所述电容器构成并联电容器。在无需增加新的光罩的情况下形成与所述第一电容器并联的第二电容器,提高了器件的总电容值。(The invention provides a method for forming a parallel capacitor and the parallel capacitor, wherein the method for forming the parallel capacitor comprises the following steps: providing a substrate, wherein a first conducting layer, a first dielectric layer and a second conducting layer are formed on the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer form a first capacitor; forming a second dielectric layer and an isolation layer on the second conducting layer, and grinding to remove the isolation layer on the second dielectric layer; and forming an interconnection layer on the second dielectric layer, wherein the interconnection layer, the second dielectric layer and the second conductive layer form a second capacitor, and the first capacitor and the capacitor form a parallel capacitor. And a second capacitor connected with the first capacitor in parallel is formed without adding a new photomask, so that the total capacitance value of the device is improved.)

1. A method of forming a parallel capacitor, comprising:

providing a substrate;

sequentially forming a first conducting layer, a first dielectric layer and a second conducting layer, wherein the first conducting layer covers part of the surface of the substrate, the first dielectric layer covers the first conducting layer, the second conducting layer covers part of the surface of the first dielectric layer and the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer which are stacked mutually form a first capacitor;

forming a second dielectric layer, wherein the second dielectric layer covers the second conductive layer;

Forming an isolation layer, wherein the isolation layer covers the second dielectric layer and the first dielectric layer;

Performing a chemical mechanical polishing process to remove the isolation layer on the second dielectric layer;

Forming a first plug, a second plug and an interconnection layer, wherein the first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected with the first conductive layer, the second plug penetrates through the isolation layer and the second dielectric layer and is electrically connected with the second conductive layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected with the interconnection layer, and the first plug and the second plug are insulated from each other.

2. the method of claim 1, wherein the second conductive layer, the second dielectric layer, and the interconnect layer form a second capacitor, the first capacitor and the second capacitor form a parallel capacitor, and the capacitance of the parallel capacitor is greater than or equal to 3.3fF/μm 2.

3. The method of claim 1, wherein the first dielectric layer is made of silicon oxide.

4. the method of forming a parallel capacitor of claim 1 wherein said first dielectric layer is formed by a high temperature oxidation process.

5. the method of claim 1, wherein the second dielectric layer is made of silicon nitride or silicon oxynitride.

6. The method of claim 1, wherein the first and second conductive layers are polysilicon.

7. The method of forming a parallel capacitor of claim 1 wherein said first dielectric layer has a thickness between.

8. The method of forming a parallel capacitor of claim 1 wherein said second dielectric layer has a thickness between said first and second dielectric layers.

9. the method of forming a parallel capacitor of claim 1 wherein said first conductive layer has a thickness between.

10. The method of forming a parallel capacitor of claim 1 wherein said second conductive layer has a thickness between.

11. A parallel capacitor, comprising:

the capacitor comprises a substrate, wherein a first conducting layer, a first dielectric layer and a second conducting layer are formed on the substrate, the first conducting layer covers part of the surface of the substrate, the first dielectric layer covers the first conducting layer, and the second conducting layer covers part of the surface of the first dielectric layer and the substrate, wherein the first conducting layer, the first dielectric layer and the second conducting layer which are stacked mutually form a first capacitor;

a second dielectric layer covering the second conductive layer;

the isolation layer covers partial surfaces of the first dielectric layer and the second dielectric layer;

The first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected with the first conducting layer;

The second plug penetrates through the isolation layer and the second dielectric layer and is electrically connected with the second conducting layer; and the number of the first and second groups,

the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected with the interconnection layer, the first plug and the second plug are insulated from each other, the interconnection layer, the second dielectric layer and the second conductive layer which are stacked mutually form a second capacitor, and the first capacitor and the second capacitor form a parallel capacitor.

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for forming a parallel capacitor and a parallel capacitor.

Background

A PIP (poly-insulator-poly) capacitor is a device that is widely used for frequency modulation and to prevent analog circuits from emitting noise.

however, the capacitor of the current PIP structure generally has a problem of small capacitance value, thereby causing a defect of poor filtering effect of the integrated circuit. At present, in order to improve the capacitance value of a capacitor with a PIP structure, a common method is to use a new photomask to form another capacitor with a PIP structure in parallel with the capacitor with the PIP structure, but multiple process steps such as photolithography and etching are additionally added, which inevitably increases the process time and reduces the working efficiency, and simultaneously does not meet the requirement of a semiconductor device with a smaller size, so that a new method for forming a parallel capacitor is urgently needed to solve the problem that the capacitance value of the capacitor with the PIP structure is smaller without adding additional process steps as much as possible.

Disclosure of Invention

The present invention provides a method for forming a parallel capacitor and a parallel capacitor, so as to solve the problem of increasing the capacitance of the capacitor of the PIP structure without adding additional process steps.

to solve the above technical problem, the present invention provides a method for forming a parallel capacitor, comprising:

providing a substrate;

sequentially forming a first conducting layer, a first dielectric layer and a second conducting layer, wherein the first conducting layer covers part of the surface of the substrate, the first dielectric layer covers the first conducting layer, the second conducting layer covers part of the surface of the first dielectric layer and the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer which are stacked mutually form a first capacitor;

Forming a second dielectric layer, wherein the second dielectric layer covers the second conductive layer;

forming an isolation layer, wherein the isolation layer covers the second dielectric layer and the first dielectric layer;

performing a chemical mechanical polishing process to remove the isolation layer on the second dielectric layer;

forming a first plug, a second plug and an interconnection layer, wherein the first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected with the first conductive layer, the second plug penetrates through the isolation layer and the second dielectric layer and is electrically connected with the second conductive layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected with the interconnection layer, and the first plug and the second plug are insulated from each other.

optionally, in the method for forming a parallel capacitor, the second conductive layer, the second dielectric layer, and the interconnection layer form a second capacitor, the first capacitor and the second capacitor form a parallel capacitor, and a capacitance value of the parallel capacitor is greater than or equal to 3.3fF/μm 2.

Optionally, in the method for forming a parallel capacitor, the first dielectric layer is made of silicon oxide.

Optionally, in the method for forming a parallel capacitor, the first dielectric layer is formed by a high-temperature oxidation process.

optionally, in the method for forming the parallel capacitor, the second dielectric layer is made of silicon nitride or silicon oxynitride.

optionally, in the method for forming a parallel capacitor, the first conductive layer and the second conductive layer are both made of polysilicon.

optionally, in the method for forming a parallel capacitor, the thickness of the first dielectric layer is between the thicknesses of the first dielectric layer and the second dielectric layer.

Optionally, in the method for forming a parallel capacitor, the thickness of the second dielectric layer is between the thicknesses of the first dielectric layer and the second dielectric layer.

optionally, in the method for forming a parallel capacitor, the thickness of the first conductive layer is between.

optionally, in the method for forming a parallel capacitor, the thickness of the second conductive layer is between the thicknesses of the first conductive layer and the second conductive layer.

Based on the same inventive concept, the present invention also provides a parallel capacitor, comprising:

The capacitor comprises a substrate, wherein a first conducting layer, a first dielectric layer and a second conducting layer are formed on the substrate, the first conducting layer covers part of the surface of the substrate, the first dielectric layer covers the first conducting layer, and the second conducting layer covers part of the surface of the first dielectric layer and the substrate, wherein the first conducting layer, the first dielectric layer and the second conducting layer which are stacked mutually form a first capacitor;

a second dielectric layer covering the second conductive layer;

The isolation layer covers partial surfaces of the first dielectric layer and the second dielectric layer;

The first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected with the first conducting layer;

The second plug penetrates through the isolation layer and the second dielectric layer and is electrically connected with the second conducting layer; and the number of the first and second groups,

The interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected with the interconnection layer, the first plug and the second plug are insulated from each other, the interconnection layer, the second dielectric layer and the second conductive layer which are stacked mutually form a second capacitor, and the first capacitor and the second capacitor form a parallel capacitor.

In summary, the present invention provides a method for forming a parallel capacitor and a parallel capacitor, the method for forming a parallel capacitor includes: providing a substrate, wherein a first conducting layer, a first dielectric layer and a second conducting layer are sequentially formed on the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer form a first capacitor; forming a second dielectric layer on the second conductive layer; forming isolation layers on the second medium layer and the first medium layer, and grinding to remove the isolation layer on the surface of the second medium layer; and forming an interconnection layer on the second dielectric layer, wherein the interconnection layer, the second dielectric layer and the second conductive layer form a second capacitor, and the first capacitor and the second capacitor form a parallel capacitor. Under the condition that a new photomask and new process steps are not needed to be added, the isolation layer on the surface of the second dielectric layer is removed through grinding, the second dielectric layer is used as an intermediate insulation medium of the second conducting layer and the interconnection layer, so that the second capacitor connected with the first capacitor in parallel is obtained, and the total capacitance value of the device is remarkably improved due to the parallel capacitor formed by the first capacitor and the second capacitor.

Drawings

FIG. 1 is a flow chart of a method of forming a parallel capacitor according to an embodiment of the present invention;

FIGS. 2-6 are semiconductor structure diagrams at various process steps for forming a parallel capacitor according to an embodiment of the present invention;

Wherein the reference numbers indicate:

100-substrate, 110-first conductive layer, 120-first dielectric layer, 130-second conductive layer, 140-second dielectric layer, 150-isolation layer, 160-interconnect layer, 200-first capacitor, 210-first plug, 220-second plug, 300-second capacitor, 310-trench.

Detailed Description

the method for forming the parallel capacitor and the parallel capacitor proposed by the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.

The invention provides a method for forming a parallel capacitor, and referring to fig. 1, fig. 1 is a flow chart of a method for forming a parallel capacitor according to an embodiment of the invention, wherein the method for forming a parallel capacitor comprises the following steps:

S10: providing a substrate;

s20: sequentially forming a first conducting layer, a first dielectric layer and a second conducting layer, wherein the first conducting layer covers part of the surface of the substrate, the first dielectric layer covers the first conducting layer, the second conducting layer covers part of the surface of the first dielectric layer and the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer which are stacked mutually form a first capacitor;

s30: forming a second dielectric layer, wherein the second dielectric layer covers the second conductive layer;

s40: forming an isolation layer, wherein the isolation layer covers the second dielectric layer and the first dielectric layer;

S50: performing a chemical mechanical polishing process to remove the isolation layer on the second dielectric layer;

S60: forming a first plug, a second plug and an interconnection layer, wherein the first plug penetrates through the isolation layer and the first dielectric layer and is electrically connected with the first conductive layer, the second plug penetrates through the isolation layer and the second dielectric layer and is electrically connected with the second conductive layer, the interconnection layer is formed on the isolation layer and the second dielectric layer, the first plug and the second plug are respectively electrically connected with the interconnection layer, and the first plug and the second plug are insulated from each other.

specifically, referring to fig. 2-6, fig. 2-6 are semiconductor structure diagrams in various process steps for forming a parallel capacitor according to an embodiment of the present invention.

First, as shown in fig. 2, a substrate 100 is provided; a first conductive layer 110, a first dielectric layer 120 and a second conductive layer 130 are sequentially formed, the first conductive layer 110 covers a portion of the surface of the substrate 100, the first dielectric layer 120 covers the first conductive layer 110, the first conductive layer 110 on the side of the substrate 100 that is close to the side not covered by the first conductive layer 110 is completely covered by the first dielectric layer 120, this allows the first conductive layer 110 to be completely isolated from the second conductive layer 130 subsequently formed on the first dielectric layer 120 and the substrate 100 not covered by the first conductive layer 110, the second conductive layer 130 covers a portion of the surface of the first dielectric layer 120 and the substrate 100 (the substrate 100 not covered by the first conductive layer 110), the first conductive layer 110, the first dielectric layer 120 and the second conductive layer 130 stacked on each other form a first capacitor 200. Specifically, the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, the material of the substrate 100 may also be gallium arsenide, silicon gallium arsenide compound, and the like, the substrate 100 may also have a silicon-on-insulator or silicon-on-silicon epitaxial layer structure, and of course, the substrate 100 may also be made of other semiconductor materials, which are not listed here. The substrate 100 may have a known structure such as an N-well or a P-well. Further, the first conductive layer 110 and the second conductive layer 130 are made of polysilicon, and after the second conductive layer 130 is formed, a cobalt compound thin film needs to be formed on the position of the surface of the first conductive layer 110, which needs to be subsequently contacted with a first plug, and the position of the surface of the second conductive layer 130, which needs to be subsequently contacted with a second plug through processes such as photolithography, etching, Atomic Layer Deposition (ALD), and the like, so that the first conductive layer 110 and the second conductive layer 130, which are made of polysilicon, have a conductive function at specific positions, thereby achieving the subsequent electrical connection between the first conductive layer 110 and the first plug 210 and the subsequent electrical connection between the second conductive layer 130 and the second plug 220, the first conductive layer 110, which is partially covered with the cobalt compound thin film, serves as an upper plate of the first capacitor 200 to be formed subsequently, and the second conductive layer 130, which is partially covered with the cobalt compound thin film, serves as a lower plate of the first capacitor 200 to be formed subsequently The first dielectric layer 120 serves as an intermediate insulating dielectric of the first capacitor 200, thereby constituting the first capacitor 200 of a PIP (polysilicon-insulating layer-polysilicon) structure.

preferably, the thickness of the first dielectric layer 120 is between the thicknesses of the first dielectric layer 120, the material of the first dielectric layer 120 is silicon oxide, and in this embodiment, the first dielectric layer 120 is formed by a high-temperature oxidation process; the thickness of the first conductive layer 110 is between; the thickness of the second conductive layer 130 is between the thicknesses of the first conductive layer 110, the first dielectric layer 120 and the second conductive layer 130, which may be the thicknesses commonly used in the art for the corresponding layers.

further, as shown in fig. 3, a second dielectric layer 140 is formed, and the second dielectric layer 140 covers the second conductive layer 130. Specifically, the thickness of the second dielectric layer 140 is between the thicknesses of the first dielectric layer 140 and the second dielectric layer 140 is made of silicon nitride or silicon oxynitride, and the material is selected to be silicon nitride or silicon oxynitride, so that the second dielectric layer 140 is suitable for being used as an intermediate insulating medium of a second capacitor 300 to be formed subsequently.

next, as shown in fig. 4, an isolation layer 150 is formed, wherein the isolation layer 150 covers the second dielectric layer 140 and the first dielectric layer 120 not covered by the second conductive layer 130. The isolation layer 150 may be made of a common silicon oxide, and in this embodiment, the isolation layer 150 may be formed by a chemical vapor deposition process. The isolation layer 150 may cover the second dielectric layer 140 and fill the trenches formed by the second conductive layer 130 and the second dielectric layer 140 on the first dielectric layer 120, so that the first plug and the second plug penetrating the isolation layer 150 can be insulated from the second conductive layer 130, thereby improving the yield of the device. In addition, the isolation layer 150 is formed on the second dielectric layer 140, so that a favorable condition is provided for a subsequent chemical mechanical polishing process, and the stress generated by polishing between layers below the isolation layer 150 can be reduced by polishing the flat surface of the isolation layer 150, thereby avoiding the situation that the topography of each layer is damaged.

then, as shown in fig. 5, a chemical mechanical polishing process is performed to remove the isolation layer 150 on the second dielectric layer 140. Specifically, the isolation layer 150 on the second dielectric layer 140 is removed by a chemical mechanical polishing process, and the isolation layer 150 in a trench formed by forming the second conductive layer 130 and the second dielectric layer 140 on the first dielectric layer 120 is remained. Preferably, when the chemical mechanical polishing process is performed, the isolation layer 150 and a part of the second dielectric layer with a certain thickness on the second dielectric layer 140 may also be removed, and the thickness of the second dielectric layer with a part of the thickness removed by the chemical mechanical polishing process may be the thickness of the second dielectric layer with a part of the thickness correspondingly removed when the isolation layer 150 is removed by polishing, so that the isolation layer 150 on the second dielectric layer with a residual thickness after polishing is cleaned, and the situation that the isolation layer 150 still remains on the surface of the second dielectric layer 140 is avoided.

Further, as shown in fig. 6, a first plug 210, a second plug 220 and an interconnection layer 160 are formed, the first plug 210 penetrates through the isolation layer 150 and the first dielectric layer 120 and is electrically connected to the first conductive layer 110, the second plug 220 penetrates through the isolation layer 150 and the second dielectric layer 140 and is electrically connected to the second conductive layer 130, the interconnection layer 160 is formed on the isolation layer 150 and the second dielectric layer 140, the first plug 210 and the second plug 220 are respectively electrically connected to the interconnection layer 160, and the first plug 210 and the second plug 220 are insulated from each other, as seen in fig. 6, a trench 310 is formed in the interconnection layer 160, and the trench 310 can electrically disconnect the first plug 210 from the second plug 220. Wherein the stacked interconnection layer 160, the second dielectric layer 140 and the second conductive layer 130 form a second capacitor 300, the first capacitor 200 and the second capacitor 300 form a parallel capacitor, the second conductive layer 130 with a part of the surface covered by the cobalt compound film serves as an upper plate of the second capacitor 300, the second dielectric layer 140 serves as an intermediate insulating medium of the second capacitor 300, the interconnection layer 160 serves as a lower plate of the second capacitor 300, thereby forming a second capacitor of a PIM (polysilicon-insulating layer-metal) structure, thereby forming a parallel capacitor of a PPM (polysilicon-metal) structure, a capacitance value of the parallel capacitor is greater than or equal to 3.3fF/μm2, a capacitance value of a present PIP structure capacitor can only achieve about 1.3fF/μm2 at most, the parallel capacitor formed by the invention can obviously improve the total capacitance value of the device.

Before the interconnection layer 160 is formed, the isolation layer 150 on the second dielectric layer 140 is removed by a chemical mechanical polishing process without adding a new photomask, and the second dielectric layer 140 is used as an intermediate insulating medium between the second conductive layer 130 and the interconnection layer 160 to obtain the second capacitor 300 connected in parallel with the first capacitor 200, so that the total capacitance of the device is significantly improved by the formed parallel capacitor, and the vertical distance between the interconnection layer 160 and the first conductive layer 110 and the second conductive layer 130 is also reduced, thereby reducing the volume of the circuit and meeting the requirement of a semiconductor device with a smaller size.

Based on the same inventive concept, the present invention further provides a parallel capacitor, as shown in fig. 6, including:

a substrate 100, wherein a first conductive layer 110, a first dielectric layer 120 and a second conductive layer 130 are formed on the substrate 100, the first conductive layer 110 covers a part of the surface of the substrate 100, the first dielectric layer 120 covers the first conductive layer 110, the second conductive layer 130 covers a part of the surface of the first dielectric layer 120 and the substrate 100, and the first conductive layer 110, the first dielectric layer 120 and the second conductive layer 130 which are stacked with each other form a first capacitor 200;

A second dielectric layer 140, wherein the second dielectric layer 140 covers the second conductive layer 130;

An isolation layer 150, wherein the isolation layer 150 covers a portion of the surfaces of the first dielectric layer 120 and the second dielectric layer 140;

a first plug 210, wherein the first plug 210 penetrates through the isolation layer 150 and the first dielectric layer 120 and is electrically connected to the first conductive layer 110;

A second plug 220, wherein the second plug 220 penetrates through the isolation layer 150 and the second dielectric layer 140 and is electrically connected to the second conductive layer 130; and the number of the first and second groups,

An interconnection layer 160, wherein the interconnection layer 160 is formed on the isolation layer 150 and the second dielectric layer 140, the first plug 210 and the second plug 220 are electrically connected to the interconnection layer 160, respectively, and the first plug 210 and the second plug 220 are insulated from each other, wherein the interconnection layer 160, the second dielectric layer 140 and the second conductive layer 130 stacked on each other constitute a second capacitor 300, the first capacitor 200 and the second capacitor 300 constitute a parallel capacitor, the first capacitor 200 is constituted by using the first conductive layer 110, the first dielectric layer 120 and the second conductive layer 130 in a conventional process, and the second capacitor 300 is obtained in parallel with the first capacitor 200 by using the second dielectric layer 140 in a conventional process as an intermediate insulation medium of the interconnection layer 160 and the second conductive layer 130, so that a vertical distance between the interconnection layer 160 and the first conductive layer 110 and the second conductive layer 130 is reduced, therefore, the size of the circuit is reduced, the requirement of a semiconductor device with a smaller size is met, and the total capacitance value of the device is improved.

In summary, the present invention provides a method for forming a parallel capacitor and a parallel capacitor, the method for forming a parallel capacitor includes: providing a substrate, wherein a first conducting layer, a first dielectric layer and a second conducting layer are sequentially formed on the substrate, and the first conducting layer, the first dielectric layer and the second conducting layer form a first capacitor (PIP structure); forming a second dielectric layer and an isolation layer on the second conductive layer, and grinding to remove the isolation layer on the surface of the second dielectric layer; and forming an interconnection layer on the second dielectric layer, wherein the interconnection layer, the second dielectric layer and the second conductive layer form a second capacitor (PIM structure), and the first capacitor and the capacitor form a parallel capacitor (PPM structure). Under the condition that other process steps such as photoetching are not additionally carried out, the isolation layer on the surface of the second dielectric layer is removed through grinding, the second dielectric layer is used as an intermediate insulation medium of the second conducting layer and the interconnection layer to obtain a second capacitor connected with the first capacitor in parallel, and the total capacitance value of the device is remarkably improved due to the formed parallel capacitor; meanwhile, the size of the parallel capacitor in height is reduced, so that the size of the circuit is reduced, and the requirements of a semiconductor device with a smaller size are met.

the above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.