阅读说明：本技术 集成电路以及用于形成集成电路的系统和方法 (Integrated circuit and system and method for forming integrated circuit ) 是由 杨荣展 江庭玮 高章瑞 庄惠中 鲁立忠 田丽钧 沈孟弘 谢尚志 卢麒友 于 2017-11-28 设计创作，主要内容包括：集成电路结构包括栅极结构组、第一导电结构、第一组通孔和第二组通孔,以及第一组导电结构。该栅极结构组位于第一层级处。第一导电结构在第一方向上延伸,与该栅极结构组重叠并且位于第二层级处。第一组通孔位于栅极结构组和第一导电结构之间。第一组通孔将该栅极结构组连接至第一导电结构。第一组导电结构在第二方向上延伸,与第一导电结构重叠并且位于第三层级处。第二组通孔将第一组导电结构连接至第一导电结构,并且位于第一组导电结构和第一导电结构之间。(The integrated circuit structure includes a set of gate structures, a first conductive structure, a first set of vias and a second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures, and is located at a second level. The first set of vias is located between the set of gate structures and the first conductive structure. A first set of vias connects the set of gate structures to the first conductive structure. The first set of conductive structures extends in the second direction, overlaps the first conductive structures, and is located at a third level. The second set of vias connects the first set of conductive structures to the first conductive structure and is located between the first set of conductive structures and the first conductive structure.)

1. An integrated circuit structure comprising standard cells, each of the standard cells comprising:

a gate structure group located at a first level, each gate in the gate structure group being separated from each other in a first direction and extending in a second direction different from the first direction;

a first conductive structure extending in the first direction, overlapping each gate of the set of gate structures and located at a second level;

a first set of vias between the set of gate structures and the first conductive structure, each via in the first set of vias located at a position where the first conductive structure overlaps each gate in the set of gate structures, the first set of vias connecting the each gate in the set of gate structures to the first conductive structure;

a first set of conductive structures extending in the second direction, overlapping the first conductive structures, at a third level, each conductive structure of the first set of conductive structures being separated from each other in the first direction and positioned between a pair of gates of the set of gate structures;

a second set of vias between the first set of conductive structures and the first conductive structure, each via in the second set of vias being located where the first set of conductive structures overlaps the first conductive structure, and the second set of vias connecting the first set of conductive structures to the first conductive structure; and

A second set of conductive structures extending in the second direction, overlying the first set of conductive structures and positioned between the pair of gates in the set of gate structures, at a fifth level, connected to the first set of conductive structures by additional vias, each of the additional vias being located at a position where each of the first and second sets of conductive structures overlaps the first conductive structure, the first set of conductive structures being connected to the second set of conductive structures by the second and additional vias, centers of the second and additional vias being aligned in the first and second directions;

a first power rail;

a second power supply rail, the first power supply rail and the second power supply rail being located at the second level;

wherein the first conductive structure, the first set of vias, the first set of conductive structures, the second set of vias, and the second set of conductive structures are configured to provide a first supply voltage or a second supply voltage different from the first supply voltage to the set of gate structures, and the first conductive structure, the first set of vias, the first set of conductive structures, the second set of vias, and the second set of conductive structures are located between and electrically connected to the first supply rail and the second supply rail.

2. The integrated circuit structure of claim 1, further comprising:

a second conductive structure extending in the first direction, overlapping the first set of conductive structures, overlying the first conductive structure, and located at a fourth level;

wherein a third set of the additional vias is located between the second conductive structure and the first set of conductive structures, each via of the third set of vias is located at a position where the second set of conductive structures overlaps the first set of conductive structures, and the third set of vias connects the second conductive structure to the first set of conductive structures.

3. The integrated circuit structure of claim 2,

a fourth set of the additional vias is located between the second set of conductive structures and the second conductive structure, each of the fourth set of vias is located at a position where the second set of conductive structures overlaps the second conductive structure, and the fourth set of vias connects the second set of conductive structures to the second conductive structure.

4. The integrated circuit structure of claim 3,

the first supply rail is configured to provide the first supply voltage; and

The second supply rail is configured to provide the second supply voltage.

5. The integrated circuit structure of claim 3,

centers of the second set of vias, the third set of vias, and the fourth set of vias are aligned in the first direction and the second direction.

6. The integrated circuit structure of claim 3,

the second set of conductive structures has the same width as the first set of conductive structures.

7. The integrated circuit structure of claim 3,

the second set of conductive structures has the same length as the first set of conductive structures.

8. The integrated circuit structure of claim 3,

each conductive structure of the first or second set of conductive structures is located between a pair of gate structures of the set of gate structures.

9. An integrated circuit structure comprising standard cells, each of the standard cells comprising:

a first set of electrically conductive structures extending in a first direction, located at a first level, comprising two first electrically conductive structures, and each of the two first electrically conductive structures being separated from each other in a second direction different from the first direction, the two first electrically conductive structures being electrically connected to a drain of a transistor device;

A second set of conductive structures extending in the second direction, including two second conductive structures, each of the two second conductive structures overlapping two of the first set of conductive structures on a second level different from the first level, and each of the second set of conductive structures being separated from each other in the first direction;

a first set of vias between the second set of conductive structures and the first set of conductive structures, the first set of vias connecting the second set of conductive structures to the first set of conductive structures, and each via in the first set of vias at a location where each conductive structure in the second set of conductive structures overlaps each conductive structure in the first set of conductive structures;

a third set of conductive structures extending in the first direction, overlapping the second set of conductive structures, covering portions of the first set of conductive structures, at a third level different from the first and second levels, each conductive structure in the third set of conductive structures being separated from each other in the second direction; and

a second set of vias between the third set of conductive structures and the second set of conductive structures, the second set of vias connecting the third set of conductive structures to the second set of conductive structures, and each via in the second set of vias being located at a position where each conductive structure in the third set of conductive structures overlaps each conductive structure in the second set of conductive structures;

A first power rail; and

a second power supply rail, the first power supply rail and the second power supply rail being located at the first level;

wherein the first set of conductive structures, the second set of conductive structures, the first set of vias, the third set of conductive structures, the second set of vias are configured to provide the first supply voltage or a second supply voltage different from the first supply voltage to the set of gate structures, and the first set of conductive structures, the second set of conductive structures, the first set of vias, the third set of conductive structures, the second set of vias are located between and electrically connected to the first supply rail and the second supply rail.

10. A method of fabricating an integrated circuit structure, the method comprising:

placing a first set of conductive structure layout patterns on a first layout level, the first set of conductive structure layout patterns corresponding to a first set of conductive structures in one standard cell of a fabricated integrated circuit structure, the first set of conductive structure layout patterns including two first conductive structure layout patterns extending in a first direction, each of the two first conductive structure layout patterns being separated from each other in a second direction different from the first direction, the two first conductive structures being electrically connected to drains of transistor devices;

Placing a second set of conductive structure layout patterns on a second layout level different from the first layout level, the second set of conductive structure layout patterns corresponding to a second set of conductive structures in the one standard cell in which the integrated circuit structure is fabricated, the second set of conductive structure layout patterns including two second conductive structure layout patterns extending in the second direction, each of the two second conductive structure layout patterns overlapping the two first conductive structure layout patterns and each of the second set of conductive structure layout patterns being separated from each other in the first direction;

placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, the first set of via layout patterns corresponding to fabricating a first set of vias connecting the second set of conductive structures to the first set of conductive structures, and each via layout pattern of the first set of via layout patterns being located at a position where each conductive structure layout pattern of the second set of conductive structure layout patterns overlaps each conductive structure layout pattern of the first set of conductive structure layout patterns;

Placing a set of power rail layout patterns on the first layout level, the set of power rail layout patterns corresponding to a set of manufacturing power rails,

wherein the first set of conductive structure layout patterns, the second set of conductive structure layout patterns, the first set of via layout patterns are configured to provide a first power supply voltage or a second power supply voltage different from the first power supply voltage to the drain electrode, and the first set of conductive structure layout patterns, the second set of conductive structure layout patterns, the first set of via layout patterns are located between and electrically connected to a first power supply rail and a second power supply rail of the set of power supply rails;

storing at least one of the layout patterns on a non-transitory computer readable medium and performing at least one of the operations by a hardware processor;

the integrated circuit structure is fabricated based on at least one of the above-described layout patterns of the integrated circuit.

Technical Field

Embodiments of the invention relate generally to the field of semiconductor technology, and more particularly, to integrated circuit structures and methods of fabricating the same.

Background

In many Integrated Circuits (ICs), power rails are used to distribute power to functional circuit elements formed in a substrate. Power is typically transferred to the power rails using a metal layer between the power rails and the power strip at a level above the power rail level.

The resistance of an IC structure including such a metal layer may affect power delivery efficiency, heat generation, and susceptibility to Electromigration (EM). The routing of the metal layer may also affect additional routing of electrical connections to the functional circuit elements.

Disclosure of Invention

According to an aspect of the invention, there is provided an integrated circuit structure comprising: a gate structure group located at a first level, each gate in the gate structure group being separated from each other in a first direction and extending in a second direction different from the first direction; a first conductive structure extending in the first direction, overlapping the set of gate structures and located at a second level; a first set of vias between the set of gate structures and the first conductive structure, each via in the first set of vias located at a position where the first conductive structure overlaps each gate in the set of gates, the first set of vias connecting the set of gate structures to the first conductive structure; a first set of conductive structures extending in the second direction, overlapping the first conductive structures, at a third level, each conductive structure of the first set of conductive structures being separated from each other in the first direction and positioned between a pair of gates of the set of gate structures; and a second set of vias between the first set of conductive structures and the first conductive structure, each via in the second set of vias being located at a position where the first set of conductive structures overlaps the first conductive structure, and the second set of vias connecting the first set of conductive structures to the first conductive structure.

According to another aspect of the invention, there is provided an integrated circuit structure comprising: a first set of conductive structures extending in a first direction, located at a first level, and each separated from each other in a second direction different from the first direction; a second set of conductive structures extending in the second direction, overlapping the first set of conductive structures, on a second level different from the first level, and each conductive structure of the second set of conductive structures being separated from each other in the first direction; a first set of vias between the second set of conductive structures and the first set of conductive structures, the first set of vias connecting the second set of conductive structures to the first set of conductive structures, and each via in the first set of vias at a location where each conductive structure in the second set of conductive structures overlaps each conductive structure in the first set of conductive structures; a third set of conductive structures extending in the first direction, overlapping the second set of conductive structures, covering portions of the first set of conductive structures, at a third level different from the first and second levels, each conductive structure in the third set of conductive structures being separated from each other in the second direction; and a second set of vias located between the third set of conductive structures and the second set of conductive structures, the second set of vias connecting the third set of conductive structures to the second set of conductive structures, and each via of the second set of vias located at a position where each conductive structure of the third set of conductive structures overlaps each conductive structure of the second set of conductive structures.

According to yet another aspect of the invention, there is provided a method of fabricating an integrated circuit structure, the method comprising: placing a first set of conductive structure layout patterns on a first layout level, the first set of conductive structure layout patterns corresponding to a first set of conductive structures that fabricate integrated circuit structures, the first set of conductive structure layout patterns extending in a first direction, each conductive structure layout pattern of the first set of conductive structure layout patterns being separated from one another in a second direction different from the first direction; placing a second set of conductive structure layout patterns on a second layout level different from the first layout level, the second set of conductive structure layout patterns corresponding to a second set of conductive structures that fabricate the integrated circuit structure, the second set of conductive structure layout patterns extending in the second direction, overlapping the first set of conductive structure layout patterns, and each conductive structure layout pattern in the second set of conductive structure layout patterns being separated from each other in the first direction; placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, the first set of via layout patterns corresponding to fabricating a first set of vias connecting the second set of conductive structures to the first set of conductive structures and each via layout pattern of the first set of via layout patterns being located at a position where each conductive structure layout pattern of the second set of conductive structure layout patterns overlaps each conductive structure layout pattern of the first set of conductive structure layout patterns, wherein at least one of the layout patterns is stored on a non-transitory computer readable medium and at least one of the operations is performed by a hardware processor; the integrated circuit structure is fabricated based on at least one of the above-described layout patterns of the integrated circuit.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagram of a layout design of an IC structure, according to some embodiments.

Fig. 2A and 2B are diagrams of IC structures according to some embodiments.

FIG. 3 is a diagram of a layout design, according to some embodiments.

FIG. 4 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 5 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 6 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 7 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 8 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 9 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 10 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 11 is a diagram of a layout design of an IC structure, according to some embodiments.

Fig. 12A and 12B are diagrams of IC structures according to some embodiments.

FIG. 13 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 14 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 15 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 16 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 17 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 18 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 19 is a diagram of a layout design of an IC structure, according to some embodiments.

Fig. 20A-20D are diagrams of layout designs of IC structures according to some embodiments.

FIG. 21A is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 21B is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 22 is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 23A is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 23B is a diagram of a layout design of an IC structure, according to some embodiments.

Figure 23C is a diagram of a layout design of an IC structure according to some embodiments.

Figure 23D is a diagram of a layout design of an IC structure according to some embodiments.

Fig. 24 is a diagram of an IC structure according to some embodiments.

FIG. 25A is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 25B is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 26A is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 26B is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 26C is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 26D is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 27A is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 27B is a diagram of a layout design of an IC structure, according to some embodiments.

FIG. 27C is a diagram of a layout design of an IC structure, according to some embodiments.

Figure 27D is a diagram of a layout design of an IC structure according to some embodiments.

Figure 28 is a flow diagram of a method of forming an IC structure according to some embodiments.

Fig. 29 is a flow diagram of a method of manufacturing an IC according to some embodiments.

FIG. 30 is a block diagram of a system for designing an IC layout design, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, the IC structure includes a set of gate structures, a first conductive structure, a first set of vias and a second set of vias, and the first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the group of gate structures, and is located at a second level. The first set of vias is located between the set of gate structures and the first conductive structure. The first set of vias connects the set of gate structures to the first conductive structure. The first set of conductive structures extends in the second direction, overlaps the first conductive structures, and is located at a third level. The second set of vias connects the first set of conductive structures to the first conductive structure and is located between the first set of conductive structures and the first conductive structure. In some embodiments, the IC structure is part of an input pin or an output pin. In some embodiments, the first conductive structure is located on a first metal level (e.g., M0). In some embodiments, the first set of conductive structures is located on a second metal level (e.g., M1).

In some embodiments, the center of a via in the first set of vias is aligned with the center of a via in the second set of vias in the first direction X and in the second direction Y, and is referred to as a stacked configuration. In some embodiments, vias arranged in a stacked configuration have a lower resistance than other methods.

FIG. 1 is a diagram of a layout design 100 of an IC structure, according to some embodiments. In some embodiments, the layout design 100 corresponds to a layout design with two input pins, a first pin (e.g., conductive structure layout patterns 114a, 128a) and a second pin (e.g., conductive structure layout patterns 114b, 128 b). Other configurations, locations, or numbers of elements in the layout design 100 of fig. 1 are within the scope of the invention.

The layout design 100 includes one or more gate layout patterns 102a, 102b, 102n (collectively "gate layout pattern groups 104") separated from each other in a first direction X. The gate layout pattern group 104 extends in the second direction Y and is located above the active region layout pattern (not shown). The second direction Y is different from the first direction X. Each layout pattern in the gate layout pattern group 104 is separated from adjacent layout patterns in the gate layout pattern group 104 by a pitch P1 (not shown) in the first direction X. The set of gate layout patterns 104 may be used to fabricate a corresponding set of gates 202 (shown in fig. 2A-2B) of the IC structure 200. The gate layout pattern group 104 is located on a first layout level of the layout design 100. Other configurations or numbers of gates in the set of gate layout patterns 104 are within the scope of the invention.

The layout design 100 also includes a first conductive structure layout pattern 106 located between the sets of rail layout patterns 108a, 108 b. Each of the first conductive structure layout pattern 106 and the rail layout pattern groups 108a, 108b extends in the first direction X and is separated from each other in the second direction Y. The first conductive structure layout pattern 106 may be used to fabricate a corresponding first conductive structure 206 (shown in fig. 2A-2B) of the IC structure 200. The sets of guide track layout patterns 108a, 108B may be used to fabricate respective sets of guide tracks 208a, 208B (shown in fig. 2A-2B) of the IC structure 200. Rail 208a is configured to provide a first power supply voltage VDD and rail 208b is configured to provide a second power supply voltage VSS different from the first power supply voltage VDD. In some embodiments, rail 208a is configured to provide a second supply voltage VSS and rail 208b is configured to provide a first supply voltage VDD.

In some embodiments, the distance D1 (not shown) between the first conductive structure layout pattern 106 and the rail layout pattern 108a is the same as the distance D2 (not shown) between the first conductive structure layout pattern 106 and the rail layout pattern 108 b. In some embodiments, the distance D1 (not shown) between the first conductive structure layout pattern 106 and the rail layout pattern 108a is different from the distance D2 (not shown) between the first conductive structure layout pattern 106 and the rail layout pattern 108 b.

The first conductive structure layout pattern 106 or the set of rail layout patterns 108a, 108b is located on a second layout level of the layout design 100. The second layout level of the layout design 100 is different from the first layout level. The first conductive structure layout pattern 106 overlaps the gate layout pattern group 104. In some embodiments, the guide layout patterns 108a, 108b overlap the gate layout pattern group 104. In some embodiments, the second layout level is a metal zero (M0) layer. The first conductive structure layout pattern 106 is located on the same layout level as one or more of the set of rail layout patterns 108a, 108 b. One or more of the first conductive structure layout pattern 106 or the rail layout patterns 108a, 108b are located on a different layout level than the gate layout pattern group 104. Other configurations or numbers of the first conductive structure layout pattern 106 or the rails in the set of rail layout patterns 108a, 108b are within the scope of the invention.

The layout design 100 also includes one or more via layout patterns 110a, 110 b. The first set of via layout patterns 112 may be used to fabricate a respective first set of vias 212A, 212B, 212c. Each via layout pattern of the first set of via layout patterns 112 is located above a corresponding gate layout pattern of the gate layout pattern set 104. The first group of via layout patterns 112 is located between the gate layout pattern group 104 and the first conductive structure layout pattern 106. In some embodiments, each via layout pattern of the first set of via layout patterns 112 is located at a position where the first conductive structure layout pattern 106 overlaps a corresponding gate layout pattern of the gate layout pattern set 104. In some embodiments, the center of one or more via layout patterns in the first set of via layout patterns 112 is located above the center of the corresponding gate layout pattern of the gate layout pattern set 104. In some embodiments, a center of a via layout pattern of the first set of via layout patterns 112 is aligned with another via layout pattern of the first set of via layout patterns 112 in the first direction X. The first set of via layout patterns 112 is located on a Via Contact (VC) layout level between the first layout level and the second layout level of the layout design 100. Other configurations of the first set of via layout patterns 112 are within the scope of the invention.

The layout design 100 also includes conductive structure layout patterns 114a and 114b (collectively referred to as "a first set of conductive structure layout patterns 114 (not shown)"). Each of the first group of conductive structure layout patterns 114 (not shown) extends in the second direction Y and is separated from each other in the first direction X. The first group of conductive structure layout patterns 114 (not shown) first overlaps the first conductive structure layout pattern 106. The conductive structure layout patterns 114a, 114B may be used to fabricate respective conductive structures 214a, 214B of the IC structure 200 (as shown in fig. 2A-2B).

The conductive structure layout pattern 114a is positioned between the gate layout patterns 102d and 102 e. The conductive structure layout pattern 114b is positioned between the gate layout patterns 102j and 102 k. The conductive structure layout pattern 114a does not overlap the gate layout patterns 102d and 102 e. The conductive structure layout pattern 114b does not overlap the gate layout patterns 102j and 102 k. In some embodiments, the conductive structure layout pattern 114a at least overlaps the gate layout pattern 102d or 102 e. In some embodiments, the conductive structure layout pattern 114b overlaps at least the gate layout pattern 102j or 102 k.

In some embodiments, the conductive structure layout patterns 114a and 114b each have the same length (not labeled) as each other in the second direction Y. In some embodiments, the conductive structure layout patterns 114a and 114b each have a length (not shown) different from each other in the second direction Y. In some embodiments, the conductive structure layout patterns 114a and 114b each have the same width (not labeled) as each other in the first direction X. In some embodiments, the conductive structure layout patterns 114a and 114b each have a different width (not shown) from each other in the first direction X.

A first set of conductive structure layout patterns 114 (not shown) is located on a third layout level of the layout design 100. The third layout level of the layout design 100 is different from the first and second layout levels. In some embodiments, the third layout level is a metal one (M1) layer. The conductive layout pattern 114a is located on the same layout level as the conductive layout pattern 114 b. Other configurations or numbers of the first set of conductive structure layout patterns 114 are within the scope of the present invention.

Layout design 100 also includes a set of conductive structure layout patterns 140. Each of the layout patterns in the conductive structure layout pattern group 140 extends in the second direction Y and is separated from each other in the first direction X. The conductive structure layout pattern group 140 is located between the first group of via layout patterns 112 and the gate layout pattern group 104. In some embodiments, each conductive structure layout pattern of the set of conductive structure layout patterns 140 is located between a respective via layout pattern of the first set of via layout patterns 112 and a respective gate layout pattern of the set of gate layout patterns 104.

A conductive structure layout pattern group 140 is placed on a metal-on-polysilicon (MP) layout level. The conductive structure layout pattern group 140 includes one or more conductive structure layout patterns 140a, 140 b. The conductive structure layout pattern group 140 may be used to fabricate a corresponding contact group 204a, 204B.

The conductive structure layout pattern group 140 overlaps the gate layout pattern group 104. In some embodiments, the conductive structure layout pattern group 140 is not included in the layout design 100. Other configurations or numbers of conductive structure layout patterns 140 are within the scope of the present invention.

The layout design 100 also includes one or more via layout patterns 118a, 118b (collectively referred to as "a second set of via layout patterns 118" (not shown)). The second set of via layout patterns 118 may be used to fabricate a corresponding second set of vias 218a and 218B (shown in fig. 2A-2B) of the IC structure 200. The second set of via layout patterns 118 (not shown) is located between the first set of conductive structure layout patterns 114 and the first conductive structure layout pattern 106. Each via layout pattern 118a, 118b of the second set of via layout patterns 118 (not shown) is located above a respective layout pattern 114a, 114b (first conductive structure layout pattern 106) of the first set of conductive structure layout patterns 114 (not shown). In some embodiments, each via layout pattern 118a, 118b of the second set of via layout patterns 118 is located at a position where a respective layout pattern 114a, 114b of the first set of conductive structure layout patterns 114 (not shown) overlaps the first conductive structure layout pattern 106.

In some embodiments, the center of one or more via layout patterns 118a, 118b in the second set of via layout patterns 118 is located above the center of the corresponding layout pattern 114a, 114b in the first set of conductive structure layout patterns 114 (not shown). In some embodiments, the centers of the via layout patterns in the second set of via layout patterns 118 (not shown) are aligned with the centers of the layout patterns in the first set of conductive structure layout patterns 114 (not shown) in the first direction X or in the second direction Y. The second set of via layout patterns 118 (not shown) is located on a layout level (V0) between the second layout level and the third layout level of the layout design 100. Other configurations of the second set of via layout patterns 118 (not shown) are within the scope of the present invention.

The layout design 100 also includes a second conductive structure layout pattern 122. The second conductive structure layout pattern 122 extends in the first direction X and is located between the rail layout pattern groups 108a, 108 b. The second conductive structure layout pattern 122 may be used to fabricate a corresponding second conductive structure 222 (shown in fig. 2A-2B) of the IC structure 200. In some embodiments, a distance D1 '(not shown) between the second conductive structure layout pattern 122 and the guide rail layout pattern 108a is the same as a distance D2' (not shown) between the second conductive structure layout pattern 122 and the guide rail layout pattern 108 b. In some embodiments, a distance D1 '(not shown) between the second conductive structure layout pattern 122 and the guide rail layout pattern 108a is different from a distance D2' (not shown) between the second conductive structure layout pattern 122 and the guide rail layout pattern 108 b.

In some embodiments, each of the first and second conductive structure layout patterns 106 and 122 has a length (not shown) in the first direction X different from each other. In some embodiments, each of the first and second conductive structure layout patterns 106 and 122 has the same length (not shown) as each other in the first direction X.

In some embodiments, each of the first and second conductive structure layout patterns 106 and 122 has a different width (not shown) from each other in the second direction Y. In some embodiments, each of the first and second conductive structure layout patterns 106 and 122 has the same width (not shown) as each other in the second direction Y.

The second conductive structure layout pattern 122 is located on the fourth layout level of the layout design 100. The fourth layout level of the layout design 100 is different from the first, second, and third layout levels. In some embodiments, the fourth layout level is a metal two (M2) layer. The second conductive structure layout pattern 122 overlaps the gate layout pattern group 104 and is located in the first group conductive structure layout pattern 116 (not shown). Other configurations or numbers of the second conductive structure layout patterns 122 are within the scope of the present invention.

The layout design 100 also includes one or more via layout patterns 124a, 124b (collectively referred to as a "third set of via layout patterns 124" (not shown)). The third set of via layout patterns 124 may be used to fabricate a corresponding third set of vias 224a and 224B of the IC structure 200 (as shown in fig. 2A-2B). The third set of via layout patterns 124 (not shown) is located between the first set of conductive structure layout patterns 114 and the second conductive structure layout patterns 122. Each via layout pattern 124a, 124b of the third set of via layout patterns 124 (not shown) is located above a respective layout pattern 114a, 114b of the first set of conductive structure layout patterns 114 (not shown). In some embodiments, each via layout pattern 124a, 124b of the third set of via layout patterns 124 is located at a position where the second conductive structure layout pattern 122 overlaps a corresponding layout pattern 114a, 114b of the first set of conductive structure layout patterns 114 (not shown).

In some embodiments, the center of one or more via layout patterns 124a, 124b in the third set of via layout patterns 124 is located above the center of the corresponding layout patterns 114a, 114b in the first set of conductive structure layout patterns 114 (not shown). In some embodiments, the centers of the via layout patterns 124a, 124b in the third set of via layout patterns 124 are aligned with the centers of the respective via layout patterns 118a, 118b in the second set of via layout patterns 118 (not shown) in the first direction X or the second direction Y. The third group of via layout patterns 124 (not shown) is located on a layout level (V1) between the third layout level and the fourth layout level. Other configurations of the third set of via layout patterns 124 (not shown) are within the scope of the present invention.

Layout design 100 also includes conductive structure layout patterns 128a and 128b (collectively referred to as "second set of conductive structure layout patterns 128" (not shown)). Each of the second group of conductive structure layout patterns 128 (not shown) extends in the second direction Y and is separated from each other in the first direction X. The second group of conductive structure layout patterns 128 (not shown) overlap the second conductive structure layout pattern 122. The conductive structure layout patterns 128a, 128B may be used to fabricate respective conductive structures 228a, 228B of the IC structure 200 (as shown in fig. 2A-2B).

The conductive structure layout pattern 128a is positioned between the gate layout patterns 102d and 102 e. The conductive structure layout pattern 128b is positioned between the gate layout patterns 102j and 102 k. The conductive structure layout pattern 128a does not overlap the gate layout patterns 102d and 102 e. The conductive structure layout pattern 128b does not overlap the gate layout patterns 102j and 102 k. In some embodiments, the conductive structure layout pattern 128a overlaps at least the gate layout pattern 102d or 102 e. In some embodiments, the conductive structure layout pattern 128b overlaps at least the gate layout pattern 102j or 102 k.

In some embodiments, at least two of the conductive structure layout patterns 114a, 114b, 128a, and 128b have the same length (not shown) in the second direction Y. In some embodiments, at least two of the conductive structure layout patterns 114a, 114b, 128a, and 128b have different lengths (not shown) in the second direction Y. In some embodiments, at least two of the conductive structure layout patterns 114a, 114b, 128a, and 128b have the same width (not shown) in the first direction X. In some embodiments, at least two of the conductive structure layout patterns 114a, 114b, 128a, and 128b have different widths (not shown) in the first direction X.

A second set of conductive structure layout patterns 128 (not shown) is located on a fifth layout level of the layout design 100. The fifth layout level of the layout design 100 is different from the first, second, third, and fourth layout levels. In some embodiments, the fifth layout level is a metal three (M3) layer. The conductive structure layout pattern 128a and the conductive structure layout pattern 128b are located on the same layout level. Other configurations or numbers of the second set of conductive structure layout patterns 128 are within the scope of the present invention.

The layout design 100 also includes one or more via layout patterns 130a, 130b (collectively referred to as a "fourth set of via layout patterns 130" (not shown)). The fourth set of via layout patterns 130 may be used to fabricate a corresponding fourth set of vias 230a and 230B (shown in fig. 2A-2B) of the IC structure 200. A fourth set of via layout patterns 130 (not shown) is located between the second conductive structure layout pattern 122 and the second set of conductive structure layout patterns 128.

Each via layout pattern 130a, 130b of the fourth set of via layout patterns 130 (not shown) is located below a corresponding layout pattern 128a, 128b of the second set of conductive structure layout patterns 128 (not shown). Each via layout pattern 130a, 130b in the fourth set of via layout patterns 130 (not shown) is located above a corresponding layout pattern 114a, 114b in the first set of conductive structure layout patterns 114 (not shown). In some embodiments, each via layout pattern 130a, 130b of the fourth set of via layout patterns 130 is located at a position where the respective layout pattern 128a, 128b of the second set of conductive structure layout patterns 128 (not shown) overlaps the second conductive structure layout pattern 122.

In some embodiments, the center of the via layout pattern 130a is aligned with the center of the via layout pattern 130b in the first direction X. In some embodiments, the centers of the via layout patterns 130a, 130b in the fourth set of via layout patterns 130 are aligned in the first direction X or the second direction Y with the centers of the respective via layout patterns 118a, 118b in the second set of via layout patterns 118 (not shown) or with the centers of the respective via layout patterns 124a, 124b in the third set of via layout patterns 124 (not shown). The fourth set of via layout patterns 130 (not shown) is located on a layout level (V2) between the fourth layout level and the fifth layout level of the layout design 100. Other configurations of the fourth set of via layout patterns 130 (not shown) are within the scope of the present invention.

In some embodiments, a center of one or more via layout patterns of the via layout pattern group 118, 124, or 130 is aligned with a center of another via layout pattern of the via layout pattern group 118, 124, or 130 in the first direction X and the second direction Y. In some embodiments, the via layout pattern groups 118, 124, 130 are referred to as a stacked via configuration since the center of each via is aligned with the center of at least another via layout pattern of the via layout pattern groups 118, 124, 130 on another layer in the first direction X and the second direction Y. In some embodiments, the resistance of an IC structure (e.g., IC structure 200) fabricated using layout design 100 is reduced by using a stacked via configuration, as compared to other approaches.

In some embodiments, a metal mesh structure (e.g., integrated circuit 200) configured as a dual input pin is created by utilizing at least the conductive structure layout pattern 106, 114a, 114b, 122, 128a, or 128b and the via layout pattern 112, 118a, 118b, 124a, 124b, 130a, 130 b. In some embodiments, the first conductive structure layout pattern 106 of the M0 layer occupies one M0 routing track, and the second conductive structure layout pattern 122 of the M2 layer occupies one M2 routing track.

In some embodiments, by utilizing layout design 100, the number of via layout patterns (e.g., via layout pattern groups 112, 118, 124, and 130) is increased, resulting in multiple connections between underlying and overlying conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, the second set of via layout patterns 118, the third set of via layout patterns 124, and the fourth set of via layout patterns 130 are aligned in a stacked via configuration, resulting in a lower resistance. In some embodiments, each of the second set of via layout patterns 118, the third set of via layout patterns 124, and the fourth set of via layout patterns 130 has 2 square via layout patterns.

In some embodiments, the first set of conductive structure layout patterns 114 of the M1 layer and the second set of conductive structure layout patterns 128 of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the first set of conductive structure layout patterns 114 of the M1 layer and the second set of conductive structure layout patterns 128 of the M3 layer use two or more one width (1W) M1 or two M3 routing tracks, resulting in lower resistance than other methods. In some embodiments, as the number of via layout patterns in each of the second set of via layout patterns 118, the third set of via layout patterns 124, and the fourth set of via layout patterns 130 increases, and the number of conductive structure layout patterns in the first set of conductive structure layout patterns 114 and the second set of conductive structure layout patterns 128 increases, a plurality of input pins are provided in the layout design 100, resulting in a plurality of current paths being created between the lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in a layout design 100 with better speed performance than other approaches.

In some embodiments, as the number of via layout patterns in each of the second set of via layout patterns 118, the third set of via layout patterns 124, and the fourth set of via layout patterns 130 increases, the resistance of the respective layout design is further reduced. In some embodiments, one or more of the layout designs 100 or 300, 1100, 1300, 1900 or 2300A-2300D or 2500A-2700D of FIGS. 1, 3-11, 13-19 or 23A-23D or 25A-27D have at least the same Direct Current (DC) Electromigration (EM) performance, Root Mean Square (RMS) EM performance or peak EM performance as the other methods. In some embodiments, one or more of the layout designs 100 or 300, 1300, 1900 or 2300A-2300D or 2500A-2700D in FIG. 1, 3-11, 13-19, or 23A-23D, or 25A-27D results in an improvement in timing (timing) of 87.5% as compared to other methods. One or more of the layout designs 100 or 300, 1100 or 1300 or 1900 or 2300A-2300D or 2500A-2700D in FIGS. 1, 3-11, 13-19 or 23A-23D or 25A-27D are built within cell boundaries and do not result in an increased area of the corresponding layout design as compared to other approaches.

In some embodiments, the layout design 100 is a standard cell 101 of an IC structure. Standard cell 101 or standard cell 1101 (shown in fig. 11) has a width (not shown) in first direction X and a height H1 in second direction Y. In some embodiments, standard cell 101 or standard cell 1101 (FIG. 11) is a logic gate cell. In some embodiments, the logic gate units include AND, OR, NAND, NOR, XOR, INV, AND-OR-inversion (AOI), OR-AND-inversion (OAI), multiplexers, flip-flops, BUFFs, latches, delays, clock units, AND the like. In some embodiments, the standard cell is a memory cell. In some embodiments, the memory cells include Static Random Access Memory (SRAM), dynamic ram (dram), resistive ram (rram), magnetoresistive ram (mram), Read Only Memory (ROM), and the like. In some embodiments, the standard cell includes one or more active or passive components. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), and the like, finfets, planar MOS transistors with raised sources/drains, and the like. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, and the like. Standard cell 101 or standard cell 1101 (shown in FIG. 11) includes other components not shown for ease of illustration.

Fig. 2A and 2B are diagrams of an IC structure 200 according to some embodiments. Fig. 2A is a cross-sectional view of an IC structure 200 corresponding to layout design 100 intersecting plane a-a 'according to some embodiments, and fig. 2B is a cross-sectional view of an IC structure 200 corresponding to layout design 100 intersecting plane B-B' according to some embodiments. The IC structure 200 is fabricated by the layout design 100.

The structural relationship, including alignment, length and width, and the construction of the IC structure 200 are similar to those of the layout design 100 of fig. 1 and will not be described in fig. 2A-2B for simplicity.

The IC structure 200 includes a gate set 202 located on a first level of the IC structure 200. Each gate in the gate group 202 is separated from each other in the first direction X and extends in the second direction Y. In some embodiments, one or more gates in the gate set 202 are part of one or more transistor devices (not shown).

Other numbers of gates or other configurations of gate sets 202 are within the scope of the invention.

The IC structure 200 further includes a first conductive structure 206 extending in the first direction X and overlapping the gate set 202.

The IC structure 200 further includes a set of rails 208a, 208b extending in the first direction X and overlapping the set of gates 202. The first conductive structure 206 is located between the sets of rails 208a, 208 b. The first conductive structure 206 and the sets of rails 208a, 208b are located on a second level of the IC structure 200. The first conductive structure 206 or one or more of the sets of rails 208a, 208b is located on a second level (M0) of the IC structure 200. The second level of the IC structure 200 is located above the first level of the IC structure 200. Other numbers of gates or other configurations of the first conductive structure 206 or the sets of rails 208a, 208b are within the scope of the invention.

In some embodiments, the rail sets 208a, 208b are configured to provide the first power supply voltage VDD or the second power supply voltage VSS to the IC structure 200. In some embodiments, the sets of rails 208a, 208b are electrically connected to the first conductive structure 206 (not shown).

The IC structure 200 also includes one or more contacts 204a, 204b, 204c, 204d, 204e, 204f, 204g (collectively "contact groups 204"). Each contact in the contact set 204 is located over a respective gate in the gate set 202. Each contact in the contact set 204 is electrically connected to a respective gate in the gate set 202. In some embodiments, the IC structure 200 does not include a contact set 204. One or more contacts in the set of contacts 204 are located on a metal-on-polysilicon (MP) level of the IC structure 200. The MP level of the IC structure 200 is located above the first level of the IC structure 200. In some embodiments, the set of contacts 204 is not included in the IC structure 200, and the first set of vias 212 is connected to the set of gates 202. Other numbers of contacts or other configurations of the contact sets 204 are within the scope of the invention.

The IC structure 200 also includes one or more vias 212a, 212b, 212a, 212g (collectively "the first set of vias 212") located between the set of gate structures 202 and the first conductive structure 206. Each via in the first set of vias 212 is located over a respective gate in the gate set 202. Each via of the first set of vias 212 is located at a position where the first conductive structure 206 overlaps each gate of the gate set 202. A first set of vias 212 electrically connects the gate set 202 to the first conductive structure 206. Each via in via set 212 is electrically connected to a respective gate in gate set 202.

One or more vias in the via group 212 are located on the via contact (VC layer) level of the IC structure 200. The VC level of the IC structure 200 is above the first level of the IC structure 200. Other numbers of vias or other configurations of the first set of vias 212 are within the scope of the invention.

The IC structure 200 further includes a first set of conductive structures 214 extending in the second direction Y and overlapping the first conductive structures 206. The first set of conductive structures includes conductive structures 214a and 214 b. Each conductive structure 214a, 214b of the first set of conductive structures is separated from each other in the first direction X and is positioned between a pair of gates in the gate set 202. For example, conductive structure 214a is positioned between gates 202b and 202 c. Similarly, conductive structure 214b is positioned between gates 202e and 202 f.

One or more conductive structures of the first set of conductive structures 214a, 214b are located on a third level (M1) of the IC structure 200. The third level of the IC structure 200 is located above the first level and the second level of the IC structure 200. Other numbers of conductive structures or other configurations of the first set of conductive structures 214a, 214b are within the scope of the invention.

The IC structure 200 also includes a second set of vias 218a and 218b located between the first set of conductive structures 214a, 214b and the first conductive structure 206. Each via in the second set of vias 218a, 218b is located below a respective conductive structure in the first set of conductive structures 214a, 214 b. Each via of the second set of vias 218a, 218b is located at a position where the first set of conductive structures 214a, 214b overlaps the first conductive structure 206. The second set of vias 218a, 218b electrically connect the first set of conductive structures 214a, 214b to the first conductive structure 206.

The first set of conductive structures 214a, 214b are electrically connected to one or more gates in gate set 202 through at least one or more vias in via sets 218a, 218 b. One or more of the second set of vias 218a, 218b are located on the V0 level of the IC structure 200. The V0 level of the IC structure 200 is located above the second and third levels of the IC structure 200. Other numbers of vias or other configurations of the second set of vias 218a, 218b are within the scope of the invention.

The IC structure 200 further includes a second conductive structure 222 extending in the first direction X and overlapping the first set of conductive structures 214a, 214 b. The second conductive structure 222 is located between the sets of rails 208a, 208 b. In some embodiments, the second conductive structure 222 overlies the first conductive structure 206. In some embodiments, a side of the second conductive structure 222 is aligned with a side of the first conductive structure 206 in at least the first direction X or the second direction Y.

The second conductive structure 222 is located on a fourth level (M2) of the IC structure 200. The fourth level of the IC structure 200 is above the first, second, and third levels of the IC structure 200. Other numbers or configurations of conductive structures 222 are within the scope of the present invention.

The IC structure 200 also includes a third set of vias 224a and 224b between the second conductive structure 222 and the first set of conductive structures 214a, 214 b. Each via in the third set of vias 224a, 224b is located over a respective conductive structure in the first set of conductive structures 214a, 214 b.

Each via of the third set of vias 224a, 224b is located at a position where the second conductive structure 222 overlaps the first set of conductive structures 214a, 214 b. A third set of vias 224a, 224b electrically connects second conductive structure 222 to first set of conductive structures 214a, 214 b. One or more vias of the third set of vias 224a, 224b are located on the V1 level of the IC structure 200. The V1 level of the IC structure 200 is located above the first, second, and third levels of the IC structure 200. Other numbers of vias or other configurations of the third set of vias 224a, 224b are within the scope of the invention.

The IC structure 200 further includes a second set of conductive structures 228 extending in the second direction Y and overlapping the second conductive structures 222 and the first conductive structures 206. The second set of conductive structures includes conductive structures 228a and 228 b.

Each conductive structure 228a, 228b of the second set of conductive structures is separated from each other in the first direction X and is positioned between a pair of gates of the gate set 202. For example, conductive structure 228a is positioned between gates 202b and 202 c. Similarly, conductive structure 228b is positioned between gates 202e and 202 f.

In some embodiments, the conductive structures 228a, 228b of the second set of conductive structures 228 overlie the respective conductive structures 214a, 214b of the first set of conductive structures 214. In some embodiments, one side of the conductive structures 228a, 228b in the second set of conductive structures 228 is aligned with the respective conductive structures 214a, 214b in the first set of conductive structures 214 in at least the first direction X or the second direction Y.

In some embodiments, at least two of the conductive structures 214a, 214b, 228a, and 228b have the same length (not shown) in the second direction Y. In some embodiments, at least two of the conductive structures 214a, 214b, 228a, and 228b have different lengths (not shown) in the second direction Y. In some embodiments, at least two of the conductive structures 214a, 214b, 228a, and 228b have the same width (not shown) in the first direction X. In some embodiments, at least two of the conductive structures 214a, 214b, 228a, and 228b have different widths (not shown) in the first direction X.

One or more conductive structures of the second set of conductive structures 228a, 228b are located on a fifth level (M3) of the IC structure 200. The fifth level of the IC structure 200 is located above the first, second, third, and fourth levels of the IC structure 200. Other numbers of conductive structures or other configurations of the second set of conductive structures 228a, 228b are within the scope of the present invention.

The IC structure 200 also includes a fourth set of vias 230a and 230b located between the second set of conductive structures 228a, 228b and the second conductive structure 222. Each via in the fourth set of vias 230a, 230b is located below a respective conductive structure of the second set of conductive structures 228a, 228 b. Each via in the fourth set of vias 230a, 230b is located at a position where the second set of conductive structures 228a, 228b overlaps the second conductive structure 222. A fourth set of vias 230a, 230b electrically connects the second set of conductive structures 228a, 228b to the second conductive structure 222.

One or more vias of the fourth set of vias 230a, 230b are located on the V2 level of the IC structure 200. The V2 level of the IC structure 200 is located above the first, second, third, and fourth levels of the IC structure 200. Other numbers of vias or other configurations of the fourth set of vias 230a, 230b are within the scope of the invention.

M0 is separated from gate set 202 by VC. In some embodiments, M0 is separated from gate group 202 by VC and MP. In some embodiments, one or more metal layers (not shown) separate the gate sets 202, VC, MP, or M0. M1 was separated from M0 by V0. In some embodiments, one or more metal layers (not shown) separate M0 and M1. M2 was separated from M1 by V1. In some embodiments, one or more metal layers (not shown) separate M1 and M2. M3 was separated from M2 by V2. In some embodiments, one or more metal layers (not shown) separate M2 and M3. In some embodiments, each conductive structure of the IC structures 200, 1200 located in either M0 or M3 extends in the same direction. In some embodiments, each conductive structure of the IC structures 200, 1200 located in either M1 or M2 extends in the same direction. Other configurations of via layers or metal layers are within the scope of the invention.

In some embodiments, one or more of first conductive structure 206, first set of vias 212, first set of conductive structure 214, second set of vias 218, second conductive structure 222, third set of vias 224, second set of conductive structure 228, and fourth set of vias 230 are referred to as input pins. In some embodiments, the input pin is electrically connected to an input side of one or more transistor devices (not shown). In some embodiments, one or more gates in gate set 202 correspond to an input side of one or more transistor devices (not shown). In some embodiments, the input pins are also referred to as metal mesh structures. In some embodiments, the input pin is configured to provide the first power supply voltage VDD or the second power supply voltage VSS to the gate set 202. In some embodiments, since the first set of conductive structures 214 or the second set of conductive structures 228 have two conductive structures (e.g., conductive structures 214a, 214b or conductive structures 228a, 228b), the input pins of the IC structure 200 are referred to as dual-input pins. In some embodiments, the positions of the elements in the IC structure 200 may be adjusted to be located at other positions, and the number of elements in the IC structure 200 may be adjusted to other numbers. Other configurations, locations, or numbers of elements in the IC structure 200 of fig. 2A and 2B are within the scope of the present invention.

In some embodiments, the center of one or more vias of the set of vias 218, 224, or 230 is aligned with the center of vias of the set of vias 218, 224, or 230 in the first direction X and the second direction Y. In some embodiments, the resistance of an IC structure (e.g., IC structure 200) fabricated using layout design 100 is reduced by using a stacked via configuration, as compared to other approaches.

In some embodiments, a metal mesh structure (e.g., integrated circuit 200) configured as a dual-input pin is created by utilizing at least conductive structures 206, 214a, 214b, 222, 228a, or 228b and vias 218a, 218b, 224a, 224b, 230a, 230 b. In some embodiments, the first conductive structure 206 of the M0 layer occupies one M0 routing track, and the second conductive structure 222 of the M2 layer occupies one M2 routing track.

In some embodiments, by utilizing integrated circuit 200, the number of vias (e.g., vias 212a,.., 212g, 218a, 218b, 224a, 224b, 230a, and 230b) is increased, resulting in lower resistance than other approaches. In some embodiments, vias 218a, 224a, 230a and vias 218b, 224b, and 230b are aligned in a separately stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, each of vias 218a, 224a, 230a and vias 218b, 224b, and 230b is a square via.

In some embodiments, the conductive structures 214a, 214b of the M1 layer and the corresponding conductive structures 228a, 228b of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the conductive structures 214a, 214b of the M1 layer use two or more 1W M1 routing tracks and the conductive structures 228a, 228b of the M3 layer use two M3 routing tracks, resulting in lower resistance than other approaches. In some embodiments, as the number of vias 218a, 218b, 224a, 224b, 230a, and 230b increases and the number of conductive structures 214a, 214b, 222, 228a, and 228b increases, more input pins are provided in the integrated circuit 200, resulting in multiple current paths between underlying and overlying conductive structures (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in integrated circuit 200 having better speed performance than other approaches.

In some embodiments, as the number of vias 218a, 218b, 224a, 224b, 230a, and 230b increases, the resistance of the respective integrated circuit is further reduced. In some embodiments, one or more of the integrated circuits 200, 1200, or 2400 of fig. 2A and 2B, 12A and 12B, or 24 have at least the same DC EM performance, RMS EM performance, or peak EM performance as the other methods. In some embodiments, one or more of the integrated circuits 200, 1200, or 2400 of fig. 2A and 2B, 12A and 12B, or 24 results in an 87.5% improvement in timing compared to other methods.

FIG. 3 is a diagram of a layout design 300 of an IC structure, according to some embodiments. Components identical or similar to those in fig. 1, 3 to 10 (shown below), 11 to 19 (shown below) and 20A to 30 (shown below) have the same reference numerals, and thus detailed descriptions thereof are omitted.

Layout design 300 is a variation of layout design 100 of FIG. 1. In some embodiments, layout design 300 corresponds to a layout design with dual input pins having a first pin (e.g., conductive structure layout pattern 314a, 328a) and a second pin (e.g., conductive structure layout pattern 314b, 328 b). In some embodiments, layout design 300 shows that the component locations of the dual-input pins can be adjusted to be located at other locations, and the component number of the dual-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 300 of fig. 3 are within the scope of the invention.

In contrast to layout design 100 of fig. 1, conductive structure layout patterns 314a, 328a, 314b, 328b of layout design 300 replace respective conductive structure layout patterns 114a, 128a, 114b, and 128 b. In contrast to layout design 100 of fig. 1, via layout patterns 318a, 324a, 330a, 318b, 324b, and 330b of layout design 300 replace respective via layout patterns 118a, 124a, 130a, 118b, 124b, and 130 b.

The conductive structure layout patterns 314a, 328a, 314b, 328b are similar to the corresponding conductive structure layout patterns 114a, 128a, 114b, and 128b, and thus similar detailed descriptions of these layout patterns are omitted. The via layout patterns 318a, 324a, 330a, 318b, 324b, and 330b are similar to the corresponding via layout patterns 118a, 124a, 130a, 118b, 124b, and 130b, and thus similar detailed descriptions of these layout patterns are omitted.

Conductive structure layout patterns 314a and 328a and via layout patterns 318a, 324a and 330a are positioned between gate layout patterns 102e and 102 f. Conductive structure layout patterns 314b and 328b and via layout patterns 318b, 324b, and 330b are positioned between gate layout patterns 102i and 102 j. Other configurations of the via layout pattern or the conductive structure layout pattern of fig. 3-10 are within the scope of the invention.

In some embodiments, by utilizing layout design 300, a metal mesh configuration configured as dual input pins is created. In some embodiments, by utilizing layout design 300, the number of via layout patterns (e.g., via layout patterns 318a, 318b, 324a, 324b, 330a, and 330b) is increased, resulting in multiple connections between underlying and overlying conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318a, 324a, and 330a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318b, 324b, and 330b are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, one or more of via layout patterns 318a, 318b, 324a, 324b, 330a, and 330b is a square via layout pattern. In some embodiments, the conductive structure layout patterns 314a, 314b of the M1 layer and the corresponding conductive structure layout patterns 328a, 328b of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 314a, 314b of the M1 layer each use a 1W M1 routing track and the conductive structure layout patterns 328a, 328b of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, as the number of via layout patterns 318a, 318b, 324a, 324b, 330a, and 330b increases and the number of conductive structure layout patterns 314a, 314b, 328a, 328b increases, more input pins are provided in layout design 300, resulting in more current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 300 having better speed performance than other approaches.

FIG. 4 is a diagram of a layout design 400 of an IC structure, according to some embodiments.

Layout design 400 is a variation of layout design 100 of FIG. 1. In some embodiments, layout design 400 corresponds to a three-input pin layout design having a first pin (e.g., conductive structure layout patterns 414a, 428a), a second pin (e.g., conductive structure layout patterns 414b, 428b), and a third pin (e.g., conductive structure layout patterns 414c, 428 c). In some embodiments, layout design 400 shows that the component locations of the three-input pins can be adjusted to be located at other locations, and the component numbers of the three-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 400 of fig. 4 are within the scope of the invention.

In contrast to layout design 100 of fig. 1, conductive structure layout patterns 414a, 428a, 414b, 428b of layout design 400 replace respective conductive structure layout patterns 114a, 128a, 114b, and 128 b. In comparison to the layout design 100 of fig. 1, the via layout patterns 418a, 424a, 430a, 418b, 424b, and 430b of the layout design 400 replace the respective via layout patterns 118a, 124a, 130a, 118b, 124b, and 130 b. In contrast to the layout design 100 of fig. 1, the layout design 400 of fig. 4 further includes conductive structure layout patterns 414c and 428c, and via layout patterns 418c, 424c, and 430 c.

The conductive structure layout patterns 414a, 428a, 414b, 428b are similar to the corresponding conductive structure layout patterns 114a, 128a, 114b, 128b, and thus similar detailed descriptions of these layout patterns are omitted. The via layout patterns 418a, 424a, 430a, 418b, 424b, and 430b are similar to the corresponding via layout patterns 118a, 124a, 130a, 118b, 124b, and 130b, and thus similar detailed descriptions of these layout patterns are omitted. The conductive structure layout patterns 414c, 428c are similar to the corresponding conductive structure layout patterns 114a, 128a, and therefore similar detailed descriptions of these layout patterns are omitted. The via layout patterns 418c, 424c, and 430c are similar to the corresponding via layout patterns 118a, 124a, and 130a, and thus similar detailed descriptions of these layout patterns are omitted.

The conductive structure layout patterns 414a and 428a and the via layout patterns 418a, 424a and 430a are positioned between the gate layout patterns 102c and 102 d. Conductive structure layout patterns 414b and 428b and via layout patterns 418b, 424b and 430b are positioned between gate layout patterns 102k and 1021. Conductive structure layout patterns 414c and 428c and via layout patterns 418c, 424c and 430c are positioned between gate layout patterns 102g and 102 h.

In some embodiments, by utilizing layout design 400, a metal mesh configured as a three input pin is created. In some embodiments, by utilizing layout design 400, the number of via layout patterns (e.g., via layout patterns 418a, 418b, 418c, 424a, 424b, 424c, 430a, 430b, and 430c) is increased, creating multiple connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418a, 424a, and 430a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418b, 424b, and 430b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 418a, 418b, 418c, 424a, 424b, 424c, 430a, 430b, and 430c is a square via layout pattern. In some embodiments, the conductive structure layout patterns 414a, 414b, 414c of the M1 layer are aligned with the corresponding conductive structure layout patterns 428a, 428b, 428c of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 414a, 414b, 414c of the M1 layer each use a 1W M1 routing track and the conductive structure layout patterns 428a, 428b, 428c of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, as the number of via layout patterns 418a, 418b, 418c, 424a, 424b, 424c, 430a, 430b, and 430c increases and the number of conductive structure layout patterns 414a, 414b, 414c, 428a, 428b, 428c increases, more input pins are provided in the layout design 400, thereby creating more current paths between the lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 400 having better speed performance than other approaches.

Fig. 5 is a diagram of a layout design 500 of an IC structure, according to some embodiments.

Layout design 500 is a variation of layout design 300 of fig. 3 and layout design 400 of fig. 4. In some embodiments, the layout design 500 corresponds to a layout design with five input pins, a first pin (e.g., conductive structure layout patterns 414a, 428a), a second pin (e.g., conductive structure layout patterns 414b, 428b), a third pin (e.g., conductive structure layout patterns 414c, 428c), a fourth pin (e.g., conductive structure layout patterns 314a, 328a), and a fifth pin (e.g., conductive structure layout patterns 314b, 328 b). In some embodiments, layout design 500 shows that the component locations of the five-input pins can be adjusted to be located at other locations, and the component numbers of the five-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 500 of fig. 5 are within the scope of the invention.

Layout design 500 combines layout design 300 and layout design 400. For example, the layout design 500 includes five M1 conductive structure layout patterns (e.g., conductive structure layout patterns 314a, 314b, 414a, 414b, and 414c), five M3 conductive structure layout patterns (e.g., conductive structure layout patterns 328a, 328b, 428a, 428b, and 428c), five V0 via layout patterns (e.g., via layout patterns 318a, 318b, 418a, 418b, and 418c), five V1 via layout patterns (e.g., via layout patterns 324a, 324b, 424a, 424b, and 424c), and five V2 via layout patterns (e.g., via layout patterns 330a, 330b, 430a, 430b, and 430 c).

In some embodiments, by utilizing layout design 500, a metal mesh configuration configured as a five input pin is created. In some embodiments, by utilizing layout design 500, the number of via layout patterns (e.g., via layout patterns 318a, 318b, 418a, 418b, 418c, 324a, 324b, 424a, 424b, 424c, 330a, 330b, 430a, 430b, and 430c) is increased, creating more connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318a, 324a, and 330a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318b, 324b, and 330b are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418a, 424a, and 430a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418b, 424b, and 430b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 314a, 314b, 414a, 414b, 414c of the M1 layer are aligned with the corresponding conductive structure layout patterns 328a, 328b, 428a, 428b, 428c of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 314a, 314b, 414a, 414b, 414c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 328a, 328b, 428a, 428b, 428c of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 318a, 318b, 418a, 418b, 418c, 324a, 324b, 424a, 424b, 424c, 330a, 330b, 430a, 430b, and 430c is a square via layout pattern. In some embodiments, as the number of via layout patterns 318a, 318b, 418a, 418b, 418c, 324a, 324b, 424a, 424b, 424c, 330a, 330b, 430a, 430b, and 430c increases and the number of conductive structure layout patterns 314a, 314b, 414a, 414b, 414c, 328a, 328b, 428a, 428b, 428c increases, more input pins are provided in layout design 500, thereby creating more current paths between lower and upper conductive feature patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 500 having better speed performance than other approaches.

FIG. 6 is a diagram of a layout design 600 of an IC structure, according to some embodiments.

Layout design 600 is a variation of layout design 500 of FIG. 5. In some embodiments, the layout design 600 corresponds to a four-input pin layout design having a first pin (e.g., conductive structure layout patterns 414a, 428a), a second pin (e.g., conductive structure layout patterns 414b, 428b), a third pin (e.g., conductive structure layout patterns 314b, 328b), and a fourth pin (e.g., conductive structure layout patterns 614a, 628 a). In some embodiments, layout design 600 shows that the component locations of the four-input pins can be adjusted to be located at other locations, and the component number of the four-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 600 of fig. 6 are within the scope of the invention.

In contrast to the layout design 500 of fig. 5, the layout design 600 of fig. 6 does not include the conductive structure layout patterns 414c and 428c, and the via layout patterns 418c, 424c, and 430 c.

In contrast to layout design 500 of fig. 5, conductive structure layout patterns 614a and 628a of layout design 600 replace respective conductive structure layout patterns 314a and 328a, and via layout patterns 618a, 624a, and 630a of layout design 600 replace respective via layout patterns 318a, 324a, and 330 a.

The conductive structure layout patterns 614a and 628a, and the via layout patterns 618a, 624a, and 630a are located between the gate layout patterns 102f and 102 g. The conductive structure layout patterns 614a, 628a are similar to the respective conductive structure layout patterns 314a, 328a, and therefore similar detailed descriptions of these layout patterns are omitted. The via layout patterns 618a, 624a, and 630a are similar to the corresponding via layout patterns 318a, 324a, and 330a, and thus similar detailed descriptions of these layout patterns are omitted.

In some embodiments, layout design 600 includes four M1 conductive structure layout patterns (e.g., conductive structure layout patterns 314b, 414a, 414b, and 614a), four M3 conductive structure layout patterns (e.g., conductive structure layout patterns 328b, 428a, 428b, and 628a), four V0 via layout patterns (e.g., via layout patterns 318b, 418a, 418b, and 618a), four V1 via layout patterns (e.g., via layout patterns 324b, 424a, 424b, and 624a), and four V2 via layout patterns (e.g., via layout patterns 330b, 430a, 430b, and 630 a).

In some embodiments, by utilizing layout design 600, a metal mesh configuration configured as four input pins is created. In some embodiments, by utilizing layout design 600, the number of via layout patterns (e.g., via layout patterns 318b, 324b, 330b, 418a, 418b, 424a, 424b, 430a, 430b, 618a, 624a, and 630a) is increased, creating more connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318b, 324b, and 330b are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418a, 424a, and 430a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418b, 424b, and 430b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 618a, 624a, and 630a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 314b, 414a, 414b, 614a of the M1 layer are aligned with the corresponding conductive structure layout patterns 328b, 428a, 428b, 628a of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 314b, 414a, 414b, 614a of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 328b, 428a, 428b, 628a of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 318b, 324b, 330b, 418a, 418b, 424a, 424b, 430a, 430b, 618a, 624a, and 630a is a square via layout pattern. In some embodiments, as the number of via layout patterns 318b, 324b, 330b, 418a, 418b, 424a, 424b, 430a, 430b, 618a, 624a, 630a increases and the number of conductive structure layout patterns 314b, 414a, 414b, 614a, 328b, 428a, 428b, 628a increases, more input pins are provided in the layout design 600, thereby creating multiple current paths between the underlying and overlying conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 600 having better speed performance than other approaches.

Fig. 7 is a diagram of a layout design 700 of an IC structure, according to some embodiments.

Layout design 700 is a variation of layout design 500 of FIG. 5. In some embodiments, layout design 700 corresponds to a double-height, three-input pin layout design having a first pin (e.g., conductive structure layout pattern 714a, 728a), a second pin (e.g., conductive structure layout pattern 714b, 728b), and a third pin (e.g., conductive structure layout pattern 714c, 728 c). In some embodiments, layout design 700 shows that the component locations of the three-input pins can be adjusted to be located at other locations, and the component numbers of the three-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 700 of fig. 7 are within the scope of the invention.

Layout design 700 shows an enlarged view of a portion of layout design 500 extending from gate layout pattern 102d to gate layout pattern 102 k.

Height H2 of layout design 700 is twice height H1 of one or more of layout designs 100 and 300-600.

In contrast to layout design 500 of FIG. 5, layout design 700 includes a first portion 704a and a second portion 704 b. The first portion 704a is a mirror image of the second portion 704b with respect to the first line 702. In some embodiments, first portion 704a is not a mirror image of second portion 704b with respect to first line 702. Layout design 700 is symmetric with respect to first line 702.

The first portion 704a includes layout patterns as described in the layout pattern 500 of fig. 5, and thus similar detailed descriptions of these layout patterns are omitted.

The second portion 704b includes a third conductive structure layout pattern 706, a rail layout pattern 708a, a fourth conductive structure layout pattern 722, and via layout patterns 718a, 724a, 730a, 718b, 724b, 730b, 718c, 724c, and 730 c.

In contrast to layout design 500 of fig. 5, conductive structure layout patterns 714a, 728a, 714b, 728b, 714c, and 728c of layout design 700 replace respective conductive structure layout patterns 314a, 328a, 314b, 328b, 414c, and 428 c. The conductive structure layout patterns 714a, 728a, 714b, 728b, 714c, and 728c are similar to the corresponding conductive structure layout patterns 314a, 328a, 314b, 328b, 414c, and 428c, and therefore similar detailed descriptions of these layout patterns are omitted.

Conductive structure layout patterns 714a, 728a, 714b, 728b, 714c, and 728c extend in the second direction Y to intersect the first line 702, entering the second portion 704b of the layout design 700.

The layout patterns in the second portion 704b are similar to the corresponding layout patterns in the first portion 704a, and therefore similar detailed descriptions of these layout patterns are omitted.

Via layout patterns 718a, 724a, and 730a are similar to via layout patterns 318a, 324a, and 330a, and therefore similar detailed descriptions of these layout patterns are omitted.

Via layout patterns 718b, 724b, and 730b are similar to via layout patterns 318b, 324b, and 330b, and therefore similar detailed descriptions of these layout patterns are omitted.

The via layout patterns 718c, 724c, and 730c are similar to the via layout patterns 418a, 424a, and 430a, and thus similar detailed descriptions of these layout patterns are omitted.

The third conductive structure layout pattern 706 is similar to the first conductive structure layout pattern 106, and thus similar detailed descriptions of these layout patterns are omitted.

The fourth conductive structure layout pattern 722 is similar to the second conductive structure layout pattern 122, and thus a similar detailed description of these layout patterns is omitted.

The rail layout pattern 708a is similar to the rail layout pattern 108a, and therefore a similar detailed description of these layout patterns is omitted.

In some embodiments, layout design 700 includes three M1 conductive structure layout patterns (e.g., conductive structure layout patterns 714a, 714b, and 714c), three M3 conductive structure layout patterns (e.g., conductive structure layout patterns 728a, 728b, and 728c), six V0 via layout patterns (e.g., via layout patterns 318a, 318b, 418c, 718a, 718b, and 718c), six V1 via layout patterns (e.g., via layout patterns 324a, 324b, 424c, 724a, 724b, and 724c), and six V2 via layout patterns (e.g., via layout patterns 330a, 330b, 430c, 730a, 730b, and 730 c). In some embodiments, layout design 700 includes two M2 conductive structure layout patterns (e.g., conductive structure layout patterns 122 and 722) and two M0 conductive structure layout patterns (e.g., conductive structure layout patterns 106 and 706).

In some embodiments, by utilizing layout design 700, a metal mesh configuration configured as double-height, three-input pins is created. In some embodiments, by utilizing layout design 700, an increased number of via layout patterns (e.g., via layout patterns 318a, 318b, 324a, 324b, 330a, 330b, 418c, 424c, 430c, 718a, 718b, 718c, 724a, 724b, 724c, 730a, 730b, and 730c), more connections are made between the underlying and overlying conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318a, 324a, and 330a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318b, 324b, and 330b are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 718a, 724a, and 730a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 718b, 724b, and 730b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 718c, 724c, and 730c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 714a, 714b, 714c of the M1 layer are aligned with the corresponding conductive structure layout patterns 728a, 728b, 728c of the M3 layer, resulting in a lower resistance than other methods.

In some embodiments, the conductive structure layout patterns 714a, 714b, 714c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 728a, 728b, 728c of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of the via layout patterns 318a, 318b, 324a, 324b, 330a, 330b, 418c, 424c, 430c, 718a, 718b, 718c, 724a, 724b, 724c, 730a, 730b, and 730c is a square via layout pattern. In some embodiments, as the number of via layout patterns 318a, 318b, 324a, 324b, 330a, 330b, 418c, 424c, 430c, 718a, 718b, 718c, 724a, 724b, 724c, 730a, 730b, 730c increases and the number of conductive structure layout patterns 714a, 714b, 714c, 728a, 728b, 728c increases, more input pins are provided in the layout design 700, thereby creating multiple current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 700 having better speed performance than other approaches.

FIG. 8 is a diagram of a layout design 800 of an IC structure, according to some embodiments.

Layout design 800 is a variation of layout design 700 of FIG. 7. In some embodiments, layout design 800 corresponds to a double-height, dual-input pin layout design having a first pin (e.g., conductive structure layout pattern 714a, 728a) and a second pin (e.g., conductive structure layout pattern 714c, 728 c). In some embodiments, layout design 800 shows that the component locations of the dual-input pins can be adjusted to be located at other locations, and the component number of the dual-input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 800 of FIG. 8 are within the scope of the invention.

In contrast to layout design 700 of fig. 7, layout design 800 of fig. 8 does not include conductive structure layout patterns 714b and 728b, and via layout patterns 718b, 724b, 730b, 318b, 324b, and 330 b.

Layout design 800 shows an enlarged view of a portion of layout design 500 extending from gate layout pattern 102c to gate layout pattern 102 j. In contrast to layout design 700 of fig. 7, layout design 800 of fig. 8 is shifted by one poly pitch (P1) in first direction X and thus extends from gate layout pattern 102c to gate layout pattern 102 j.

In some embodiments, by utilizing layout design 800, a metal mesh configuration configured as double-height, dual-input pins is created. In some embodiments, by utilizing layout design 800, the number of via layout patterns (e.g., via layout patterns 318a, 324a, 330a, 418c, 424c, 430c, 718a, 718c, 724a, 724c, 730a, and 730c) is increased, creating more connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout patterns 318a, 324a, and 330a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 718a, 724a, and 730a are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 718c, 724c, and 730c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 714a, 714c of the M1 layer and the corresponding conductive structure layout patterns 728a, 728c of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 714a, 714c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 728a, 728c of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of the via layout patterns 318a, 324a, 330a, 418c, 424c, 430c, 718a, 718c, 724a, 724c, 730a, and 730c is a square via layout pattern. In some embodiments, as the number of via layout patterns 318a, 324a, 330a, 418c, 424c, 430c, 718a, 718c, 724a, 724c, 730a, 730c increases and the number of conductive structure layout patterns 714a, 714c, 728a, 728c increases, multiple input pins are provided in the layout design 800, creating multiple current paths between the lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 800 having better speed performance than other approaches.

FIG. 9 is a diagram of a layout design 900 of an IC structure according to some embodiments.

Layout design 900 is a variation of layout design 700 of FIG. 7. In some embodiments, layout design 900 corresponds to a layout design with three times the height of the first pins (e.g., conductive structure layout patterns 914c, 928c), single input pins. In some embodiments, layout design 900 shows that the component locations of the single input pins can be adjusted to be located at other locations, and the component numbers of the single input pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 900 of fig. 9 are within the scope of the invention.

Layout design 900 shows an enlarged portion of layout design 700 extending from gate layout pattern 102e to gate layout pattern 102 j.

Height H3 of layout design 900 is three times the height H1 of one or more of layout designs 100 and 300-600.

In contrast to layout design 700 of FIG. 7, layout design 900 also includes a third portion 904 c. The third portion 904c is a mirror image of the second portion 704b with respect to the second line 902. In some embodiments, the third portion 904c is not a mirror image of the second portion 704b relative to the second line 902.

The third portion 904c includes a fifth conductive structure layout pattern 906, a rail layout pattern 908b, a sixth conductive structure layout pattern 922, and via layout patterns 918c, 924c, and 930 c.

In contrast to layout design 700 of fig. 7, layout design 900 does not include conductive structure layout patterns 714a, 728a, 714b, 728b and via layout patterns 718a, 724a, 730a, 718b, 724b, and 730 b.

In contrast to layout design 700 of fig. 7, conductive structure layout patterns 914c and 928c of layout design 900 replace respective conductive structure layout patterns 714c and 728 c. The conductive structure layout patterns 914c and 928c are similar to the corresponding conductive structure layout patterns 714c and 728c, and thus similar detailed descriptions of these layout patterns are omitted. Conductive structure layout patterns 914c and 928c extend in the second direction Y to intersect the first line 702 and the second line 902, entering the third portion 904c of the layout design 900.

The layout patterns in the third portion 904c are similar to the corresponding layout patterns in the first portion 704a or the second portion 704b, and thus similar detailed descriptions of these layout patterns are omitted.

The via layout patterns 918c, 924c and 930c are similar to the via layout patterns 318a, 324a and 330a or the via layout patterns 718c, 724c and 730c, and thus similar detailed descriptions of these layout patterns are omitted.

The fifth conductive structure layout pattern 906 is similar to the first conductive structure layout pattern 106 or the third conductive structure layout pattern 706, and thus a similar detailed description of these layout patterns is omitted.

The sixth conductive structure layout pattern 922 is similar to the second conductive structure layout pattern 122 or the fourth conductive structure layout pattern 722, and thus similar detailed descriptions of these layout patterns are omitted.

The guide rail layout pattern 908b is similar to the guide rail layout pattern 108b, and therefore a similar detailed description of these layout patterns is omitted.

In some embodiments, by utilizing layout design 900, a metal mesh configured as a triple height, single input pin is created. In some embodiments, by utilizing layout design 900, the number of via layout patterns (e.g., via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, and 930c) is increased, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 718c, 724c, and 730c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 918c, 924c and 930c are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the conductive structure layout pattern 914c of the M1 layer and the corresponding conductive structure layout pattern 928c of the M3 layer are aligned, resulting in a lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 914c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 928c of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of the via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, and 930c are square via layout patterns. In some embodiments, as the number of via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, 930c increases and the number of conductive structure layout patterns 914a, 914c increases, more input pins are provided in layout design 900, thereby creating multiple current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 900 having better speed performance than other approaches.

Fig. 10 is a diagram of a layout design 1000 of an IC structure, according to some embodiments.

Layout design 1000 is a variation of layout design 800 of FIG. 8 and layout design 900 of FIG. 9. In some embodiments, layout design 1000 corresponds to a layout design with three times the height, dual input pins for a first pin (e.g., conductive structure layout patterns 1014b, 1028b) and a second pin (e.g., conductive structure layout patterns 1014c, 1028 c). In some embodiments, layout design 1000 shows that the three-height, dual-input pin component locations can be adjusted to be located at other locations, and the three-height, dual-input pin component count can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1000 of FIG. 10 are within the scope of the invention.

Layout design 1000 combines elements of layout design 800 and layout design 900. For example, layout design 1000 includes some elements of height H3 similar to layout design 800 of layout design 900. Height H3 of layout design 1000 is three times the height H1 of one or more of layout designs 100 and 300-600.

Layout design 1000 shows an enlarged portion of layout design 900 extending from gate layout pattern 102d to gate layout pattern 102 i.

In comparison to layout design 800 of fig. 8, conductive structure layout patterns 1014c, 1028c, 1014b, and 1028b of layout design 1000 replace respective conductive structure layout patterns 714a, 728a, 714c, and 728 c. The conductive structure layout patterns 1014c, 1028c, 1014b, and 1028b are similar to the corresponding conductive structure layout patterns 714a, 728a, 714c, and 728c, and therefore, similar detailed descriptions of these layout patterns are omitted. The conductive structure layout patterns 1014c, 1028c, 1014b, and 1028b extend in the second direction Y to intersect the first line 702 and the second line 902 into the third portion 904c of the layout design 1000.

Similar to layout design 900, layout design 1000 also includes a third portion 904 c.

The third portion 904c of the layout design 1000 includes a fifth conductive structure layout pattern 906, a rail layout pattern 908b, a sixth conductive structure layout pattern 922, and via layout patterns 1018b, 1024b, 1030b, 1018c, 1024c, and 1030 c.

Via layout patterns 1018b, 1024b, and 1030b are similar to via layout patterns 318a, 324a, and 330a or via layout patterns 718a, 724a, and 730a, and therefore similar detailed descriptions of these layout patterns are omitted. The via layout patterns 1018c, 1024c, and 1030c are similar to the via layout patterns 418c, 424c, and 430c or the via layout patterns 718c, 724c, and 730c, and thus similar detailed descriptions of these layout patterns are omitted.

In some embodiments, by utilizing layout design 1000, a metal mesh configuration configured as three times height, dual input pins is produced. In some embodiments, by utilizing layout design 1000, the number of via layout patterns (e.g., via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, 930c, 1018b, 1024b, 1030b, 1018c, 1024c, and 1030c) is increased, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 418c, 424c, and 430c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 718c, 724c, and 730c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 918c, 924c and 930c are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, via layout patterns 1018b, 1024b, and 1030b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1018c, 1024c, and 1030c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1014b, 1014c of the M1 layer and the corresponding conductive structure layout patterns 1028b, 1028c of the M3 layer are aligned, resulting in a lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 1014b, 1014c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1028b, 1028c of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of the via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, 930c, 1018b, 1024b, 1030b, 1018c, 1024c, and 1030c is a square via layout pattern. In some embodiments, as the number of via layout patterns 418c, 424c, 430c, 718c, 724c, 730c, 918c, 924c, 930c, 1018b, 1024b, 1030b, 1018c, 1024c, 1030c, and the number of conductive structure layout patterns 1014c, 1028c, 1014b, and 1028b increase, a plurality of input pins are provided in the layout design 1000, thereby creating more current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1000 having better speed performance than other approaches.

FIG. 11 is a diagram of a layout design 1100 of an IC structure, according to some embodiments.

In some embodiments, layout design 1100 corresponds to a layout design with dual output pins having a first pin (e.g., conductive structure layout patterns 1114a, 1128a) and a second pin (e.g., conductive structure layout patterns 1114b, 1128 b). Other configurations, locations, or numbers of elements in the layout design 1100 of FIG. 11 are within the scope of the invention.

Layout design 1100 includes other components, which are not shown for ease of illustration. For example, the gate layout pattern group 104 is located on a first layout level (e.g., polysilicon poly).

The layout design 1100 has a width (not shown) in the first direction X and a height H1 in the second direction Y. Layout design 1100 is a standard cell 1101. In some embodiments, standard cell 1101 is a logic gate cell.

The layout design 1100 includes a conductive structure layout pattern 1106a and a conductive structure layout pattern 1106b between the sets of rail layout patterns 108a, 108 b. The conductive structure layout patterns 1106a, 1106b (collectively referred to as "conductive structure layout pattern group 1106" (not shown)) extend in the first direction X and are located at a second layout level (e.g., M0). Each of the conductive structure layout patterns 1106a, 1106b in the conductive structure layout pattern group 1106 is separated from each other in the second direction Y. The conductive structure layout patterns 1106a, 1106B may be used to fabricate respective conductive structures 1206a, 1206B of the IC structure 1200 (as shown in fig. 12A-12B). One or more of the conductive structure layout patterns 1106a, 1106b or the set of guide track layout patterns 108a, 108b are located on the same layout level as one or more other of the conductive structure layout patterns 1106a, 1106b or the set of guide track layout patterns 108a, 108 b.

The conductive structure layout pattern 1106a is separated from the conductive structure layout pattern 1106b by a distance D3 (not shown). The conductive structure layout pattern 1106a is separated from the rail layout pattern 108a by a distance D4 (not shown). The conductive structure layout pattern 1106b is separated from the rail layout pattern 108b by a distance D5 (not shown).

Other configurations or numbers of conductive structure layout patterns 1106a, 1106b or rails in the set of rail layout patterns 108a, 108b are within the scope of the invention.

The layout design 1100 also includes conductive structure layout patterns 1114a, 1114b (collectively referred to as "conductive structure layout pattern groups 1114" (not shown)) that extend in the second direction Y and overlap the conductive structure layout pattern groups 1106. The conductive structure layout patterns 1114a, 1114B may be used to fabricate respective conductive structures 1214a, 1214B of the IC structure 1200 (as shown in fig. 12A-12B). The conductive structure layout pattern group 1114 is located at a third layout level (M1). Each of the conductive structure layout patterns 1114a, 1114b in the conductive structure layout pattern group 1114 is separated from each other in the first direction X. The conductive structure layout pattern 1114a is separated from the conductive structure layout pattern 1114b by a distance D6 (not shown). Other configurations or numbers of conductive structure layout patterns 1114a, 1114b are within the scope of the present invention.

The layout design 1100 also includes via layout patterns 1118a, 1118b, 1118c, 1118d (collectively, "via layout pattern group 1118" (not shown)). Via layout patterns 1118a, 1118B, 1118c, 1118d may be used to fabricate respective via structures 1218a, 1218B, 1218c, 1218d of IC structure 1200 (as shown in fig. 12A-12B). The via layout pattern group 1118 is located between the conductive structure layout pattern group 1114 and the conductive structure layout pattern group 1106. The via layout patterns 1118a and 1118b in the via layout pattern group 1118 are located above the layout pattern 1106a in the conductive structure layout pattern group 1106. The via layout patterns 1118c and 1118d in the via layout pattern group 1118 are located above the layout pattern 1106b in the conductive structure layout pattern group 1106. In some embodiments, each via layout pattern 1118a, 1118b, 1118c, 1118d in the set of via layout patterns 1118 is located at a position where each conductive layout pattern 1114a, 1114b in the set of conductive layout patterns 1114 overlaps each conductive layout pattern 1106a, 1106b in the set of conductive layout patterns 1106.

In some embodiments, the center of one or more via layout patterns 1118a, 1118b in the set of via layout patterns 1118 is located above the center of the layout pattern 1106a in the set of conductive structure layout patterns 1106. In some embodiments, the center of one or more via layout patterns 1118c, 1118d in the set of via layout patterns 1118 is located above the center of the layout pattern 1106b in the set of conductive structure layout patterns 1106. In some embodiments, the centers of the via layout patterns in the via layout pattern group 1118 are aligned with the centers of the layout patterns in the conductive structure layout pattern group 1106 in the first direction X or in the second direction Y. The via layout pattern group 1118 is located at the V0 layout level between the second layout level and the third layout level of the layout design 1100. Other configurations of the via layout pattern group 1118 are within the scope of the invention.

The layout design 1100 also includes conductive structure layout patterns 1122a, 1122b between the sets of rail layout patterns 108a, 108 b. The conductive structure layout patterns 1122a, 1122b (collectively referred to as "conductive structure layout pattern groups 1122 (not shown)) extend in the first direction X and are located at a fourth layout level (e.g., M2). Each of the conductive structure layout patterns 1122a, 1122b in the conductive structure layout pattern group 1122 is separated from each other in the second direction Y. Conductive structure layout patterns 1122A, 1122B may be used to fabricate respective conductive structures 1222A, 1222B of IC structure 1200 (as shown in fig. 12A-12B). The conductive layout pattern group 1122 overlaps with the conductive layout pattern group 1114. In some embodiments, the conductive structures 1122a, 1122b in the conductive structure layout pattern group 1122 cover at least a portion of the respective conductive structures 1106a, 1106b of the conductive structure layout pattern group 1106. In some embodiments, one side of the conductive structures 1122a, 1122b of the conductive structure layout pattern group 1122 is aligned with a respective side of the respective conductive structure layout pattern 1106a, 1106b of the conductive structure layout pattern group 1106, at least in the first direction X or the second direction Y.

Conductive structure layout pattern 1122a is separated from conductive structure layout pattern 1122b by a distance D3' (not shown). The conductive structure layout pattern 1122a is separated from the guide rail layout pattern 108a by a distance D4' (not shown). The conductive structure layout pattern 1122b is separated from the guide rail layout pattern 108b by a distance D5' (not shown).

In some embodiments, one or more of the conductive structure layout pattern groups 1106, 1122 has a different length (not shown) in the first direction X than the other of the conductive structure layout pattern groups 1106, 1122. In some embodiments, one or more layout patterns of the set of conductive structure layout patterns 1106, 1122 have the same length (not shown) in the first direction X as the other layout pattern of the set of conductive structure layout patterns 1106, 1122.

In some embodiments, one or more of the conductive structure layout pattern groups 1106, 1122 has a different width (not shown) in the second direction Y than the other of the conductive structure layout pattern groups 1106, 1122. In some embodiments, one or more of the conductive structure layout pattern groups 1106, 1122 has the same width (not shown) in the second direction Y as the other of the conductive structure layout pattern groups 1106, 1122.

Other configurations or numbers of conductive structure layout patterns 1122a, 1122b are within the scope of the present invention.

Layout design 1100 also includes via layout patterns 1124a, 1124b, 1124c, 1124d (collectively "via layout pattern group 1124" (not shown)). The via layout patterns 1124a, 1124B, 1124c, 1124d may be used to fabricate corresponding via structures 1224a, 1224B, 1224c, 1224d of the IC structure 1200 (as shown in fig. 12A-12B). Via layout pattern group 1124 is located between conductive structure layout pattern group 1122 and conductive structure layout pattern group 1114. The set of via layout patterns 1124 is located above the set of conductive structure layout patterns 1114. In some embodiments, each via layout pattern 1124a, 1124b, 1124c, 1124d in the set of via layout patterns 1124 is located at a position where each conductive structure layout pattern 1122a, 1122b in the set of conductive structure layout patterns 1122 overlaps each conductive structure layout pattern 1114a, 1114b in the set of conductive structure layout patterns 1114.

In some embodiments, the center of one or more via layout patterns 1124a, 1124c in the via layout pattern group 1124 is located above the center of the layout pattern 1114a in the conductive structure layout pattern group 1114. In some embodiments, the center of one or more via layout patterns 1124b, 1124d in the via layout pattern group 1124 is located above the center of the layout pattern 1114b of the conductive structure layout pattern group 1114. In some embodiments, the centers of the via layout patterns in the via layout pattern group 1124 are aligned with the centers of the layout patterns in the conductive structure layout pattern group 1114 in the first direction X or in the second direction Y. The via layout pattern group 1124 is located at the V1 layout level between the third layout level and the fourth layout level of the layout design 1100. Other configurations of the via layout pattern group 1124 are within the scope of the present invention.

The layout design 1100 also includes conductive structure layout patterns 1128a, 1128b (collectively referred to as "conductive structure layout pattern group 1128" (not shown)) extending in the second direction Y and located on a fifth layout level (e.g., M3). Each of the conductive structure layout patterns 1128a, 1128b in the conductive structure layout pattern group 1128 is separated from each other in the first direction X. The conductive structure layout patterns 1128a, 1128B may be used to fabricate corresponding conductive structures 1228a, 1228B of the IC structure 1200 (as shown in fig. 12A-12B). The conductive structure layout pattern group 1128 overlaps with the conductive structure layout pattern groups 1106 and 1122. In some embodiments, the conductive structure layout patterns 1128a, 1128b in the set of conductive structure layout patterns 1128 at least cover portions of the respective conductive structure layout patterns 1114a, 1114b in the set of conductive structure layout patterns 1114. In some embodiments, one side of the conductive structure layout patterns 1128a, 1128b in the set of conductive structure layout patterns 1128 is aligned with a corresponding side of the corresponding conductive structure layout patterns 1114a, 1114b in the set of conductive structure layout patterns 1114, at least in the first direction X or the second direction Y.

The conductive structure layout pattern 1128a is separated from the conductive structure layout pattern 1128b by a distance D6' (not shown).

In some embodiments, one or more of the set of conductive structure layout patterns 1114, 1128 has a different length (not shown) in the first direction X than the other of the set of conductive structure layout patterns 1114, 1128. In some embodiments, one or more of the set of conductive structure layout patterns 1114, 1128 has the same length in the first direction X as the other of the set of conductive structure layout patterns 1114, 1128 (not shown).

In some embodiments, one or more of the set of conductive structure layout patterns 1114, 1128 has a different width (not shown) in the second direction Y than the other of the set of conductive structure layout patterns 1114, 1128. In some embodiments, one or more of the set of conductive structure layout patterns 1114, 1128 has the same width in the second direction Y as the other of the set of conductive structure layout patterns 1114, 1128 (not shown).

Other configurations or numbers of conductive structure layout patterns 1128a, 1128b are within the scope of the invention.

The layout design 1100 also includes via layout patterns 1130a, 1130b, 1130c, 1130d (collectively referred to as "via layout pattern group 1130" (not shown)). The via layout patterns 1130a, 1130B, 1130c, 1130d may be used to fabricate the corresponding via structures 1230a, 1230B, 1230c, 1230d of the IC structure 1200 (shown in fig. 12A-12B). The via layout pattern group 1130 is located between the conductive structure layout pattern group 1128 and the conductive structure layout pattern group 1122. The via layout patterns 1130a and 1130b in the via layout pattern group 1130 are located above the layout pattern 1122a in the conductive structure layout pattern group 1122. The via layout patterns 1130c and 1130d of the via layout pattern group 1130 are located above the layout pattern 1122b of the conductive structure layout pattern group 1122. In some embodiments, each via layout pattern 1130a, 1130b, 1130c, 1130d in the via layout pattern group 1130 is located at a position where each conductive structure layout pattern 1128a, 1128b in the conductive structure layout pattern group 1128 overlaps each conductive structure layout pattern 1122a, 1122b in the conductive structure layout pattern group 1122.

In some embodiments, the center of one or more via layout patterns 1130a, 1130b in the via layout pattern group 1130 is located at the center of the layout pattern 1106a in the conductive structure layout pattern group 1106 or above the center of the layout pattern 1122a in the conductive structure layout pattern group 1122. In some embodiments, the center of one or more via layout patterns 1130c, 1130d in the via layout pattern group 1130 is located at the center of the layout pattern 1106b in the conductive structure layout pattern group 1106 or above the center of the layout pattern 1122b in the conductive structure layout pattern group 1122. In some embodiments, the centers of the via layout patterns in the via layout pattern group 1130 are aligned with the centers of the layout patterns in the conductive structure layout pattern group 1106 or 1122 in the first direction X or in the second direction Y. The via layout pattern group 1130 is located at the V2 layout level between the fourth layout level and the fifth layout level of the layout design 1100. Other configurations of the via layout pattern group 1130 are within the scope of the present invention.

In some embodiments, a center of at least one via layout pattern of the set of via layout patterns 1118, 1124, 1130 is aligned with a center of at least another via layout pattern of the set of via layout patterns 1118, 1124, 1130 in the first direction X or the second direction Y. In some embodiments, the via layout pattern groups 1118, 1124, 1130 are referred to as a stacked via configuration because the center of each via is aligned with the center of at least another via layout pattern of the via layout pattern groups 1118, 1124, 1130 on another layer in the first direction X and the second direction Y. In some embodiments, by using a stacked via configuration, the resistance is reduced compared to other approaches.

In some embodiments, because layout design 1100 occupies 2M 2 routing tracks (e.g., conductive structure layout patterns 1122a and 1122b), more routing resources are provided to reach upper metal layers (e.g., metal 3, metal 4, etc.) than other methods. In some embodiments, a metal mesh structure (e.g., integrated circuit 1200) configured as dual output pins is created by utilizing at least the conductive structure layout pattern 1106a, 1106b, 1114a, 1114b, 1122a, 1122b, 1128a, or 1128b and the via layout pattern 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130 d. In some embodiments, the set of conductive structure layout patterns 1106 of the M0 layer occupies two M0 routing tracks, and the set of conductive structure layout patterns 1122 of the M2 layer occupies two M2 routing tracks.

In some embodiments, by utilizing layout design 1100, the number of via layout patterns (e.g., via layout pattern groups 1118, 1124, and 1130) is increased, creating more connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, via layout pattern group 1118, via layout pattern group 1124, and via layout pattern group 1130 are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, each layout pattern of via layout pattern group 1118, via layout pattern group 1124, and via layout pattern group 1130 has a 4-square via layout pattern.

In some embodiments, the set of conductive structure layout patterns 1114 of the M1 layer and the set of conductive structure layout patterns 1128 of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the set of conductive structure layout patterns 1114 of the M1 layer and the set of conductive structure layout patterns 1128 of the M3 layer use two or more 1W M1 or two M3 routing tracks, resulting in lower resistance than other methods. In some embodiments, as the number of via layout patterns in each of via layout pattern group 1118, via layout pattern group 1124, and via layout pattern group 1130 increases, and the number of conductive structure layout patterns in conductive structure layout pattern group 1114 and conductive structure layout pattern group 1128 increases, multiple output pins are provided in layout design 1100, resulting in multiple current paths being created between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in a layout design 1100 with better speed performance than other approaches.

Fig. 12A and 12B are diagrams of an IC structure 1200 according to some embodiments. Fig. 12A is a cross-sectional view of an IC structure 1200 corresponding to a layout design 1100 that intersects a plane a-a 'according to some embodiments, and fig. 12B is a cross-sectional view of an IC structure 1200 corresponding to a layout design 1100 that intersects a plane B-B' according to some embodiments. The IC structure 1200 is fabricated from the layout design 1100.

The structural relationships, including alignment, length, and width, and the construction of the IC structure 1200 are similar to those of the layout design 1100 of fig. 11 and will not be described in fig. 12A-12B for the sake of brevity.

IC structure 1200 includes other components not shown for ease of illustration. For example, a set of gates similar to the integrated circuit 204 on a first level of the IC structure 200.

The IC structure 1200 includes conductive structures 1206a, 1206b (collectively referred to as "conductive structure groups 1206" (not shown)) extending in a first direction X and separated from each other in a second direction Y.

IC structure 1200 also includes sets of rails 1208a, 1208b that extend in first direction X. Conductive structure set 1206 is positioned between rail sets 1208a, 1208 b. Conductive structure groups 1206 and rail groups 1208a, 1208b are located on a second level of the IC structure 1200. One or more of the conductive structures 1206a, 1206b or the sets of rails 1208a, 1208b are located on a second level (M0) of the IC structure 1200. The second level of the IC structure 1200 is above the first level of the IC structure 1200. Other numbers of conductive structures 1206a, 1206b or sets of rails 1208a, 1208b are within the scope of the invention.

In some embodiments, the rail sets 1208a, 1208b are configured to provide either the first supply voltage VDD or the second supply voltage VSS to the IC structure 1200. In some embodiments, the sets of rails 1208a, 1208b are electrically connected to the conductive structures 1206a, 1206b (not shown).

In some embodiments, the set of conductive structures 1206 is electrically connected to one or more drains or sources of transistor devices (not shown).

The IC structure 1200 further includes a set of conductive structures 1214 extending in the second direction Y and overlapping the set of conductive structures 1206. The set of conductive structures includes conductive structures 1214a and 1214 b. Each conductive structure 1214a, 1214b in the set of conductive structures is separated from each other in the first direction X.

The conductive structures 1214a, 1214b are located on a third level (M1) of the IC structure 1200. The third level of the IC structure 1200 is located above the first level and the second level of the IC structure 1200. Other numbers or configurations of conductive structures 1214a, 1214b are within the scope of the present invention.

The IC structure 1200 also includes a set of vias 1218 between the conductive structures 1214a, 1214b and the conductive structures 1206a, 1206 b. Via group 1218 includes one or more of vias 1218a, 1218b, 1218c, 1218 d. Each via 1218a, 1218b, 1218c, 1218d in the set of vias 1218 is located beneath a conductive structure 1214a, 1214b in the set of conductive structures 1214.

Each via 1218a, 1218b, 1218c, 1218d in the set of vias 1218 is located where the set of conductive structures 1214 overlaps the set of conductive structures 1206. The set of vias 1218 electrically connects the set of conductive structures 1214 to the set of conductive structures 1206. One or more vias 1218a, 1218b, 1218c, 1218d in the set of vias 1218 are located at the V0 level of the IC structure 1200. The V0 level of the IC structure 1200 is located above the first level and the second level of the IC structure 1200. Other numbers of vias or other configurations of the set 1218 of vias are within the scope of the invention.

The IC structure 1200 also includes conductive structures 1222a, 1222b (collectively "conductive structure groups 1222" (not shown)) that extend in the first direction X and overlap the conductive structure groups 1214. Each conductive structure 1222a, 1222b of the conductive structure group 1222 is separated from each other in the second direction Y.

Conductive structure group 1222 is positioned between rail groups 1208a, 1208 b. In some embodiments, the conductive structures 1222a, 1222b in the set of conductive structures 1222 overlap at least a portion of the respective conductive structure 1206a, 1206b in the set of conductive structures 1206. In some embodiments, one side of the conductive structures 1222a, 1222b of the group of conductive structures 1222 is aligned with one side of a respective conductive structure 1206a, 1206b of the group of conductive structures 1206 at least in the first direction X or the second direction Y, the group of conductive structures 1222 being located on a fourth level (M2) of the IC structure 1200. The fourth level of the IC structure 1200 is above the first, second, and third levels of the IC structure 1200. Other numbers or configurations of conductive structure groups 1222 are within the scope of the present invention.

IC structure 1200 also includes a set of vias 1224 located between the set of conductive structures 1222 and the set of conductive structures 1214. The set of vias 1224 includes one or more of the vias 1224a, 1224b, 1224c, 1224 d.

Vias 1224a, 1224c of the set of vias 1224 are located over conductive structures 1214a of the set of conductive structures 1214. Vias 1224b, 1224d of the set of vias 1224 are located over conductive structures 1214b of the set of conductive structures 1214. Each via 1224a, 1224b, 1224c, 1224d of the set of vias 1224 is located where the set of conductive structures 1222 overlaps the set of conductive structures 1214. The set of vias 1224 electrically connects the set of conductive structures 1222 to the set of conductive structures 1214. One or more vias 1224a, 1224b, 1224c, 1224d of the set of vias 1224 are located at the V1 level of the IC structure 1200. The V1 level of the IC structure 1200 is located above the first, second, and third levels of the IC structure 1200. Other numbers of vias or other configurations of the via sets 1224 are within the scope of the invention.

IC structure 1200 also includes a set of conductive structures 1228 extending in second direction Y and overlapping set of conductive structures 1222 and set of conductive structures 1206. Conductive structure group 1228 includes conductive structures 1228a and 1228 b. Each of the conductive structures 1228a, 1228b in the set of conductive structures 1228 is separated from each other in the first direction X.

A set of conductive structures 1228 is positioned between the sets of rails 1208a, 1208 b. In some embodiments, the conductive structures 1228a, 1228b in the set of conductive structures 1228 cover at least a portion of the respective conductive structures 1214a, 1214b in the set of conductive structures 1214. In some embodiments, at least one side of the conductive structures 1228a, 1228b in the set of conductive structures 1228 is aligned with a side of a respective conductive structure 1214a, 1214b in the set of conductive structures 1214, at least in the first direction X or the second direction Y, the set of conductive structures 1228 being located on a fifth level (M3) of the IC structure 1200. The fifth level of the IC structure 1200 is above the first level, the second level, the third level, and the fourth level of the IC structure 1200.

In some embodiments, at least two of the conductive structures 1214a, 1214b, 1228a, and 1228b have the same length in the second direction Y (not shown). In some embodiments, at least two of the conductive structures 1214a, 1214b, 1228a, and 1228b have different lengths in the second direction Y (not shown). In some embodiments, at least two of the conductive structures 1214a, 1214b, 1228a, and 1228b have the same width (not shown) in the first direction Y. In some embodiments, at least two of the conductive structures 1214a, 1214b, 1228a, and 1228b have different widths (not shown) in the first direction X.

Other numbers of conductive structures and other configurations of the set of conductive structures 1228 are within the scope of the invention.

IC structure 1200 also includes a set of vias 1230 located between the set of conductive structures 1228 and the set of conductive structures 1222. The set of vias 1230 includes one or more of the vias 1230a, 1230b, 1230c, 1230 d.

The vias 1230a, 1230b in the set of vias 1230 are positioned over the conductive structures 1222a in the set of conductive structures 1222. The vias 1230c, 1230d in the set of vias 1230 are located over the conductive structures 1222b in the set of conductive structures 1222. Each via 1230a, 1230b, 1230c, 1230d in the set of vias 1230 is located where the set of conductive structures 1228 overlaps the set of conductive structures 1222. The set of vias 1230 electrically connect the set of conductive structures 1228 to the set of conductive structures 1222. One or more vias 1230a, 1230b, 1230c, 1230d of the set of vias 1230 are located on the V2 level of the IC structure 1200. The V2 level of the IC structure 1200 is located above the first, second, third, and fourth levels of the IC structure 1200. Other numbers of vias or other configurations of sets of vias 1230 are within the scope of the invention.

In some embodiments, one or more of conductive structure group 1206, via group 1218, conductive structure group 1214, via group 1224, conductive structure group 1222, via group 1230, and conductive structure group 1228 is referred to as an output pin. In some embodiments, the output pin is electrically connected to an output side (e.g., drain or source) of one or more transistor devices (not shown). In some embodiments, the output pins are also referred to as metal mesh structures. In some embodiments, the output pins of IC structure 1200 are referred to as dual output pins because conductive structure group 1214 or conductive structure group 1228 has two conductive structures (e.g., conductive structures 1214a, 1214b or conductive structures 1228a, 1228 b). In some embodiments, the positions of the elements in the IC structure 1200 may be adjusted to be located at other positions, and the number of elements in the IC structure 1200 may be adjusted to other numbers. Other configurations, locations, or numbers of elements in the IC structure 1200 of fig. 12A and 12B are within the scope of the invention.

In some embodiments, the set of vias 1218, 1224, 1230 are referred to as a stacked via configuration because the center of each via is aligned in the first direction X or the second direction Y with the center of at least another via in the set of vias 1218, 1224, 1230 on another layer. In some embodiments, the IC structure 1200 has a lower resistance than other approaches due to the stacked via configuration. In some embodiments, as the number of vias 1218a, 1218b, 1224a, 1224b, 1230a, and 1230b increases and the number of conductive structures 1214a, 1214b, 1222a, 1222b, 1228a, and 1228b increases, multiple output pins are provided in the integrated circuit 1200, creating multiple current paths between the lower and upper conductive structures (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in integrated circuit 1200 having better speed performance than other approaches.

Fig. 13 is a diagram of a layout design 1300 of an IC structure according to some embodiments. Components identical or similar to those in fig. 1, 3 to 10, 11 to 19 (shown below), and 20A to 30 (shown below) have the same reference numerals, and thus detailed descriptions thereof are omitted. Other configurations of the via layout pattern or the conductive structure layout pattern of fig. 11 and 13-19 are within the scope of the invention.

Layout design 1300 is a variation of layout design 1100 of FIG. 11. In some embodiments, the layout design 1300 corresponds to a layout design for a three-output pin having a first pin (e.g., conductive structure layout patterns 1114a, 1128a), a second pin (e.g., conductive structure layout patterns 1114b, 1128b), and a third pin (e.g., conductive structure layout patterns 1314c, 1328 c). In some embodiments, layout design 1300 shows that the component locations of the three output pins can be adjusted to be located at other locations, and the component number of the three output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1300 of fig. 13 are within the scope of the invention.

In contrast to layout design 1100 of fig. 11, layout design 1300 also includes a conductive structure layout pattern 1314c between conductive structure layout patterns 1114a and 1114b, and a conductive structure layout pattern 1328c between conductive structure layout patterns 1128a and 1128 b. The conductive structure layout patterns 1314c, 1328c are similar to the corresponding conductive structure layout patterns 1114a, 1128a, and therefore similar detailed descriptions of these layout patterns are omitted.

In comparison with the layout design 1100 of fig. 11, the layout design 1300 further includes layout patterns 1318e, 1324e, 1330e, 1318f, 1324f, and 1330f that are similar to the respective via layout patterns 1118a, 1124a, 1130a, 1118c, 1124c, and 1130c, and thus a similar detailed description of these layout patterns is omitted.

Each of via layout patterns 1318e, 1324e, and 1330e is positioned between a respective via layout pattern 1118a, 1124a, 1130a and a respective via layout pattern 1118b, 1124b, and 1130 b. Each of via layout patterns 1318f, 1324f, and 1330f is located between a respective via layout pattern 1118c, 1124c, 1130c and a respective via layout pattern 1118d, 1124d, and 1130 d.

In some embodiments, by utilizing layout design 1300, a metal mesh configured as a three output pin is created. In some embodiments, by utilizing layout design 1300, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, and 1330f) is increased, resulting in multiple connections between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118a, 1124a, and 1130a are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118b, 1124b, and 1130b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118c, 1124c, and 1130c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118d, 1124d, and 1130d are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318e, 1324e, and 1330e are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318f, 1324f, and 1330f are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c of the M1 layer are aligned with the corresponding conductive structure layout patterns 1128a, 1128b, 1328c of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1128a, 1128b, 1328c of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, and 1330f are square via layout patterns. In some embodiments, as the number of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, and 1330f increases and the number of conductive structure layout patterns 1114a, 1114b, 1314c, 1128a, 1128b, 1328c increases, multiple output pins are provided in layout design 1300, creating multiple current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1300 having better speed performance than other approaches.

Fig. 14 is a diagram of a layout design 1400 of an IC structure according to some embodiments.

Layout design 1400 is a variation of layout design 1300 of FIG. 13. In some embodiments, the layout design 1400 corresponds to a layout design for four output pins having a first pin (e.g., conductive structure layout patterns 1114a, 1128a), a second pin (e.g., conductive structure layout patterns 1114b, 1128b), a third pin (e.g., conductive structure layout patterns 1314c, 1328c), and a fourth pin (e.g., conductive structure layout patterns 1414d, 1428 d). In some embodiments, layout design 1400 shows that the component locations of the four output pins can be adjusted to be located at other locations, and the component number of the four output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1400 of FIG. 14 are within the scope of the present invention.

In contrast to layout design 1300 of fig. 13, layout design 1400 further includes a conductive structure layout pattern 1414d between conductive structure layout patterns 1314c and 1114b, and a conductive structure layout pattern 1428d between conductive structure layout patterns 1328c and 1128 b. The conductive structure layout patterns 1414d, 1428d are similar to the corresponding conductive structure layout patterns 1114a, 1128a, and therefore similar detailed descriptions of these layout patterns are omitted.

In comparison with the layout design 1300 of fig. 13, the layout design 1400 further includes via layout patterns 1418g, 1424g, 1430g, 1418h, 1424h, and 1430h that are similar to the respective via layout patterns 1118a, 1124a, 1130a, 1118c, 1124c, and 1130c, and thus similar detailed descriptions of these layout patterns are omitted.

Each of via layout patterns 1418g, 1424g, and 1430g is positioned between a respective via layout pattern 1318e, 1324e, and 1330e and a respective via layout pattern 1118b, 1124b, and 1130 b. Each of via layout patterns 1418h, 1424h, and 1430h is positioned between a respective via layout pattern 1318f, 1324f, and 1330f and a respective via layout pattern 1118d, 1124d, and 1130 d.

In some embodiments, by utilizing layout design 1400, a metal mesh configuration configured as four output pins is created. In some embodiments, by utilizing layout design 1400, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, and 1430h) is increased, resulting in multiple connections between lower and upper conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118a, 1124a, and 1130a are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118b, 1124b, and 1130b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118c, 1124c, and 1130c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118d, 1124d, and 1130d are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318e, 1324e, and 1330e are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318f, 1324f, and 1330f are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 1418g, 1424g, and 1430g are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 1418h, 1424h, and 1430h are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d of the M1 layer are aligned with the corresponding conductive structure layout patterns 1128a, 1128b, 1328c, 1428d of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1128a, 1128b, 1328c, 1428d of the M3 layer each use one M3 routing track, resulting in lower resistance than other approaches. In some embodiments, one or more of the via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, and 1430h are square via layout patterns. In some embodiments, as the number of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, and 1430h increases and the number of conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1128a, 1128b, 1328c, 1428d increases, more output pins are provided in layout design 1400, creating multiple current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1400 having better speed performance than other approaches.

Fig. 15 is a diagram of a layout design 1400 of an IC structure according to some embodiments.

Layout design 1500 is a variation of layout design 1400 of FIG. 14. In some embodiments, the layout design 1500 corresponds to a layout design for a five-output pin having a first pin (e.g., conductive structure layout pattern 1114a, 1128a), a second pin (e.g., conductive structure layout pattern 1114b, 1128b), a third pin (e.g., conductive structure layout pattern 1314c, 1328c), a fourth pin (e.g., conductive structure layout pattern 1414d, 1428d), and a fifth pin (e.g., conductive structure layout pattern 1514e, 1528 e). In some embodiments, layout design 1500 shows that the component locations for the five output pins can be adjusted to be located at other locations, and the component count for the five output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1500 of FIG. 15 are within the scope of the invention.

In contrast to the layout design 1400 of fig. 14, the layout design 1500 further includes a conductive structure layout pattern 1514e between the conductive structure layout patterns 1314c and 1414d, and a conductive structure layout pattern 1528e between the conductive structure layout patterns 1328c and 1428 d. The conductive structure layout patterns 1514e, 1528e are similar to the corresponding conductive structure layout patterns 1114a, 1128a, and therefore similar detailed descriptions of these layout patterns are omitted.

In comparison with the layout design 1400 of fig. 14, the layout design 1500 further includes via layout patterns 1518i, 1524i, 1530i, 1518j, 1524j, and 1530j that are similar to the respective via layout patterns 1118a, 1124a, 1130a, 1118c, 1124c, and 1130c, and thus similar detailed descriptions of these layout patterns are omitted.

Each of the via layout patterns 1518i, 1524i, and 1530i is positioned between a corresponding via layout pattern 1318e, 1324e, and 1330e and a corresponding via layout pattern 1418g, 1424g, and 1430 g. Each of the via layout patterns 1518j, 1524j, and 1530j is positioned between a corresponding via layout pattern 1318f, 1324f, and 1330f and a corresponding via layout pattern 1418h, 1424h, and 1430 h.

In some embodiments, by utilizing layout design 1500, a metal mesh configured as five output pins is created. In some embodiments, by utilizing layout design 1500, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, 1430h, 1518i, 1518j, 1524i, 1524j, 1530i, and 1530j) is increased, resulting in multiple connections between lower and upper conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118a, 1124a, and 1130a are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118b, 1124b, and 1130b are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118c, 1124c, and 1130c are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1118d, 1124d, and 1130d are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318e, 1324e, and 1330e are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, via layout patterns 1318f, 1324f, and 1330f are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the via layout patterns 1418g, 1424g, and 1430g are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 1418h, 1424h, and 1430h are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 1518i, 1524i, and 1530i are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the via layout patterns 1518j, 1524j, and 1530j are aligned in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e of the M1 layer are aligned with the corresponding conductive structure layout patterns 1128a, 1128b, 1328c, 1428d, 1528e of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e of the M1 layer all use a 1W M1 routing track, and the conductive structure layout patterns 1128a, 1128b, 1328c, 1428d, 1528e of the M3 layer all use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, 1430h, 1518i, 1518j, 1524i, 1524j, 1530i, and 1530j is a square via layout pattern. In some embodiments, as the number of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, 1430h, 1518i, 1518j, 1524i, 1524j, 1530i, and 1530j increases and the number of conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e, 1128a, 1128b, 1328c, 1428d, 1528e increases, a plurality of output pins are provided in the layout design 1500, creating a plurality of current paths between lower and upper conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1500 having better speed performance than other approaches.

FIG. 16 is a diagram of a layout design 1600 of an IC structure, according to some embodiments.

Layout design 1600 is a variation of layout design 1500 of FIG. 15. In some embodiments, the layout design 1600 corresponds to a layout design for a six output pin having a first pin (e.g., conductive structure layout pattern 1114a, 1128a), a second pin (e.g., conductive structure layout pattern 1114b, 1128b), a third pin (e.g., conductive structure layout pattern 1314c, 1328c), a fourth pin (e.g., conductive structure layout pattern 1414d, 1428d), a fifth pin (e.g., conductive structure layout pattern 1514e, 1528e), and a sixth pin (e.g., conductive structure layout pattern 1614f, 1628 f). In some embodiments, layout design 1600 shows that the component locations for the six output pins can be adjusted to be located at other locations, and the component number for the six output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in layout design 1600 of FIG. 16 are within the scope of the present invention.

In contrast to layout design 1500 of fig. 15, layout design 1600 also includes a conductive structure layout pattern 1614f located between conductive structure layout patterns 1314c and 1514e, and a conductive structure layout pattern 1628f located between conductive structure layout patterns 1328c and 1528 e. The conductive structure layout patterns 1614f, 1628f are similar to the corresponding conductive structure layout patterns 1114a, 1128a, and therefore similar detailed descriptions of these layout patterns are omitted.

In comparison with the layout design 1500 of fig. 15, the layout design 1600 also includes via layout patterns 1618k, 1624k, 1630k, 1618l, 1624l, and 1630l that are similar to the respective via layout patterns 1118a, 1124a, 1130a, 1118c, 1124c, and 1130c, and thus similar detailed descriptions of these layout patterns are omitted.

Each of the via layout patterns 1618k, 1624k, and 1630k is positioned between a respective via layout pattern 1318e, 1324e, and 1330e and a respective via layout pattern 1518i, 1524i, and 1530 i. Each of the via layout patterns 1618l, 1624l, and 1630l is positioned between a corresponding via layout pattern 1318f, 1324f, and 1330f and a corresponding via layout pattern 1518j, 1524j, and 1530 j.

In some embodiments, by utilizing layout design 1600, a metal mesh configuration configured as six output pins is created. In some embodiments, by utilizing layout design 1600, via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, 1430h, 1518i, 1518j, 1524i, 1524j, 1530i, and 1530j, 1618k, 1618l, 1624k, 1624l, 1630k, and 1630l are increased in number resulting in multiple connections between underlying and overlying conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than in some embodiments, via layout patterns 1618k, 1624k, and 1630k are aligned in stacked via configurations, resulting in lower resistance than in some embodiments, the via layout patterns 1618l, 1624l, and 1630l are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e, 1614f of the M1 layer are aligned with the corresponding conductive structure layout patterns 1128a, 1128b, 1328c, 1428d, 1528e, 1628f of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e, 1614f of the M1 layer all use a 1W M1 routing track, and the conductive structure layout patterns 1128a, 1128b, 1328c, 1428d, 1528e, 1628f of the M3 layer all use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 1618k, 1618l, 1624k, 1624l, 1630k, and 1630l are square via layout patterns. In some embodiments, as the number of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, 1330f, 1418g, 1418h, 1424g, 1424h, 1430g, 1430h, 1518i, 1518j, 1524i, 1524j, 1530i, 1530j, 1618k, 1618l, 1624k, 1624l, 1630k, and 1630l increases and the number of conductive structure layout patterns 1114a, 1114b, 1314c, 1414d, 1514e, 1614f, 1128a, 1128b, 1328c, 1428d, 1528e, 1628f increases, a plurality of output pins are provided in the layout design 1600, creating a plurality of current paths between the lower and upper conductive features (e.g., metal layers M0, M6326, 3683, 3M, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1600 having better speed performance than other approaches.

Fig. 17 is a diagram of a layout design 1700 of an IC structure, according to some embodiments.

Layout design 1700 is a variation of layout design 1300 of FIG. 13. Height H2 of layout design 1700 is twice height H1 of one or more of layout designs 1100 and 1300-1600. In some embodiments, layout design 1700 corresponds to a double-height, triple-output pin layout design with a first pin (e.g., conductive structure layout patterns 1714a, 1728a), a second pin (e.g., conductive structure layout patterns 1714b, 1728b), and a third pin (e.g., conductive structure layout patterns 1714c, 1728 c). In some embodiments, layout design 1700 shows that the component locations for the double height, three output pins can be adjusted to be located at other locations, and the component count for the double height, three output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1700 of FIG. 17 are within the scope of the invention.

In contrast to layout design 1300 of FIG. 13, layout design 1700 includes a first portion 1704a and a second portion 1704 b. The first portion 1704a is a mirror image of the second portion 1704b relative to the first line 1702. In some embodiments, first portion 1704a is not a mirror image of second portion 1704b relative to first line 1702. Layout design 1700 is symmetric with respect to first line 1702.

The first portion 1704a includes layout patterns as described in the layout pattern 1300 of fig. 13, and thus similar detailed descriptions of these layout patterns are omitted.

The second portion 1704b includes a conductive structure layout pattern 1706a, a conductive structure layout pattern 1706b, a rail layout pattern 1708a, a conductive structure layout pattern 1722b, and via layout patterns 1718a, 1724a, 1730a, 1718b, 1724b, 1730b, 1718c, 1724c, 1730c, 1718d, 1724d, 1730d, 1718e, 1724e, 1730e, 1718f, 1724f, and 1730 f.

In comparison to layout design 1300 of FIG. 13, conductive structure layout patterns 1714a, 1728a, 1714b, 1728b, 1714c, and 1728c of layout design 1700 replace respective conductive structure layout patterns 1114a, 1128a, 1114b, 1128b, 1314c, and 1328 c. The conductive structure layout patterns 1714a, 1728a, 1714b, 1728b, 1714c, and 1728c are similar to the corresponding conductive structure layout patterns 1114a, 1128a, 1114b, 1128b, 1314c, and 1328c, and thus similar detailed descriptions of these layout patterns are omitted.

Conductive structure layout patterns 1714a, 1728a, 1714b, 1728b, 1714c, and 1728c extend in second direction Y to intersect first line 1702, entering second portion 1704b of layout design 1700.

The layout patterns in the second portion 1704b are similar to the corresponding layout patterns in the first portion 1704a, and therefore similar detailed descriptions of these layout patterns are omitted.

The via layout patterns 1718a, 1724a, 1730a, 1718b, 1724b, 1730b, 1718c, 1724c, 1730c, 1718d, 1724d, 1730d, 1718e, 1724e, 1730e, 1718f, 1724f, and 1730f are similar to the corresponding via layout patterns 1118a, 1124a, 1130a, 1118b, 1124b, 1130b, 1118c, 1124c, 1130c, 1118d, 1124d, 1130d, 1318e, 1324e, 131e, 1318f, 1324f, and 1330f, and thus similar detailed descriptions of these layout patterns are omitted.

The conductive structure layout patterns 1706a, 1706b, 1722a, 1722b are similar to the corresponding conductive structure layout patterns 1106a, 1106b, 1122a, 1122b, and thus a similar detailed description of these layout patterns is omitted.

The rail layout pattern 1708a is similar to the rail layout pattern 108a, and thus a similar detailed description of these layout patterns is omitted.

In some embodiments, by utilizing layout design 1700, a metal mesh configuration configured as double-height, triple-output pins is created. In some embodiments, by utilizing layout design 1700, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1318e, 1318f, 1324e, 1324f, 1330e, and 1330f, 1718a, 1718b, 1718c, 1718d, 1718e, 1718f, 1724a, 1724b, 1724c, 1724d, 1724e, 1724f, 1730a, 1730b, 1730c, 1730d, 1730e, and 1730f) is increased, resulting in more connections between the underlying and overlying conductive feature layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in a lower resistance than other methods. In some embodiments, one or more of via layout patterns 1718a, 1724a, and 1730a, or via layout patterns 1718b, 1724b, and 1730b, or via layout patterns 1718c, 1724c, and 1730c, or via layout patterns 1718d, 1724d, and 1730d, or via layout patterns 1718e, 1724e, and 1730e, or via layout patterns 1718f, 1724f, and 1730f are aligned in a stacked via configuration, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1714a, 1714b, 1714c of the M1 layer and the corresponding conductive structure layout patterns 1728a, 1728b, 1728c of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1714a, 1714b, 1714c of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1728a, 1728b, 1728c of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 1718a, 1718b, 1718c, 1718d, 1718e, 1718f, 1724a, 1724b, 1724c, 1724d, 1724e, 1724f, 1730a, 1730b, 1730c, 1730d, 1730e, and 1730f is a square via layout pattern. In some embodiments, as the number of via layout patterns 1718a, 1718b, 1718c, 1718d, 1718e, 1718f, 1724a, 1724b, 1724c, 1724d, 1724e, 1724f, 1730a, 1730b, 1730c, 1730d, 1730e, and 1730f increases and the number of conductive structure layout patterns 1714a, 1714b, 1714c, 1728a, 1728b, 1728c increases, a plurality of output pins are provided in layout design 1700, creating a plurality of current paths between the underlying and overlying conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1700 having better speed performance than other approaches.

FIG. 18 is a diagram of a layout design 1800 of an IC structure, according to some embodiments.

Layout design 1800 is a variation of layout design 1700 of FIG. 17. In some embodiments, layout design 1800 corresponds to a double-height, dual-output pin layout design with a first pin (e.g., conductive structure layout patterns 1714a, 1728a) and a second pin (e.g., conductive structure layout patterns 1714b, 1728 b). In some embodiments, layout design 1800 shows that the component locations for the double height, dual output pins can be adjusted to be located at other locations, and the component number for the double height, dual output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1800 of FIG. 18 are within the scope of the invention.

In contrast to layout design 1700 of FIG. 17, layout design 1800 of FIG. 18 does not include conductive structure layout patterns 1714c and 1728c, and via layout patterns 1318e, 1324e, 1330e, 1318f, 1324f, 1330f, 1718e, 1724e, 1730e, 1718f, 1724f, and 1730 f. Height H2 of layout design 1800 is twice height H1 of one or more of layout designs 1100 and 1300-1600.

In some embodiments, by utilizing layout design 1800, a metal mesh structure configured as double-height, dual-output pins is created. In some embodiments, by utilizing layout design 1800, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, and 1730d) is increased, resulting in multiple connections between underlying and overlying conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns on the V0, V1, and V2 levels in the layout design 1800 are configured in a stacked via configuration, resulting in lower resistance than other approaches. In some embodiments, the conductive structure layout patterns 1714a, 1714b of the M1 layer are aligned with the corresponding conductive structure layout patterns 1728a, 1728b of the M3 layer, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1714a, 1714b of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1728a, 1728b of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, and 1730d is a square via layout pattern. In some embodiments, as the number of via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, and 1730d increases and the number of conductive structure layout patterns 1714a, 1714b, 1728a, 1728b increases, a plurality of output pins are provided in the layout design 1800, creating a plurality of current paths between lower and upper layout patterns (e.g., metal layers M0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1800 having better speed performance than other approaches.

Fig. 19 is a diagram of a layout design 1900 of an IC structure according to some embodiments.

Layout design 1900 is a variation of layout design 1800 of FIG. 18. Height H3 of layout design 1900 is three times greater than height H1 of one or more of layout designs 1100 and 1300-1600. In some embodiments, layout design 1900 corresponds to a layout design with three times the height, dual output pins for a first pin (e.g., conductive structure layout patterns 1914a, 1928a) and a second pin (e.g., conductive structure layout patterns 1914b, 1928 b). In some embodiments, layout design 1900 shows that the component locations of the three-height, dual-output pins can be adjusted to be located at other locations, and the component number of the three-height, dual-output pins can be adjusted to other numbers. Other configurations, locations, or numbers of elements in the layout design 1900 of FIG. 19 are within the scope of the invention.

In contrast to layout design 1800 of FIG. 18, layout design 1900 also includes a third portion 1904 c. The third portion 1904c is a mirror image of the second portion 1704b relative to the second line 1902. In some embodiments, the third portion 1904c is not a mirror image of the second portion 1704b relative to the second line 1902. The layout design 1900 is symmetric about a centerline 1940.

The first portion 1704a includes a layout pattern as shown in the layout pattern 1300 of fig. 13, and the second portion 1704b includes a layout pattern as shown in the layout pattern 1700 of fig. 17, and thus similar detailed descriptions of these layout patterns are omitted.

The third portion 1904c includes a conductive structure layout pattern 1906a, a conductive structure layout pattern 1906b, a rail layout pattern 1908b, a conductive structure layout pattern 1922a, a conductive structure layout pattern 1922b, and via layout patterns 1918a, 1924a, 1930a, 1918b, 1924b, 1930b, 1918c, 1924c, 1930c, 1918d, 1924d, and 1930 d.

In contrast to layout design 1800 of FIG. 18, conductive structure layout patterns 1914a, 1928a, 1914b, 1928b of layout design 1900 replace respective conductive structure layout patterns 1714a, 1728a, 1714b, 1728 b. The conductive structure layout patterns 1914a, 1928a, 1914b, 1928b are similar to the corresponding conductive structure layout patterns 1714a, 1728a, 1714b, 1728b, and therefore a similar detailed description of these layout patterns is omitted.

Conductive structure layout patterns 1914a, 1928a, 1914b, 1928b extend in second direction Y to intersect first line 1702 and second line 1902 of layout design 1900 and extend into third portion 1904 c.

The layout pattern in the third portion 1904c is similar to the corresponding layout pattern in the first portion 1704a or the second portion 1704b, and therefore a similar detailed description of these layout patterns is omitted.

The via layout patterns 1918a, 1924a, 1930a, 1918b, 1924b, 1930b, 1918c, 1924c, 1930c, 1918d, 1924d and 1930d are similar to the respective via layout patterns 1118a, 1124a, 1130a, 1118b, 1124b, 1130b, 1118c, 1124c, 1130c, 1118d, 1124d and 1130d, or the respective via layout patterns 1718a, 1724a, 1730a, 1718b, 1724b, 1730b, 1718c, 1724c, 1730c, 1718d, 1724d and 1730d, and therefore similar detailed descriptions of these layout patterns are omitted.

Conductive structure layout patterns 1906a, 1906b, 1922a, 1922b are similar to respective conductive structure layout patterns 1106a, 1106b, 1122a, 1122b or respective conductive structure layout patterns 1706a, 1706b, 1722a, 1722b, and therefore similar detailed descriptions of these layout patterns are omitted.

The rail layout pattern 1908b is similar to the rail layout pattern 108b, and therefore a similar detailed description of these layout patterns is omitted.

In some embodiments, by utilizing layout design 1900, a metal mesh configuration configured as three times height, dual output pins is created. In some embodiments, by utilizing layout design 1900, the number of via layout patterns (e.g., via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, 1730d, 1918a, 1918b, 1918c, 1918d, 1924a, 1924b, 1924c, 1924d, 1930a, 1930b, 1930c, and 1930d) is increased, resulting in more connections between the underlying and overlying conductive component layout patterns (e.g., metal layers M0, M1, M2, M3, etc.), resulting in lower resistance than other approaches. In some embodiments, one or more of via layout patterns 1918a, 1924a, and 1930a, or via layout patterns 1918b, 1924b, and 1930b, or via layout patterns 1918c, 1924c, and 1930c, or via layout patterns 1918d, 1924d, and 1930d are aligned in a stacked via configuration, resulting in lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1914a, 1914b of the M1 layer and the corresponding conductive structure layout patterns 1928a, 1928b of the M3 layer are aligned, resulting in a lower resistance than other methods. In some embodiments, the conductive structure layout patterns 1914a, 1914b of the M1 layer each use a 1W M1 routing track, and the conductive structure layout patterns 1928a, 1928b of the M3 layer each use one M3 routing track, resulting in lower resistance than other methods. In some embodiments, one or more of the via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, 1730d, 1918a, 1918b, 1918c, 1918d, 1924a, 1924b, 1924c, 1924d, 1930a, 1930b, 1930c, and 1930d is a square via layout pattern. In some embodiments, as via layout patterns 1118a, 1118b, 1118c, 1118d, 1124a, 1124b, 1124c, 1124d, 1130a, 1130b, 1130c, 1130d, 1718a, 1718b, 1718c, 1718d, 1724a, 1724b, 1724c, 1724d, 1730a, 1730b, 1730c, 1730d, 1918a, 1918b, 1918c, 1918d, 1924a, 1924b, 1924c, 1924d, 1930a, 1930b, 1930c, and 1930d increase in number and conductive structure layout patterns 1914a, 1914b, 1928a, 1928b increase in number, multiple output pins are provided in layout design 1900, creating multiple current paths between lower and upper conductive component layout patterns (e.g., metal layers 0, M1, M2, M3, etc.). In some embodiments, as the number of current paths increases, the distance of each respective current path decreases, resulting in layout design 1900 having better speed performance than other approaches.

FIGS. 20A-20D are diagrams of layout designs 2000A-2000D of IC structures, according to some embodiments.

Layout design 2000A includes cell layout pattern 2002a and power pillar layout patterns 2008a and 2014a.

The cell layout patterns 2002a, 2002b (described below), 2002c (described below), or 2002d (described below) correspond to the layout designs 100, 300-. Each of the cell layout patterns 2002a, 2002b, 2002c, or 2002d is a layout design of a standard cell.

The power pillar layout pattern 2008a includes a via layout pattern 2004a and a conductive structure layout pattern 2006 a. The power pillar layout pattern 2008a can be used to fabricate a corresponding power pillar structure 2402 (fig. 24).

The power pillar layout pattern 2014a includes a via layout pattern 2010a and a conductive structure layout pattern 2012 a. The power pillar layout pattern 2014a may be used to fabricate the corresponding power pillar structure 2404 (fig. 24).

In some embodiments, the power pillar layout patterns 2008a, a. -, 2008d and the corresponding power pillar layout patterns 2014a. -, 2014d are embedded in the corresponding cell layout patterns 2002a, 2002b, 2002c, 2202 d.

One or more of the power pillar layout patterns 2008a, ·, 2008D, and 2014a.., 2014D provide additional power pillar layout patterns to one or more of the cells in layout designs 2000A, 2000B, 2000C, and 2000D.

The via layout patterns 2004a, 2010a are located in the V0 layout level and between the second layout level (e.g., M0) and the third layout level (e.g., M1). Via layout patterns 2004a, 2010a may be used to fabricate respective vias 2404a, 2404 a' (fig. 24). The via layout patterns 2004a, 2010a are similar to the corresponding via layout patterns 1118a, 1118b, and similar detailed descriptions are omitted. .

The conductive structure layout patterns 2006a, 2012a are located on a second layout level (e.g., M0). The conductive structure layout patterns 2006a, 2012a can be used to fabricate respective conductive structures 2402a, 2402b (fig. 24). The conductive structure layout patterns 2006a, 2012a are similar to the corresponding conductive structure layout patterns 1106a, 1106b, and similar detailed descriptions are omitted.

Layout design 2000B, 2000C, or 2000D is similar to layout design 2000A, and a similar detailed description is omitted. Each of layout designs 2000B, 2000C, and 2000D is a variation of layout design 2000A. For example, layout design 2000B corresponds to layout design 2000A having a different width in first direction X. Similarly, layout designs 2000C and 2000D also have a different width in first direction X than layout design 2000A. In some embodiments, one or more of layout designs 2000A, 2000B, 2000C, and 2000D have the same width in first direction X as another of layout designs 2000A, 2000B, 2000C, and 2000D.

Each element in layout design 2000B, 2000C, or 2000D is similar to the corresponding element in layout design 2000A, and therefore a similar detailed description of these layout patterns is omitted.

In contrast to layout design 2000A of fig. 20A, power pillar layout patterns 2008B, 2014B in layout design 2000B replace respective power pillar layout patterns 2008a, 2014a, cell layout pattern 2002B in layout design 2000B replaces cell layout pattern 2002a, conductive structure layout patterns 2006B, 2012B in layout design 2000B replace respective conductive structure layout patterns 2006a, 2012a, and via layout patterns 2004B, 2010B in layout design 2000B replace respective via layout patterns 2004a, 2010A.

In contrast to layout design 2000A of fig. 20A, power pillar layout patterns 2008C, 2014C in layout design 2000C replace respective power pillar layout patterns 2008a, 2014a, cell layout pattern 2002C in layout design 2000C replaces cell layout pattern 2002a, conductive structure layout patterns 2006C, 2012C in layout design 2000C replace respective conductive structure layout patterns 2006a, 2012a, and via layout patterns 2004C, 2010C in layout design 2000C replace respective via layout patterns 2004a, 2010A.

In contrast to layout design 2000A of fig. 20A, power pillar layout patterns 2008D, 2014D in layout design 2000D replace respective power pillar layout patterns 2008a, 2014a, cell layout pattern 2002D in layout design 2000D replaces cell layout pattern 2002a, conductive structure layout patterns 2006D, 2012D in layout design 2000D replace respective conductive structure layout patterns 2006a, 2012a, and via layout patterns 2004D, 2010D in layout design 2000D replace respective via layout patterns 2004a, 2010A.

The cell layout pattern 2002b, 2002c, or 2002d corresponds to the layout designs 100, 300-. The cell layout pattern 2002b, 2002c, or 2002d is a layout design of a standard cell.

Fig. 21A is a diagram of a layout design 2100A of an IC structure, according to some embodiments.

The layout design 2100A includes rail layout patterns 2102a, 2102b, 2102c (collectively referred to as "rail layout pattern groups 2102", not shown) each extending in the first direction X and separated from each other in the second direction Y. The rail layout pattern group 2102 is located on a second layout level (e.g., M0). The set of rail layout patterns 2102 may be used to fabricate the rail structures 2402a, 2402b (fig. 24). The rail layout pattern group 2102 is similar to the rail layout pattern groups 108a, 108b, and detailed description is omitted.

Layout design 2100A also includes a set of power pillar layout patterns 2103 arranged in rows and columns. For simplicity, the arrows marking the power post layout pattern group 2103 point to the power post layout patterns 2108c, 2114c, 2124 c. However, power post layout pattern group 2103 also refers to one or more components not labeled in 2100A (e.g., one or more of power post layout patterns 2108a, 2108b, 2108c, 2114a, a. Other configurations of the power pillar layout pattern, the via layout pattern, or the conductive structure layout pattern are within the scope of the present invention.

The power post layout pattern group 2103 includes one or more of power post layout patterns 2108a, 2108b, 2108c, 2114a, 2114b, 2114c, 2124a, 2124b, and 2124 c.

One or more of the power pillar layout patterns 2108a, 2108b, 2108c, 2124a, 2124b, and 2124c can be used to fabricate a power pillar structure (e.g., the source conductive structure 2402 of fig. 24) that is connected to a first power supply voltage VDD. One or more of the power pillar layout patterns 2114a, 2114b, and 2114c may be used to fabricate a power pillar structure (e.g., the source conductive structure 2404 of fig. 24) connected to the second power supply voltage VSS.

Each of the power pillar layout patterns 2108a, 2108b, 2108c includes a respective via layout pattern 2104a, 2104b, 2104c and a respective conductive structure layout pattern 2106a, 2106 c. Each of the power pillar layout patterns 2114a, 2114b, 2114c includes a corresponding via layout pattern 2110a, 2110b, 2110c and a corresponding conductive structure layout pattern 2112a, 2112b, 2112 c.

Each of the power pillar layout patterns 2124a, 2124b, 2124c includes a respective via layout pattern 2120a, 2120b, 2120c and a respective conductive structure layout pattern 2122a, 2122b, 2122 c.

Each of the via layout patterns 2104a,..., 2104c is located at a position where the corresponding conductive structure layout pattern 2106a,.., 2106c overlaps the rail layout pattern 2102 a. Similarly, each of the via layout patterns 2110a, e.g., 2110c and 2120a, e.g., 2120c is located at a position where the corresponding conductive structure layout pattern 2112a, e.g., the conductive structure layout pattern 2112c and 2122a, e.g., the conductive structure layout pattern 2122c overlaps the corresponding rail layout pattern 2102b and 2102 c.

In some embodiments, the power pillar patterns 2108a, 2108b, 2108c, 2114a, 2114b, 2114c, 2124a, 2124b, and 2124c of fig. 21A are referred to as part of a chip-level design, and the power pillar patterns 2008a, 2008b, 2008c, 2008D, 2014a, 2014b, 2014c, 2014D of fig. 20A-20D are referred to as part of a cell-level design.

Fig. 21B is a diagram of a layout design 2100B of an IC structure, according to some embodiments.

Layout design 2100B is a variation of layout design 2100A of fig. 21A and layout design 2000 of fig. 20A-20D. Layout design 2100B combines layout design 2100A of fig. 21A and layout designs 2000A-2000D of fig. 20A-20D.

The cell layout patterns 2002a and 2002b are placed directly beside each other. In some embodiments, the placement of the cell layout patterns 2002a and 2002b corresponds to operation 2806 (FIG. 28).

Each of the unit layout patterns 2002a and 2002b is placed over the rail layout patterns 2102a and 2102 b.

The cell layout patterns 2002c and 2002d are placed directly beside each other. Each of the unit layout patterns 2002c and 2002d is placed over the rail layout patterns 2102b and 2102 c. In some embodiments, the placement of the cell layout patterns 2002c and 2002d corresponds to operation 2806 (FIG. 28).

In some embodiments, the layout design 2100B is an exemplary layout design after one or more of operations 2802 and 2814 of the method 2800 of FIG. 28, and details of placing the layout design are described in more detail below in FIG. 28.

The power pillar layout pattern 2108a provides a current path 2130a to the cell layout pattern 2002 a. The power column layout pattern 2108b provides a current path 2130d to the cell layout pattern 2002a, and a current path 2130e to the cell layout pattern 2002 b. The power pillar layout pattern 2108c provides a current path 2130h to the cell layout pattern 2002 b. In some embodiments, as shown in fig. 21B, the current path provided from the power post layout pattern (e.g., power post layout pattern 2108a or 2124a) to the cell layout pattern (e.g., cell layout pattern 2002a or 2002c) is shown with a curve in the direction of the cell layout pattern (e.g., current path 2130a or 2134 a). For example, a current path 2130a is provided from the power post layout pattern 2108a to the cell layout pattern 2002a, and the current path 2130a is bent toward the cell layout pattern 2002 a. Similarly, a current path 2134a is provided from the power post layout pattern 2124a to the cell layout pattern 2002c, and the current path 2134a is bent toward the cell layout pattern 2002 c. In some embodiments, as shown in fig. 21B, the current path provided from the cell layout pattern (e.g., cell layout pattern 2002a or 2002c) to the power pillar layout pattern (e.g., power pillar layout pattern 2114a or 2014a') is shown as a straight line in the direction of the power pillar layout pattern (e.g., current path 2132a or 2132B). For example, the current path 2132a is provided from the cell layout pattern 2002a to the power supply pillar layout pattern 2114a, and the current path 2132a is a straight line in the direction of the power supply pillar layout pattern 2114 a. Similarly, the current path 2132b is provided from the cell layout pattern 2002c to the power column layout pattern 2014a ', and the current path 2132b is a straight line in the direction of the power column layout pattern 2014 a'.

The current path 2132a is provided from the cell layout pattern 2002a to the power pillar layout pattern 2114 a. The current path 2132d is provided from the cell layout patterns 2002a and 2002c to the power supply pillar layout pattern 2114 b. A current path 2132e is provided from each of the cell layout patterns 2002b and 2002d to the power supply pillar layout pattern 2114 b. A current path 2132j is provided from each of the cell layout patterns 2002b and 2002d to the power supply pillar layout pattern 2114 c.

The power column layout pattern 2124a provides a current path 2134a to the cell layout pattern 2002 c. The power column layout pattern 2124b provides a current path 2134d to the cell layout pattern 2002c and a current path 2134e to the cell layout pattern 2002 d. The power column layout pattern 2124c provides a current path 2134h to the cell layout pattern 2002 d.

The power pillar layout pattern 2008a provides additional current paths 2130b, 2130c to the cell layout pattern 2002 a. The power pillar layout pattern 2008b provides additional current paths 2130f, 2130g to the cell layout pattern 2002 b.

Additional current paths 2132b, 2132c are provided from the cell layout pattern 2002a or 2002c to the power pillar layout pattern 2014 a'. The additional current paths 2132f, 2132g are provided from the cell layout pattern 2002b or 2002d to the power pillar layout pattern 2008 d. Additional current paths 2132h, 2132i are provided from the cell layout patterns 2002b and 2002d to the power pillar layout pattern 2014 b.

The power pillar layout pattern 2014c provides additional current paths 2134b, 2134c to the cell layout pattern 2002 c. The power pillar layout pattern 2014d provides additional current paths 2134f, 2134g to the cell layout pattern 2002 d.

In some embodiments, one or more of the current paths 2130b, 2130c, 2130f, 2130g, 2132b, 2132c, 2132f, 2132g, 2132h, 2132i, 2134b, 2134c, 2134f, 2134g are referred to as additional current paths in that they provide paths for current flow, while one or more of the current paths 2130a, 2130d, 2130e, 2130h, 2132a, 2132d, 2132e, 2132j, 2134a, 2134d, 2134e, and 2134h do not provide paths for current flow.

By utilizing one or more of the power pillar layout patterns 2008a, 2008b, 2014a', 2008d, 2014b, 2014c, or 2014d, the density of the cell-level embedded power pillar layout patterns and corresponding power pillars present in each of the cells 2002a, 2002b, 2002c, 2002d is increased, resulting in lower resistance than other approaches. Further, by increasing the density of the power post layout pattern and the corresponding power post present in each of the cells 2002a, 2002b, 2002c, 2002d, additional current paths 2130b, 2130c, 2130f, 2130g, 2132b, 2132c, 2132f, 2132g, 2132i, 2134b, 2134c, 2134f, or 2134g are provided to or from each of the cells 2002a, 2002b, 2002c, 2002d and the corresponding IC device (not shown), thereby producing better synchronization timing than other methods.

FIG. 22 is a diagram of a layout design 2200 of an IC structure, according to some embodiments.

Layout design 2200 is a variation of layout design 2100B of FIG. 21B and layout designs 2000A-2000D of FIGS. 20A-20D.

In contrast to layout design 2100B of fig. 21B, layout design 2200 does not include rail layout pattern 2102c, cell 2002d, and power column layout patterns 2014c, 2014d, 2124a, 2124B, and 2124 c.

In contrast to layout design 2100B of fig. 21B, cell 2201a of layout design 2200 replaces cell 2002a, and cell 2201B of layout design 2200 replaces cell 2002B.

The cell 2201a includes one or more of via layout patterns 2202a, 2202 b. The via layout patterns 2202a, 2202. -, 2202h are similar to the via layout pattern group 1118, and therefore similar detailed descriptions of these layout patterns are omitted.

Cell 2201a also includes one or more of conductive structure layout patterns 2204a, ·, 2204f extending in the second direction Y and located on a third layout level (e.g., M1). The conductive structure layout patterns 2204a, ·, 2204f are similar to the conductive structure layout patterns 1128a or 1128b, and therefore similar detailed descriptions of these layout patterns are omitted.

The cell 2201a also includes one or more conductive structure layout patterns 2210a, 2210b, 2210e (collectively referred to as "conductive structure layout pattern group 2210", not shown) extending in the first direction X and located on a second layout level (e.g., M0). The conductive structure layout pattern group 2210 is similar to the conductive structure layout pattern group 1106, and thus a similar detailed description of these layout patterns is omitted.

In some embodiments, conductive structure layout pattern 2204c, via layout patterns 2004a and 2202d correspond to layout design 1000 of fig. 10. In some embodiments, the conductive structure layout pattern 2204f, the via layout pattern 2202h, and the power pillar layout pattern 2014a' correspond to the layout design 1000 of fig. 10.

In contrast to layout design 2000A of fig. 20A, conductive structure layout pattern 2204c and via layout patterns 2004a and 2202d of layout design 2200 replace power column layout pattern 2008a, and conductive feature layout pattern 2204e ' and via layout patterns 2202g ' and 2202h ' of layout design 2200 replace power column layout pattern 2114 c. The conductive structure layout pattern 2204e overlaps the power pillar layout pattern 2114 b. The power pillar layout pattern 2204c' overlaps the conductive structure layout pattern 2208 b.

The cell 2201b is similar to the cell 2201a, and therefore a similar detailed description of these layout patterns is omitted. In contrast to layout design 2100B of fig. 21B, cell 2201B of layout design 2200 does not include power pillar layout patterns 2008d, 2108c, and 2114 c. In contrast to layout design 2100B of fig. 21B, conductive structure layout pattern 2204e ' and via layout patterns 2202g ' and 2202h ' of cell 2201B replace power pillar layout pattern 2114c of cell 2201 a. The conductive structure layout pattern 2204c' overlaps the power pillar layout pattern 2008 b. The power pillar layout pattern 2014b overlaps the conductive structure layout pattern 2204 g'.

In some embodiments, the power pillar layout pattern 2204c, 2204e, 2204c 'or 2204e' is related to a source conductive structure layout pattern, wherein the source conductive structure layout pattern is a combination of the power pillar layout pattern described in fig. 20A-20D and the output pin layout patterns 1100 and 1300-1900 described in fig. 11 and 13-19.

Fig. 23A is a diagram of a layout design 2300A of an IC structure, according to some embodiments.

Layout design 2300A is a variation of layout design 1100 of FIG. 11, layout design 1300 of FIGS. 13-19, 1900, or 2200 of FIG. 22. Layout design 2300A combines the components of layout design 2200 and layout design 1300-1900. Layout design 2300A is a variation of layout design 2200 of fig. 22. Layout design 2300A corresponds to cell 2201a or cell 2201b of fig. 22. In contrast to cell 2201a of layout design 2200 of fig. 22, layout design 2300A does not include power pillar layout pattern 2114b, via layout pattern 2202g, or conductive structure layout pattern 2204 e.

Layout design 2300A includes a source conductive structure layout pattern 2302 and a source conductive structure layout pattern 2304. The source conductive structure layout patterns 2302, 2304 may be used to fabricate the respective source conductive structures 2402, 2404 of the IC structure 200 (as shown in fig. 24).

The source conductive structure layout pattern 2302 or 2304 is similar to the corresponding source pillar layout pattern 2204c or 2204f (fig. 22), and thus similar detailed description of these layout patterns is omitted. In some embodiments, the source conductive structure layout pattern 2302 or 2304 corresponds to the power pillar layout patterns described in fig. 20A-20D (e.g., the power pillar layout patterns 2008a, 2008 j, 2008D, 2014a, 2014 j, 2014D), the power pillar layout pattern group 2103 described in fig. 21A or one or more of the power pillar layout patterns 2204c, 2204e, 2204c ', 2204e' described in fig. 22 in combination with the output pin layout designs 1100 and 1300 + 1900 described in fig. 11 and 13-19.

In some embodiments, the source conductive structure layout pattern 2302 corresponds to an output pin connected to a source or drain (defined by MD region 2420a in fig. 24) of a transistor (not shown). In some embodiments, the source conductive structure layout pattern 2304 corresponds to an output pin connected to a source or drain (defined by MD region 2420b in fig. 24) of another transistor (not shown). In some embodiments, the source conductive structure layout patterns 2302 or 2304 correspond to one or more of the layout designs 1100 and 1300-1900.

The source conductive structure layout pattern 2302 is positioned on the first power supply voltage VDD side (e.g., overlapping with the rail layout pattern 2102 a), and the source conductive structure layout pattern 2304 is positioned on the second power supply voltage VSS side (e.g., overlapping with the rail layout pattern 2102 b). The source conductive structure layout pattern 2302 and the source conductive structure layout pattern 2304 are directly opposite to each other (e.g., the centers of each of the layout patterns 2302 and 2304 are aligned in the second direction Y).

The source conductive structure layout pattern 2302 includes a conductive structure layout pattern 2204c, via layout patterns 2004a and 2202d, a rail layout pattern 2102a, and a conductive structure layout pattern 2210 b.

The conductive structure layout pattern 2204c may be used to fabricate the conductive structures 2404c of the IC structure 2400 (as shown in fig. 24). Via layout patterns 2004a, 2202d can be used to fabricate respective vias 2404a, 2402d of IC structure 2400 (as shown in fig. 24). The guide track layout pattern 2102a may be used to fabricate a guide track 2402a (shown in fig. 24) of the IC structure 2400. The conductive structure layout pattern 2210b may be used to fabricate the conductive structure 2410b of the IC structure 2400 (shown in fig. 24).

The source conductive structure layout pattern 2304 is a mirror image of the source conductive structure layout pattern 2302 with respect to the line 2350, and similar detailed description is omitted. The source conductive structure layout pattern 2304 includes a conductive structure layout pattern 2204c ', via layout patterns 2004 a' and 2202h, a rail layout pattern 2102b, and a conductive structure layout pattern 2210 d.

The conductive structure layout pattern 2204c 'may be used to fabricate the conductive structure 2404 c' of the IC structure 2400 (as shown in fig. 24). Via layout patterns 2004a ', 2202h can be used to fabricate respective vias 2404a ', 2402d ' (as shown in fig. 24) of IC structure 2400. The guide track layout pattern 2102b may be used to fabricate a guide track 2402b (shown in fig. 24) of the IC structure 2400. The conductive structure layout pattern 2210d may be used to fabricate the conductive structure 2410d of the IC structure 2400 (as shown in fig. 24).

Layout design 2300A also includes an Oxide Definition (OD) layout pattern 2340A, a Metal Diffusion (MD) layout pattern 2320A, and via layout patterns 2310A, 2310 b.

OD layout pattern 2340A extends in first direction X and is located on the OD level of layout design 2300A. OD layout pattern 2340a may be used to fabricate OD region 2440a of IC structure 2400 (as shown in fig. 24). In some embodiments, the OD layout pattern 2340a defines an active region or source diffusion region of a transistor (not shown) of the IC structure 2400.

Metal Diffusion (MD) layout pattern 2320A extends in the second direction Y and is located at the MD level of layout design 2300A. MD layout pattern 2320a may be used to fabricate MD region 2420a of IC structure 2400 (shown in fig. 24).

The via layout pattern 2310a is located above the MD layout pattern 2320a and below the rail layout pattern 2102 a.

The via layout pattern 2310b is located above the MD layout pattern 2320a and below the conductive structure layout pattern 2210 b. In some embodiments, the via layout patterns 2310a and 2310b are located on the VC level. The via layout patterns 2310a, 2310b may be used to fabricate respective vias 2450a and 2450b of IC structure 2400 (as shown in fig. 24).

In some embodiments, the OD level is below the MD level. In some embodiments, the MD level is located below the VC level. In some embodiments, the VC level is located below the M0 level.

Layout design 2300A also includes OD layout pattern 2340b, MD layout pattern 2320b, and via layout patterns 2310c, 2310 d.

OD layout pattern 2340b extends in the first direction X and is located on the OD level of layout design 2300A. OD layout pattern 2340b may be used to fabricate OD region 2440b of IC structure 2400 (as shown in fig. 24). In some embodiments, the OD layout pattern 2340b defines an active region or source diffusion region of a transistor (not shown) of the IC structure 2400.

MD layout pattern 2320b extends in the second direction Y and is located on the MD level of layout design 2300A. MD layout pattern 2320b may be used to fabricate MD region 2420b of IC structure 2400 (as shown in fig. 24).

The via layout pattern 2310c is located above the MD layout pattern 2320a and below the rail layout pattern 2102 b.

The via layout pattern 2310d is located above the MD layout pattern 2320b and below the conductive structure layout pattern 2210 d. In some embodiments, the via layout patterns 2310d and 2310c are located on the VC level. Layout patterns 2310c, 2310d may be used to fabricate respective vias 2450c and 2450d of IC structure 2400 (as shown in fig. 24).

A set of current paths 2330 is shown from rail layout pattern 2102a to OD layout pattern 2340 a. Current path set 2330 includes two or more current paths. In some embodiments, the source-level conductive structure layout pattern 2302 provides at least additional current paths for the set of current paths 2330 as compared to other approaches.

A set of current paths 2332 is shown from OD layout pattern 2340b to rail layout pattern 2102 b. Current path set 2332 includes two or more current paths. In some embodiments, the source conductive structure layout pattern 2304 provides at least additional current paths for the current path set 2332 as compared to other approaches.

By utilizing the source conductive structure layout pattern 2302 or 2304 (and corresponding IC structures 2402, 2404 fabricated using a similar source conductive structure layout pattern 2302 or 2304), the density of the cell-level embedded power pillar layout patterns and corresponding power pillars present in the layout design 2300A is increased, resulting in lower resistance than other approaches. In addition, each of the source conductive structure layout patterns 2302 or 2304 provides at least two current paths (e.g., current path 2330 or 2332) between the rail layout pattern 2102a or 2102b and the OD layout pattern 2340a or 2340b, resulting in better synchronous timing operation than other methods.

Fig. 23B is a diagram of a layout design 2300B of an IC structure, according to some embodiments.

Layout design 2300B is an enlarged view of a portion of layout design 2300A of FIG. 23A, and for simplicity, FIG. 23A does not include other layers (e.g., OD, PO, etc.). For example, the layout design 2300B shows a portion of the layout design 2300A that is positioned between the line 2350 and the rail layout pattern 2102a from the M1 layout level to the MD layout level. Layout design 2300B does not include other layers for simplicity.

Fig. 23C is a diagram of a layout design 2300C of an IC structure, according to some embodiments.

Layout design 2300C is an enlarged view of a portion of layout design 2300A of fig. 23A, and for simplicity, fig. 23A does not include other layers (e.g., OD, PO, etc.). For example, the layout design 2300C shows a portion of the layout design 2300A that is positioned between the line 2350 and the rail layout pattern 2102b from the M1 layout level to the M0 layout level to the MD layout level. Layout design 2300C does not include other layers for simplicity.

Fig. 23D is a diagram of a layout design 2300D of an IC structure, according to some embodiments.

Layout design 2300D is a variation of layout design 2300A of fig. 23A. In contrast to the layout design 2300A of fig. 23A, the layout design 2300D includes an M0 level, an M1 level, and a V0 level. For simplicity, layout design 2300C does not include an OD level, a PO level, an MD level, and a VC level.

Fig. 24 is a diagram of an IC structure 2400 according to some embodiments. Fig. 24 is a cross-sectional view of an IC structure 2400 corresponding to a layout design 2300A, 2300B, or 2300C intersected by a plane E-E', according to some embodiments. The IC structure 2400 is fabricated from the layout design 2300A, 2300B, or 2300C. In some embodiments, the M0 level, the M1 level, and the V0 level are fabricated by the layout design 2300D.

The structural relationships, including alignment, length, and width, and the configuration of the IC structure 2400 are similar to those of the layout designs 2300A-2300C of fig. 23A-23C and will not be described in fig. 24 for the sake of brevity.

The IC structure 2400 includes an OD region 2440a and an OD region 2440b extending in the first direction X and separated from each other in the second direction Y. In some embodiments, the OD region 2440a defines an active region or source diffusion region of a first transistor (not shown) of the IC structure 2400. In some embodiments, the OD region 2440b defines an active region or source diffusion region of a second transistor (not shown) of the IC structure 2400. In some embodiments, the first transistor and the second transistor are integrated together to form a transistor. In some embodiments, the first transistor is different from the second transistor. In some embodiments, the first transistor is the same as the second transistor.

IC structure 2400 also includes MD regions 2420a and MD regions 2420b that extend in the second direction Y and are separated from each other in the first direction X. MD regions 2420a, 2420b are located on the MD level of IC structure 2400.

IC structure 2400 also includes vias 2450a, 2450b, 2450c, 2450d positioned over MD regions 2420a, 2420 b. Vias 2450a, 2450b, 2450c, 2450d are located on the VC level. Vias 2450a, 2450b provide electrical connections between the M0 level and the MD level. Vias 2450a electrically connect conductive structures 2402a to MD regions 2420 a. Via 2450b electrically connects conductive structure 2410b to MD region 2420 a.

Vias 2450c, 2450d provide electrical connections between the M0 level and the MD level. Vias 2450c electrically connect conductive structures 2402b to MD regions 2420 b. Via 2450d electrically connects conductive structure 2410d to MD region 2420 b.

IC structure 2400 also includes conductive structures 2410b, 2410d and guide rails 2402a, 2402b located on the M0 level. Each of the guide tracks 2402a, 2402b or each of the conductive structures 2410b, 2410d extends in the first direction X and is separated from each other in the second direction Y. The guide track 2402a is configured to provide a first power supply voltage VDD. The guide rail 2402b is configured to supply the second power supply voltage VSS.

IC structure 2400 also includes vias 2404a, 2402d, 2404a ', 2402d' positioned above the M0 level.

Vias 2404a, 2402d, 2404a ', 2402d' are located on the V0 level. Vias 2404a, 2402d provide electrical connections between the M1 level and the M0 level. Vias 2404a electrically connect the rails 2402a to the conductive structures 2404 c. Via 2402d electrically connects conductive structure 2410b to conductive structure 2404 c.

Vias 2404a ', 2402d' provide electrical connections between level M1 and level M0. Vias 2404a 'electrically connect the rails 2402b to the conductive structures 2404 c'. Via 2402d 'electrically connects conductive structure 2410d to conductive structure 2404 c'.

IC structure 2400 also includes conductive structures 2404c, 2404c' located on the M1 level. Each of the conductive structures 2404c, 2404c' extends in the second direction Y and is spaced apart from each other in the first direction X.

The rails 2402a, conductive structures 2410b, 2404c, and vias 2404a, 2402d are grouped together as source conductive structures 2402. In some embodiments, the source conductive structures 2402, 2404 are referred to as power pillar structures. In some embodiments, source conductive structure 2402 corresponds to an output pin connected to a source (defined by MD region 2420a in fig. 24) of a first transistor (not shown).

The guide 2402b, conductive structures 2410d, 2404c ', and vias 2404a ', 2402d ' are grouped together as source conductive structures 2404. In some embodiments, the source conductive structure 2404 corresponds to an output pin connected to a source (defined by MD region 2420b in fig. 24) of a second transistor (not shown). In some embodiments, source conductive structures 2402 or 2404 are fabricated from one or more of layout designs 1100 and 1300, 1900, 2300A, 2300B, 2300C, 2300D, 2500A, 2500B, 2600A-2600D, 2700A-2700D. The source conductive structure 2402 or 2404 is similar to the IC structure 1200 of fig. 12A and 12B. In some embodiments, the source conductive structure 2402 or 2404 corresponds to a source metal mesh structure.

The source conductive structure 2402 provides at least two current paths (current paths 2330a and 2330b) from the rail 2402a to the OD region 2440 a. In some embodiments, the current path 2330a flows from the rail 2402a (level M0) of the IC structure 2400 through via 2450a (level VC), MD region 2420a (level MD), to OD region 2440a (level OD). In some embodiments, the current path 2330b flows from the conductive structure 2404c (level M1) through via 2402d (level V0), conductive structure 2410b (level M0), via (2450b), MD region 2420a (level MD) to OD region 2440a (level OD). The source conductive structure 2402 provides two or more current paths (e.g., current paths 2330a and 2330b) between the guide track 2402a and the OD region 2440a, resulting in better synchronous timing operation than other approaches.

The source conductive structure 2404 provides at least two current paths (current paths 2332a and 2332b) from the OD region 2440b to the rail 2402 b. In some embodiments, the current path 2332a flows from OD region 2440b (OD level) through MD region 2420b (MD level), via 2450b (VC level), conductive structure 2410d (M0 level), to via 2402d '(V0 level) to conductive structure 2404c' (M1 level). In some embodiments, the current path 2332b flows from OD region 2440b (OD level) through MD region 2420b (MD level), via 2450c (VC level), rail 2402b (M0 level), via 2404a '(V0 level), to conductive structure 2404c' (M1 level). Source conductive structure 2404 provides two or more current paths (e.g., current paths 2332a and 2332b) between OD region 2440b and rail 2402b, resulting in better synchronous timing operation than other approaches.

By utilizing the source conductive structures 2402, 2404, the density of embedded power pillars present in the integrated circuit 2400 is increased, resulting in a lower resistance than other approaches. In addition, the source conductive structure 2402 provides an additional current path (e.g., current path 2330b) between the guide track 2402a and the OD region 2440a, resulting in better synchronous timing operation than other approaches. Similarly, source conductive structure 2404 provides an additional current path (e.g., current path 2332b) between guide track 2402b and OD region 2440b, resulting in better synchronous timing operation than other approaches.

Fig. 25A and 25B are diagrams of respective layout designs 2500A and 2500B of an IC structure, according to some embodiments.

Layout designs 2500A and 2500B are variations of layout design 2300A of FIG. 23A.

In contrast to the layout design 2300A of fig. 23A, the four M0 conductive structure layout patterns (e.g., the conductive structure layout patterns 2514a-2514d) in each of the layout designs 2500A and 2500B replace the five M0 conductive structure layout patterns (e.g., the conductive structure layout patterns 2210A-2210 e). The conductive structure layout patterns 2514a-2514d are similar to the conductive structure layout patterns 2210A-2210e of the layout design 2300A), and thus a similar detailed description of these layout patterns is omitted.

In contrast to the layout design 2300A of 23A, the current path 2530, 2532 of each respective layout design 2500A, 2500B replaces the respective current path 2330, 2332. The current paths 2530, 2532 are similar to the current paths 2330, 2332 of the layout design 2300A, and therefore similar detailed descriptions of these layout patterns are omitted.

In comparison to the layout design 2300A of fig. 23A, the source conductive structure layout patterns 2502, 2504 of the respective layout designs 2500A, 2500B replace the respective source conductive structure layout patterns 2302, 2304. The conductive structure layout patterns 2502, 2504 are similar to the source conductive structure layout patterns 2302, 2304 of the layout design 2300A, and thus similar detailed descriptions of these layout patterns are omitted.

Fig. 25A shows a source conductive structure layout pattern 2502 located on the first power supply voltage VDD side (e.g., overlapping with the rail layout pattern 2102 a). By utilizing four M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2514a-2514d) and a source metal mesh (e.g., source conductive structure layout pattern 2502) located on the VDD side of the power rail layout pattern 2102a, the density of the cell-level embedded power pillar layout patterns present in the layout design 2500A is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2502 provides at least two current paths (e.g., current path group 2530) between the rail layout pattern 2102a and the OD layout pattern 2340a, resulting in better synchronous timing operation than other methods.

The layout design 2500B of fig. 25B shows the source conductive structure layout pattern 2504 located on the second power supply voltage VSS side (e.g., overlapping with the rail layout pattern 2102B). By utilizing four M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2514a-2514d) and a source metal mesh (e.g., source conductive structure layout pattern 2504) located on the VSS side of the power rail layout pattern 2102B, the density of the cell-level embedded power pillar layout patterns present in layout design 2500B is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2504 provides at least two current paths (e.g., current path group 2532) between the rail layout pattern 2102b and the OD layout pattern 2340b, resulting in better synchronous timing operation than other methods.

Fig. 26A, 26B, 26C, and 26D are diagrams of respective layout designs 2600A, 2600B, 2600C, and 2600D of IC structures, according to some embodiments.

Layout designs 2600A, 2600B, 2600C, and 2600D are variations of the respective layout design 2500A of fig. 25A or the respective layout design 2500B of fig. 25B.

In contrast to the layout design 2500A of fig. 25A or the layout design 2500B of fig. 25B, five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614a-2614e) in each of the layout designs 2600A, 2600B, 2600C, and 2600D replace four M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2514 a-2514D). The conductive structure layout patterns 2614a-2614e are similar to the conductive structure layout patterns 2514a-2514d in the layout designs 2500A, 2500B, and therefore, similar detailed descriptions of these layout patterns are omitted.

In contrast to the layout design 2500A of FIG. 25A or the layout design 2500B of FIG. 25B, the current paths 2630A-2630C, 2632a-2632D of each respective layout design 2600A, 2600B, 2600C, and 2600D replace the respective current paths 2530, 2532. The current paths 2630A-2630c, 2632a-2632d are similar to the current paths 2530, 2532 of the layout designs 2500A, 2500B and therefore similar detailed descriptions of these layout patterns are omitted.

The layout design 2600A of fig. 26A shows the source conductive structure layout pattern 2602A and the source conductive structure layout pattern 2604A directly opposite each other over the first power supply voltage VDD and the second power supply voltage VSS (e.g., the centers of each of the layout patterns 2602A and 2604A are aligned in the second direction Y). By utilizing five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614A-2614e), a source metal mesh (e.g., source conductive structure layout pattern 2602A) located on the VDD side of the power rail layout pattern 2102A, and a source metal mesh (e.g., source conductive structure layout pattern 2604A) located on the VSS side of the power rail layout pattern 2102b, the density of the cell-level embedded power pillar layout patterns present in layout design 2600A is increased, resulting in lower resistance than other approaches. Further, the source conductive structure layout pattern 2602A provides at least two current paths (e.g., current path group 2630a) between the rail layout pattern 2102A and the OD layout pattern 2340a, and the source conductive structure layout pattern 2604A provides at least two current paths (e.g., current path group 2632A) between the rail layout pattern 2102b and the OD layout pattern 2340b, resulting in better synchronous timing operation than other methods.

The layout design 2600B of fig. 26B shows the source conductive structure layout pattern 2602B and the source conductive structure layout pattern 2604B staggered from each other (e.g., the centers of each of the layout patterns 2602A and 2604A are not aligned in the first direction X and the second direction Y). By utilizing five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614a-2614e), a source metal mesh (e.g., source conductive structure layout pattern 2602B) located on the VDD side of the power rail layout pattern 2102a, and a staggered source metal mesh (e.g., source conductive structure layout pattern 2604B) located on the VSS side of the power rail layout pattern 2102B, the density of the cell-level embedded power pillar layout patterns present in layout design 2600B is increased, resulting in lower resistance than other approaches. Further, the source conductive structure layout pattern 2602B provides at least two current paths (e.g., current path group 2630B) between the rail layout pattern 2102a and the OD layout pattern 2340a, and the source conductive structure layout pattern 2604B provides at least two current paths (e.g., current path group 2632B) between the rail layout pattern 2102B and the OD layout pattern 2340B, resulting in better synchronous timing operation than other methods.

The layout design 2600C of fig. 26C shows a source conductive structure layout pattern 2602C located on the first power supply voltage VDD side (e.g., overlapping the rail layout pattern 2102 a). By utilizing five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614a-2614e) and the source metal mesh (e.g., source conductive structure layout pattern 2602C) located on the VDD side of the power rail layout pattern 2102a, the density of the cell-level embedded power pillar layout patterns present in layout design 2600C is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2602C provides at least two current paths (e.g., current path group 2630C) between the rail layout pattern 2102a and the OD layout pattern 2340a, resulting in better synchronous timing operation than other methods.

The layout design 2600D of fig. 26D shows the source conductive structure layout pattern 2604D on the second power supply voltage VSS side (e.g., overlapping the rail layout pattern 2102 b). By utilizing five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614a-2614e) and the source metal mesh (e.g., source conductive structure layout pattern 2604D) located on the VSS side of the power rail layout pattern 2102b, the density of the cell-level embedded power pillar layout patterns present in layout design 2600D is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2604D provides at least two current paths (e.g., current path group 2632D) between the rail layout pattern 2102b and the OD layout pattern 2340b, resulting in better synchronous timing operation than other methods.

Fig. 27A, 27B, 27C, and 27D are diagrams of respective layout designs 2700A, 2700B, 2700C, and 2700D of IC structures according to some embodiments.

Layout designs 2700A, 2700B, 2700C, and 2700D are variations of the respective layout designs 2600A, 2600B, 2600C, and 2600D of fig. 26A, 26B, 26C, and 26D, respectively.

For example, each of layout designs 2700A, 2700B, 2700C, and 2700D includes six strips of M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2714a-2714 f). The six M0 conductive structure layout patterns 2714a-2714f replace the five M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2614a-2614e) of fig. 26A, 26B, 26C, and 26D, respectively. The conductive structure layout patterns 2714a-2714f are similar to the conductive structure layout patterns 2614a-2614e of layout designs 2600A, 2600B, 2600C, and 2500D, and therefore, similar detailed descriptions of these layout patterns are omitted.

In contrast to layout design 2600A of FIG. 26A, layout design 2600B of FIG. 26B, layout design 2600C of FIG. 26C, or layout design 2600D of FIG. 26D, current paths 2730A-2730C, 2732a-2732D of each respective layout design 2700A, 2700B, 2700C, and 2700D replace respective current paths 2630A-2630C, 2632a-2632D, and therefore similar detailed descriptions are omitted.

The layout design 2700A of fig. 27A shows the source conductive structure layout pattern 2702A and the source conductive structure layout pattern 2704A that are directly opposite to each other over the first power supply voltage VDD and the second power supply voltage VSS (e.g., the center of each of the layout patterns 2702A and 2704A is aligned in the second direction Y). By utilizing six strips of M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2714A-2714f), a source metal mesh (e.g., source conductive structure layout pattern 2702A) located on the VDD side of power rail layout pattern 2102A, and a source metal mesh (e.g., source conductive structure layout pattern 2704A) located on the VSS side of power rail layout pattern 2102b, the density of the cell-level embedded power pillar layout patterns present in layout design 2700A is increased, resulting in lower resistance than other approaches. Further, the source conductive structure layout pattern 2702A provides at least two current paths (e.g., current path group 2730a) between the rail layout pattern 2102A and the OD layout pattern 2340a, and the source conductive structure layout pattern 2704A provides at least two current paths (e.g., current path group 2732A) between the rail layout pattern 2102b and the OD layout pattern 2340b, resulting in better synchronous timing operation than other methods.

Layout design 2700B of fig. 27B shows source conductive structure layout pattern 2702B and source conductive structure layout pattern 2704B staggered from each other (e.g., the centers of each layout pattern 2702A and 2704A are not aligned in the first direction X and the second direction Y). By utilizing six strips of M0 conductive structure layout patterns (e.g., conductive structure layout patterns 2714a-2714f), a source metal mesh (e.g., source conductive structure layout pattern 2702B) located on the VDD side of power rail layout pattern 2102a, and a staggered source metal mesh (e.g., source conductive structure layout pattern 2704B) located on the VSS side of power rail layout pattern 2102B, the density of the cell-level embedded power pillar layout patterns present in layout design 2700B is increased, resulting in lower resistance than other approaches. Further, the source conductive structure layout pattern 2702B provides at least two current paths (e.g., current path group 2730B) between the rail layout pattern 2102a and the OD layout pattern 2340a, and the source conductive structure layout pattern 2704B provides at least two current paths (e.g., current path group 2732B) between the rail layout pattern 2102B and the OD layout pattern 2340B, resulting in better synchronous timing operation than other methods.

Layout design 2700C of fig. 27C shows source conductive structure layout pattern 2702C on the first power supply voltage VDD side (e.g., overlapping with rail layout pattern 2102 a). By utilizing six strips of the M0 conductive structure layout pattern (e.g., conductive structure layout patterns 2714a-2714f) and the source metal mesh (e.g., source conductive structure layout pattern 2702C) located on the VDD side of the power rail layout pattern 2102a, the density of the cell-level embedded power pillar layout pattern present in layout design 2600C is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2702C provides at least two current paths (e.g., current path group 2730C) between the rail layout pattern 2102a and the OD layout pattern 2340a, resulting in better synchronous timing operation than other methods.

Layout design 2700D of fig. 27D shows source conductive structure layout pattern 2704D on the second power supply voltage VSS side (e.g., overlapping with rail layout pattern 2102 b). By utilizing six strips of the M0 conductive structure layout pattern (e.g., conductive structure layout patterns 2714a-2714f) and the source metal mesh (e.g., source conductive structure layout pattern 2704D) located on the VSS side of the power rail layout pattern 2102b, the density of the cell-level embedded power pillar layout pattern present in layout design 2700D is increased, resulting in lower resistance than other approaches. In addition, the source conductive structure layout pattern 2704D provides at least two current paths (e.g., current path group 2732D) between the rail layout pattern 2102b and the OD layout pattern 2340b, resulting in better synchronous timing operation than other methods.

Fig. 28 is a flow diagram of a method 2800 of forming or manufacturing an IC according to some embodiments. It should be understood that additional operations may be performed before, during, and/or after the method 2800 shown in fig. 28, and that some other processes are only briefly described herein. In some embodiments, the method 2800 may be used to form an integrated circuit such as the IC structure 200, 1200, or 2400 (fig. 2A-2B, 12A-12B, or 24). In some embodiments, the method 2800 may be used to form an integrated circuit having a similar structural relationship to one or more of the layout patterns 100, 300, 1100, 1300, 2300D or 2500A-2700D (FIG. 1, 3-11, 13-23D or 25A-27D).

In operation 2802 of method 2800, a first layout design (e.g., layout design 2100A) of a first cell (e.g., a component of layout design 2100A) is placed on the layout. In some embodiments, operation 2802 further comprises generating a first layout design (e.g., layout design 2100A) for the first cell.

In operation 2804, a second layout design (e.g., layout designs 2000A-2000D) for a second cell (e.g., cell layout patterns 2002a-2002D) is placed with the first cell. In some embodiments, operation 2804 further comprises generating a second layout design for the second cell.

In operation 2806, a third layout design (e.g., layout designs 2000A-2000D) of a third cell (e.g., cell layout patterns 2002a-2002D) is placed with the first cell (e.g., cell layout patterns 2002 a-2002D). In some embodiments, the third cell is different from the second cell. In some embodiments, operation 2806 further comprises generating a third layout design for a third cell.

At operation 2808, at least a third layout design (e.g., layout designs 2000A-2000D) is moved if the third layout design (e.g., layout designs 2000A-2000D) overlaps the second layout design (e.g., layout designs 2000A-2000D). In some embodiments, operation 2808 is not performed if the third layout design (e.g., layout designs 2000A-2000D) does not overlap the second layout design (e.g., layout designs 2000A-2000D). In some embodiments, operation 2808 includes moving the third layout design (e.g., layout designs 2000A-2000D) in the first direction X until the third layout design (e.g., layout designs 2000A-2000D) does not overlap the second layout design (e.g., layout designs 2000A-2000D). In some embodiments, operation 2808 includes moving the third layout design (e.g., layout designs 2000A-2000D) in the second direction Y until the third layout design (e.g., layout designs 2000A-2000D) does not overlap with the second layout design (e.g., layout designs 2000A-2000D).

In operation 2810, it is determined whether routing resources are available. In some embodiments, operation 2810 is performed by system 3000. In some embodiments, routing resources refer to spacing for additional conductive structure layout patterns (or corresponding conductive structures) or via layout patterns (or corresponding vias) to provide interconnection with an underlying or overlying layer. If a determination is made that routing resources are available, operation 2810 proceeds to operation 2814. If a determination is made that routing resources are not available, operation 2810 proceeds to operation 2812.

In operation 2812, the second cell (e.g., cell layout pattern 2002a) or the third cell (e.g., cell layout pattern 2002c) is moved until a corresponding second power pillar layout pattern (e.g., power pillar layout pattern 2014 a) in the second cell (e.g., cell layout pattern 2002a) or a third power pillar layout pattern (e.g., power pillar layout pattern 2008c) in the third cell (e.g., cell layout pattern 2002c) overlaps with the first power pillar layout pattern (e.g., power pillar layout pattern 2108c) of the first cell.

In some embodiments, operation 2812 includes removing the overlapping second power pillar layout pattern (e.g., power pillar layout pattern 2014a) or third power pillar layout pattern (e.g., power pillar layout pattern 2008 c).

In some embodiments, operation 2812 includes replacing the third power pillar layout pattern (e.g., power pillar layout pattern 2014a) and the first power pillar layout pattern (e.g., power pillar layout pattern 2114b) with a new power pillar layout pattern (e.g., power pillar layout pattern 2014 a'). In some embodiments, operation 2812 includes merging the second or third power pillar layout pattern with the first power pillar layout pattern to place a new power pillar layout pattern (e.g., power pillar layout pattern 2014 a').

In some embodiments, the layout design 2200 of fig. 22 shows the result of operation 2812. For example, in these embodiments, a first power pillar layout pattern (e.g., power pillar layout pattern 2114b) of a first cell (e.g., layout design 2100A) overlaps or shares the same location with a second power pillar layout pattern (e.g., power pillar layout pattern 2014a) of a second cell (e.g., cell layout pattern 2002a) and merges to place the power pillar layout pattern (e.g., power pillar layout pattern 2014a') on the layout.

In operation 2814, if a second power pillar layout pattern (e.g., power pillar layout pattern 2014a) in a second cell (e.g., cell layout pattern 2002a) or a third power pillar layout pattern (e.g., power pillar layout pattern 2008c) in a third cell (e.g., cell layout pattern 2002c) overlaps with a first power pillar layout pattern (e.g., power pillar layout pattern 2114a) of the first cell, the second cell (e.g., cell layout pattern 2002a) or the third cell (e.g., cell layout pattern 2002c) is moved.

In some embodiments, if the second power pillar layout pattern (e.g., power pillar layout pattern 2014a) of the second cell (e.g., cell layout pattern 2002a) or the third power pillar layout pattern (e.g., power pillar layout pattern 2008c) of the third cell (e.g., cell layout pattern 2002c) does not overlap the first power pillar layout pattern (e.g., power pillar layout pattern 2114a) of the first cell, the second cell (e.g., cell layout pattern 2002a) or the third cell (e.g., cell layout pattern 2002c) is not moved in operation 2814.

In some embodiments, in operation 2814, even if routing resources are available, if the second power pillar layout pattern (e.g., power pillar layout pattern 2014a) of the second cell (e.g., cell layout pattern 2002a) or the third power pillar layout pattern (e.g., power pillar layout pattern 2008c) of the third cell (e.g., cell layout pattern 2002c) overlaps with the first power pillar layout pattern (e.g., power pillar layout pattern 2114a) of the first cell, the second power pillar layout pattern (e.g., power pillar layout pattern 2014a) or the third power pillar layout pattern (e.g., power pillar layout pattern 2008c) merges to form a power pillar layout pattern (e.g., power pillar layout pattern 2014a') similar to operation 2812.

In some embodiments, operation 2814 also includes operation 2814a (not shown) when the second cell is placed on a different row than the third cell. In some embodiments, operation 2814a (not shown) includes merging the second power pillar layout pattern (e.g., power pillar layout pattern 2014a) of the second cell (e.g., cell layout pattern 2002a) with the third power pillar layout pattern (e.g., power pillar layout pattern 2008c) of the third cell (e.g., cell layout pattern 2002c) to form a new power pillar layout pattern (e.g., power pillar layout pattern 2014 a') of the second cell (e.g., cell layout pattern 2002a) or the third cell (e.g., cell layout pattern 2002c), the result being as shown in layout design 2100 of fig. 21B.

In operation 2816, the IC structure 200, 1200, or 2400 is fabricated based on at least a first layout design (e.g., layout design 2100A) of a first cell layout pattern (e.g., layout design 2100A), a second layout design (e.g., layout designs 2000A-2000D) of a second cell layout pattern (e.g., cell layout patterns 2002a-2002D), or a third layout design (e.g., layout designs 2000A-2000D) of a third cell (e.g., cell layout patterns 2002 a-2002D).

In some embodiments, the first power pillar layout pattern of the method 2800 includes at least one or more of the set of power pillar layout patterns 2103, 2204C, 2204e, 2204C 'or 2204e' (fig. 22) or the source conductive structure layout patterns 2302, 2304, 2402, 2404, 2502, 2504, 2602A, 2602B, 2602C, 2604A, 2604B, 2604D, 2702A, 2702B, 2702C, 2704A, 2704B, 2704D. In some embodiments, the second or third power column layout pattern of the method 2800 includes at least one or more power column layout patterns 2008a, 2008B, 2008C, 2008D, 2014A, 2014B, 2014C, 2014D, 2204C, 2204e, 2204C ', or 2204e' (fig. 22) or source conductive structure layout patterns 2302, 2304, 2402, 2404, 2502, 2504, 2602A, 2602B, 2602C, 2604A, 2604B, 2604D, 2702A, 2702B, 2702C, 2704A, 2704B, 2704D.

In some embodiments, the first layout design of the method 2800 includes one or more of the layout patterns 100, 300, 1100, 1300, 2300D, or 2500A-2700D (FIG. 1, 3-11, 13-23D, or 25A-27D). In some embodiments, the second layout design of the method 2800 includes one or more of the layout patterns 100, 300, 1100, 1300, 2300D, or 2500A-2700D (FIG. 1, 3-11, 13-23D, or 25A-27D). In some embodiments, the third layout design of the method 2800 includes one or more of the layout patterns 100, 300, 1100, 1300, 2300D, or 2500A-2700D (FIG. 1, 3-11, 13-23D, or 25A-27D).

In some embodiments, one or more of operations 2808, 2810, 2812, and 2814 are not performed.

Fig. 29 is a flow diagram of a method 2900 of forming or fabricating an IC according to some embodiments. It should be understood that additional operations may be implemented before, during, and/or after the method 2900 shown in fig. 29. In some embodiments, method 2900 may be used to form an integrated circuit such as IC structure 200, 1200, or 2400 (fig. 2A-2B, 12A-12B, or 24). In some embodiments, the method 2900 may be used to form an integrated circuit having a similar structural relationship to one or more of the layout patterns 100, 300, 1100, 1300, 2300D, or 2500A-2700D (FIG. 1, 3-11, 13-23D, or 25A-27D).

In operation 2902 of method 2900, a first set of conductive structure layout patterns (e.g., first conductive structure layout pattern 106, set of conductive structure layout patterns 1106) is placed on a first layout level (e.g., M0). In some embodiments, the first set of conductive structure layout patterns corresponds to a first set of conductive structures (e.g., first conductive structure 206, conductive structure set 1206) that fabricate the integrated circuit structures 200, 1200, 2400. In some embodiments, the first set of conductive structure layout patterns extends in a first direction X. In some embodiments, each of the first set of conductive structure layout patterns is separated from each other in the second direction Y. In some embodiments, operation 2902 includes generating a first set of conductive structure layout patterns.

In operation 2904, a second set of conductive structure layout patterns (e.g., the first set of conductive structure layout patterns 114, the set of conductive structure layout patterns 1114) is placed on a second layout level (e.g., M1) different from the first layout level. In some embodiments, the second set of conductive structure layout patterns corresponds to the second set of conductive structures (e.g., conductive structures 214a, 214b, 1214a, 1214b) from which the integrated circuit structures 200, 1200, 2400 were fabricated. In some embodiments, the second set of conductive structure layout patterns extends in the second direction Y and overlaps the first set of conductive structure layout patterns. In some embodiments, each of the conductive structure layout patterns in the second set of conductive structure layout patterns is separated from each other in the first direction X. In some embodiments, operation 2904 includes generating a second set of conductive structure layout patterns.

In operation 2906, a first set of via layout patterns (e.g., second set of via layout patterns 118, via layout pattern set 1118) is placed between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns. In some embodiments, the first set of via layout patterns is located at V0. In some embodiments, the first set of via layout patterns corresponds to a first set of vias (e.g., second set of vias 218a and 218b, via structures 1218a, 1218b, 1218c, 1218d) of the fabrication IC structures 200, 1200, 2400. In some embodiments, the first set of vias electrically connects the second set of conductive structures to the first set of conductive structures. In some embodiments, each via layout pattern of the first set of via layout patterns is located at a position where each conductive structure layout pattern of the second set of conductive structure layout patterns overlaps each conductive structure layout pattern of the first set of conductive structure layout patterns. In some embodiments, operation 2906 includes generating a first set of via layout patterns.

In operation 2908, a third set of conductive structure layout patterns (e.g., second conductive structure layout pattern 122, conductive structure layout pattern set 1122) is placed at a third layout level (e.g., M2) different from the first and second layout levels. In some embodiments, the third set of conductive structure layout patterns corresponds to the third set of conductive structures (e.g., second conductive structure 222, conductive structures 1222a, 1222b) of the fabricated integrated circuit structures 200, 1200, 2400. In some embodiments, the third set of conductive structure layout patterns extends in the first direction X, overlaps the second set of conductive structure layout patterns, and covers a portion of the first set of conductive structure layout patterns. In some embodiments, each of the conductive structure layout patterns of the third set of conductive structure layout patterns is separated from each other in the second direction Y. In some embodiments, operation 2908 includes generating a third set of conductive structure layout patterns.

In operation 2910, a second set of via layout patterns (e.g., third set of via layout patterns 124, set of via layout patterns 1124) is placed between the third set of conductive structure layout patterns and the second set of conductive structure layout patterns. In some embodiments, the second set of via layout patterns is located at V1. In some embodiments, the second set of via layout patterns corresponds to a second set of vias (e.g., third set of vias 224a and 224b, via structures 1224a, 1224b, 1224c, 1224d) of the fabricated IC structures 200, 1200, 2400. In some embodiments, the second set of vias electrically connects the third set of conductive structures of the IC structures 200, 1200, 2400 to the second set of conductive structures. In some embodiments, each via layout pattern of the second set of via layout patterns is located at a position where each conductive structure layout pattern of the third set of conductive structure layout patterns overlaps each conductive structure layout pattern of the second set of conductive structure layout patterns. In some embodiments, operation 2910 includes generating a second set of via layout patterns.

In operation 2912, a fourth set of conductive structure layout patterns (e.g., the second set of conductive structure layout patterns 128, the set of conductive structure layout patterns 1128) is placed on a fourth layout level (e.g., M3) different from the first, second, and third layout levels. In some embodiments, the fourth set of conductive structure layout patterns corresponds to a fourth set of conductive structures (e.g., conductive structures 228a, 228b, 1228a, 1228b) from which the integrated circuit structures 200, 1200, 2400 were fabricated. In some embodiments, the fourth set of conductive structure layout patterns extends in the second direction, overlaps the third set of conductive structure layout patterns and the first set of conductive structure layout patterns, and covers a portion of the second set of conductive structure layout patterns. In some embodiments, each of the conductive structure layout patterns in the fourth set of conductive structure layout patterns is separated from each other in the first direction. In some embodiments, operation 2912 includes generating a fourth set of conductive structure layout patterns.

In operation 2914, a third set of via layout patterns (e.g., fourth set of via layout patterns 130, via layout pattern set 1130) is placed between the fourth set of conductive structure layout patterns and the third set of conductive structure layout patterns. In some embodiments, the third set of via layout patterns is located at V2. In some embodiments, the third set of via layout patterns corresponds to a third set of vias (e.g., fourth set of vias 230a and 230b, via structures 1230a, 1230b, 1230c, 1230d) for fabricating the IC structures 200, 1200, 2400. In some embodiments, a third set of vias electrically connects a fourth set of conductive structures of the IC structures 200, 1200, 2400 to the third set of conductive structures. In some embodiments, each via layout pattern of the third set of via layout patterns is located at a position where each conductive structure layout pattern of the fourth set of conductive structure layout patterns overlaps with each conductive structure layout pattern of the third set of conductive structure layout patterns. In some embodiments, operation 2914 includes generating a third set of via layout patterns.

In some embodiments, a center of at least one via layout pattern of the first set of via layout patterns, the second set of via layout patterns, or the third set of via layout patterns is aligned with a center of another via layout pattern of the first set of via layout patterns, the second set of via layout patterns, or the third set of via layout patterns in each of the first direction and the second direction.

In operation 2916, a power rail layout pattern group (e.g., rail layout pattern groups 108a, 108b, rail layout pattern group 2102) is placed on a first layout level (M0). In some embodiments, the set of power rail layout patterns corresponds to the set of power rails (e.g., set of rails 208a, 208b, set of rail layout patterns 2102) from which the IC structures 200, 1200, 2400 are fabricated. In some embodiments, the set of power rails is configured to provide either a first power supply voltage VDD or a second power supply voltage VSS. In some embodiments, at least the first, second, third, or fourth set of conductive structure layout patterns is located between the first set of power rail layout patterns. In some embodiments, operation 2916 includes generating a set of rail layout patterns.

In operation 2918, a gate layout pattern group (e.g., gate layout pattern group 104) is placed on a fifth layout level (e.g., polysilicon level) different from the first, second, third, and fourth layout levels. In some embodiments, the set of gate layout patterns corresponds to a set of gates (e.g., gate set 202) for fabricating the integrated circuit structures 200, 1200, 2400. In some embodiments, the gate layout pattern group 104 is located below the first layout level (M0). In some embodiments, the gate layout pattern group extends in the second direction. In some embodiments, each of the gate layout patterns in the gate layout pattern group is separated from each other in the first direction. In some embodiments, operation 2918 is not implemented. In some embodiments, operation 2918 includes generating a set of gate layout patterns.

In operation 2920, a conductive structure layout pattern (e.g., conductive structure layout pattern 140) is placed on a sixth layout level different from the first, second, third, fourth, and fifth layout levels. In some embodiments, the fifth set of conductive structure layout patterns corresponds to the fifth set of conductive structures (e.g., contact groups 204a, 204b, and 204c) of the fabricated integrated circuit structures 200, 1200, 2400. In some embodiments, the fifth set of conductive structure layout patterns extends in the second direction Y and overlaps the set of gate layout patterns. In some embodiments, each of the conductive structure layout patterns in the fifth set of conductive structure layout patterns is separated from each other in the first direction X. In some embodiments, operation 2920 is not performed. In some embodiments, operation 2920 includes generating a fifth set of conductive structure layout patterns.

In operation 2922, a fourth set of via layout patterns (e.g., the first set of via layout patterns 112) is placed between the set of gate layout patterns and the first set of conductive structure layout patterns. In some embodiments, operation 2922 includes placing a fourth set of via layout patterns between the set of gate layout patterns and the fifth set of conductive structure layout patterns. In some embodiments, the fourth set of via layout patterns is located at VC. In some embodiments, the fourth set of via layout patterns corresponds to a fourth set of vias (e.g., via sets 212a, 212b, and 212c) of the fabricated IC structures 200, 2400. In some embodiments, a fourth set of vias electrically connects the gate set to the first set of conductive structures. In some embodiments, each via layout pattern of the fourth set of via layout patterns is located at a position where each conductive structure layout pattern of the first set of conductive structure layout patterns overlaps each gate layout pattern of the set of gate layout patterns. In some embodiments, operation 2922 is not performed. In some embodiments, operation 2922 includes generating a fourth set of via layout patterns.

In operation 2924, the integrated circuit structures 200, 1200, 2400 are fabricated based on at least one of the layout patterns of the method 2900. In some embodiments, operation 2924 further includes fabricating a mask set based on the one or more layout patterns in method 2900, and using the mask set to fabricate the one or more integrated circuit structures in method 2900. In some embodiments, at least one of the layout patterns of method 2900 is stored on a non-transitory computer readable medium and at least one of the above-described operations of method 2900 is implemented by a hardware processor. In some embodiments, the operation 2924 further includes fabricating the integrated circuit structure 200, 1200, 2400 based on at least one of the layout designs 100, 300, 1100, 1300, 2300D or 2500A-2700D (FIG. 1, 3-11, 13-23D or 25A-27D).

Other configurations of one or more via layout patterns, conductive structure layout patterns, set of rail layout patterns, or set of gate layout patterns of method 2900 are within the scope of the invention. Other configurations of the hierarchy are within the scope of the invention.

In some embodiments, one or more of operations 2902, 2904, 2906, 2908, 2910, 2912, 2914, 2916, 2918, 2920, or 2922 are not implemented.

In some embodiments, the layout design of method 2800 or 2900 corresponds to layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D.

In some embodiments, the first, second, third, fourth, or fifth set of conductive structure layout patterns of the method 2800 or 2900 correspond to one or more of the layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D.

In some embodiments, the first, second, third, or fourth set of via layout patterns of methods 2800 or 2900 correspond to one or more of layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D.

In some embodiments, the set of guide layout patterns of the method 2800 or 2900 corresponds to one or more layout patterns of the layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D.

In some embodiments, the gate layout pattern set of the method 2800 or 2900 corresponds to one or more of the layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D.

One or more operations of methods 2800 or 2900 are performed by a processing device configured to execute instructions for fabricating an IC, such as IC structures 200, 1200, or 2400. In some embodiments, one or more operations of methods 2800 or 2900 are implemented using the same processing device as used in a different one or more operations of methods 2800 or 2900. In some embodiments, a different processing device is used to implement one or more operations of method 2800 or 2900 that are different than those used to implement one or more of methods 2800 or 2900.

FIG. 30 is a schematic diagram of a system 3000 for designing an IC layout design, according to some embodiments. In some embodiments, system 3000 generates or places one or more IC layout designs as described herein. The system 3000 includes a hardware processor 3002 and a non-transitory computer-readable storage medium 3004, wherein the non-transitory computer-readable storage medium 3004 is encoded with (i.e., stores) computer program code 3006 (i.e., a set of executable instructions). Computer-readable storage medium 3004 is also encoded with instructions 3007, wherein the instructions are for interfacing with a manufacturing machine that produces an integrated circuit. The processor 3002 is electrically connected to the computer readable storage medium 3004 by a bus 3008. Processor 3002 is also electrically connected to I/O interface 3010 via bus 3008. A network interface 3012 is also electrically connected to the processor 3002 through the bus 3008. The network interface 3012 is connected to a network 3014, thereby enabling the processor 3002 and the computer-readable storage medium 3004 to be connected to external elements through the network 3014. The processor 3002 is configured to execute computer program code 3006 encoded in a computer-readable storage medium 3004 such that the system 3000 may be used to implement some or all of the operations described by the method 2800 or the method 2900.

In some embodiments, processor 3002 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In some embodiments, computer-readable storage medium 3004 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). Computer-readable storage medium 3004 includes, for example, semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 3004 includes a compact disk read only memory (CD-ROM), a compact disk read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In some embodiments, storage medium 3004 stores computer program code 3006 configured to cause system 3000 to implement method 2800 or 2900. In some embodiments, the storage medium 3004 also stores information needed to implement the method 2800 or 2900 and information generated during implementation of the method 2800 or 2900, such as the layout design 3016, the first set of conductive structure layout patterns 3018, the second set of conductive structure layout patterns 3020, the third set of conductive structure layout patterns 3022, the fourth set of conductive structure layout patterns 3024, the fifth set of conductive structure layout patterns 3026, the set of gate layout patterns 3028, the at least one set of via layout patterns 3030, the set of rail layout patterns 3032, and the user interface 3034, and/or a set of executable instructions to implement the operations of the method 2800 or 2900. In some embodiments, at least one set of via layout patterns 3030 includes one or more of the first set, second set, third set, or fourth set of via layout patterns of fig. 29.

In some embodiments, storage medium 3004 stores instructions 3007 for interfacing with a manufacturing machine. The instructions 3007 enable the processor 3002 to generate manufacturing instructions readable by a manufacturing machine to efficiently implement the method 2800 or 2900 in a manufacturing process.

System 3000 includes I/O interface 3010. The I/O interface 3010 is connected to an external circuit. In some embodiments, I/O interface 3010 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and/or cursor direction keys for communicating information and commands to processor 3002.

System 3000 also includes a network interface 3012 connected to processor 3002. Network interface 3012 allows system 3000 to communicate with a network 3014, to which one or more other computer systems are connected. Network interface 3012 comprises a wireless network interface such as bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, methods 2800 or 2900 are implemented in two or more systems 3000, and information such as layout design, a first set of conductive structure layout patterns, a second set of conductive structure layout patterns, a third set of conductive structure layout patterns, a fourth set of conductive structure layout patterns, a fifth set of conductive structure layout patterns, a set of gate layout patterns, at least one set of via layout patterns, a set of rail layout patterns, and a user interface is exchanged between different systems 3000 over network 3014.

The system 3000 is configured to receive information related to layout design through the I/O interface 3010 or the network interface 3012. Information is communicated over the bus 3008 to the processor 3002 to determine a layout design for generating the integrated circuit structure 200, 1200, or 2400. The layout design is then stored in the computer readable medium 3004 as layout design 3016. The system 3000 is configured to receive information related to a first set of conductive structure layout patterns via the I/O interface 3010 or the network interface 3012. This information is stored in the computer-readable medium 3004 as a first set of conductive structure layout patterns 3018. The system 3000 is configured to receive information related to the second set of conductive structure layout patterns via the I/O interface 3010 or the network interface 3012. This information is stored in the computer readable medium 3004 as a second set of conductive structure layout patterns 3020. System 3000 is configured to receive information related to the third set of conductive structure layout patterns via I/O interface 3010 or network interface 3012. This information is stored in the computer readable medium 3004 as a third set of conductive structure layout patterns 3022. System 3000 is configured to receive information related to the fourth set of conductive structure layout patterns via I/O interface 3010 or network interface 3012. This information is stored in the computer medium 3004 as a fourth set of conductive structure layout patterns 3024. The system 3000 is configured to receive information related to the fifth set of conductive structure layout patterns through the I/O interface 3010 or the network interface 3012. This information is stored in the computer readable medium 3004 as a fifth set of conductive structure layout patterns 3026. The system 3000 is configured to receive information related to the gate layout pattern group through the I/O interface 3010 or the network interface 3012. This information is stored in the computer-readable medium 3004 as a gate layout pattern group 3028. The system 3000 is configured to receive information related to at least one set of via layout patterns through the I/O interface 3010 or the network interface 3012. This information is stored in the computer readable medium 3004 as at least one set of via layout patterns 3030. The system 3000 is configured to receive information related to a group of rail layout patterns through the I/O interface 3010 or the network interface 3012. This information is stored in the computer-readable medium 3004 as the guide rail layout pattern group 3032. System 3000 is configured to receive information related to a user interface via I/O interface 3010 or network interface 3012. This information is stored in the computer readable medium 3004 as the user interface 3034.

In some embodiments, method 2800 or 2900 is implemented as a standalone software application for execution by a processor. In some embodiments, method 2800 or 2900 is implemented as a software application as part of an additional software application. In some embodiments, method 2800 or 2900 is implemented as a plug-in to a software application. In some embodiments, the method 2800 or 2900 is implemented as a software application that is part of an EDA tool. In some embodiments, the method 2800 or 2900 is implemented as a software application used by an EDA tool. In some embodiments, EDA tools are used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, a material such as that available from CADENCE DESIGN SYSTEMS, incOr another suitable layout generation tool, produces the layout. In some embodiments, the layout is generated based on a netlist that is created based on a principle design. In some embodiments, method 2800 or 2900 is implemented by a manufacturing device to manufacture an integrated circuit (e.g., integrated circuit 200, 1200, or 2400) using a mask set manufactured based on one or more layout designs generated by system 3000 (e.g., layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D).

The system 3000 of FIG. 30 generates a layout design (e.g., layout designs 100, 300, 1100, 1300, 1900, 2000A-2000D, 2100A-2100B, 2300A-2300D, 2500A-2500B, 2600A-2600D, or 2700A-2700D) for the integrated circuit structure 200, 1200, or 2400 that occupies less area than other methods and provides better routing resources than other methods.

One aspect of the invention relates to an integrated circuit structure. The integrated circuit structure includes a set of gate structures at a first level, each gate in the set of gate structures being separated from each other in a first direction and extending in a second direction different from the first direction. The integrated circuit structure also includes a first conductive structure extending in the first direction, overlapping the set of gate set structures, and located at the second level. The integrated circuit structure also includes a first set of vias between the set of gate structures and the first conductive structure, each via in the first set of vias being located at a position where the first conductive structure overlaps each gate in the set of gates, and the first set of vias connecting the set of gate structures to the first conductive structure. The integrated circuit structure also includes a first set of conductive structures extending in the second direction, overlapping the first conductive structures, located at a third level, each conductive structure of the first set of conductive structures being separated from each other in the first direction and positioned between a pair of gates of the set of gate structures. The integrated circuit structure further includes a second set of vias located between the first set of conductive structures and the first conductive structure, each via of the second set of vias located at a position where the first set of conductive structures overlaps the first conductive structure, and the second set of vias connecting the first set of conductive structures to the first conductive structure. In some embodiments, the integrated circuit structure includes a second conductive structure extending in the first direction, overlapping the first set of conductive structures, overlying the first conductive structure, and located at a fourth level; and a third set of vias located between the second conductive structure and the first set of conductive structures, each via in the third set of vias being located at a position where the second conductive structure overlaps the first set of conductive structures, and the third set of vias connecting the second conductive structure to the first set of conductive structures. In some embodiments, the integrated circuit structure includes a second set of conductive structures extending in the second direction, overlapping the first and second conductive structures, overlying the first set of conductive structures, located at a fifth level, each conductive structure of the second set of conductive structures being separated from each other in the first direction and positioned between the set of gate structures; and a fourth set of vias located between the second set of conductive structures and the second conductive structure, each via in the fourth set of vias being located at a position where the second set of conductive structures overlaps the second conductive structure, and the fourth set of vias connecting the second set of conductive structures to the second conductive structure. In some embodiments, the integrated circuit structure further comprises a first power supply rail configured to provide a first power supply voltage; and a second power rail configured to provide a second power supply voltage different from the first power supply voltage, wherein at least the first conductive structure, the second conductive structure, the first set of conductive structures, or the second set of conductive structures is located between the first power rail and the second power rail. In some embodiments, the centers of the second set of vias, the centers of the third set of vias, and the centers of the fourth set of vias are aligned in the first direction and the second direction. In some embodiments, the second set of conductive structures has the same width as the first set of conductive structures. In some embodiments, the second set of conductive structures has the same length as the first set of conductive structures. In some embodiments, each conductive structure of the first set of conductive structures or the second set of conductive structures is located between a pair of gate structures of the set of gate structures. In some embodiments, the second set of conductive structures has a different length than the first set of conductive structures, and the integrated circuit structure is configured to provide the control signal to the gates of the set of gate structures.

In an embodiment, the integrated circuit structure further comprises: a second conductive structure extending in the first direction, overlapping the first set of conductive structures, overlying the first conductive structure, and located at a fourth level; and a third set of vias between the second conductive structure and the first set of conductive structures, each via in the third set of vias being located at a position where the second set of conductive structures overlaps the first set of conductive structures, and the third set of vias connecting the second conductive structures to the first set of conductive structures.

In an embodiment, the integrated circuit structure further comprises: a second set of conductive structures extending in the second direction, overlapping the first and second conductive structures, overlying the first set of conductive structures, at a fifth level, each conductive structure of the second set of conductive structures being separated from each other in the first direction and positioned between the sets of gate structures; and a fourth set of vias between the second set of conductive structures and the second conductive structure, each via in the fourth set of vias being located at a position where the second set of conductive structures overlaps the second conductive structure, and the fourth set of vias connecting the second set of conductive structures to the second conductive structure.

In an embodiment, the integrated circuit structure further comprises: a first power rail configured to provide a first power supply voltage; and a second power rail configured to provide a second power voltage different from the first power voltage, wherein at least the first conductive structure, the second conductive structure, the first set of conductive structures, or the second set of conductive structures is located between the first power rail and the second power rail.

In an embodiment, the centers of the second set of vias, the third set of vias, and the fourth set of vias are aligned in the first direction and the second direction.

In an embodiment, the second set of conductive structures has the same width as the first set of conductive structures.

In an embodiment, the second set of conductive structures has the same length as the first set of conductive structures.

In an embodiment, each conductive structure of the first or second set of conductive structures is located between a pair of gate structures of the set of gate structures.

In an embodiment, the second set of conductive structures has a different length than the first set of conductive structures, and the integrated circuit structure is configured to provide control signals to gates in the set of gate structures.

Another aspect of the invention relates to an integrated circuit structure that includes a first set of conductive structures extending in a first direction and located at a first level, and each conductive structure of the first set of conductive structures is separated from each other in a second direction different from the first direction. The integrated circuit structure further includes a second set of conductive structures extending in the second direction, overlapping the first set of conductive structures, located at a second level different from the first level, and each of the conductive structures in the second set of conductive structures being separated from each other in the first direction. The integrated circuit structure further includes a first set of vias located between the second set of conductive structures and the first set of conductive structures, the first set of vias connecting the second set of conductive structures to the first set of conductive structures, and each via in the first set of vias is located at a position where each conductive structure in the second set of conductive structures overlaps each conductive structure in the first set of conductive structures. The integrated circuit structure further includes a portion extending in the first direction, overlapping the second set of conductive structures, overlying the first set of conductive structures, a third set of conductive structures located at a third level different from the first and second levels, each conductive structure of the third set of conductive structures being separated from each other in the second direction. The integrated circuit structure further includes a second set of vias located between the third set of conductive structures and the second set of conductive structures, the second set of vias connecting the third set of conductive structures to the second set of conductive structures, and each via of the second set of vias is located at a position where each conductive structure of the third set of conductive structures overlaps each conductive structure of the second set of conductive structures. In some embodiments, the integrated circuit structure further comprises a portion extending in the second direction, overlapping the third set of conductive structures and the first set of conductive structures, covering the second set of conductive structures, a fourth set of conductive structures located at a fourth level different from the first, second, and third levels, and each conductive structure in the fourth set of conductive structures is separated from each other in the first direction; and a third set of vias located between the fourth set of conductive structures and the third set of conductive structures, the third set of vias connecting the fourth set of conductive structures to the third set of conductive structures, and each via in the third set of vias being located at a position where each conductive structure in the fourth set of conductive structures overlaps each conductive structure in the third set of conductive structures. In some embodiments, the second set of conductive structures includes: a first structure extending in a second direction; and a second structure extending in a second direction, the second structure being separated from the first structure in the first direction; the fourth set of conductive structures includes: a third structure extending in a second direction; and a fourth structure extending in the second direction, the fourth structure being separated from the third structure in the first direction. In some embodiments, the centers of the first set of vias, the centers of the second set of vias, and the centers of the third set of vias are aligned in a first direction and a second direction; the second set of conductive structures has the same width as the fourth set of conductive structures; or the second set of conductive structures has the same length as the fourth set of conductive structures. In some embodiments, the first set of conductive structures has a different length than the third set of conductive structures; and the integrated circuit structure is connected to the drain terminal of the transistor that is part of the standard cell.

In some embodiments, the integrated circuit structure further comprises a first power supply rail configured to provide a first power supply voltage, and a second power supply rail configured to provide a second power supply voltage different from the first power supply voltage, wherein at least the first set of conductive structures, the second set of conductive structures, the third set of conductive structures, or the fourth set of conductive structures is located between the first power supply rail and the second power supply rail.

In an embodiment, the integrated circuit structure further comprises: a fourth set of conductive structures extending in the second direction, overlapping the third set of conductive structures and the first set of conductive structures, covering portions of the second set of conductive structures, at a fourth level different from the first, second, and third levels, and each of the fourth set of conductive structures being separated from each other in the first direction; and a third set of vias between the fourth set of conductive structures and the third set of conductive structures, the third set of vias connecting the fourth set of conductive structures to the third set of conductive structures, and each via in the third set of vias is located at a position where each conductive structure in the fourth set of conductive structures overlaps each conductive structure in the third set of conductive structures.

In an embodiment, the second set of conductive structures comprises: a first structure extending in the second direction; and a second structure extending in the second direction, the second structure being separated from the first structure in the first direction; the fourth set of conductive structures includes: a third structure extending in the second direction; and a fourth structure extending in the second direction, the fourth structure being separated from the third structure in the first direction.

In an embodiment, the centers of the first set of vias, the second set of vias, and the third set of vias are aligned in the first direction and the second direction; the second set of conductive structures has the same width as the fourth set of conductive structures; or the second set of conductive structures has the same length as the fourth set of conductive structures.

In an embodiment, the first set of conductive structures has a different length than the third set of conductive structures; and the integrated circuit structure is connected to a drain terminal of a transistor, which is part of a standard cell.

In an embodiment, the integrated circuit structure further comprises: a first power rail configured to provide a first power supply voltage; and a second power rail configured to provide a second power voltage different from the first power voltage, wherein at least the first, second, third, or fourth set of conductive structures is located between the first and second power rails.

Another aspect of the invention relates to a method of fabricating an integrated circuit structure. The method includes placing a first set of conductive structure layout patterns on a first layout level, the first set of conductive structure layout patterns corresponding to a first set of conductive structures that fabricate the integrated circuit structure, the first set of conductive structure layout patterns extending in a first direction, each conductive structure layout pattern in the first set of conductive structure layout patterns being separated from one another in a second direction different from the first direction. The method also includes placing a second set of conductive structure layout patterns on a second layout level different from the first layout level, the second set of conductive structure layout patterns corresponding to a second set of conductive structures that fabricate the integrated circuit structure, the second set of conductive structure layout patterns extending in a second direction, overlapping the first set of conductive structure layout patterns, and each conductive structure layout pattern in the second set of conductive structure layout patterns being separated from each other in the first direction. The method also includes placing a first set of via layout patterns between a second set of conductive structure layout patterns and the first set of conductive structure layout patterns, the first set of via layout patterns corresponding to fabricating a first set of vias connecting the second set of conductive structures to the first set of conductive structures, and each via layout pattern of the first set of via layout patterns being located at a position where each conductive structure layout pattern of the second set of conductive structure layout patterns overlaps each conductive structure layout pattern of the first set of conductive structure layout patterns, wherein at least one of the layout patterns is stored on a non-transitory computer readable medium, and at least one of the operations is implemented by a hardware processor. The method also includes fabricating an integrated circuit structure based on at least one of the above-described layout patterns of the integrated circuit. In some embodiments, the method further includes placing a third set of conductive structure layout patterns at a third layout level different from the first layout level and the second layout level, the third set of conductive structure layout patterns corresponding to a third set of conductive structures for fabricating the integrated circuit structure, the third set of conductive structure layout patterns extending in the first direction, overlapping the second set of conductive structure layout patterns, covering a portion of the first set of conductive structure layout patterns, each conductive structure layout pattern in the third set of conductive structure layout patterns being separated from each other in the second direction; and placing a second set of via layout patterns between the third set of conductive structure layout patterns and the second set of conductive structure layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias connecting the third set of conductive structures to the second set of conductive structures, and each via layout pattern of the second set of via layout patterns being located at a position where each conductive structure layout pattern of the third set of conductive structure layout patterns overlaps each conductive structure layout pattern of the second set of conductive structure layout patterns. In some embodiments, the method further includes placing a fourth set of conductive structure layout patterns on a fourth layout level different from the first, second, and third layout levels, the fourth set of conductive structure layout patterns corresponding to a fourth set of conductive structures for fabricating the integrated circuit structure, the fourth set of conductive structure layout patterns extending in the second direction, overlapping the third set of conductive structure layout patterns and the first set of conductive structure layout patterns, covering portions of the second set of conductive structure layout patterns, and each conductive structure layout pattern of the fourth set of conductive structure layout patterns being separated from each other in the first direction. In some embodiments, the method further comprises placing a third set of via layout patterns between a fourth set of conductive structure layout patterns and a third set of conductive structure layout patterns, the third set of via layout patterns corresponding to fabricating a third set of vias connecting the fourth set of conductive structures to the third set of conductive structures, and each via layout pattern of the third set of via layout patterns being located at a position where each conductive structure layout pattern of the fourth set of conductive structure layout patterns overlaps each conductive structure layout pattern of the third set of conductive structure layout patterns. In some embodiments, the method further comprises placing a set of power rail layout patterns on a first layout level, the set of power rail layout patterns corresponding to a set of manufacturing power rails, wherein the set of power rails is configured to provide a first power supply voltage or a second power supply voltage different from the first power supply voltage, wherein at least a first set of conductive structure layout patterns, a second set of conductive structure layout patterns, a third set of conductive structure layout patterns, or a fourth set of conductive structure layout patterns is located between the first set of power rail layout patterns.

In an embodiment, the method of fabricating an integrated circuit structure further comprises: placing a third set of conductive structure layout patterns at a third layout level different from the first layout level and the second layout level, the third set of conductive structure layout patterns corresponding to a third set of conductive structures that fabricate the integrated circuit structure, the third set of conductive structure layout patterns extending in the first direction, overlapping the second set of conductive structure layout patterns, covering portions of the first set of conductive structure layout patterns, each conductive structure layout pattern in the third set of conductive structure layout patterns being separated from each other in the second direction; and placing a second set of via layout patterns between the third set of conductive structure layout patterns and the second set of conductive structure layout patterns, the second set of via layout patterns corresponding to fabricating a second set of vias connecting the third set of conductive structures to the second set of conductive structures, and each via layout pattern of the second set of via layout patterns being located at a position where each conductive structure layout pattern of the third set of conductive structure layout patterns overlaps each conductive structure layout pattern of the second set of conductive structure layout patterns.

In an embodiment, the method of fabricating an integrated circuit structure further comprises: placing a fourth set of conductive structure layout patterns on a fourth layout level different from the first, second, and third layout levels, the fourth set of conductive structure layout patterns corresponding to a fourth set of conductive structures for fabricating the integrated circuit structure, the fourth set of conductive structure layout patterns extending in the second direction, overlapping the third set of conductive structure layout patterns and the first set of conductive structure layout patterns, covering portions of the second set of conductive structure layout patterns, and each conductive structure layout pattern in the fourth set of conductive structure layout patterns being separated from each other in the first direction.

In an embodiment, the method of fabricating an integrated circuit structure further comprises: placing a third set of via layout patterns between the fourth set of conductive structure layout patterns and the third set of conductive structure layout patterns, the third set of via layout patterns corresponding to fabricating a third set of vias connecting the fourth set of conductive structures to the third set of conductive structures, and each via layout pattern of the third set of via layout patterns being located at a position where each conductive structure layout pattern of the fourth set of conductive structure layout patterns overlaps each conductive structure layout pattern of the third set of conductive structure layout patterns.

In an embodiment, the method of fabricating an integrated circuit structure further comprises: placing a set of power rail layout patterns on the first layout level, the set of power rail layout patterns corresponding to a set of manufacturing power rails, wherein the set of power rails is configured to provide a first power supply voltage or a second power supply voltage different from the first power supply voltage, wherein at least the first set of conductive structure layout patterns, the second set of conductive structure layout patterns, the third set of conductive structure layout patterns, or the fourth set of conductive structure layout patterns are located between the set of power rail layout patterns.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.